blob: 75afc524b659ae2c8a1d71d7cc091c79aa427176 [file] [log] [blame]
Alexander Shishkine443b332012-05-11 17:25:46 +03001/*
2 * core.c - ChipIdea USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13/*
14 * Description: ChipIdea USB IP core family device controller
15 *
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
19 * - UTIL: utilities
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
24 *
25 * Compile Options
26 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
27 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
29 * => case 4: Hi > Dn
30 * => case 5: Hi > Di
31 * => case 8: Hi <> Do
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
34 *
35 * Main Features
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
39 *
40 * USBTEST Report
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
43 *
44 * TODO List
45 * - OTG
Michael Grzeschike4ce4ec2013-06-13 17:59:47 +030046 * - Interrupt Traffic
Alexander Shishkine443b332012-05-11 17:25:46 +030047 * - GET_STATUS(device) - always reports 0
48 * - Gadget API (majority of optional features)
49 * - Suspend & Remote Wakeup
50 */
51#include <linux/delay.h>
52#include <linux/device.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030053#include <linux/dma-mapping.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030054#include <linux/platform_device.h>
55#include <linux/module.h>
Richard Zhaofe6e1252012-07-07 22:56:42 +080056#include <linux/idr.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030057#include <linux/interrupt.h>
58#include <linux/io.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030059#include <linux/kernel.h>
60#include <linux/slab.h>
61#include <linux/pm_runtime.h>
62#include <linux/usb/ch9.h>
63#include <linux/usb/gadget.h>
64#include <linux/usb/otg.h>
65#include <linux/usb/chipidea.h>
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +030066#include <linux/usb/of.h>
67#include <linux/phy.h>
Peter Chen1542d9c2013-08-14 12:44:03 +030068#include <linux/regulator/consumer.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030069
70#include "ci.h"
71#include "udc.h"
72#include "bits.h"
Alexander Shishkineb70e5a2012-05-11 17:25:54 +030073#include "host.h"
Alexander Shishkine443b332012-05-11 17:25:46 +030074#include "debug.h"
Peter Chenc10b4f02013-08-14 12:44:06 +030075#include "otg.h"
Alexander Shishkine443b332012-05-11 17:25:46 +030076
Alexander Shishkin5f36e232012-05-11 17:25:47 +030077/* Controller register map */
Alexander Shishkine443b332012-05-11 17:25:46 +030078static uintptr_t ci_regs_nolpm[] = {
79 [CAP_CAPLENGTH] = 0x000UL,
80 [CAP_HCCPARAMS] = 0x008UL,
81 [CAP_DCCPARAMS] = 0x024UL,
82 [CAP_TESTMODE] = 0x038UL,
83 [OP_USBCMD] = 0x000UL,
84 [OP_USBSTS] = 0x004UL,
85 [OP_USBINTR] = 0x008UL,
86 [OP_DEVICEADDR] = 0x014UL,
87 [OP_ENDPTLISTADDR] = 0x018UL,
88 [OP_PORTSC] = 0x044UL,
89 [OP_DEVLC] = 0x084UL,
Alexander Shishkin5f36e232012-05-11 17:25:47 +030090 [OP_OTGSC] = 0x064UL,
Alexander Shishkine443b332012-05-11 17:25:46 +030091 [OP_USBMODE] = 0x068UL,
92 [OP_ENDPTSETUPSTAT] = 0x06CUL,
93 [OP_ENDPTPRIME] = 0x070UL,
94 [OP_ENDPTFLUSH] = 0x074UL,
95 [OP_ENDPTSTAT] = 0x078UL,
96 [OP_ENDPTCOMPLETE] = 0x07CUL,
97 [OP_ENDPTCTRL] = 0x080UL,
98};
99
100static uintptr_t ci_regs_lpm[] = {
101 [CAP_CAPLENGTH] = 0x000UL,
102 [CAP_HCCPARAMS] = 0x008UL,
103 [CAP_DCCPARAMS] = 0x024UL,
104 [CAP_TESTMODE] = 0x0FCUL,
105 [OP_USBCMD] = 0x000UL,
106 [OP_USBSTS] = 0x004UL,
107 [OP_USBINTR] = 0x008UL,
108 [OP_DEVICEADDR] = 0x014UL,
109 [OP_ENDPTLISTADDR] = 0x018UL,
110 [OP_PORTSC] = 0x044UL,
111 [OP_DEVLC] = 0x084UL,
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300112 [OP_OTGSC] = 0x0C4UL,
Alexander Shishkine443b332012-05-11 17:25:46 +0300113 [OP_USBMODE] = 0x0C8UL,
114 [OP_ENDPTSETUPSTAT] = 0x0D8UL,
115 [OP_ENDPTPRIME] = 0x0DCUL,
116 [OP_ENDPTFLUSH] = 0x0E0UL,
117 [OP_ENDPTSTAT] = 0x0E4UL,
118 [OP_ENDPTCOMPLETE] = 0x0E8UL,
119 [OP_ENDPTCTRL] = 0x0ECUL,
120};
121
Alexander Shishkin8e229782013-06-24 14:46:36 +0300122static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
Alexander Shishkine443b332012-05-11 17:25:46 +0300123{
124 int i;
125
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300126 kfree(ci->hw_bank.regmap);
Alexander Shishkine443b332012-05-11 17:25:46 +0300127
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300128 ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
129 GFP_KERNEL);
130 if (!ci->hw_bank.regmap)
Alexander Shishkine443b332012-05-11 17:25:46 +0300131 return -ENOMEM;
132
133 for (i = 0; i < OP_ENDPTCTRL; i++)
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300134 ci->hw_bank.regmap[i] =
135 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
Alexander Shishkine443b332012-05-11 17:25:46 +0300136 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
137
138 for (; i <= OP_LAST; i++)
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300139 ci->hw_bank.regmap[i] = ci->hw_bank.op +
Alexander Shishkine443b332012-05-11 17:25:46 +0300140 4 * (i - OP_ENDPTCTRL) +
141 (is_lpm
142 ? ci_regs_lpm[OP_ENDPTCTRL]
143 : ci_regs_nolpm[OP_ENDPTCTRL]);
144
145 return 0;
146}
147
148/**
149 * hw_port_test_set: writes port test mode (execute without interruption)
150 * @mode: new value
151 *
152 * This function returns an error code
153 */
Alexander Shishkin8e229782013-06-24 14:46:36 +0300154int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
Alexander Shishkine443b332012-05-11 17:25:46 +0300155{
156 const u8 TEST_MODE_MAX = 7;
157
158 if (mode > TEST_MODE_MAX)
159 return -EINVAL;
160
Felipe Balbi727b4dd2013-03-30 12:53:55 +0200161 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
Alexander Shishkine443b332012-05-11 17:25:46 +0300162 return 0;
163}
164
165/**
166 * hw_port_test_get: reads port test mode value
167 *
168 * This function returns port test mode value
169 */
Alexander Shishkin8e229782013-06-24 14:46:36 +0300170u8 hw_port_test_get(struct ci_hdrc *ci)
Alexander Shishkine443b332012-05-11 17:25:46 +0300171{
Felipe Balbi727b4dd2013-03-30 12:53:55 +0200172 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
Alexander Shishkine443b332012-05-11 17:25:46 +0300173}
174
Alexander Shishkin8e229782013-06-24 14:46:36 +0300175static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
Alexander Shishkine443b332012-05-11 17:25:46 +0300176{
177 u32 reg;
178
179 /* bank is a module variable */
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300180 ci->hw_bank.abs = base;
Alexander Shishkine443b332012-05-11 17:25:46 +0300181
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300182 ci->hw_bank.cap = ci->hw_bank.abs;
Richard Zhao77c44002012-06-29 17:48:53 +0800183 ci->hw_bank.cap += ci->platdata->capoffset;
Svetoslav Neykov938d3232013-03-30 12:54:03 +0200184 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
Alexander Shishkine443b332012-05-11 17:25:46 +0300185
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300186 hw_alloc_regmap(ci, false);
187 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
Felipe Balbi727b4dd2013-03-30 12:53:55 +0200188 __ffs(HCCPARAMS_LEN);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300189 ci->hw_bank.lpm = reg;
190 hw_alloc_regmap(ci, !!reg);
191 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
192 ci->hw_bank.size += OP_LAST;
193 ci->hw_bank.size /= sizeof(u32);
Alexander Shishkine443b332012-05-11 17:25:46 +0300194
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300195 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
Felipe Balbi727b4dd2013-03-30 12:53:55 +0200196 __ffs(DCCPARAMS_DEN);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300197 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
Alexander Shishkine443b332012-05-11 17:25:46 +0300198
Richard Zhao09c94e62012-05-15 21:58:18 +0800199 if (ci->hw_ep_max > ENDPT_MAX)
Alexander Shishkine443b332012-05-11 17:25:46 +0300200 return -ENODEV;
201
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300202 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
203 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
Alexander Shishkine443b332012-05-11 17:25:46 +0300204
205 /* setup lock mode ? */
206
207 /* ENDPTSETUPSTAT is '0' by default */
208
209 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
210
211 return 0;
212}
213
Alexander Shishkin8e229782013-06-24 14:46:36 +0300214static void hw_phymode_configure(struct ci_hdrc *ci)
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +0300215{
216 u32 portsc, lpm, sts;
217
218 switch (ci->platdata->phy_mode) {
219 case USBPHY_INTERFACE_MODE_UTMI:
220 portsc = PORTSC_PTS(PTS_UTMI);
221 lpm = DEVLC_PTS(PTS_UTMI);
222 break;
223 case USBPHY_INTERFACE_MODE_UTMIW:
224 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
225 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
226 break;
227 case USBPHY_INTERFACE_MODE_ULPI:
228 portsc = PORTSC_PTS(PTS_ULPI);
229 lpm = DEVLC_PTS(PTS_ULPI);
230 break;
231 case USBPHY_INTERFACE_MODE_SERIAL:
232 portsc = PORTSC_PTS(PTS_SERIAL);
233 lpm = DEVLC_PTS(PTS_SERIAL);
234 sts = 1;
235 break;
236 case USBPHY_INTERFACE_MODE_HSIC:
237 portsc = PORTSC_PTS(PTS_HSIC);
238 lpm = DEVLC_PTS(PTS_HSIC);
239 break;
240 default:
241 return;
242 }
243
244 if (ci->hw_bank.lpm) {
245 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
246 hw_write(ci, OP_DEVLC, DEVLC_STS, sts);
247 } else {
248 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
249 hw_write(ci, OP_PORTSC, PORTSC_STS, sts);
250 }
251}
252
Alexander Shishkine443b332012-05-11 17:25:46 +0300253/**
254 * hw_device_reset: resets chip (execute without interruption)
255 * @ci: the controller
256 *
257 * This function returns an error code
258 */
Alexander Shishkin8e229782013-06-24 14:46:36 +0300259int hw_device_reset(struct ci_hdrc *ci, u32 mode)
Alexander Shishkine443b332012-05-11 17:25:46 +0300260{
261 /* should flush & stop before reset */
262 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
263 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
264
265 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
266 while (hw_read(ci, OP_USBCMD, USBCMD_RST))
267 udelay(10); /* not RTOS friendly */
268
Richard Zhao77c44002012-06-29 17:48:53 +0800269 if (ci->platdata->notify_event)
270 ci->platdata->notify_event(ci,
Alexander Shishkin8e229782013-06-24 14:46:36 +0300271 CI_HDRC_CONTROLLER_RESET_EVENT);
Alexander Shishkine443b332012-05-11 17:25:46 +0300272
Alexander Shishkin8e229782013-06-24 14:46:36 +0300273 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
Alexander Shishkin758fc982012-05-11 17:25:53 +0300274 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
Alexander Shishkine443b332012-05-11 17:25:46 +0300275
276 /* USBMODE should be configured step by step */
277 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
Alexander Shishkineb70e5a2012-05-11 17:25:54 +0300278 hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
Alexander Shishkine443b332012-05-11 17:25:46 +0300279 /* HW >= 2.3 */
280 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
281
Alexander Shishkineb70e5a2012-05-11 17:25:54 +0300282 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
283 pr_err("cannot enter in %s mode", ci_role(ci)->name);
Alexander Shishkine443b332012-05-11 17:25:46 +0300284 pr_err("lpm = %i", ci->hw_bank.lpm);
285 return -ENODEV;
286 }
287
288 return 0;
289}
290
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300291/**
292 * ci_otg_role - pick role based on ID pin state
293 * @ci: the controller
294 */
Alexander Shishkin8e229782013-06-24 14:46:36 +0300295static enum ci_role ci_otg_role(struct ci_hdrc *ci)
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300296{
297 u32 sts = hw_read(ci, OP_OTGSC, ~0);
298 enum ci_role role = sts & OTGSC_ID
299 ? CI_ROLE_GADGET
300 : CI_ROLE_HOST;
301
302 return role;
303}
304
305/**
306 * ci_role_work - perform role changing based on ID pin
307 * @work: work struct
308 */
309static void ci_role_work(struct work_struct *work)
310{
Alexander Shishkin8e229782013-06-24 14:46:36 +0300311 struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300312 enum ci_role role = ci_otg_role(ci);
313
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300314 if (role != ci->role) {
315 dev_dbg(ci->dev, "switching from %s to %s\n",
316 ci_role(ci)->name, ci->roles[role]->name);
317
318 ci_role_stop(ci);
319 ci_role_start(ci, role);
320 }
Alexander Shishkin0c3f3dc2013-06-11 13:41:48 +0300321
322 enable_irq(ci->irq);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300323}
324
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300325static irqreturn_t ci_irq(int irq, void *data)
326{
Alexander Shishkin8e229782013-06-24 14:46:36 +0300327 struct ci_hdrc *ci = data;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300328 irqreturn_t ret = IRQ_NONE;
Richard Zhaob183c192012-09-12 14:58:11 +0300329 u32 otgsc = 0;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300330
Richard Zhaob183c192012-09-12 14:58:11 +0300331 if (ci->is_otg)
332 otgsc = hw_read(ci, OP_OTGSC, ~0);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300333
Richard Zhaob183c192012-09-12 14:58:11 +0300334 if (ci->role != CI_ROLE_END)
335 ret = ci_role(ci)->irq(ci);
336
337 if (ci->is_otg && (otgsc & OTGSC_IDIS)) {
338 hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
339 disable_irq_nosync(ci->irq);
340 queue_work(ci->wq, &ci->work);
341 ret = IRQ_HANDLED;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300342 }
343
Richard Zhaob183c192012-09-12 14:58:11 +0300344 return ret;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300345}
346
Peter Chen1542d9c2013-08-14 12:44:03 +0300347static int ci_get_platdata(struct device *dev,
348 struct ci_hdrc_platform_data *platdata)
349{
350 /* Get the vbus regulator */
351 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
352 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
353 return -EPROBE_DEFER;
354 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
355 platdata->reg_vbus = NULL; /* no vbus regualator is needed */
356 } else if (IS_ERR(platdata->reg_vbus)) {
357 dev_err(dev, "Getting regulator error: %ld\n",
358 PTR_ERR(platdata->reg_vbus));
359 return PTR_ERR(platdata->reg_vbus);
360 }
361
362 return 0;
363}
364
Richard Zhaofe6e1252012-07-07 22:56:42 +0800365static DEFINE_IDA(ci_ida);
366
Alexander Shishkin8e229782013-06-24 14:46:36 +0300367struct platform_device *ci_hdrc_add_device(struct device *dev,
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800368 struct resource *res, int nres,
Alexander Shishkin8e229782013-06-24 14:46:36 +0300369 struct ci_hdrc_platform_data *platdata)
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800370{
371 struct platform_device *pdev;
Richard Zhaofe6e1252012-07-07 22:56:42 +0800372 int id, ret;
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800373
Peter Chen1542d9c2013-08-14 12:44:03 +0300374 ret = ci_get_platdata(dev, platdata);
375 if (ret)
376 return ERR_PTR(ret);
377
Richard Zhaofe6e1252012-07-07 22:56:42 +0800378 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
379 if (id < 0)
380 return ERR_PTR(id);
381
382 pdev = platform_device_alloc("ci_hdrc", id);
383 if (!pdev) {
384 ret = -ENOMEM;
385 goto put_id;
386 }
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800387
388 pdev->dev.parent = dev;
389 pdev->dev.dma_mask = dev->dma_mask;
390 pdev->dev.dma_parms = dev->dma_parms;
391 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
392
393 ret = platform_device_add_resources(pdev, res, nres);
394 if (ret)
395 goto err;
396
397 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
398 if (ret)
399 goto err;
400
401 ret = platform_device_add(pdev);
402 if (ret)
403 goto err;
404
405 return pdev;
406
407err:
408 platform_device_put(pdev);
Richard Zhaofe6e1252012-07-07 22:56:42 +0800409put_id:
410 ida_simple_remove(&ci_ida, id);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800411 return ERR_PTR(ret);
412}
Alexander Shishkin8e229782013-06-24 14:46:36 +0300413EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800414
Alexander Shishkin8e229782013-06-24 14:46:36 +0300415void ci_hdrc_remove_device(struct platform_device *pdev)
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800416{
Lothar Waßmann98c35532012-11-22 10:11:25 +0100417 int id = pdev->id;
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800418 platform_device_unregister(pdev);
Lothar Waßmann98c35532012-11-22 10:11:25 +0100419 ida_simple_remove(&ci_ida, id);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800420}
Alexander Shishkin8e229782013-06-24 14:46:36 +0300421EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800422
Peter Chen3f124d22013-08-14 12:44:07 +0300423static inline void ci_role_destroy(struct ci_hdrc *ci)
424{
425 ci_hdrc_gadget_destroy(ci);
426 ci_hdrc_host_destroy(ci);
427}
428
Bill Pemberton41ac7b32012-11-19 13:21:48 -0500429static int ci_hdrc_probe(struct platform_device *pdev)
Alexander Shishkine443b332012-05-11 17:25:46 +0300430{
431 struct device *dev = &pdev->dev;
Alexander Shishkin8e229782013-06-24 14:46:36 +0300432 struct ci_hdrc *ci;
Alexander Shishkine443b332012-05-11 17:25:46 +0300433 struct resource *res;
434 void __iomem *base;
435 int ret;
Sascha Hauer691962d2013-06-13 17:59:57 +0300436 enum usb_dr_mode dr_mode;
Lothar Waßmanne98b44e2013-08-14 12:44:01 +0300437 struct device_node *of_node = dev->of_node ?: dev->parent->of_node;
Alexander Shishkine443b332012-05-11 17:25:46 +0300438
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300439 if (!dev->platform_data) {
Alexander Shishkine443b332012-05-11 17:25:46 +0300440 dev_err(dev, "platform data missing\n");
441 return -ENODEV;
442 }
443
444 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Felipe Balbi19290812013-03-30 02:46:27 +0200445 base = devm_ioremap_resource(dev, res);
446 if (IS_ERR(base))
447 return PTR_ERR(base);
Alexander Shishkine443b332012-05-11 17:25:46 +0300448
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300449 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
450 if (!ci) {
451 dev_err(dev, "can't allocate device\n");
452 return -ENOMEM;
Alexander Shishkine443b332012-05-11 17:25:46 +0300453 }
454
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300455 ci->dev = dev;
Richard Zhao77c44002012-06-29 17:48:53 +0800456 ci->platdata = dev->platform_data;
Richard Zhaoa2c3d692012-07-07 22:56:46 +0800457 if (ci->platdata->phy)
458 ci->transceiver = ci->platdata->phy;
459 else
460 ci->global_phy = true;
Alexander Shishkine443b332012-05-11 17:25:46 +0300461
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300462 ret = hw_device_init(ci, base);
463 if (ret < 0) {
464 dev_err(dev, "can't initialize hardware\n");
465 return -ENODEV;
466 }
467
Alexander Shishkineb70e5a2012-05-11 17:25:54 +0300468 ci->hw_bank.phys = res->start;
469
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300470 ci->irq = platform_get_irq(pdev, 0);
471 if (ci->irq < 0) {
472 dev_err(dev, "missing IRQ\n");
473 return -ENODEV;
474 }
475
476 INIT_WORK(&ci->work, ci_role_work);
477 ci->wq = create_singlethread_workqueue("ci_otg");
478 if (!ci->wq) {
479 dev_err(dev, "can't create workqueue\n");
480 return -ENODEV;
481 }
482
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +0300483 if (!ci->platdata->phy_mode)
Lothar Waßmanne98b44e2013-08-14 12:44:01 +0300484 ci->platdata->phy_mode = of_usb_get_phy_mode(of_node);
Michael Grzeschik40dcd0e2013-06-13 17:59:56 +0300485
Fabio Estevam03779f02013-08-14 12:43:56 +0300486 hw_phymode_configure(ci);
487
Sascha Hauer691962d2013-06-13 17:59:57 +0300488 if (!ci->platdata->dr_mode)
Lothar Waßmanne98b44e2013-08-14 12:44:01 +0300489 ci->platdata->dr_mode = of_usb_get_dr_mode(of_node);
Alexander Shishkineb70e5a2012-05-11 17:25:54 +0300490
Sascha Hauer691962d2013-06-13 17:59:57 +0300491 if (ci->platdata->dr_mode == USB_DR_MODE_UNKNOWN)
492 ci->platdata->dr_mode = USB_DR_MODE_OTG;
493
494 dr_mode = ci->platdata->dr_mode;
495 /* initialize role(s) before the interrupt is requested */
496 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
497 ret = ci_hdrc_host_init(ci);
498 if (ret)
499 dev_info(dev, "doesn't support host\n");
500 }
501
502 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
503 ret = ci_hdrc_gadget_init(ci);
504 if (ret)
505 dev_info(dev, "doesn't support gadget\n");
506 }
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300507
508 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
509 dev_err(dev, "no supported roles\n");
510 ret = -ENODEV;
511 goto rm_wq;
512 }
513
514 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
515 ci->is_otg = true;
Richard Zhao86ad01a2012-09-12 14:58:07 +0300516 /* ID pin needs 1ms debouce time, we delay 2ms for safe */
517 mdelay(2);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300518 ci->role = ci_otg_role(ci);
519 } else {
520 ci->role = ci->roles[CI_ROLE_HOST]
521 ? CI_ROLE_HOST
522 : CI_ROLE_GADGET;
523 }
524
525 ret = ci_role_start(ci, ci->role);
526 if (ret) {
527 dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300528 goto rm_wq;
529 }
530
531 platform_set_drvdata(pdev, ci);
Richard Zhao77c44002012-06-29 17:48:53 +0800532 ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300533 ci);
534 if (ret)
535 goto stop;
536
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300537 if (ci->is_otg)
Peter Chenc10b4f02013-08-14 12:44:06 +0300538 ci_hdrc_otg_init(ci);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300539
Alexander Shishkinadf0f732013-03-30 12:53:53 +0200540 ret = dbg_create_files(ci);
541 if (!ret)
542 return 0;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300543
Alexander Shishkinadf0f732013-03-30 12:53:53 +0200544 free_irq(ci->irq, ci);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300545stop:
Peter Chen3f124d22013-08-14 12:44:07 +0300546 ci_role_destroy(ci);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300547rm_wq:
548 flush_workqueue(ci->wq);
549 destroy_workqueue(ci->wq);
Alexander Shishkine443b332012-05-11 17:25:46 +0300550
551 return ret;
552}
553
Bill Pembertonfb4e98a2012-11-19 13:26:20 -0500554static int ci_hdrc_remove(struct platform_device *pdev)
Alexander Shishkine443b332012-05-11 17:25:46 +0300555{
Alexander Shishkin8e229782013-06-24 14:46:36 +0300556 struct ci_hdrc *ci = platform_get_drvdata(pdev);
Alexander Shishkine443b332012-05-11 17:25:46 +0300557
Alexander Shishkinadf0f732013-03-30 12:53:53 +0200558 dbg_remove_files(ci);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300559 flush_workqueue(ci->wq);
560 destroy_workqueue(ci->wq);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300561 free_irq(ci->irq, ci);
Peter Chen3f124d22013-08-14 12:44:07 +0300562 ci_role_destroy(ci);
Alexander Shishkine443b332012-05-11 17:25:46 +0300563
564 return 0;
565}
566
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300567static struct platform_driver ci_hdrc_driver = {
568 .probe = ci_hdrc_probe,
Bill Pemberton76904172012-11-19 13:21:08 -0500569 .remove = ci_hdrc_remove,
Alexander Shishkine443b332012-05-11 17:25:46 +0300570 .driver = {
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300571 .name = "ci_hdrc",
Alexander Shishkine443b332012-05-11 17:25:46 +0300572 },
573};
574
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300575module_platform_driver(ci_hdrc_driver);
Alexander Shishkine443b332012-05-11 17:25:46 +0300576
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300577MODULE_ALIAS("platform:ci_hdrc");
Alexander Shishkine443b332012-05-11 17:25:46 +0300578MODULE_LICENSE("GPL v2");
579MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300580MODULE_DESCRIPTION("ChipIdea HDRC Driver");