blob: b0413e190625b26c0552e8a737479f52b3dd5c9d [file] [log] [blame]
Eric Anholt7d573822009-01-02 13:33:00 -08001/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/i2c.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Eric Anholt7d573822009-01-02 13:33:00 -080031#include <linux/delay.h>
Damien Lespiau178f7362013-08-06 20:32:18 +010032#include <linux/hdmi.h>
David Howells760285e2012-10-02 18:01:07 +010033#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h>
Eric Anholt7d573822009-01-02 13:33:00 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Eric Anholt7d573822009-01-02 13:33:00 -080038#include "i915_drv.h"
39
Paulo Zanoni30add222012-10-26 19:05:45 -020040static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
41{
Paulo Zanonida63a9f2012-10-26 19:05:46 -020042 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
Paulo Zanoni30add222012-10-26 19:05:45 -020043}
44
Daniel Vetterafba0182012-06-12 16:36:45 +020045static void
46assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
47{
Paulo Zanoni30add222012-10-26 19:05:45 -020048 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
Daniel Vetterafba0182012-06-12 16:36:45 +020049 struct drm_i915_private *dev_priv = dev->dev_private;
50 uint32_t enabled_bits;
51
Paulo Zanoniaffa9352012-11-23 15:30:39 -020052 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
Daniel Vetterafba0182012-06-12 16:36:45 +020053
Paulo Zanonib242b7f2013-02-18 19:00:26 -030054 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
Daniel Vetterafba0182012-06-12 16:36:45 +020055 "HDMI port enabled, expecting disabled\n");
56}
57
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -030058struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
Chris Wilsonea5b2132010-08-04 13:50:23 +010059{
Paulo Zanonida63a9f2012-10-26 19:05:46 -020060 struct intel_digital_port *intel_dig_port =
61 container_of(encoder, struct intel_digital_port, base.base);
62 return &intel_dig_port->hdmi;
Chris Wilsonea5b2132010-08-04 13:50:23 +010063}
64
Chris Wilsondf0e9242010-09-09 16:20:55 +010065static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
66{
Paulo Zanonida63a9f2012-10-26 19:05:46 -020067 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
Chris Wilsondf0e9242010-09-09 16:20:55 +010068}
69
Damien Lespiau178f7362013-08-06 20:32:18 +010070static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
David Härdeman3c17fe42010-09-24 21:44:32 +020071{
Damien Lespiau178f7362013-08-06 20:32:18 +010072 switch (type) {
73 case HDMI_INFOFRAME_TYPE_AVI:
Paulo Zanonied517fb2012-05-14 17:12:50 -030074 return VIDEO_DIP_SELECT_AVI;
Damien Lespiau178f7362013-08-06 20:32:18 +010075 case HDMI_INFOFRAME_TYPE_SPD:
Paulo Zanonied517fb2012-05-14 17:12:50 -030076 return VIDEO_DIP_SELECT_SPD;
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +010077 case HDMI_INFOFRAME_TYPE_VENDOR:
78 return VIDEO_DIP_SELECT_VENDOR;
Jesse Barnes45187ac2011-08-03 09:22:55 -070079 default:
Damien Lespiau178f7362013-08-06 20:32:18 +010080 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
Paulo Zanonied517fb2012-05-14 17:12:50 -030081 return 0;
Jesse Barnes45187ac2011-08-03 09:22:55 -070082 }
Jesse Barnes45187ac2011-08-03 09:22:55 -070083}
84
Damien Lespiau178f7362013-08-06 20:32:18 +010085static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
Jesse Barnes45187ac2011-08-03 09:22:55 -070086{
Damien Lespiau178f7362013-08-06 20:32:18 +010087 switch (type) {
88 case HDMI_INFOFRAME_TYPE_AVI:
Paulo Zanonied517fb2012-05-14 17:12:50 -030089 return VIDEO_DIP_ENABLE_AVI;
Damien Lespiau178f7362013-08-06 20:32:18 +010090 case HDMI_INFOFRAME_TYPE_SPD:
Paulo Zanonied517fb2012-05-14 17:12:50 -030091 return VIDEO_DIP_ENABLE_SPD;
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +010092 case HDMI_INFOFRAME_TYPE_VENDOR:
93 return VIDEO_DIP_ENABLE_VENDOR;
Paulo Zanonifa193ff2012-05-04 17:18:20 -030094 default:
Damien Lespiau178f7362013-08-06 20:32:18 +010095 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
Paulo Zanonied517fb2012-05-14 17:12:50 -030096 return 0;
Paulo Zanonifa193ff2012-05-04 17:18:20 -030097 }
Paulo Zanonifa193ff2012-05-04 17:18:20 -030098}
99
Damien Lespiau178f7362013-08-06 20:32:18 +0100100static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300101{
Damien Lespiau178f7362013-08-06 20:32:18 +0100102 switch (type) {
103 case HDMI_INFOFRAME_TYPE_AVI:
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300104 return VIDEO_DIP_ENABLE_AVI_HSW;
Damien Lespiau178f7362013-08-06 20:32:18 +0100105 case HDMI_INFOFRAME_TYPE_SPD:
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300106 return VIDEO_DIP_ENABLE_SPD_HSW;
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100107 case HDMI_INFOFRAME_TYPE_VENDOR:
108 return VIDEO_DIP_ENABLE_VS_HSW;
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300109 default:
Damien Lespiau178f7362013-08-06 20:32:18 +0100110 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300111 return 0;
112 }
113}
114
Damien Lespiau178f7362013-08-06 20:32:18 +0100115static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200116 enum transcoder cpu_transcoder,
117 struct drm_i915_private *dev_priv)
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300118{
Damien Lespiau178f7362013-08-06 20:32:18 +0100119 switch (type) {
120 case HDMI_INFOFRAME_TYPE_AVI:
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -0300121 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
Damien Lespiau178f7362013-08-06 20:32:18 +0100122 case HDMI_INFOFRAME_TYPE_SPD:
Rodrigo Vivi7d9bceb2013-02-25 19:55:16 -0300123 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100124 case HDMI_INFOFRAME_TYPE_VENDOR:
125 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300126 default:
Damien Lespiau178f7362013-08-06 20:32:18 +0100127 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300128 return 0;
129 }
130}
131
Daniel Vettera3da1df2012-05-08 15:19:06 +0200132static void g4x_write_infoframe(struct drm_encoder *encoder,
Damien Lespiau178f7362013-08-06 20:32:18 +0100133 enum hdmi_infoframe_type type,
Ville Syrjäläfff63862013-12-10 15:19:08 +0200134 const void *frame, ssize_t len)
Jesse Barnes45187ac2011-08-03 09:22:55 -0700135{
Ville Syrjäläfff63862013-12-10 15:19:08 +0200136 const uint32_t *data = frame;
David Härdeman3c17fe42010-09-24 21:44:32 +0200137 struct drm_device *dev = encoder->dev;
138 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300139 u32 val = I915_READ(VIDEO_DIP_CTL);
Damien Lespiau178f7362013-08-06 20:32:18 +0100140 int i;
David Härdeman3c17fe42010-09-24 21:44:32 +0200141
Paulo Zanoni822974a2012-05-28 16:42:51 -0300142 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
143
Paulo Zanoni1d4f85a2012-05-04 17:18:18 -0300144 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
Damien Lespiau178f7362013-08-06 20:32:18 +0100145 val |= g4x_infoframe_index(type);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700146
Damien Lespiau178f7362013-08-06 20:32:18 +0100147 val &= ~g4x_infoframe_enable(type);
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300148
149 I915_WRITE(VIDEO_DIP_CTL, val);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700150
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300151 mmiowb();
Jesse Barnes45187ac2011-08-03 09:22:55 -0700152 for (i = 0; i < len; i += 4) {
David Härdeman3c17fe42010-09-24 21:44:32 +0200153 I915_WRITE(VIDEO_DIP_DATA, *data);
154 data++;
155 }
Paulo Zanoniadf00b22012-09-25 13:23:34 -0300156 /* Write every possible data byte to force correct ECC calculation. */
157 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
158 I915_WRITE(VIDEO_DIP_DATA, 0);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300159 mmiowb();
David Härdeman3c17fe42010-09-24 21:44:32 +0200160
Damien Lespiau178f7362013-08-06 20:32:18 +0100161 val |= g4x_infoframe_enable(type);
Paulo Zanoni60c5ea22012-05-04 17:18:22 -0300162 val &= ~VIDEO_DIP_FREQ_MASK;
Daniel Vetter4b24c932012-05-08 14:41:00 +0200163 val |= VIDEO_DIP_FREQ_VSYNC;
Jesse Barnes45187ac2011-08-03 09:22:55 -0700164
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300165 I915_WRITE(VIDEO_DIP_CTL, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300166 POSTING_READ(VIDEO_DIP_CTL);
David Härdeman3c17fe42010-09-24 21:44:32 +0200167}
168
Paulo Zanonifdf12502012-05-04 17:18:24 -0300169static void ibx_write_infoframe(struct drm_encoder *encoder,
Damien Lespiau178f7362013-08-06 20:32:18 +0100170 enum hdmi_infoframe_type type,
Ville Syrjäläfff63862013-12-10 15:19:08 +0200171 const void *frame, ssize_t len)
Paulo Zanonifdf12502012-05-04 17:18:24 -0300172{
Ville Syrjäläfff63862013-12-10 15:19:08 +0200173 const uint32_t *data = frame;
Paulo Zanonifdf12502012-05-04 17:18:24 -0300174 struct drm_device *dev = encoder->dev;
175 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonied517fb2012-05-14 17:12:50 -0300176 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Damien Lespiau178f7362013-08-06 20:32:18 +0100177 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
Paulo Zanonifdf12502012-05-04 17:18:24 -0300178 u32 val = I915_READ(reg);
179
Paulo Zanoni822974a2012-05-28 16:42:51 -0300180 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
181
Paulo Zanonifdf12502012-05-04 17:18:24 -0300182 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
Damien Lespiau178f7362013-08-06 20:32:18 +0100183 val |= g4x_infoframe_index(type);
Paulo Zanonifdf12502012-05-04 17:18:24 -0300184
Damien Lespiau178f7362013-08-06 20:32:18 +0100185 val &= ~g4x_infoframe_enable(type);
Paulo Zanonifdf12502012-05-04 17:18:24 -0300186
187 I915_WRITE(reg, val);
188
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300189 mmiowb();
Paulo Zanonifdf12502012-05-04 17:18:24 -0300190 for (i = 0; i < len; i += 4) {
191 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
192 data++;
193 }
Paulo Zanoniadf00b22012-09-25 13:23:34 -0300194 /* Write every possible data byte to force correct ECC calculation. */
195 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
196 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300197 mmiowb();
Paulo Zanonifdf12502012-05-04 17:18:24 -0300198
Damien Lespiau178f7362013-08-06 20:32:18 +0100199 val |= g4x_infoframe_enable(type);
Paulo Zanonifdf12502012-05-04 17:18:24 -0300200 val &= ~VIDEO_DIP_FREQ_MASK;
Daniel Vetter4b24c932012-05-08 14:41:00 +0200201 val |= VIDEO_DIP_FREQ_VSYNC;
Paulo Zanonifdf12502012-05-04 17:18:24 -0300202
203 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300204 POSTING_READ(reg);
Paulo Zanonifdf12502012-05-04 17:18:24 -0300205}
206
207static void cpt_write_infoframe(struct drm_encoder *encoder,
Damien Lespiau178f7362013-08-06 20:32:18 +0100208 enum hdmi_infoframe_type type,
Ville Syrjäläfff63862013-12-10 15:19:08 +0200209 const void *frame, ssize_t len)
Jesse Barnes45187ac2011-08-03 09:22:55 -0700210{
Ville Syrjäläfff63862013-12-10 15:19:08 +0200211 const uint32_t *data = frame;
Jesse Barnes45187ac2011-08-03 09:22:55 -0700212 struct drm_device *dev = encoder->dev;
213 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonied517fb2012-05-14 17:12:50 -0300214 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Damien Lespiau178f7362013-08-06 20:32:18 +0100215 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300216 u32 val = I915_READ(reg);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700217
Paulo Zanoni822974a2012-05-28 16:42:51 -0300218 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
219
Jesse Barnes64a8fc02011-09-22 11:16:00 +0530220 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
Damien Lespiau178f7362013-08-06 20:32:18 +0100221 val |= g4x_infoframe_index(type);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700222
Paulo Zanoniecb97852012-05-04 17:18:21 -0300223 /* The DIP control register spec says that we need to update the AVI
224 * infoframe without clearing its enable bit */
Damien Lespiau178f7362013-08-06 20:32:18 +0100225 if (type != HDMI_INFOFRAME_TYPE_AVI)
226 val &= ~g4x_infoframe_enable(type);
Paulo Zanoniecb97852012-05-04 17:18:21 -0300227
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300228 I915_WRITE(reg, val);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700229
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300230 mmiowb();
Jesse Barnes45187ac2011-08-03 09:22:55 -0700231 for (i = 0; i < len; i += 4) {
232 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
233 data++;
234 }
Paulo Zanoniadf00b22012-09-25 13:23:34 -0300235 /* Write every possible data byte to force correct ECC calculation. */
236 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
237 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300238 mmiowb();
Jesse Barnes45187ac2011-08-03 09:22:55 -0700239
Damien Lespiau178f7362013-08-06 20:32:18 +0100240 val |= g4x_infoframe_enable(type);
Paulo Zanoni60c5ea22012-05-04 17:18:22 -0300241 val &= ~VIDEO_DIP_FREQ_MASK;
Daniel Vetter4b24c932012-05-08 14:41:00 +0200242 val |= VIDEO_DIP_FREQ_VSYNC;
Jesse Barnes45187ac2011-08-03 09:22:55 -0700243
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300244 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300245 POSTING_READ(reg);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700246}
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700247
248static void vlv_write_infoframe(struct drm_encoder *encoder,
Damien Lespiau178f7362013-08-06 20:32:18 +0100249 enum hdmi_infoframe_type type,
Ville Syrjäläfff63862013-12-10 15:19:08 +0200250 const void *frame, ssize_t len)
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700251{
Ville Syrjäläfff63862013-12-10 15:19:08 +0200252 const uint32_t *data = frame;
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700253 struct drm_device *dev = encoder->dev;
254 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonied517fb2012-05-14 17:12:50 -0300255 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Damien Lespiau178f7362013-08-06 20:32:18 +0100256 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300257 u32 val = I915_READ(reg);
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700258
Paulo Zanoni822974a2012-05-28 16:42:51 -0300259 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
260
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700261 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
Damien Lespiau178f7362013-08-06 20:32:18 +0100262 val |= g4x_infoframe_index(type);
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700263
Damien Lespiau178f7362013-08-06 20:32:18 +0100264 val &= ~g4x_infoframe_enable(type);
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300265
266 I915_WRITE(reg, val);
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700267
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300268 mmiowb();
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700269 for (i = 0; i < len; i += 4) {
270 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
271 data++;
272 }
Paulo Zanoniadf00b22012-09-25 13:23:34 -0300273 /* Write every possible data byte to force correct ECC calculation. */
274 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
275 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300276 mmiowb();
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700277
Damien Lespiau178f7362013-08-06 20:32:18 +0100278 val |= g4x_infoframe_enable(type);
Paulo Zanoni60c5ea22012-05-04 17:18:22 -0300279 val &= ~VIDEO_DIP_FREQ_MASK;
Daniel Vetter4b24c932012-05-08 14:41:00 +0200280 val |= VIDEO_DIP_FREQ_VSYNC;
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700281
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300282 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300283 POSTING_READ(reg);
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700284}
285
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300286static void hsw_write_infoframe(struct drm_encoder *encoder,
Damien Lespiau178f7362013-08-06 20:32:18 +0100287 enum hdmi_infoframe_type type,
Ville Syrjäläfff63862013-12-10 15:19:08 +0200288 const void *frame, ssize_t len)
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300289{
Ville Syrjäläfff63862013-12-10 15:19:08 +0200290 const uint32_t *data = frame;
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300291 struct drm_device *dev = encoder->dev;
292 struct drm_i915_private *dev_priv = dev->dev_private;
293 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +0200294 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
Damien Lespiau178f7362013-08-06 20:32:18 +0100295 u32 data_reg;
296 int i;
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300297 u32 val = I915_READ(ctl_reg);
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300298
Damien Lespiau178f7362013-08-06 20:32:18 +0100299 data_reg = hsw_infoframe_data_reg(type,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200300 intel_crtc->config.cpu_transcoder,
301 dev_priv);
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300302 if (data_reg == 0)
303 return;
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300304
Damien Lespiau178f7362013-08-06 20:32:18 +0100305 val &= ~hsw_infoframe_enable(type);
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300306 I915_WRITE(ctl_reg, val);
307
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300308 mmiowb();
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300309 for (i = 0; i < len; i += 4) {
310 I915_WRITE(data_reg + i, *data);
311 data++;
312 }
Paulo Zanoniadf00b22012-09-25 13:23:34 -0300313 /* Write every possible data byte to force correct ECC calculation. */
314 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
315 I915_WRITE(data_reg + i, 0);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300316 mmiowb();
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300317
Damien Lespiau178f7362013-08-06 20:32:18 +0100318 val |= hsw_infoframe_enable(type);
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300319 I915_WRITE(ctl_reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300320 POSTING_READ(ctl_reg);
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300321}
322
Damien Lespiau5adaea72013-08-06 20:32:19 +0100323/*
324 * The data we write to the DIP data buffer registers is 1 byte bigger than the
325 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
326 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
327 * used for both technologies.
328 *
329 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
330 * DW1: DB3 | DB2 | DB1 | DB0
331 * DW2: DB7 | DB6 | DB5 | DB4
332 * DW3: ...
333 *
334 * (HB is Header Byte, DB is Data Byte)
335 *
336 * The hdmi pack() functions don't know about that hardware specific hole so we
337 * trick them by giving an offset into the buffer and moving back the header
338 * bytes by one.
339 */
Damien Lespiau9198ee52013-08-06 20:32:24 +0100340static void intel_write_infoframe(struct drm_encoder *encoder,
341 union hdmi_infoframe *frame)
Jesse Barnes45187ac2011-08-03 09:22:55 -0700342{
343 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
Damien Lespiau5adaea72013-08-06 20:32:19 +0100344 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
345 ssize_t len;
Jesse Barnes45187ac2011-08-03 09:22:55 -0700346
Damien Lespiau5adaea72013-08-06 20:32:19 +0100347 /* see comment above for the reason for this offset */
348 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
349 if (len < 0)
350 return;
351
352 /* Insert the 'hole' (see big comment above) at position 3 */
353 buffer[0] = buffer[1];
354 buffer[1] = buffer[2];
355 buffer[2] = buffer[3];
356 buffer[3] = 0;
357 len++;
358
359 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700360}
361
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300362static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
Paulo Zanonic846b612012-04-13 16:31:41 -0300363 struct drm_display_mode *adjusted_mode)
Jesse Barnesb055c8f2011-07-08 11:31:57 -0700364{
Ville Syrjäläabedc072013-01-17 16:31:31 +0200365 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
Daniel Vetter50f3b012013-03-27 00:44:56 +0100366 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Damien Lespiau5adaea72013-08-06 20:32:19 +0100367 union hdmi_infoframe frame;
368 int ret;
Jesse Barnesb055c8f2011-07-08 11:31:57 -0700369
Damien Lespiau5adaea72013-08-06 20:32:19 +0100370 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
371 adjusted_mode);
372 if (ret < 0) {
373 DRM_ERROR("couldn't fill AVI infoframe\n");
374 return;
375 }
Paulo Zanonic846b612012-04-13 16:31:41 -0300376
Ville Syrjäläabedc072013-01-17 16:31:31 +0200377 if (intel_hdmi->rgb_quant_range_selectable) {
Daniel Vetter50f3b012013-03-27 00:44:56 +0100378 if (intel_crtc->config.limited_color_range)
Damien Lespiau5adaea72013-08-06 20:32:19 +0100379 frame.avi.quantization_range =
380 HDMI_QUANTIZATION_RANGE_LIMITED;
Ville Syrjäläabedc072013-01-17 16:31:31 +0200381 else
Damien Lespiau5adaea72013-08-06 20:32:19 +0100382 frame.avi.quantization_range =
383 HDMI_QUANTIZATION_RANGE_FULL;
Ville Syrjäläabedc072013-01-17 16:31:31 +0200384 }
385
Damien Lespiau9198ee52013-08-06 20:32:24 +0100386 intel_write_infoframe(encoder, &frame);
Jesse Barnesb055c8f2011-07-08 11:31:57 -0700387}
388
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300389static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
Jesse Barnesc0864cb2011-08-03 09:22:56 -0700390{
Damien Lespiau5adaea72013-08-06 20:32:19 +0100391 union hdmi_infoframe frame;
392 int ret;
Jesse Barnesc0864cb2011-08-03 09:22:56 -0700393
Damien Lespiau5adaea72013-08-06 20:32:19 +0100394 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
395 if (ret < 0) {
396 DRM_ERROR("couldn't fill SPD infoframe\n");
397 return;
398 }
Jesse Barnesc0864cb2011-08-03 09:22:56 -0700399
Damien Lespiau5adaea72013-08-06 20:32:19 +0100400 frame.spd.sdi = HDMI_SPD_SDI_PC;
401
Damien Lespiau9198ee52013-08-06 20:32:24 +0100402 intel_write_infoframe(encoder, &frame);
Jesse Barnesc0864cb2011-08-03 09:22:56 -0700403}
404
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100405static void
406intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
407 struct drm_display_mode *adjusted_mode)
408{
409 union hdmi_infoframe frame;
410 int ret;
411
412 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
413 adjusted_mode);
414 if (ret < 0)
415 return;
416
417 intel_write_infoframe(encoder, &frame);
418}
419
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300420static void g4x_set_infoframes(struct drm_encoder *encoder,
421 struct drm_display_mode *adjusted_mode)
422{
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300423 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
Ville Syrjälä69fde0a2013-01-24 15:29:26 +0200424 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
425 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300426 u32 reg = VIDEO_DIP_CTL;
427 u32 val = I915_READ(reg);
Ville Syrjälä822cdc52014-01-23 23:15:34 +0200428 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300429
Daniel Vetterafba0182012-06-12 16:36:45 +0200430 assert_hdmi_port_disabled(intel_hdmi);
431
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300432 /* If the registers were not initialized yet, they might be zeroes,
433 * which means we're selecting the AVI DIP and we're setting its
434 * frequency to once. This seems to really confuse the HW and make
435 * things stop working (the register spec says the AVI always needs to
436 * be sent every VSync). So here we avoid writing to the register more
437 * than we need and also explicitly select the AVI DIP and explicitly
438 * set its frequency to every VSync. Avoiding to write it twice seems to
439 * be enough to solve the problem, but being defensive shouldn't hurt us
440 * either. */
441 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
442
443 if (!intel_hdmi->has_hdmi_sink) {
444 if (!(val & VIDEO_DIP_ENABLE))
445 return;
446 val &= ~VIDEO_DIP_ENABLE;
447 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300448 POSTING_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300449 return;
450 }
451
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300452 if (port != (val & VIDEO_DIP_PORT_MASK)) {
453 if (val & VIDEO_DIP_ENABLE) {
454 val &= ~VIDEO_DIP_ENABLE;
455 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300456 POSTING_READ(reg);
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300457 }
458 val &= ~VIDEO_DIP_PORT_MASK;
459 val |= port;
460 }
461
Paulo Zanoni822974a2012-05-28 16:42:51 -0300462 val |= VIDEO_DIP_ENABLE;
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300463 val &= ~VIDEO_DIP_ENABLE_VENDOR;
Paulo Zanoni822974a2012-05-28 16:42:51 -0300464
Paulo Zanonif278d972012-05-28 16:42:50 -0300465 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300466 POSTING_READ(reg);
Paulo Zanonif278d972012-05-28 16:42:50 -0300467
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300468 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
469 intel_hdmi_set_spd_infoframe(encoder);
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100470 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300471}
472
473static void ibx_set_infoframes(struct drm_encoder *encoder,
474 struct drm_display_mode *adjusted_mode)
475{
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300476 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
477 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Ville Syrjälä69fde0a2013-01-24 15:29:26 +0200478 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
479 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300480 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
481 u32 val = I915_READ(reg);
Ville Syrjälä822cdc52014-01-23 23:15:34 +0200482 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300483
Daniel Vetterafba0182012-06-12 16:36:45 +0200484 assert_hdmi_port_disabled(intel_hdmi);
485
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300486 /* See the big comment in g4x_set_infoframes() */
487 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
488
489 if (!intel_hdmi->has_hdmi_sink) {
490 if (!(val & VIDEO_DIP_ENABLE))
491 return;
492 val &= ~VIDEO_DIP_ENABLE;
493 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300494 POSTING_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300495 return;
496 }
497
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300498 if (port != (val & VIDEO_DIP_PORT_MASK)) {
499 if (val & VIDEO_DIP_ENABLE) {
500 val &= ~VIDEO_DIP_ENABLE;
501 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300502 POSTING_READ(reg);
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300503 }
504 val &= ~VIDEO_DIP_PORT_MASK;
505 val |= port;
506 }
507
Paulo Zanoni822974a2012-05-28 16:42:51 -0300508 val |= VIDEO_DIP_ENABLE;
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300509 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
510 VIDEO_DIP_ENABLE_GCP);
Paulo Zanoni822974a2012-05-28 16:42:51 -0300511
Paulo Zanonif278d972012-05-28 16:42:50 -0300512 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300513 POSTING_READ(reg);
Paulo Zanonif278d972012-05-28 16:42:50 -0300514
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300515 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
516 intel_hdmi_set_spd_infoframe(encoder);
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100517 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300518}
519
520static void cpt_set_infoframes(struct drm_encoder *encoder,
521 struct drm_display_mode *adjusted_mode)
522{
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300523 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
524 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
525 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
526 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
527 u32 val = I915_READ(reg);
528
Daniel Vetterafba0182012-06-12 16:36:45 +0200529 assert_hdmi_port_disabled(intel_hdmi);
530
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300531 /* See the big comment in g4x_set_infoframes() */
532 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
533
534 if (!intel_hdmi->has_hdmi_sink) {
535 if (!(val & VIDEO_DIP_ENABLE))
536 return;
537 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
538 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300539 POSTING_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300540 return;
541 }
542
Paulo Zanoni822974a2012-05-28 16:42:51 -0300543 /* Set both together, unset both together: see the spec. */
544 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300545 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
546 VIDEO_DIP_ENABLE_GCP);
Paulo Zanoni822974a2012-05-28 16:42:51 -0300547
548 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300549 POSTING_READ(reg);
Paulo Zanoni822974a2012-05-28 16:42:51 -0300550
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300551 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
552 intel_hdmi_set_spd_infoframe(encoder);
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100553 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300554}
555
556static void vlv_set_infoframes(struct drm_encoder *encoder,
557 struct drm_display_mode *adjusted_mode)
558{
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300559 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
560 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
561 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
562 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
563 u32 val = I915_READ(reg);
564
Daniel Vetterafba0182012-06-12 16:36:45 +0200565 assert_hdmi_port_disabled(intel_hdmi);
566
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300567 /* See the big comment in g4x_set_infoframes() */
568 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
569
570 if (!intel_hdmi->has_hdmi_sink) {
571 if (!(val & VIDEO_DIP_ENABLE))
572 return;
573 val &= ~VIDEO_DIP_ENABLE;
574 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300575 POSTING_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300576 return;
577 }
578
Paulo Zanoni822974a2012-05-28 16:42:51 -0300579 val |= VIDEO_DIP_ENABLE;
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300580 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
581 VIDEO_DIP_ENABLE_GCP);
Paulo Zanoni822974a2012-05-28 16:42:51 -0300582
583 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300584 POSTING_READ(reg);
Paulo Zanoni822974a2012-05-28 16:42:51 -0300585
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300586 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
587 intel_hdmi_set_spd_infoframe(encoder);
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100588 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300589}
590
591static void hsw_set_infoframes(struct drm_encoder *encoder,
592 struct drm_display_mode *adjusted_mode)
593{
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300594 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
595 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
596 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
Daniel Vetter3b117c82013-04-17 20:15:07 +0200597 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300598 u32 val = I915_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300599
Daniel Vetterafba0182012-06-12 16:36:45 +0200600 assert_hdmi_port_disabled(intel_hdmi);
601
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300602 if (!intel_hdmi->has_hdmi_sink) {
603 I915_WRITE(reg, 0);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300604 POSTING_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300605 return;
606 }
607
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300608 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
609 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
610
611 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300612 POSTING_READ(reg);
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300613
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300614 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
615 intel_hdmi_set_spd_infoframe(encoder);
Lespiau, Damienc8bb75a2013-08-19 16:59:04 +0100616 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300617}
618
Daniel Vetterc59423a2013-07-21 21:37:04 +0200619static void intel_hdmi_mode_set(struct intel_encoder *encoder)
Eric Anholt7d573822009-01-02 13:33:00 -0800620{
Daniel Vetterc59423a2013-07-21 21:37:04 +0200621 struct drm_device *dev = encoder->base.dev;
Eric Anholt7d573822009-01-02 13:33:00 -0800622 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterc59423a2013-07-21 21:37:04 +0200623 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
624 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
625 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300626 u32 hdmi_val;
Eric Anholt7d573822009-01-02 13:33:00 -0800627
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300628 hdmi_val = SDVO_ENCODING_HDMI;
Ville Syrjälä2af2c492013-06-25 14:16:34 +0300629 if (!HAS_PCH_SPLIT(dev))
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300630 hdmi_val |= intel_hdmi->color_range;
Adam Jacksonb599c0b2010-07-16 14:46:31 -0400631 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300632 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
Adam Jacksonb599c0b2010-07-16 14:46:31 -0400633 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300634 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
Eric Anholt7d573822009-01-02 13:33:00 -0800635
Daniel Vetterc59423a2013-07-21 21:37:04 +0200636 if (crtc->config.pipe_bpp > 24)
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -0300637 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
Jesse Barnes020f6702011-06-24 12:19:25 -0700638 else
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -0300639 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
Jesse Barnes020f6702011-06-24 12:19:25 -0700640
Zhenyu Wang2e3d6002010-09-10 10:39:40 +0800641 /* Required on CPT */
642 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
Paulo Zanonidc0fa712013-02-19 16:21:46 -0300643 hdmi_val |= HDMI_MODE_SELECT_HDMI;
Zhenyu Wang2e3d6002010-09-10 10:39:40 +0800644
David Härdeman3c17fe42010-09-24 21:44:32 +0200645 if (intel_hdmi->has_audio) {
Wu Fengguange0dac652011-09-05 14:25:34 +0800646 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
Daniel Vetterc59423a2013-07-21 21:37:04 +0200647 pipe_name(crtc->pipe));
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300648 hdmi_val |= SDVO_AUDIO_ENABLE;
Paulo Zanonidc0fa712013-02-19 16:21:46 -0300649 hdmi_val |= HDMI_MODE_SELECT_HDMI;
Daniel Vetterc59423a2013-07-21 21:37:04 +0200650 intel_write_eld(&encoder->base, adjusted_mode);
David Härdeman3c17fe42010-09-24 21:44:32 +0200651 }
Eric Anholt7d573822009-01-02 13:33:00 -0800652
Jesse Barnes75770562011-10-12 09:01:58 -0700653 if (HAS_PCH_CPT(dev))
Daniel Vetterc59423a2013-07-21 21:37:04 +0200654 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
Paulo Zanonidc0fa712013-02-19 16:21:46 -0300655 else
Daniel Vetterc59423a2013-07-21 21:37:04 +0200656 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
Eric Anholt7d573822009-01-02 13:33:00 -0800657
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300658 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
659 POSTING_READ(intel_hdmi->hdmi_reg);
David Härdeman3c17fe42010-09-24 21:44:32 +0200660
Daniel Vetterc59423a2013-07-21 21:37:04 +0200661 intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
Eric Anholt7d573822009-01-02 13:33:00 -0800662}
663
Daniel Vetter85234cd2012-07-02 13:27:29 +0200664static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
665 enum pipe *pipe)
Eric Anholt7d573822009-01-02 13:33:00 -0800666{
Daniel Vetter85234cd2012-07-02 13:27:29 +0200667 struct drm_device *dev = encoder->base.dev;
Eric Anholt7d573822009-01-02 13:33:00 -0800668 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter85234cd2012-07-02 13:27:29 +0200669 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
Imre Deak6d129be2014-03-05 16:20:54 +0200670 enum intel_display_power_domain power_domain;
Daniel Vetter85234cd2012-07-02 13:27:29 +0200671 u32 tmp;
672
Imre Deak6d129be2014-03-05 16:20:54 +0200673 power_domain = intel_display_port_power_domain(encoder);
674 if (!intel_display_power_enabled(dev_priv, power_domain))
675 return false;
676
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300677 tmp = I915_READ(intel_hdmi->hdmi_reg);
Daniel Vetter85234cd2012-07-02 13:27:29 +0200678
679 if (!(tmp & SDVO_ENABLE))
680 return false;
681
682 if (HAS_PCH_CPT(dev))
683 *pipe = PORT_TO_PIPE_CPT(tmp);
684 else
685 *pipe = PORT_TO_PIPE(tmp);
686
687 return true;
688}
689
Jesse Barnes045ac3b2013-05-14 17:08:26 -0700690static void intel_hdmi_get_config(struct intel_encoder *encoder,
691 struct intel_crtc_config *pipe_config)
692{
693 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
694 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
695 u32 tmp, flags = 0;
Ville Syrjälä18442d02013-09-13 16:00:08 +0300696 int dotclock;
Jesse Barnes045ac3b2013-05-14 17:08:26 -0700697
698 tmp = I915_READ(intel_hdmi->hdmi_reg);
699
700 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
701 flags |= DRM_MODE_FLAG_PHSYNC;
702 else
703 flags |= DRM_MODE_FLAG_NHSYNC;
704
705 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
706 flags |= DRM_MODE_FLAG_PVSYNC;
707 else
708 flags |= DRM_MODE_FLAG_NVSYNC;
709
710 pipe_config->adjusted_mode.flags |= flags;
Ville Syrjälä18442d02013-09-13 16:00:08 +0300711
712 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
713 dotclock = pipe_config->port_clock * 2 / 3;
714 else
715 dotclock = pipe_config->port_clock;
716
717 if (HAS_PCH_SPLIT(dev_priv->dev))
718 ironlake_check_encoder_dotclock(pipe_config, dotclock);
719
Damien Lespiau241bfc32013-09-25 16:45:37 +0100720 pipe_config->adjusted_mode.crtc_clock = dotclock;
Jesse Barnes045ac3b2013-05-14 17:08:26 -0700721}
722
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200723static void intel_enable_hdmi(struct intel_encoder *encoder)
Eric Anholt7d573822009-01-02 13:33:00 -0800724{
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200725 struct drm_device *dev = encoder->base.dev;
Eric Anholt7d573822009-01-02 13:33:00 -0800726 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonidc0fa712013-02-19 16:21:46 -0300727 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200728 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
Eric Anholt7d573822009-01-02 13:33:00 -0800729 u32 temp;
Wu Fengguang2deed762011-12-09 20:42:20 +0800730 u32 enable_bits = SDVO_ENABLE;
731
732 if (intel_hdmi->has_audio)
733 enable_bits |= SDVO_AUDIO_ENABLE;
Eric Anholt7d573822009-01-02 13:33:00 -0800734
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300735 temp = I915_READ(intel_hdmi->hdmi_reg);
Zhenyu Wangd8a2d0e2009-11-02 07:52:30 +0000736
Daniel Vetter7a87c282012-06-05 11:03:39 +0200737 /* HW workaround for IBX, we need to move the port to transcoder A
Paulo Zanonidc0fa712013-02-19 16:21:46 -0300738 * before disabling it, so restore the transcoder select bit here. */
739 if (HAS_PCH_IBX(dev))
740 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
Daniel Vetter7a87c282012-06-05 11:03:39 +0200741
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200742 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
743 * we do this anyway which shows more stable in testing.
744 */
745 if (HAS_PCH_SPLIT(dev)) {
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300746 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
747 POSTING_READ(intel_hdmi->hdmi_reg);
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200748 }
Daniel Vetter7a87c282012-06-05 11:03:39 +0200749
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200750 temp |= enable_bits;
751
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300752 I915_WRITE(intel_hdmi->hdmi_reg, temp);
753 POSTING_READ(intel_hdmi->hdmi_reg);
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200754
755 /* HW workaround, need to write this twice for issue that may result
756 * in first write getting masked.
757 */
758 if (HAS_PCH_SPLIT(dev)) {
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300759 I915_WRITE(intel_hdmi->hdmi_reg, temp);
760 POSTING_READ(intel_hdmi->hdmi_reg);
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200761 }
Jani Nikulab76cf762013-07-30 12:20:31 +0300762}
Jesse Barnes89b667f2013-04-18 14:51:36 -0700763
Jani Nikulab76cf762013-07-30 12:20:31 +0300764static void vlv_enable_hdmi(struct intel_encoder *encoder)
765{
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200766}
767
768static void intel_disable_hdmi(struct intel_encoder *encoder)
769{
770 struct drm_device *dev = encoder->base.dev;
771 struct drm_i915_private *dev_priv = dev->dev_private;
772 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
773 u32 temp;
Wang Xingchao3cce5742012-09-13 11:19:00 +0800774 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200775
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300776 temp = I915_READ(intel_hdmi->hdmi_reg);
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200777
778 /* HW workaround for IBX, we need to move the port to transcoder A
779 * before disabling it. */
780 if (HAS_PCH_IBX(dev)) {
781 struct drm_crtc *crtc = encoder->base.crtc;
782 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
783
784 if (temp & SDVO_PIPE_B_SELECT) {
785 temp &= ~SDVO_PIPE_B_SELECT;
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300786 I915_WRITE(intel_hdmi->hdmi_reg, temp);
787 POSTING_READ(intel_hdmi->hdmi_reg);
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200788
789 /* Again we need to write this twice. */
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300790 I915_WRITE(intel_hdmi->hdmi_reg, temp);
791 POSTING_READ(intel_hdmi->hdmi_reg);
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200792
793 /* Transcoder selection bits only update
794 * effectively on vblank. */
795 if (crtc)
796 intel_wait_for_vblank(dev, pipe);
797 else
798 msleep(50);
Daniel Vetter7a87c282012-06-05 11:03:39 +0200799 }
800 }
801
Zhenyu Wangd8a2d0e2009-11-02 07:52:30 +0000802 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
803 * we do this anyway which shows more stable in testing.
804 */
Eric Anholtc619eed2010-01-28 16:45:52 -0800805 if (HAS_PCH_SPLIT(dev)) {
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300806 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
807 POSTING_READ(intel_hdmi->hdmi_reg);
Eric Anholt7d573822009-01-02 13:33:00 -0800808 }
Zhenyu Wangd8a2d0e2009-11-02 07:52:30 +0000809
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200810 temp &= ~enable_bits;
Zhenyu Wangd8a2d0e2009-11-02 07:52:30 +0000811
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300812 I915_WRITE(intel_hdmi->hdmi_reg, temp);
813 POSTING_READ(intel_hdmi->hdmi_reg);
Zhenyu Wangd8a2d0e2009-11-02 07:52:30 +0000814
815 /* HW workaround, need to write this twice for issue that may result
816 * in first write getting masked.
817 */
Eric Anholtc619eed2010-01-28 16:45:52 -0800818 if (HAS_PCH_SPLIT(dev)) {
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300819 I915_WRITE(intel_hdmi->hdmi_reg, temp);
820 POSTING_READ(intel_hdmi->hdmi_reg);
Zhenyu Wangd8a2d0e2009-11-02 07:52:30 +0000821 }
Eric Anholt7d573822009-01-02 13:33:00 -0800822}
823
Daniel Vetter7d148ef2013-07-22 18:02:39 +0200824static int hdmi_portclock_limit(struct intel_hdmi *hdmi)
825{
826 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
827
Ville Syrjälä6375b762014-03-03 11:33:36 +0200828 if (!hdmi->has_hdmi_sink || IS_G4X(dev))
Daniel Vetter7d148ef2013-07-22 18:02:39 +0200829 return 165000;
Damien Lespiaue3c33572013-11-02 21:07:51 -0700830 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
Daniel Vetter7d148ef2013-07-22 18:02:39 +0200831 return 300000;
832 else
833 return 225000;
834}
835
Damien Lespiauc19de8e2013-11-28 15:29:18 +0000836static enum drm_mode_status
837intel_hdmi_mode_valid(struct drm_connector *connector,
838 struct drm_display_mode *mode)
Eric Anholt7d573822009-01-02 13:33:00 -0800839{
Daniel Vetter7d148ef2013-07-22 18:02:39 +0200840 if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector)))
Eric Anholt7d573822009-01-02 13:33:00 -0800841 return MODE_CLOCK_HIGH;
842 if (mode->clock < 20000)
Nicolas Kaiser5cbba412011-05-30 12:48:26 +0200843 return MODE_CLOCK_LOW;
Eric Anholt7d573822009-01-02 13:33:00 -0800844
845 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
846 return MODE_NO_DBLESCAN;
847
848 return MODE_OK;
849}
850
Ville Syrjälä71800632014-03-03 16:15:29 +0200851static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
852{
853 struct drm_device *dev = crtc->base.dev;
854 struct intel_encoder *encoder;
855 int count = 0, count_hdmi = 0;
856
857 if (!HAS_PCH_SPLIT(dev))
858 return false;
859
860 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
861 if (encoder->new_crtc != crtc)
862 continue;
863
864 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
865 count++;
866 }
867
868 /*
869 * HDMI 12bpc affects the clocks, so it's only possible
870 * when not cloning with other encoder types.
871 */
872 return count_hdmi > 0 && count_hdmi == count;
873}
874
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100875bool intel_hdmi_compute_config(struct intel_encoder *encoder,
876 struct intel_crtc_config *pipe_config)
Eric Anholt7d573822009-01-02 13:33:00 -0800877{
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100878 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
879 struct drm_device *dev = encoder->base.dev;
880 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Damien Lespiau241bfc32013-09-25 16:45:37 +0100881 int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
Daniel Vetter7d148ef2013-07-22 18:02:39 +0200882 int portclock_limit = hdmi_portclock_limit(intel_hdmi);
Daniel Vettere29c22c2013-02-21 00:00:16 +0100883 int desired_bpp;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200884
Ville Syrjälä55bc60d2013-01-17 16:31:29 +0200885 if (intel_hdmi->color_range_auto) {
886 /* See CEA-861-E - 5.1 Default Encoding Parameters */
887 if (intel_hdmi->has_hdmi_sink &&
Thierry Reding18316c82012-12-20 15:41:44 +0100888 drm_match_cea_mode(adjusted_mode) > 1)
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -0300889 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
Ville Syrjälä55bc60d2013-01-17 16:31:29 +0200890 else
891 intel_hdmi->color_range = 0;
892 }
893
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200894 if (intel_hdmi->color_range)
Daniel Vetter50f3b012013-03-27 00:44:56 +0100895 pipe_config->limited_color_range = true;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200896
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100897 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
898 pipe_config->has_pch_encoder = true;
899
Daniel Vetter4e53c2e2013-03-27 00:44:58 +0100900 /*
901 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
902 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
Daniel Vetter325b9d02013-04-19 11:24:33 +0200903 * outputs. We also need to check that the higher clock still fits
904 * within limits.
Daniel Vetter4e53c2e2013-03-27 00:44:58 +0100905 */
Ville Syrjälä6375b762014-03-03 11:33:36 +0200906 if (pipe_config->pipe_bpp > 8*3 && intel_hdmi->has_hdmi_sink &&
Ville Syrjälä71800632014-03-03 16:15:29 +0200907 clock_12bpc <= portclock_limit &&
908 hdmi_12bpc_possible(encoder->new_crtc)) {
Daniel Vettere29c22c2013-02-21 00:00:16 +0100909 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
910 desired_bpp = 12*3;
Daniel Vetter325b9d02013-04-19 11:24:33 +0200911
912 /* Need to adjust the port link by 1.5x for 12bpc. */
Daniel Vetterff9a6752013-06-01 17:16:21 +0200913 pipe_config->port_clock = clock_12bpc;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +0100914 } else {
Daniel Vettere29c22c2013-02-21 00:00:16 +0100915 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
916 desired_bpp = 8*3;
917 }
918
919 if (!pipe_config->bw_constrained) {
920 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
921 pipe_config->pipe_bpp = desired_bpp;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +0100922 }
923
Damien Lespiau241bfc32013-09-25 16:45:37 +0100924 if (adjusted_mode->crtc_clock > portclock_limit) {
Daniel Vetter325b9d02013-04-19 11:24:33 +0200925 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
926 return false;
927 }
928
Eric Anholt7d573822009-01-02 13:33:00 -0800929 return true;
930}
931
Keith Packardaa93d632009-05-05 09:52:46 -0700932static enum drm_connector_status
Chris Wilson930a9e22010-09-14 11:07:23 +0100933intel_hdmi_detect(struct drm_connector *connector, bool force)
Ma Ling9dff6af2009-04-02 13:13:26 +0800934{
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000935 struct drm_device *dev = connector->dev;
Chris Wilsondf0e9242010-09-09 16:20:55 +0100936 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
Paulo Zanonid63885d2012-10-26 19:05:49 -0200937 struct intel_digital_port *intel_dig_port =
938 hdmi_to_dig_port(intel_hdmi);
939 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000940 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonf899fc62010-07-20 15:44:45 -0700941 struct edid *edid;
Imre Deak671dedd2014-03-05 16:20:53 +0200942 enum intel_display_power_domain power_domain;
Keith Packardaa93d632009-05-05 09:52:46 -0700943 enum drm_connector_status status = connector_status_disconnected;
Ma Ling9dff6af2009-04-02 13:13:26 +0800944
Chris Wilson164c8592013-07-20 20:27:08 +0100945 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
946 connector->base.id, drm_get_connector_name(connector));
947
Imre Deak671dedd2014-03-05 16:20:53 +0200948 power_domain = intel_display_port_power_domain(intel_encoder);
949 intel_display_power_get(dev_priv, power_domain);
950
Chris Wilsonea5b2132010-08-04 13:50:23 +0100951 intel_hdmi->has_hdmi_sink = false;
Zhenyu Wang2e3d6002010-09-10 10:39:40 +0800952 intel_hdmi->has_audio = false;
Ville Syrjäläabedc072013-01-17 16:31:31 +0200953 intel_hdmi->rgb_quant_range_selectable = false;
Chris Wilsonf899fc62010-07-20 15:44:45 -0700954 edid = drm_get_edid(connector,
Daniel Kurtz3bd7d902012-03-28 02:36:14 +0800955 intel_gmbus_get_adapter(dev_priv,
956 intel_hdmi->ddc_bus));
ling.ma@intel.com2ded9e22009-07-16 17:23:09 +0800957
Keith Packardaa93d632009-05-05 09:52:46 -0700958 if (edid) {
Eric Anholtbe9f1c42009-06-21 22:14:55 -0700959 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
Keith Packardaa93d632009-05-05 09:52:46 -0700960 status = connector_status_connected;
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +0800961 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
962 intel_hdmi->has_hdmi_sink =
963 drm_detect_hdmi_monitor(edid);
Zhenyu Wang2e3d6002010-09-10 10:39:40 +0800964 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
Ville Syrjäläabedc072013-01-17 16:31:31 +0200965 intel_hdmi->rgb_quant_range_selectable =
966 drm_rgb_quant_range_selectable(edid);
Keith Packardaa93d632009-05-05 09:52:46 -0700967 }
Keith Packardaa93d632009-05-05 09:52:46 -0700968 kfree(edid);
Ma Ling9dff6af2009-04-02 13:13:26 +0800969 }
ling.ma@intel.com2ded9e22009-07-16 17:23:09 +0800970
Chris Wilson55b7d6e82010-09-19 09:29:33 +0100971 if (status == connector_status_connected) {
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +0800972 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
973 intel_hdmi->has_audio =
974 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
Paulo Zanonid63885d2012-10-26 19:05:49 -0200975 intel_encoder->type = INTEL_OUTPUT_HDMI;
Chris Wilson55b7d6e82010-09-19 09:29:33 +0100976 }
977
Imre Deak671dedd2014-03-05 16:20:53 +0200978 intel_display_power_put(dev_priv, power_domain);
979
Keith Packardaa93d632009-05-05 09:52:46 -0700980 return status;
Ma Ling9dff6af2009-04-02 13:13:26 +0800981}
982
Eric Anholt7d573822009-01-02 13:33:00 -0800983static int intel_hdmi_get_modes(struct drm_connector *connector)
984{
Imre Deak671dedd2014-03-05 16:20:53 +0200985 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
986 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
Chris Wilsonf899fc62010-07-20 15:44:45 -0700987 struct drm_i915_private *dev_priv = connector->dev->dev_private;
Imre Deak671dedd2014-03-05 16:20:53 +0200988 enum intel_display_power_domain power_domain;
989 int ret;
Eric Anholt7d573822009-01-02 13:33:00 -0800990
991 /* We should parse the EDID data and find out if it's an HDMI sink so
992 * we can send audio to it.
993 */
994
Imre Deak671dedd2014-03-05 16:20:53 +0200995 power_domain = intel_display_port_power_domain(intel_encoder);
996 intel_display_power_get(dev_priv, power_domain);
997
998 ret = intel_ddc_get_modes(connector,
Daniel Kurtz3bd7d902012-03-28 02:36:14 +0800999 intel_gmbus_get_adapter(dev_priv,
1000 intel_hdmi->ddc_bus));
Imre Deak671dedd2014-03-05 16:20:53 +02001001
1002 intel_display_power_put(dev_priv, power_domain);
1003
1004 return ret;
Eric Anholt7d573822009-01-02 13:33:00 -08001005}
1006
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001007static bool
1008intel_hdmi_detect_audio(struct drm_connector *connector)
1009{
Imre Deak671dedd2014-03-05 16:20:53 +02001010 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
1011 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001012 struct drm_i915_private *dev_priv = connector->dev->dev_private;
Imre Deak671dedd2014-03-05 16:20:53 +02001013 enum intel_display_power_domain power_domain;
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001014 struct edid *edid;
1015 bool has_audio = false;
1016
Imre Deak671dedd2014-03-05 16:20:53 +02001017 power_domain = intel_display_port_power_domain(intel_encoder);
1018 intel_display_power_get(dev_priv, power_domain);
1019
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001020 edid = drm_get_edid(connector,
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08001021 intel_gmbus_get_adapter(dev_priv,
1022 intel_hdmi->ddc_bus));
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001023 if (edid) {
1024 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1025 has_audio = drm_detect_monitor_audio(edid);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001026 kfree(edid);
1027 }
1028
Imre Deak671dedd2014-03-05 16:20:53 +02001029 intel_display_power_put(dev_priv, power_domain);
1030
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001031 return has_audio;
1032}
1033
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001034static int
1035intel_hdmi_set_property(struct drm_connector *connector,
Paulo Zanonied517fb2012-05-14 17:12:50 -03001036 struct drm_property *property,
1037 uint64_t val)
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001038{
1039 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001040 struct intel_digital_port *intel_dig_port =
1041 hdmi_to_dig_port(intel_hdmi);
Chris Wilsone953fd72011-02-21 22:23:52 +00001042 struct drm_i915_private *dev_priv = connector->dev->dev_private;
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001043 int ret;
1044
Rob Clark662595d2012-10-11 20:36:04 -05001045 ret = drm_object_property_set_value(&connector->base, property, val);
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001046 if (ret)
1047 return ret;
1048
Chris Wilson3f43c482011-05-12 22:17:24 +01001049 if (property == dev_priv->force_audio_property) {
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001050 enum hdmi_force_audio i = val;
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001051 bool has_audio;
1052
1053 if (i == intel_hdmi->force_audio)
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001054 return 0;
1055
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001056 intel_hdmi->force_audio = i;
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001057
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001058 if (i == HDMI_AUDIO_AUTO)
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001059 has_audio = intel_hdmi_detect_audio(connector);
1060 else
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001061 has_audio = (i == HDMI_AUDIO_ON);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001062
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001063 if (i == HDMI_AUDIO_OFF_DVI)
1064 intel_hdmi->has_hdmi_sink = 0;
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001065
Chris Wilson1aad7ac2011-02-09 18:46:58 +00001066 intel_hdmi->has_audio = has_audio;
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001067 goto done;
1068 }
1069
Chris Wilsone953fd72011-02-21 22:23:52 +00001070 if (property == dev_priv->broadcast_rgb_property) {
Daniel Vetterae4edb82013-04-22 17:07:23 +02001071 bool old_auto = intel_hdmi->color_range_auto;
1072 uint32_t old_range = intel_hdmi->color_range;
1073
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02001074 switch (val) {
1075 case INTEL_BROADCAST_RGB_AUTO:
1076 intel_hdmi->color_range_auto = true;
1077 break;
1078 case INTEL_BROADCAST_RGB_FULL:
1079 intel_hdmi->color_range_auto = false;
1080 intel_hdmi->color_range = 0;
1081 break;
1082 case INTEL_BROADCAST_RGB_LIMITED:
1083 intel_hdmi->color_range_auto = false;
Paulo Zanoni4f3a8bc2013-02-19 16:21:47 -03001084 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02001085 break;
1086 default:
1087 return -EINVAL;
1088 }
Daniel Vetterae4edb82013-04-22 17:07:23 +02001089
1090 if (old_auto == intel_hdmi->color_range_auto &&
1091 old_range == intel_hdmi->color_range)
1092 return 0;
1093
Chris Wilsone953fd72011-02-21 22:23:52 +00001094 goto done;
1095 }
1096
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001097 return -EINVAL;
1098
1099done:
Chris Wilsonc0c36b942012-12-19 16:08:43 +00001100 if (intel_dig_port->base.base.crtc)
1101 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001102
1103 return 0;
1104}
1105
Chon Ming Lee9514ac62013-10-16 17:07:41 +08001106static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001107{
1108 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1109 struct drm_device *dev = encoder->base.dev;
1110 struct drm_i915_private *dev_priv = dev->dev_private;
1111 struct intel_crtc *intel_crtc =
1112 to_intel_crtc(encoder->base.crtc);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001113 enum dpio_channel port = vlv_dport_to_channel(dport);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001114 int pipe = intel_crtc->pipe;
1115 u32 val;
1116
1117 if (!IS_VALLEYVIEW(dev))
1118 return;
1119
Jesse Barnes89b667f2013-04-18 14:51:36 -07001120 /* Enable clock channels for this port */
Chris Wilson0980a602013-07-26 19:57:35 +01001121 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001122 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
Jesse Barnes89b667f2013-04-18 14:51:36 -07001123 val = 0;
1124 if (pipe)
1125 val |= (1<<21);
1126 else
1127 val &= ~(1<<21);
1128 val |= 0x001000c4;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001129 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001130
1131 /* HDMI 1.0V-2dB */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001132 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1133 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1134 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1135 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1136 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1137 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1138 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1139 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001140
1141 /* Program lane clock */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001142 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1143 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
Chris Wilson0980a602013-07-26 19:57:35 +01001144 mutex_unlock(&dev_priv->dpio_lock);
Jani Nikulab76cf762013-07-30 12:20:31 +03001145
1146 intel_enable_hdmi(encoder);
1147
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001148 vlv_wait_port_ready(dev_priv, dport);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001149}
1150
Chon Ming Lee9514ac62013-10-16 17:07:41 +08001151static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001152{
1153 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1154 struct drm_device *dev = encoder->base.dev;
1155 struct drm_i915_private *dev_priv = dev->dev_private;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001156 struct intel_crtc *intel_crtc =
1157 to_intel_crtc(encoder->base.crtc);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001158 enum dpio_channel port = vlv_dport_to_channel(dport);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001159 int pipe = intel_crtc->pipe;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001160
1161 if (!IS_VALLEYVIEW(dev))
1162 return;
1163
Jesse Barnes89b667f2013-04-18 14:51:36 -07001164 /* Program Tx lane resets to default */
Chris Wilson0980a602013-07-26 19:57:35 +01001165 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001166 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
Jesse Barnes89b667f2013-04-18 14:51:36 -07001167 DPIO_PCS_TX_LANE2_RESET |
1168 DPIO_PCS_TX_LANE1_RESET);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001169 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
Jesse Barnes89b667f2013-04-18 14:51:36 -07001170 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1171 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1172 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1173 DPIO_PCS_CLK_SOFT_RESET);
1174
1175 /* Fix up inter-pair skew failure */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001176 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1177 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1178 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001179
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001180 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1181 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
Chris Wilson0980a602013-07-26 19:57:35 +01001182 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001183}
1184
Chon Ming Lee9514ac62013-10-16 17:07:41 +08001185static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001186{
1187 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1188 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001189 struct intel_crtc *intel_crtc =
1190 to_intel_crtc(encoder->base.crtc);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001191 enum dpio_channel port = vlv_dport_to_channel(dport);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001192 int pipe = intel_crtc->pipe;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001193
1194 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1195 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001196 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1197 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001198 mutex_unlock(&dev_priv->dpio_lock);
1199}
1200
Eric Anholt7d573822009-01-02 13:33:00 -08001201static void intel_hdmi_destroy(struct drm_connector *connector)
1202{
Eric Anholt7d573822009-01-02 13:33:00 -08001203 drm_connector_cleanup(connector);
Zhenyu Wang674e2d02010-03-29 15:57:42 +08001204 kfree(connector);
Eric Anholt7d573822009-01-02 13:33:00 -08001205}
1206
Eric Anholt7d573822009-01-02 13:33:00 -08001207static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
Daniel Vetter5ab432e2012-06-30 08:59:56 +02001208 .dpms = intel_connector_dpms,
Eric Anholt7d573822009-01-02 13:33:00 -08001209 .detect = intel_hdmi_detect,
1210 .fill_modes = drm_helper_probe_single_connector_modes,
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001211 .set_property = intel_hdmi_set_property,
Eric Anholt7d573822009-01-02 13:33:00 -08001212 .destroy = intel_hdmi_destroy,
1213};
1214
1215static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1216 .get_modes = intel_hdmi_get_modes,
1217 .mode_valid = intel_hdmi_mode_valid,
Chris Wilsondf0e9242010-09-09 16:20:55 +01001218 .best_encoder = intel_best_encoder,
Eric Anholt7d573822009-01-02 13:33:00 -08001219};
1220
Eric Anholt7d573822009-01-02 13:33:00 -08001221static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
Chris Wilsonea5b2132010-08-04 13:50:23 +01001222 .destroy = intel_encoder_destroy,
Eric Anholt7d573822009-01-02 13:33:00 -08001223};
1224
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001225static void
1226intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1227{
Chris Wilson3f43c482011-05-12 22:17:24 +01001228 intel_attach_force_audio_property(connector);
Chris Wilsone953fd72011-02-21 22:23:52 +00001229 intel_attach_broadcast_rgb_property(connector);
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02001230 intel_hdmi->color_range_auto = true;
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001231}
1232
Paulo Zanoni00c09d72012-10-26 19:05:52 -02001233void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1234 struct intel_connector *intel_connector)
Eric Anholt7d573822009-01-02 13:33:00 -08001235{
Paulo Zanonib9cb2342012-10-26 19:05:47 -02001236 struct drm_connector *connector = &intel_connector->base;
1237 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1238 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1239 struct drm_device *dev = intel_encoder->base.dev;
Eric Anholt7d573822009-01-02 13:33:00 -08001240 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni174edf12012-10-26 19:05:50 -02001241 enum port port = intel_dig_port->port;
Eric Anholt7d573822009-01-02 13:33:00 -08001242
Eric Anholt7d573822009-01-02 13:33:00 -08001243 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
Adam Jackson8d911042009-09-23 15:08:29 -04001244 DRM_MODE_CONNECTOR_HDMIA);
Eric Anholt7d573822009-01-02 13:33:00 -08001245 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1246
Peter Rossc3febcc2012-01-28 14:49:26 +01001247 connector->interlace_allowed = 1;
Eric Anholt7d573822009-01-02 13:33:00 -08001248 connector->doublescan_allowed = 0;
Damien Lespiau573e74a2013-09-25 16:45:40 +01001249 connector->stereo_allowed = 1;
Eric Anholt7d573822009-01-02 13:33:00 -08001250
Daniel Vetter08d644a2012-07-12 20:19:59 +02001251 switch (port) {
1252 case PORT_B:
Chris Wilsonf899fc62010-07-20 15:44:45 -07001253 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
Egbert Eich1d843f92013-02-25 12:06:49 -05001254 intel_encoder->hpd_pin = HPD_PORT_B;
Daniel Vetter08d644a2012-07-12 20:19:59 +02001255 break;
1256 case PORT_C:
Chris Wilsonf899fc62010-07-20 15:44:45 -07001257 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
Egbert Eich1d843f92013-02-25 12:06:49 -05001258 intel_encoder->hpd_pin = HPD_PORT_C;
Daniel Vetter08d644a2012-07-12 20:19:59 +02001259 break;
1260 case PORT_D:
Chris Wilsonf899fc62010-07-20 15:44:45 -07001261 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
Egbert Eich1d843f92013-02-25 12:06:49 -05001262 intel_encoder->hpd_pin = HPD_PORT_D;
Daniel Vetter08d644a2012-07-12 20:19:59 +02001263 break;
1264 case PORT_A:
Egbert Eich1d843f92013-02-25 12:06:49 -05001265 intel_encoder->hpd_pin = HPD_PORT_A;
Daniel Vetter08d644a2012-07-12 20:19:59 +02001266 /* Internal port only for eDP. */
1267 default:
Eugeni Dodonov6e4c1672012-05-09 15:37:13 -03001268 BUG();
Ma Lingf8aed702009-08-24 13:50:24 +08001269 }
Eric Anholt7d573822009-01-02 13:33:00 -08001270
Jesse Barnes7637bfd2013-03-08 10:46:01 -08001271 if (IS_VALLEYVIEW(dev)) {
Shobhit Kumar90b107c2012-03-28 13:39:32 -07001272 intel_hdmi->write_infoframe = vlv_write_infoframe;
Paulo Zanoni687f4d02012-05-28 16:42:48 -03001273 intel_hdmi->set_infoframes = vlv_set_infoframes;
Jesse Barnes7637bfd2013-03-08 10:46:01 -08001274 } else if (!HAS_PCH_SPLIT(dev)) {
1275 intel_hdmi->write_infoframe = g4x_write_infoframe;
1276 intel_hdmi->set_infoframes = g4x_set_infoframes;
Paulo Zanoni22b8bf12013-02-18 19:00:23 -03001277 } else if (HAS_DDI(dev)) {
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -03001278 intel_hdmi->write_infoframe = hsw_write_infoframe;
Paulo Zanoni687f4d02012-05-28 16:42:48 -03001279 intel_hdmi->set_infoframes = hsw_set_infoframes;
Paulo Zanonifdf12502012-05-04 17:18:24 -03001280 } else if (HAS_PCH_IBX(dev)) {
1281 intel_hdmi->write_infoframe = ibx_write_infoframe;
Paulo Zanoni687f4d02012-05-28 16:42:48 -03001282 intel_hdmi->set_infoframes = ibx_set_infoframes;
Paulo Zanonifdf12502012-05-04 17:18:24 -03001283 } else {
1284 intel_hdmi->write_infoframe = cpt_write_infoframe;
Paulo Zanoni687f4d02012-05-28 16:42:48 -03001285 intel_hdmi->set_infoframes = cpt_set_infoframes;
Jesse Barnes64a8fc02011-09-22 11:16:00 +05301286 }
Jesse Barnes45187ac2011-08-03 09:22:55 -07001287
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001288 if (HAS_DDI(dev))
Paulo Zanonibcbc8892012-10-26 19:05:51 -02001289 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1290 else
1291 intel_connector->get_hw_state = intel_connector_get_hw_state;
Imre Deak4932e2c2014-02-11 17:12:48 +02001292 intel_connector->unregister = intel_connector_unregister;
Paulo Zanonib9cb2342012-10-26 19:05:47 -02001293
1294 intel_hdmi_add_properties(intel_hdmi, connector);
1295
1296 intel_connector_attach_encoder(intel_connector, intel_encoder);
1297 drm_sysfs_connector_add(connector);
1298
1299 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1300 * 0xd. Failure to do so will result in spurious interrupts being
1301 * generated on the port when a cable is not attached.
1302 */
1303 if (IS_G4X(dev) && !IS_GM45(dev)) {
1304 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1305 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1306 }
1307}
1308
Paulo Zanonib242b7f2013-02-18 19:00:26 -03001309void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
Paulo Zanonib9cb2342012-10-26 19:05:47 -02001310{
1311 struct intel_digital_port *intel_dig_port;
1312 struct intel_encoder *intel_encoder;
Paulo Zanonib9cb2342012-10-26 19:05:47 -02001313 struct intel_connector *intel_connector;
1314
Daniel Vetterb14c5672013-09-19 12:18:32 +02001315 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
Paulo Zanonib9cb2342012-10-26 19:05:47 -02001316 if (!intel_dig_port)
1317 return;
1318
Daniel Vetterb14c5672013-09-19 12:18:32 +02001319 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
Paulo Zanonib9cb2342012-10-26 19:05:47 -02001320 if (!intel_connector) {
1321 kfree(intel_dig_port);
1322 return;
1323 }
1324
1325 intel_encoder = &intel_dig_port->base;
Paulo Zanonib9cb2342012-10-26 19:05:47 -02001326
1327 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1328 DRM_MODE_ENCODER_TMDS);
Paulo Zanoni00c09d72012-10-26 19:05:52 -02001329
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01001330 intel_encoder->compute_config = intel_hdmi_compute_config;
Daniel Vetterc59423a2013-07-21 21:37:04 +02001331 intel_encoder->mode_set = intel_hdmi_mode_set;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02001332 intel_encoder->disable = intel_disable_hdmi;
1333 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001334 intel_encoder->get_config = intel_hdmi_get_config;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001335 if (IS_VALLEYVIEW(dev)) {
Chon Ming Lee9514ac62013-10-16 17:07:41 +08001336 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1337 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
Jani Nikulab76cf762013-07-30 12:20:31 +03001338 intel_encoder->enable = vlv_enable_hdmi;
Chon Ming Lee9514ac62013-10-16 17:07:41 +08001339 intel_encoder->post_disable = vlv_hdmi_post_disable;
Jani Nikulab76cf762013-07-30 12:20:31 +03001340 } else {
1341 intel_encoder->enable = intel_enable_hdmi;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001342 }
Daniel Vetter5ab432e2012-06-30 08:59:56 +02001343
Paulo Zanonib9cb2342012-10-26 19:05:47 -02001344 intel_encoder->type = INTEL_OUTPUT_HDMI;
1345 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
Ville Syrjälä301ea742014-03-03 16:15:30 +02001346 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
Ville Syrjäläc6f14952014-03-03 16:15:31 +02001347 /*
1348 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1349 * to work on real hardware. And since g4x can send infoframes to
1350 * only one port anyway, nothing is lost by allowing it.
1351 */
1352 if (IS_G4X(dev))
1353 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
Eric Anholt7d573822009-01-02 13:33:00 -08001354
Paulo Zanoni174edf12012-10-26 19:05:50 -02001355 intel_dig_port->port = port;
Paulo Zanonib242b7f2013-02-18 19:00:26 -03001356 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
Paulo Zanonib9cb2342012-10-26 19:05:47 -02001357 intel_dig_port->dp.output_reg = 0;
Chris Wilson55b7d6e82010-09-19 09:29:33 +01001358
Paulo Zanonib9cb2342012-10-26 19:05:47 -02001359 intel_hdmi_init_connector(intel_dig_port, intel_connector);
Eric Anholt7d573822009-01-02 13:33:00 -08001360}