Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1 | /* |
| 2 | * sata_mv.c - Marvell SATA support |
| 3 | * |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 4 | * Copyright 2008: Marvell Corporation, all rights reserved. |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 5 | * Copyright 2005: EMC Corporation, all rights reserved. |
Jeff Garzik | e2b1be5 | 2005-11-18 14:04:23 -0500 | [diff] [blame] | 6 | * Copyright 2005 Red Hat, Inc. All rights reserved. |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 7 | * |
| 8 | * Please ALWAYS copy linux-ide@vger.kernel.org on emails. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | */ |
| 24 | |
Jeff Garzik | 4a05e20 | 2007-05-24 23:40:15 -0400 | [diff] [blame] | 25 | /* |
Mark Lord | 85afb93 | 2008-04-19 14:54:41 -0400 | [diff] [blame] | 26 | * sata_mv TODO list: |
| 27 | * |
| 28 | * --> Errata workaround for NCQ device errors. |
| 29 | * |
| 30 | * --> More errata workarounds for PCI-X. |
| 31 | * |
| 32 | * --> Complete a full errata audit for all chipsets to identify others. |
| 33 | * |
| 34 | * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it). |
| 35 | * |
| 36 | * --> Investigate problems with PCI Message Signalled Interrupts (MSI). |
| 37 | * |
| 38 | * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead. |
| 39 | * |
| 40 | * --> Develop a low-power-consumption strategy, and implement it. |
| 41 | * |
| 42 | * --> [Experiment, low priority] Investigate interrupt coalescing. |
| 43 | * Quite often, especially with PCI Message Signalled Interrupts (MSI), |
| 44 | * the overhead reduced by interrupt mitigation is quite often not |
| 45 | * worth the latency cost. |
| 46 | * |
| 47 | * --> [Experiment, Marvell value added] Is it possible to use target |
| 48 | * mode to cross-connect two Linux boxes with Marvell cards? If so, |
| 49 | * creating LibATA target mode support would be very interesting. |
| 50 | * |
| 51 | * Target mode, for those without docs, is the ability to directly |
| 52 | * connect two SATA ports. |
| 53 | */ |
Jeff Garzik | 4a05e20 | 2007-05-24 23:40:15 -0400 | [diff] [blame] | 54 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 55 | #include <linux/kernel.h> |
| 56 | #include <linux/module.h> |
| 57 | #include <linux/pci.h> |
| 58 | #include <linux/init.h> |
| 59 | #include <linux/blkdev.h> |
| 60 | #include <linux/delay.h> |
| 61 | #include <linux/interrupt.h> |
Andrew Morton | 8d8b600 | 2008-02-04 23:43:44 -0800 | [diff] [blame] | 62 | #include <linux/dmapool.h> |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 63 | #include <linux/dma-mapping.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 64 | #include <linux/device.h> |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 65 | #include <linux/platform_device.h> |
| 66 | #include <linux/ata_platform.h> |
Lennert Buytenhek | 15a3263 | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 67 | #include <linux/mbus.h> |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 68 | #include <scsi/scsi_host.h> |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 69 | #include <scsi/scsi_cmnd.h> |
Jeff Garzik | 6c08772 | 2007-10-12 00:16:23 -0400 | [diff] [blame] | 70 | #include <scsi/scsi_device.h> |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 71 | #include <linux/libata.h> |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 72 | |
| 73 | #define DRV_NAME "sata_mv" |
Mark Lord | 1fd2e1c | 2008-01-26 18:33:59 -0500 | [diff] [blame] | 74 | #define DRV_VERSION "1.20" |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 75 | |
| 76 | enum { |
| 77 | /* BAR's are enumerated in terms of pci_resource_start() terms */ |
| 78 | MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ |
| 79 | MV_IO_BAR = 2, /* offset 0x18: IO space */ |
| 80 | MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ |
| 81 | |
| 82 | MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ |
| 83 | MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ |
| 84 | |
| 85 | MV_PCI_REG_BASE = 0, |
| 86 | MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ |
Mark Lord | 615ab95 | 2006-05-19 16:24:56 -0400 | [diff] [blame] | 87 | MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), |
| 88 | MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), |
| 89 | MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), |
| 90 | MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), |
| 91 | MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), |
| 92 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 93 | MV_SATAHC0_REG_BASE = 0x20000, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 94 | MV_FLASH_CTL = 0x1046c, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 95 | MV_GPIO_PORT_CTL = 0x104f0, |
| 96 | MV_RESET_CFG = 0x180d8, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 97 | |
| 98 | MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, |
| 99 | MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, |
| 100 | MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ |
| 101 | MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, |
| 102 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 103 | MV_MAX_Q_DEPTH = 32, |
| 104 | MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, |
| 105 | |
| 106 | /* CRQB needs alignment on a 1KB boundary. Size == 1KB |
| 107 | * CRPB needs alignment on a 256B boundary. Size == 256B |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 108 | * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B |
| 109 | */ |
| 110 | MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), |
| 111 | MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 112 | MV_MAX_SG_CT = 256, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 113 | MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 114 | |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 115 | /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 116 | MV_PORT_HC_SHIFT = 2, |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 117 | MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ |
| 118 | /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ |
| 119 | MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 120 | |
| 121 | /* Host Flags */ |
| 122 | MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ |
| 123 | MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 124 | /* SoC integrated controllers, no PCI interface */ |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 125 | MV_FLAG_SOC = (1 << 28), |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 126 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 127 | MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 128 | ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | |
| 129 | ATA_FLAG_PIO_POLLING, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 130 | MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 131 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 132 | CRQB_FLAG_READ = (1 << 0), |
| 133 | CRQB_TAG_SHIFT = 1, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 134 | CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 135 | CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 136 | CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 137 | CRQB_CMD_ADDR_SHIFT = 8, |
| 138 | CRQB_CMD_CS = (0x2 << 11), |
| 139 | CRQB_CMD_LAST = (1 << 15), |
| 140 | |
| 141 | CRPB_FLAG_STATUS_SHIFT = 8, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 142 | CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ |
| 143 | CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 144 | |
| 145 | EPRD_FLAG_END_OF_TBL = (1 << 31), |
| 146 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 147 | /* PCI interface registers */ |
| 148 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 149 | PCI_COMMAND_OFS = 0xc00, |
| 150 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 151 | PCI_MAIN_CMD_STS_OFS = 0xd30, |
| 152 | STOP_PCI_MASTER = (1 << 2), |
| 153 | PCI_MASTER_EMPTY = (1 << 3), |
| 154 | GLOB_SFT_RST = (1 << 4), |
| 155 | |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 156 | MV_PCI_MODE = 0xd00, |
| 157 | MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, |
| 158 | MV_PCI_DISC_TIMER = 0xd04, |
| 159 | MV_PCI_MSI_TRIGGER = 0xc38, |
| 160 | MV_PCI_SERR_MASK = 0xc28, |
| 161 | MV_PCI_XBAR_TMOUT = 0x1d04, |
| 162 | MV_PCI_ERR_LOW_ADDRESS = 0x1d40, |
| 163 | MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, |
| 164 | MV_PCI_ERR_ATTRIBUTE = 0x1d48, |
| 165 | MV_PCI_ERR_COMMAND = 0x1d50, |
| 166 | |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 167 | PCI_IRQ_CAUSE_OFS = 0x1d58, |
| 168 | PCI_IRQ_MASK_OFS = 0x1d5c, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 169 | PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ |
| 170 | |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 171 | PCIE_IRQ_CAUSE_OFS = 0x1900, |
| 172 | PCIE_IRQ_MASK_OFS = 0x1910, |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 173 | PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 174 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 175 | HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, |
| 176 | HC_MAIN_IRQ_MASK_OFS = 0x1d64, |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 177 | HC_SOC_MAIN_IRQ_CAUSE_OFS = 0x20020, |
| 178 | HC_SOC_MAIN_IRQ_MASK_OFS = 0x20024, |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 179 | ERR_IRQ = (1 << 0), /* shift by port # */ |
| 180 | DONE_IRQ = (1 << 1), /* shift by port # */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 181 | HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ |
| 182 | HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ |
| 183 | PCI_ERR = (1 << 18), |
| 184 | TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ |
| 185 | TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ |
Jeff Garzik | fb621e2 | 2007-02-25 04:19:45 -0500 | [diff] [blame] | 186 | PORTS_0_3_COAL_DONE = (1 << 8), |
| 187 | PORTS_4_7_COAL_DONE = (1 << 17), |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 188 | PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ |
| 189 | GPIO_INT = (1 << 22), |
| 190 | SELF_INT = (1 << 23), |
| 191 | TWSI_INT = (1 << 24), |
| 192 | HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ |
Jeff Garzik | fb621e2 | 2007-02-25 04:19:45 -0500 | [diff] [blame] | 193 | HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 194 | HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 195 | HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | |
Mark Lord | f9f7fe0 | 2008-04-19 14:44:42 -0400 | [diff] [blame] | 196 | PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 197 | PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | |
| 198 | HC_MAIN_RSVD), |
Jeff Garzik | fb621e2 | 2007-02-25 04:19:45 -0500 | [diff] [blame] | 199 | HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | |
| 200 | HC_MAIN_RSVD_5), |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 201 | HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC), |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 202 | |
| 203 | /* SATAHC registers */ |
| 204 | HC_CFG_OFS = 0, |
| 205 | |
| 206 | HC_IRQ_CAUSE_OFS = 0x14, |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 207 | DMA_IRQ = (1 << 0), /* shift by port # */ |
| 208 | HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 209 | DEV_IRQ = (1 << 8), /* shift by port # */ |
| 210 | |
| 211 | /* Shadow block registers */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 212 | SHD_BLK_OFS = 0x100, |
| 213 | SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 214 | |
| 215 | /* SATA registers */ |
| 216 | SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ |
| 217 | SATA_ACTIVE_OFS = 0x350, |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 218 | SATA_FIS_IRQ_CAUSE_OFS = 0x364, |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 219 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 220 | LTMODE_OFS = 0x30c, |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 221 | LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ |
| 222 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 223 | PHY_MODE3 = 0x310, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 224 | PHY_MODE4 = 0x314, |
| 225 | PHY_MODE2 = 0x330, |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 226 | SATA_IFCTL_OFS = 0x344, |
| 227 | SATA_IFSTAT_OFS = 0x34c, |
| 228 | VENDOR_UNIQUE_FIS_OFS = 0x35c, |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 229 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 230 | FIS_CFG_OFS = 0x360, |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 231 | FIS_CFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ |
| 232 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 233 | MV5_PHY_MODE = 0x74, |
| 234 | MV5_LT_MODE = 0x30, |
| 235 | MV5_PHY_CTL = 0x0C, |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 236 | SATA_INTERFACE_CFG = 0x050, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 237 | |
| 238 | MV_M2_PREAMP_MASK = 0x7e0, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 239 | |
| 240 | /* Port registers */ |
| 241 | EDMA_CFG_OFS = 0, |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 242 | EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ |
| 243 | EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ |
| 244 | EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ |
| 245 | EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ |
| 246 | EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 247 | EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ |
| 248 | EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 249 | |
| 250 | EDMA_ERR_IRQ_CAUSE_OFS = 0x8, |
| 251 | EDMA_ERR_IRQ_MASK_OFS = 0xc, |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 252 | EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ |
| 253 | EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ |
| 254 | EDMA_ERR_DEV = (1 << 2), /* device error */ |
| 255 | EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ |
| 256 | EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ |
| 257 | EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 258 | EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ |
| 259 | EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 260 | EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 261 | EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 262 | EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ |
| 263 | EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ |
| 264 | EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ |
| 265 | EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 266 | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 267 | EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 268 | EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ |
| 269 | EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ |
| 270 | EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ |
| 271 | EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ |
| 272 | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 273 | EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 274 | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 275 | EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 276 | EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ |
| 277 | EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ |
| 278 | EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ |
| 279 | EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ |
| 280 | EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ |
| 281 | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 282 | EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 283 | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 284 | EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 285 | EDMA_ERR_OVERRUN_5 = (1 << 5), |
| 286 | EDMA_ERR_UNDERRUN_5 = (1 << 6), |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 287 | |
| 288 | EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | |
| 289 | EDMA_ERR_LNK_CTRL_RX_1 | |
| 290 | EDMA_ERR_LNK_CTRL_RX_3 | |
Mark Lord | 85afb93 | 2008-04-19 14:54:41 -0400 | [diff] [blame] | 291 | EDMA_ERR_LNK_CTRL_TX, |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 292 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 293 | EDMA_EH_FREEZE = EDMA_ERR_D_PAR | |
| 294 | EDMA_ERR_PRD_PAR | |
| 295 | EDMA_ERR_DEV_DCON | |
| 296 | EDMA_ERR_DEV_CON | |
| 297 | EDMA_ERR_SERR | |
| 298 | EDMA_ERR_SELF_DIS | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 299 | EDMA_ERR_CRQB_PAR | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 300 | EDMA_ERR_CRPB_PAR | |
| 301 | EDMA_ERR_INTRL_PAR | |
| 302 | EDMA_ERR_IORDY | |
| 303 | EDMA_ERR_LNK_CTRL_RX_2 | |
| 304 | EDMA_ERR_LNK_DATA_RX | |
| 305 | EDMA_ERR_LNK_DATA_TX | |
| 306 | EDMA_ERR_TRANS_PROTO, |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 307 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 308 | EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | |
| 309 | EDMA_ERR_PRD_PAR | |
| 310 | EDMA_ERR_DEV_DCON | |
| 311 | EDMA_ERR_DEV_CON | |
| 312 | EDMA_ERR_OVERRUN_5 | |
| 313 | EDMA_ERR_UNDERRUN_5 | |
| 314 | EDMA_ERR_SELF_DIS_5 | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 315 | EDMA_ERR_CRQB_PAR | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 316 | EDMA_ERR_CRPB_PAR | |
| 317 | EDMA_ERR_INTRL_PAR | |
| 318 | EDMA_ERR_IORDY, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 319 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 320 | EDMA_REQ_Q_BASE_HI_OFS = 0x10, |
| 321 | EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 322 | |
| 323 | EDMA_REQ_Q_OUT_PTR_OFS = 0x18, |
| 324 | EDMA_REQ_Q_PTR_SHIFT = 5, |
| 325 | |
| 326 | EDMA_RSP_Q_BASE_HI_OFS = 0x1c, |
| 327 | EDMA_RSP_Q_IN_PTR_OFS = 0x20, |
| 328 | EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 329 | EDMA_RSP_Q_PTR_SHIFT = 3, |
| 330 | |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 331 | EDMA_CMD_OFS = 0x28, /* EDMA command register */ |
| 332 | EDMA_EN = (1 << 0), /* enable EDMA */ |
| 333 | EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ |
| 334 | ATA_RST = (1 << 2), /* reset trans/link/phy */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 335 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 336 | EDMA_IORDY_TMOUT = 0x34, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 337 | EDMA_ARB_CFG = 0x38, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 338 | |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 339 | GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */ |
| 340 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 341 | /* Host private flags (hp_flags) */ |
| 342 | MV_HP_FLAG_MSI = (1 << 0), |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 343 | MV_HP_ERRATA_50XXB0 = (1 << 1), |
| 344 | MV_HP_ERRATA_50XXB2 = (1 << 2), |
| 345 | MV_HP_ERRATA_60X1B2 = (1 << 3), |
| 346 | MV_HP_ERRATA_60X1C0 = (1 << 4), |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 347 | MV_HP_ERRATA_XX42A0 = (1 << 5), |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 348 | MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ |
| 349 | MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ |
| 350 | MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 351 | MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 352 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 353 | /* Port private flags (pp_flags) */ |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 354 | MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ |
Mark Lord | 7210916 | 2008-01-26 18:31:33 -0500 | [diff] [blame] | 355 | MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 356 | }; |
| 357 | |
Jeff Garzik | ee9ccdf | 2007-07-12 15:51:22 -0400 | [diff] [blame] | 358 | #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) |
| 359 | #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 360 | #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 361 | #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 362 | |
Lennert Buytenhek | 15a3263 | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 363 | #define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) |
| 364 | #define WINDOW_BASE(i) (0x20034 + ((i) << 4)) |
| 365 | |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 366 | enum { |
Jeff Garzik | baf14aa | 2007-10-09 13:51:57 -0400 | [diff] [blame] | 367 | /* DMA boundary 0xffff is required by the s/g splitting |
| 368 | * we need on /length/ in mv_fill-sg(). |
| 369 | */ |
| 370 | MV_DMA_BOUNDARY = 0xffffU, |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 371 | |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 372 | /* mask of register bits containing lower 32 bits |
| 373 | * of EDMA request queue DMA address |
| 374 | */ |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 375 | EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, |
| 376 | |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 377 | /* ditto, for response queue */ |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 378 | EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, |
| 379 | }; |
| 380 | |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 381 | enum chip_type { |
| 382 | chip_504x, |
| 383 | chip_508x, |
| 384 | chip_5080, |
| 385 | chip_604x, |
| 386 | chip_608x, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 387 | chip_6042, |
| 388 | chip_7042, |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 389 | chip_soc, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 390 | }; |
| 391 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 392 | /* Command ReQuest Block: 32B */ |
| 393 | struct mv_crqb { |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 394 | __le32 sg_addr; |
| 395 | __le32 sg_addr_hi; |
| 396 | __le16 ctrl_flags; |
| 397 | __le16 ata_cmd[11]; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 398 | }; |
| 399 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 400 | struct mv_crqb_iie { |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 401 | __le32 addr; |
| 402 | __le32 addr_hi; |
| 403 | __le32 flags; |
| 404 | __le32 len; |
| 405 | __le32 ata_cmd[4]; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 406 | }; |
| 407 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 408 | /* Command ResPonse Block: 8B */ |
| 409 | struct mv_crpb { |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 410 | __le16 id; |
| 411 | __le16 flags; |
| 412 | __le32 tmstmp; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 413 | }; |
| 414 | |
| 415 | /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ |
| 416 | struct mv_sg { |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 417 | __le32 addr; |
| 418 | __le32 flags_size; |
| 419 | __le32 addr_hi; |
| 420 | __le32 reserved; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 421 | }; |
| 422 | |
| 423 | struct mv_port_priv { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 424 | struct mv_crqb *crqb; |
| 425 | dma_addr_t crqb_dma; |
| 426 | struct mv_crpb *crpb; |
| 427 | dma_addr_t crpb_dma; |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 428 | struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; |
| 429 | dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 430 | |
| 431 | unsigned int req_idx; |
| 432 | unsigned int resp_idx; |
| 433 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 434 | u32 pp_flags; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 435 | }; |
| 436 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 437 | struct mv_port_signal { |
| 438 | u32 amps; |
| 439 | u32 pre; |
| 440 | }; |
| 441 | |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 442 | struct mv_host_priv { |
| 443 | u32 hp_flags; |
| 444 | struct mv_port_signal signal[8]; |
| 445 | const struct mv_hw_ops *ops; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 446 | int n_ports; |
| 447 | void __iomem *base; |
| 448 | void __iomem *main_cause_reg_addr; |
| 449 | void __iomem *main_mask_reg_addr; |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 450 | u32 irq_cause_ofs; |
| 451 | u32 irq_mask_ofs; |
| 452 | u32 unmask_all_irqs; |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 453 | /* |
| 454 | * These consistent DMA memory pools give us guaranteed |
| 455 | * alignment for hardware-accessed data structures, |
| 456 | * and less memory waste in accomplishing the alignment. |
| 457 | */ |
| 458 | struct dma_pool *crqb_pool; |
| 459 | struct dma_pool *crpb_pool; |
| 460 | struct dma_pool *sg_tbl_pool; |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 461 | }; |
| 462 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 463 | struct mv_hw_ops { |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 464 | void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 465 | unsigned int port); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 466 | void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 467 | void (*read_preamp)(struct mv_host_priv *hpriv, int idx, |
| 468 | void __iomem *mmio); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 469 | int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 470 | unsigned int n_hc); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 471 | void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 472 | void (*reset_bus)(struct ata_host *host, void __iomem *mmio); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 473 | }; |
| 474 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 475 | static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); |
| 476 | static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); |
| 477 | static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); |
| 478 | static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 479 | static int mv_port_start(struct ata_port *ap); |
| 480 | static void mv_port_stop(struct ata_port *ap); |
| 481 | static void mv_qc_prep(struct ata_queued_cmd *qc); |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 482 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc); |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 483 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 484 | static int mv_hardreset(struct ata_link *link, unsigned int *class, |
| 485 | unsigned long deadline); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 486 | static void mv_eh_freeze(struct ata_port *ap); |
| 487 | static void mv_eh_thaw(struct ata_port *ap); |
Mark Lord | f273827 | 2008-01-26 18:32:29 -0500 | [diff] [blame] | 488 | static void mv6_dev_config(struct ata_device *dev); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 489 | |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 490 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 491 | unsigned int port); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 492 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 493 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, |
| 494 | void __iomem *mmio); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 495 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 496 | unsigned int n_hc); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 497 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 498 | static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 499 | |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 500 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 501 | unsigned int port); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 502 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 503 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, |
| 504 | void __iomem *mmio); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 505 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 506 | unsigned int n_hc); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 507 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 508 | static void mv_soc_enable_leds(struct mv_host_priv *hpriv, |
| 509 | void __iomem *mmio); |
| 510 | static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, |
| 511 | void __iomem *mmio); |
| 512 | static int mv_soc_reset_hc(struct mv_host_priv *hpriv, |
| 513 | void __iomem *mmio, unsigned int n_hc); |
| 514 | static void mv_soc_reset_flash(struct mv_host_priv *hpriv, |
| 515 | void __iomem *mmio); |
| 516 | static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 517 | static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 518 | static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 519 | unsigned int port_no); |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 520 | static int mv_stop_edma(struct ata_port *ap); |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 521 | static int mv_stop_edma_engine(void __iomem *port_mmio); |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 522 | static void mv_edma_cfg(struct ata_port *ap, int want_ncq); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 523 | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 524 | static void mv_pmp_select(struct ata_port *ap, int pmp); |
| 525 | static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, |
| 526 | unsigned long deadline); |
| 527 | static int mv_softreset(struct ata_link *link, unsigned int *class, |
| 528 | unsigned long deadline); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 529 | |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 530 | /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below |
| 531 | * because we have to allow room for worst case splitting of |
| 532 | * PRDs for 64K boundaries in mv_fill_sg(). |
| 533 | */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 534 | static struct scsi_host_template mv5_sht = { |
Tejun Heo | 68d1d07 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 535 | ATA_BASE_SHT(DRV_NAME), |
Jeff Garzik | baf14aa | 2007-10-09 13:51:57 -0400 | [diff] [blame] | 536 | .sg_tablesize = MV_MAX_SG_CT / 2, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 537 | .dma_boundary = MV_DMA_BOUNDARY, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 538 | }; |
| 539 | |
| 540 | static struct scsi_host_template mv6_sht = { |
Tejun Heo | 68d1d07 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 541 | ATA_NCQ_SHT(DRV_NAME), |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 542 | .can_queue = MV_MAX_Q_DEPTH - 1, |
Jeff Garzik | baf14aa | 2007-10-09 13:51:57 -0400 | [diff] [blame] | 543 | .sg_tablesize = MV_MAX_SG_CT / 2, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 544 | .dma_boundary = MV_DMA_BOUNDARY, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 545 | }; |
| 546 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 547 | static struct ata_port_operations mv5_ops = { |
| 548 | .inherits = &ata_sff_port_ops, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 549 | |
| 550 | .qc_prep = mv_qc_prep, |
| 551 | .qc_issue = mv_qc_issue, |
| 552 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 553 | .freeze = mv_eh_freeze, |
| 554 | .thaw = mv_eh_thaw, |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 555 | .hardreset = mv_hardreset, |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 556 | .error_handler = ata_std_error_handler, /* avoid SFF EH */ |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 557 | .post_internal_cmd = ATA_OP_NULL, |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 558 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 559 | .scr_read = mv5_scr_read, |
| 560 | .scr_write = mv5_scr_write, |
| 561 | |
| 562 | .port_start = mv_port_start, |
| 563 | .port_stop = mv_port_stop, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 564 | }; |
| 565 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 566 | static struct ata_port_operations mv6_ops = { |
| 567 | .inherits = &mv5_ops, |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 568 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
Mark Lord | f273827 | 2008-01-26 18:32:29 -0500 | [diff] [blame] | 569 | .dev_config = mv6_dev_config, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 570 | .scr_read = mv_scr_read, |
| 571 | .scr_write = mv_scr_write, |
| 572 | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 573 | .pmp_hardreset = mv_pmp_hardreset, |
| 574 | .pmp_softreset = mv_softreset, |
| 575 | .softreset = mv_softreset, |
| 576 | .error_handler = sata_pmp_error_handler, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 577 | }; |
| 578 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 579 | static struct ata_port_operations mv_iie_ops = { |
| 580 | .inherits = &mv6_ops, |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 581 | .qc_defer = ata_std_qc_defer, /* FIS-based switching */ |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 582 | .dev_config = ATA_OP_NULL, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 583 | .qc_prep = mv_qc_prep_iie, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 584 | }; |
| 585 | |
Arjan van de Ven | 98ac62d | 2005-11-28 10:06:23 +0100 | [diff] [blame] | 586 | static const struct ata_port_info mv_port_info[] = { |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 587 | { /* chip_504x */ |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 588 | .flags = MV_COMMON_FLAGS, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 589 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 590 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 591 | .port_ops = &mv5_ops, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 592 | }, |
| 593 | { /* chip_508x */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 594 | .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 595 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 596 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 597 | .port_ops = &mv5_ops, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 598 | }, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 599 | { /* chip_5080 */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 600 | .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 601 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 602 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 603 | .port_ops = &mv5_ops, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 604 | }, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 605 | { /* chip_604x */ |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 606 | .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 607 | ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 608 | ATA_FLAG_NCQ, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 609 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 610 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 611 | .port_ops = &mv6_ops, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 612 | }, |
| 613 | { /* chip_608x */ |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 614 | .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 615 | ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 616 | ATA_FLAG_NCQ | MV_FLAG_DUAL_HC, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 617 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 618 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 619 | .port_ops = &mv6_ops, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 620 | }, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 621 | { /* chip_6042 */ |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 622 | .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 623 | ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 624 | ATA_FLAG_NCQ, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 625 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 626 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 627 | .port_ops = &mv_iie_ops, |
| 628 | }, |
| 629 | { /* chip_7042 */ |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 630 | .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 631 | ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 632 | ATA_FLAG_NCQ, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 633 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 634 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 635 | .port_ops = &mv_iie_ops, |
| 636 | }, |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 637 | { /* chip_soc */ |
Mark Lord | 02c1f32 | 2008-04-16 14:58:13 -0400 | [diff] [blame] | 638 | .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 639 | ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | |
Mark Lord | 02c1f32 | 2008-04-16 14:58:13 -0400 | [diff] [blame] | 640 | ATA_FLAG_NCQ | MV_FLAG_SOC, |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 641 | .pio_mask = 0x1f, /* pio0-4 */ |
| 642 | .udma_mask = ATA_UDMA6, |
| 643 | .port_ops = &mv_iie_ops, |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 644 | }, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 645 | }; |
| 646 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 647 | static const struct pci_device_id mv_pci_tbl[] = { |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 648 | { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, |
| 649 | { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, |
| 650 | { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, |
| 651 | { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, |
Alan Cox | cfbf723 | 2007-07-09 14:38:41 +0100 | [diff] [blame] | 652 | /* RocketRAID 1740/174x have different identifiers */ |
| 653 | { PCI_VDEVICE(TTI, 0x1740), chip_508x }, |
| 654 | { PCI_VDEVICE(TTI, 0x1742), chip_508x }, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 655 | |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 656 | { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, |
| 657 | { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, |
| 658 | { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, |
| 659 | { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, |
| 660 | { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, |
Jeff Garzik | 2917953 | 2005-11-11 08:08:03 -0500 | [diff] [blame] | 661 | |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 662 | { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, |
| 663 | |
Florian Attenberger | d9f9c6b | 2007-07-02 17:09:29 +0200 | [diff] [blame] | 664 | /* Adaptec 1430SA */ |
| 665 | { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, |
| 666 | |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 667 | /* Marvell 7042 support */ |
Morrison, Tom | 6a3d586 | 2007-03-06 02:38:10 -0800 | [diff] [blame] | 668 | { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, |
| 669 | |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 670 | /* Highpoint RocketRAID PCIe series */ |
| 671 | { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, |
| 672 | { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, |
| 673 | |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 674 | { } /* terminate list */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 675 | }; |
| 676 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 677 | static const struct mv_hw_ops mv5xxx_ops = { |
| 678 | .phy_errata = mv5_phy_errata, |
| 679 | .enable_leds = mv5_enable_leds, |
| 680 | .read_preamp = mv5_read_preamp, |
| 681 | .reset_hc = mv5_reset_hc, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 682 | .reset_flash = mv5_reset_flash, |
| 683 | .reset_bus = mv5_reset_bus, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 684 | }; |
| 685 | |
| 686 | static const struct mv_hw_ops mv6xxx_ops = { |
| 687 | .phy_errata = mv6_phy_errata, |
| 688 | .enable_leds = mv6_enable_leds, |
| 689 | .read_preamp = mv6_read_preamp, |
| 690 | .reset_hc = mv6_reset_hc, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 691 | .reset_flash = mv6_reset_flash, |
| 692 | .reset_bus = mv_reset_pci_bus, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 693 | }; |
| 694 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 695 | static const struct mv_hw_ops mv_soc_ops = { |
| 696 | .phy_errata = mv6_phy_errata, |
| 697 | .enable_leds = mv_soc_enable_leds, |
| 698 | .read_preamp = mv_soc_read_preamp, |
| 699 | .reset_hc = mv_soc_reset_hc, |
| 700 | .reset_flash = mv_soc_reset_flash, |
| 701 | .reset_bus = mv_soc_reset_bus, |
| 702 | }; |
| 703 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 704 | /* |
| 705 | * Functions |
| 706 | */ |
| 707 | |
| 708 | static inline void writelfl(unsigned long data, void __iomem *addr) |
| 709 | { |
| 710 | writel(data, addr); |
| 711 | (void) readl(addr); /* flush to avoid PCI posted write */ |
| 712 | } |
| 713 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 714 | static inline unsigned int mv_hc_from_port(unsigned int port) |
| 715 | { |
| 716 | return port >> MV_PORT_HC_SHIFT; |
| 717 | } |
| 718 | |
| 719 | static inline unsigned int mv_hardport_from_port(unsigned int port) |
| 720 | { |
| 721 | return port & MV_PORT_MASK; |
| 722 | } |
| 723 | |
Mark Lord | 1cfd19a | 2008-04-19 15:05:50 -0400 | [diff] [blame] | 724 | /* |
| 725 | * Consolidate some rather tricky bit shift calculations. |
| 726 | * This is hot-path stuff, so not a function. |
| 727 | * Simple code, with two return values, so macro rather than inline. |
| 728 | * |
| 729 | * port is the sole input, in range 0..7. |
| 730 | * shift is one output, for use with the main_cause and main_mask registers. |
| 731 | * hardport is the other output, in range 0..3 |
| 732 | * |
| 733 | * Note that port and hardport may be the same variable in some cases. |
| 734 | */ |
| 735 | #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ |
| 736 | { \ |
| 737 | shift = mv_hc_from_port(port) * HC_SHIFT; \ |
| 738 | hardport = mv_hardport_from_port(port); \ |
| 739 | shift += hardport * 2; \ |
| 740 | } |
| 741 | |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 742 | static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) |
| 743 | { |
| 744 | return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); |
| 745 | } |
| 746 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 747 | static inline void __iomem *mv_hc_base_from_port(void __iomem *base, |
| 748 | unsigned int port) |
| 749 | { |
| 750 | return mv_hc_base(base, mv_hc_from_port(port)); |
| 751 | } |
| 752 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 753 | static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) |
| 754 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 755 | return mv_hc_base_from_port(base, port) + |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 756 | MV_SATAHC_ARBTR_REG_SZ + |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 757 | (mv_hardport_from_port(port) * MV_PORT_REG_SZ); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 758 | } |
| 759 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 760 | static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) |
| 761 | { |
| 762 | void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); |
| 763 | unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; |
| 764 | |
| 765 | return hc_mmio + ofs; |
| 766 | } |
| 767 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 768 | static inline void __iomem *mv_host_base(struct ata_host *host) |
| 769 | { |
| 770 | struct mv_host_priv *hpriv = host->private_data; |
| 771 | return hpriv->base; |
| 772 | } |
| 773 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 774 | static inline void __iomem *mv_ap_base(struct ata_port *ap) |
| 775 | { |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 776 | return mv_port_base(mv_host_base(ap->host), ap->port_no); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 777 | } |
| 778 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 779 | static inline int mv_get_hc_count(unsigned long port_flags) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 780 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 781 | return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 782 | } |
| 783 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 784 | static void mv_set_edma_ptrs(void __iomem *port_mmio, |
| 785 | struct mv_host_priv *hpriv, |
| 786 | struct mv_port_priv *pp) |
| 787 | { |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 788 | u32 index; |
| 789 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 790 | /* |
| 791 | * initialize request queue |
| 792 | */ |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 793 | pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ |
| 794 | index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 795 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 796 | WARN_ON(pp->crqb_dma & 0x3ff); |
| 797 | writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 798 | writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 799 | port_mmio + EDMA_REQ_Q_IN_PTR_OFS); |
| 800 | |
| 801 | if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 802 | writelfl((pp->crqb_dma & 0xffffffff) | index, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 803 | port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); |
| 804 | else |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 805 | writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 806 | |
| 807 | /* |
| 808 | * initialize response queue |
| 809 | */ |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 810 | pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ |
| 811 | index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 812 | |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 813 | WARN_ON(pp->crpb_dma & 0xff); |
| 814 | writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); |
| 815 | |
| 816 | if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 817 | writelfl((pp->crpb_dma & 0xffffffff) | index, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 818 | port_mmio + EDMA_RSP_Q_IN_PTR_OFS); |
| 819 | else |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 820 | writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 821 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 822 | writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 823 | port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 824 | } |
| 825 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 826 | /** |
| 827 | * mv_start_dma - Enable eDMA engine |
| 828 | * @base: port base address |
| 829 | * @pp: port private data |
| 830 | * |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 831 | * Verify the local cache of the eDMA state is accurate with a |
| 832 | * WARN_ON. |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 833 | * |
| 834 | * LOCKING: |
| 835 | * Inherited from caller. |
| 836 | */ |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 837 | static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio, |
Mark Lord | 7210916 | 2008-01-26 18:31:33 -0500 | [diff] [blame] | 838 | struct mv_port_priv *pp, u8 protocol) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 839 | { |
Mark Lord | 7210916 | 2008-01-26 18:31:33 -0500 | [diff] [blame] | 840 | int want_ncq = (protocol == ATA_PROT_NCQ); |
| 841 | |
| 842 | if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { |
| 843 | int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); |
| 844 | if (want_ncq != using_ncq) |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 845 | mv_stop_edma(ap); |
Mark Lord | 7210916 | 2008-01-26 18:31:33 -0500 | [diff] [blame] | 846 | } |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 847 | if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 848 | struct mv_host_priv *hpriv = ap->host->private_data; |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 849 | int hardport = mv_hardport_from_port(ap->port_no); |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 850 | void __iomem *hc_mmio = mv_hc_base_from_port( |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 851 | mv_host_base(ap->host), hardport); |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 852 | u32 hc_irq_cause, ipending; |
| 853 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 854 | /* clear EDMA event indicators, if any */ |
Mark Lord | f630d56 | 2008-01-26 18:31:00 -0500 | [diff] [blame] | 855 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 856 | |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 857 | /* clear EDMA interrupt indicator, if any */ |
| 858 | hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 859 | ipending = (DEV_IRQ | DMA_IRQ) << hardport; |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 860 | if (hc_irq_cause & ipending) { |
| 861 | writelfl(hc_irq_cause & ~ipending, |
| 862 | hc_mmio + HC_IRQ_CAUSE_OFS); |
| 863 | } |
| 864 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 865 | mv_edma_cfg(ap, want_ncq); |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 866 | |
| 867 | /* clear FIS IRQ Cause */ |
| 868 | writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); |
| 869 | |
Mark Lord | f630d56 | 2008-01-26 18:31:00 -0500 | [diff] [blame] | 870 | mv_set_edma_ptrs(port_mmio, hpriv, pp); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 871 | |
Mark Lord | f630d56 | 2008-01-26 18:31:00 -0500 | [diff] [blame] | 872 | writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 873 | pp->pp_flags |= MV_PP_FLAG_EDMA_EN; |
| 874 | } |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 875 | } |
| 876 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 877 | /** |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 878 | * mv_stop_edma_engine - Disable eDMA engine |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 879 | * @port_mmio: io base address |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 880 | * |
| 881 | * LOCKING: |
| 882 | * Inherited from caller. |
| 883 | */ |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 884 | static int mv_stop_edma_engine(void __iomem *port_mmio) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 885 | { |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 886 | int i; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 887 | |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 888 | /* Disable eDMA. The disable bit auto clears. */ |
| 889 | writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 890 | |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 891 | /* Wait for the chip to confirm eDMA is off. */ |
| 892 | for (i = 10000; i > 0; i--) { |
| 893 | u32 reg = readl(port_mmio + EDMA_CMD_OFS); |
Jeff Garzik | 4537deb | 2007-07-12 14:30:19 -0400 | [diff] [blame] | 894 | if (!(reg & EDMA_EN)) |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 895 | return 0; |
| 896 | udelay(10); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 897 | } |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 898 | return -EIO; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 899 | } |
| 900 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 901 | static int mv_stop_edma(struct ata_port *ap) |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 902 | { |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 903 | void __iomem *port_mmio = mv_ap_base(ap); |
| 904 | struct mv_port_priv *pp = ap->private_data; |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 905 | |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 906 | if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) |
| 907 | return 0; |
| 908 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
| 909 | if (mv_stop_edma_engine(port_mmio)) { |
| 910 | ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); |
| 911 | return -EIO; |
| 912 | } |
| 913 | return 0; |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 914 | } |
| 915 | |
Jeff Garzik | 8a70f8d | 2005-10-05 17:19:47 -0400 | [diff] [blame] | 916 | #ifdef ATA_DEBUG |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 917 | static void mv_dump_mem(void __iomem *start, unsigned bytes) |
| 918 | { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 919 | int b, w; |
| 920 | for (b = 0; b < bytes; ) { |
| 921 | DPRINTK("%p: ", start + b); |
| 922 | for (w = 0; b < bytes && w < 4; w++) { |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 923 | printk("%08x ", readl(start + b)); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 924 | b += sizeof(u32); |
| 925 | } |
| 926 | printk("\n"); |
| 927 | } |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 928 | } |
Jeff Garzik | 8a70f8d | 2005-10-05 17:19:47 -0400 | [diff] [blame] | 929 | #endif |
| 930 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 931 | static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) |
| 932 | { |
| 933 | #ifdef ATA_DEBUG |
| 934 | int b, w; |
| 935 | u32 dw; |
| 936 | for (b = 0; b < bytes; ) { |
| 937 | DPRINTK("%02x: ", b); |
| 938 | for (w = 0; b < bytes && w < 4; w++) { |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 939 | (void) pci_read_config_dword(pdev, b, &dw); |
| 940 | printk("%08x ", dw); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 941 | b += sizeof(u32); |
| 942 | } |
| 943 | printk("\n"); |
| 944 | } |
| 945 | #endif |
| 946 | } |
| 947 | static void mv_dump_all_regs(void __iomem *mmio_base, int port, |
| 948 | struct pci_dev *pdev) |
| 949 | { |
| 950 | #ifdef ATA_DEBUG |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 951 | void __iomem *hc_base = mv_hc_base(mmio_base, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 952 | port >> MV_PORT_HC_SHIFT); |
| 953 | void __iomem *port_base; |
| 954 | int start_port, num_ports, p, start_hc, num_hcs, hc; |
| 955 | |
| 956 | if (0 > port) { |
| 957 | start_hc = start_port = 0; |
| 958 | num_ports = 8; /* shld be benign for 4 port devs */ |
| 959 | num_hcs = 2; |
| 960 | } else { |
| 961 | start_hc = port >> MV_PORT_HC_SHIFT; |
| 962 | start_port = port; |
| 963 | num_ports = num_hcs = 1; |
| 964 | } |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 965 | DPRINTK("All registers for port(s) %u-%u:\n", start_port, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 966 | num_ports > 1 ? num_ports - 1 : start_port); |
| 967 | |
| 968 | if (NULL != pdev) { |
| 969 | DPRINTK("PCI config space regs:\n"); |
| 970 | mv_dump_pci_cfg(pdev, 0x68); |
| 971 | } |
| 972 | DPRINTK("PCI regs:\n"); |
| 973 | mv_dump_mem(mmio_base+0xc00, 0x3c); |
| 974 | mv_dump_mem(mmio_base+0xd00, 0x34); |
| 975 | mv_dump_mem(mmio_base+0xf00, 0x4); |
| 976 | mv_dump_mem(mmio_base+0x1d00, 0x6c); |
| 977 | for (hc = start_hc; hc < start_hc + num_hcs; hc++) { |
Dan Aloni | d220c37 | 2006-04-10 23:20:22 -0700 | [diff] [blame] | 978 | hc_base = mv_hc_base(mmio_base, hc); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 979 | DPRINTK("HC regs (HC %i):\n", hc); |
| 980 | mv_dump_mem(hc_base, 0x1c); |
| 981 | } |
| 982 | for (p = start_port; p < start_port + num_ports; p++) { |
| 983 | port_base = mv_port_base(mmio_base, p); |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 984 | DPRINTK("EDMA regs (port %i):\n", p); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 985 | mv_dump_mem(port_base, 0x54); |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 986 | DPRINTK("SATA regs (port %i):\n", p); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 987 | mv_dump_mem(port_base+0x300, 0x60); |
| 988 | } |
| 989 | #endif |
| 990 | } |
| 991 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 992 | static unsigned int mv_scr_offset(unsigned int sc_reg_in) |
| 993 | { |
| 994 | unsigned int ofs; |
| 995 | |
| 996 | switch (sc_reg_in) { |
| 997 | case SCR_STATUS: |
| 998 | case SCR_CONTROL: |
| 999 | case SCR_ERROR: |
| 1000 | ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); |
| 1001 | break; |
| 1002 | case SCR_ACTIVE: |
| 1003 | ofs = SATA_ACTIVE_OFS; /* active is not with the others */ |
| 1004 | break; |
| 1005 | default: |
| 1006 | ofs = 0xffffffffU; |
| 1007 | break; |
| 1008 | } |
| 1009 | return ofs; |
| 1010 | } |
| 1011 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1012 | static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1013 | { |
| 1014 | unsigned int ofs = mv_scr_offset(sc_reg_in); |
| 1015 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1016 | if (ofs != 0xffffffffU) { |
| 1017 | *val = readl(mv_ap_base(ap) + ofs); |
| 1018 | return 0; |
| 1019 | } else |
| 1020 | return -EINVAL; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1021 | } |
| 1022 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1023 | static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1024 | { |
| 1025 | unsigned int ofs = mv_scr_offset(sc_reg_in); |
| 1026 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1027 | if (ofs != 0xffffffffU) { |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1028 | writelfl(val, mv_ap_base(ap) + ofs); |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1029 | return 0; |
| 1030 | } else |
| 1031 | return -EINVAL; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1032 | } |
| 1033 | |
Mark Lord | f273827 | 2008-01-26 18:32:29 -0500 | [diff] [blame] | 1034 | static void mv6_dev_config(struct ata_device *adev) |
| 1035 | { |
| 1036 | /* |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1037 | * Deal with Gen-II ("mv6") hardware quirks/restrictions: |
| 1038 | * |
| 1039 | * Gen-II does not support NCQ over a port multiplier |
| 1040 | * (no FIS-based switching). |
| 1041 | * |
Mark Lord | f273827 | 2008-01-26 18:32:29 -0500 | [diff] [blame] | 1042 | * We don't have hob_nsect when doing NCQ commands on Gen-II. |
| 1043 | * See mv_qc_prep() for more info. |
| 1044 | */ |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1045 | if (adev->flags & ATA_DFLAG_NCQ) { |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 1046 | if (sata_pmp_attached(adev->link->ap)) { |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1047 | adev->flags &= ~ATA_DFLAG_NCQ; |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 1048 | ata_dev_printk(adev, KERN_INFO, |
| 1049 | "NCQ disabled for command-based switching\n"); |
| 1050 | } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) { |
| 1051 | adev->max_sectors = GEN_II_NCQ_MAX_SECTORS; |
| 1052 | ata_dev_printk(adev, KERN_INFO, |
| 1053 | "max_sectors limited to %u for NCQ\n", |
| 1054 | adev->max_sectors); |
| 1055 | } |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1056 | } |
Mark Lord | f273827 | 2008-01-26 18:32:29 -0500 | [diff] [blame] | 1057 | } |
| 1058 | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1059 | static void mv_config_fbs(void __iomem *port_mmio, int enable_fbs) |
| 1060 | { |
| 1061 | u32 old_fcfg, new_fcfg, old_ltmode, new_ltmode; |
| 1062 | /* |
| 1063 | * Various bit settings required for operation |
| 1064 | * in FIS-based switching (fbs) mode on GenIIe: |
| 1065 | */ |
| 1066 | old_fcfg = readl(port_mmio + FIS_CFG_OFS); |
| 1067 | old_ltmode = readl(port_mmio + LTMODE_OFS); |
| 1068 | if (enable_fbs) { |
| 1069 | new_fcfg = old_fcfg | FIS_CFG_SINGLE_SYNC; |
| 1070 | new_ltmode = old_ltmode | LTMODE_BIT8; |
| 1071 | } else { /* disable fbs */ |
| 1072 | new_fcfg = old_fcfg & ~FIS_CFG_SINGLE_SYNC; |
| 1073 | new_ltmode = old_ltmode & ~LTMODE_BIT8; |
| 1074 | } |
| 1075 | if (new_fcfg != old_fcfg) |
| 1076 | writelfl(new_fcfg, port_mmio + FIS_CFG_OFS); |
| 1077 | if (new_ltmode != old_ltmode) |
| 1078 | writelfl(new_ltmode, port_mmio + LTMODE_OFS); |
Mark Lord | 0c58912 | 2008-01-26 18:31:16 -0500 | [diff] [blame] | 1079 | } |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1080 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 1081 | static void mv_edma_cfg(struct ata_port *ap, int want_ncq) |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1082 | { |
| 1083 | u32 cfg; |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 1084 | struct mv_port_priv *pp = ap->private_data; |
| 1085 | struct mv_host_priv *hpriv = ap->host->private_data; |
| 1086 | void __iomem *port_mmio = mv_ap_base(ap); |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1087 | |
| 1088 | /* set up non-NCQ EDMA configuration */ |
| 1089 | cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ |
| 1090 | |
| 1091 | if (IS_GEN_I(hpriv)) |
| 1092 | cfg |= (1 << 8); /* enab config burst size mask */ |
| 1093 | |
| 1094 | else if (IS_GEN_II(hpriv)) |
| 1095 | cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; |
| 1096 | |
| 1097 | else if (IS_GEN_IIE(hpriv)) { |
Jeff Garzik | e728eab | 2007-02-25 02:53:41 -0500 | [diff] [blame] | 1098 | cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ |
| 1099 | cfg |= (1 << 22); /* enab 4-entry host queue cache */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1100 | cfg |= (1 << 18); /* enab early completion */ |
Jeff Garzik | e728eab | 2007-02-25 02:53:41 -0500 | [diff] [blame] | 1101 | cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */ |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1102 | |
| 1103 | if (want_ncq && sata_pmp_attached(ap)) { |
| 1104 | cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ |
| 1105 | mv_config_fbs(port_mmio, 1); |
| 1106 | } else { |
| 1107 | mv_config_fbs(port_mmio, 0); |
| 1108 | } |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1109 | } |
| 1110 | |
Mark Lord | 7210916 | 2008-01-26 18:31:33 -0500 | [diff] [blame] | 1111 | if (want_ncq) { |
| 1112 | cfg |= EDMA_CFG_NCQ; |
| 1113 | pp->pp_flags |= MV_PP_FLAG_NCQ_EN; |
| 1114 | } else |
| 1115 | pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN; |
| 1116 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1117 | writelfl(cfg, port_mmio + EDMA_CFG_OFS); |
| 1118 | } |
| 1119 | |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 1120 | static void mv_port_free_dma_mem(struct ata_port *ap) |
| 1121 | { |
| 1122 | struct mv_host_priv *hpriv = ap->host->private_data; |
| 1123 | struct mv_port_priv *pp = ap->private_data; |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 1124 | int tag; |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 1125 | |
| 1126 | if (pp->crqb) { |
| 1127 | dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); |
| 1128 | pp->crqb = NULL; |
| 1129 | } |
| 1130 | if (pp->crpb) { |
| 1131 | dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); |
| 1132 | pp->crpb = NULL; |
| 1133 | } |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 1134 | /* |
| 1135 | * For GEN_I, there's no NCQ, so we have only a single sg_tbl. |
| 1136 | * For later hardware, we have one unique sg_tbl per NCQ tag. |
| 1137 | */ |
| 1138 | for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { |
| 1139 | if (pp->sg_tbl[tag]) { |
| 1140 | if (tag == 0 || !IS_GEN_I(hpriv)) |
| 1141 | dma_pool_free(hpriv->sg_tbl_pool, |
| 1142 | pp->sg_tbl[tag], |
| 1143 | pp->sg_tbl_dma[tag]); |
| 1144 | pp->sg_tbl[tag] = NULL; |
| 1145 | } |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 1146 | } |
| 1147 | } |
| 1148 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1149 | /** |
| 1150 | * mv_port_start - Port specific init/start routine. |
| 1151 | * @ap: ATA channel to manipulate |
| 1152 | * |
| 1153 | * Allocate and point to DMA memory, init port private memory, |
| 1154 | * zero indices. |
| 1155 | * |
| 1156 | * LOCKING: |
| 1157 | * Inherited from caller. |
| 1158 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1159 | static int mv_port_start(struct ata_port *ap) |
| 1160 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1161 | struct device *dev = ap->host->dev; |
| 1162 | struct mv_host_priv *hpriv = ap->host->private_data; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1163 | struct mv_port_priv *pp; |
James Bottomley | dde2020 | 2008-02-19 11:36:56 +0100 | [diff] [blame] | 1164 | int tag; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1165 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1166 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 1167 | if (!pp) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1168 | return -ENOMEM; |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 1169 | ap->private_data = pp; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1170 | |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 1171 | pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); |
| 1172 | if (!pp->crqb) |
| 1173 | return -ENOMEM; |
| 1174 | memset(pp->crqb, 0, MV_CRQB_Q_SZ); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1175 | |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 1176 | pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); |
| 1177 | if (!pp->crpb) |
| 1178 | goto out_port_free_dma_mem; |
| 1179 | memset(pp->crpb, 0, MV_CRPB_Q_SZ); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1180 | |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 1181 | /* |
| 1182 | * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. |
| 1183 | * For later hardware, we need one unique sg_tbl per NCQ tag. |
| 1184 | */ |
| 1185 | for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { |
| 1186 | if (tag == 0 || !IS_GEN_I(hpriv)) { |
| 1187 | pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, |
| 1188 | GFP_KERNEL, &pp->sg_tbl_dma[tag]); |
| 1189 | if (!pp->sg_tbl[tag]) |
| 1190 | goto out_port_free_dma_mem; |
| 1191 | } else { |
| 1192 | pp->sg_tbl[tag] = pp->sg_tbl[0]; |
| 1193 | pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; |
| 1194 | } |
| 1195 | } |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1196 | return 0; |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 1197 | |
| 1198 | out_port_free_dma_mem: |
| 1199 | mv_port_free_dma_mem(ap); |
| 1200 | return -ENOMEM; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1201 | } |
| 1202 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1203 | /** |
| 1204 | * mv_port_stop - Port specific cleanup/stop routine. |
| 1205 | * @ap: ATA channel to manipulate |
| 1206 | * |
| 1207 | * Stop DMA, cleanup port memory. |
| 1208 | * |
| 1209 | * LOCKING: |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1210 | * This routine uses the host lock to protect the DMA stop. |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1211 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1212 | static void mv_port_stop(struct ata_port *ap) |
| 1213 | { |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 1214 | mv_stop_edma(ap); |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 1215 | mv_port_free_dma_mem(ap); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1216 | } |
| 1217 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1218 | /** |
| 1219 | * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries |
| 1220 | * @qc: queued command whose SG list to source from |
| 1221 | * |
| 1222 | * Populate the SG list and mark the last entry. |
| 1223 | * |
| 1224 | * LOCKING: |
| 1225 | * Inherited from caller. |
| 1226 | */ |
Jeff Garzik | 6c08772 | 2007-10-12 00:16:23 -0400 | [diff] [blame] | 1227 | static void mv_fill_sg(struct ata_queued_cmd *qc) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1228 | { |
| 1229 | struct mv_port_priv *pp = qc->ap->private_data; |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 1230 | struct scatterlist *sg; |
Jeff Garzik | 3be6cbd | 2007-10-18 16:21:18 -0400 | [diff] [blame] | 1231 | struct mv_sg *mv_sg, *last_sg = NULL; |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 1232 | unsigned int si; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1233 | |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 1234 | mv_sg = pp->sg_tbl[qc->tag]; |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 1235 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1236 | dma_addr_t addr = sg_dma_address(sg); |
| 1237 | u32 sg_len = sg_dma_len(sg); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1238 | |
Olof Johansson | 4007b49 | 2007-10-02 20:45:27 -0500 | [diff] [blame] | 1239 | while (sg_len) { |
| 1240 | u32 offset = addr & 0xffff; |
| 1241 | u32 len = sg_len; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1242 | |
Olof Johansson | 4007b49 | 2007-10-02 20:45:27 -0500 | [diff] [blame] | 1243 | if ((offset + sg_len > 0x10000)) |
| 1244 | len = 0x10000 - offset; |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 1245 | |
Olof Johansson | 4007b49 | 2007-10-02 20:45:27 -0500 | [diff] [blame] | 1246 | mv_sg->addr = cpu_to_le32(addr & 0xffffffff); |
| 1247 | mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); |
Jeff Garzik | 6c08772 | 2007-10-12 00:16:23 -0400 | [diff] [blame] | 1248 | mv_sg->flags_size = cpu_to_le32(len & 0xffff); |
Olof Johansson | 4007b49 | 2007-10-02 20:45:27 -0500 | [diff] [blame] | 1249 | |
| 1250 | sg_len -= len; |
| 1251 | addr += len; |
| 1252 | |
Jeff Garzik | 3be6cbd | 2007-10-18 16:21:18 -0400 | [diff] [blame] | 1253 | last_sg = mv_sg; |
Olof Johansson | 4007b49 | 2007-10-02 20:45:27 -0500 | [diff] [blame] | 1254 | mv_sg++; |
Olof Johansson | 4007b49 | 2007-10-02 20:45:27 -0500 | [diff] [blame] | 1255 | } |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1256 | } |
Jeff Garzik | 3be6cbd | 2007-10-18 16:21:18 -0400 | [diff] [blame] | 1257 | |
| 1258 | if (likely(last_sg)) |
| 1259 | last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1260 | } |
| 1261 | |
Jeff Garzik | 5796d1c | 2007-10-26 00:03:37 -0400 | [diff] [blame] | 1262 | static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1263 | { |
Mark Lord | 559eeda | 2006-05-19 16:40:15 -0400 | [diff] [blame] | 1264 | u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1265 | (last ? CRQB_CMD_LAST : 0); |
Mark Lord | 559eeda | 2006-05-19 16:40:15 -0400 | [diff] [blame] | 1266 | *cmdw = cpu_to_le16(tmp); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1267 | } |
| 1268 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1269 | /** |
| 1270 | * mv_qc_prep - Host specific command preparation. |
| 1271 | * @qc: queued command to prepare |
| 1272 | * |
| 1273 | * This routine simply redirects to the general purpose routine |
| 1274 | * if command is not DMA. Else, it handles prep of the CRQB |
| 1275 | * (command request block), does some sanity checking, and calls |
| 1276 | * the SG load routine. |
| 1277 | * |
| 1278 | * LOCKING: |
| 1279 | * Inherited from caller. |
| 1280 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1281 | static void mv_qc_prep(struct ata_queued_cmd *qc) |
| 1282 | { |
| 1283 | struct ata_port *ap = qc->ap; |
| 1284 | struct mv_port_priv *pp = ap->private_data; |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 1285 | __le16 *cw; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1286 | struct ata_taskfile *tf; |
| 1287 | u16 flags = 0; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1288 | unsigned in_index; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1289 | |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 1290 | if ((qc->tf.protocol != ATA_PROT_DMA) && |
| 1291 | (qc->tf.protocol != ATA_PROT_NCQ)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1292 | return; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1293 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1294 | /* Fill in command request block |
| 1295 | */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1296 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1297 | flags |= CRQB_FLAG_READ; |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 1298 | WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1299 | flags |= qc->tag << CRQB_TAG_SHIFT; |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1300 | flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1301 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1302 | /* get current queue index from software */ |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 1303 | in_index = pp->req_idx; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1304 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1305 | pp->crqb[in_index].sg_addr = |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 1306 | cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1307 | pp->crqb[in_index].sg_addr_hi = |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 1308 | cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1309 | pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); |
| 1310 | |
| 1311 | cw = &pp->crqb[in_index].ata_cmd[0]; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1312 | tf = &qc->tf; |
| 1313 | |
| 1314 | /* Sadly, the CRQB cannot accomodate all registers--there are |
| 1315 | * only 11 bytes...so we must pick and choose required |
| 1316 | * registers based on the command. So, we drop feature and |
| 1317 | * hob_feature for [RW] DMA commands, but they are needed for |
| 1318 | * NCQ. NCQ will drop hob_nsect. |
| 1319 | */ |
| 1320 | switch (tf->command) { |
| 1321 | case ATA_CMD_READ: |
| 1322 | case ATA_CMD_READ_EXT: |
| 1323 | case ATA_CMD_WRITE: |
| 1324 | case ATA_CMD_WRITE_EXT: |
Jens Axboe | c15d85c | 2006-02-15 15:59:25 +0100 | [diff] [blame] | 1325 | case ATA_CMD_WRITE_FUA_EXT: |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1326 | mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); |
| 1327 | break; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1328 | case ATA_CMD_FPDMA_READ: |
| 1329 | case ATA_CMD_FPDMA_WRITE: |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 1330 | mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1331 | mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); |
| 1332 | break; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1333 | default: |
| 1334 | /* The only other commands EDMA supports in non-queued and |
| 1335 | * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none |
| 1336 | * of which are defined/used by Linux. If we get here, this |
| 1337 | * driver needs work. |
| 1338 | * |
| 1339 | * FIXME: modify libata to give qc_prep a return value and |
| 1340 | * return error here. |
| 1341 | */ |
| 1342 | BUG_ON(tf->command); |
| 1343 | break; |
| 1344 | } |
| 1345 | mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); |
| 1346 | mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); |
| 1347 | mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); |
| 1348 | mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); |
| 1349 | mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); |
| 1350 | mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); |
| 1351 | mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); |
| 1352 | mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); |
| 1353 | mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ |
| 1354 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1355 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1356 | return; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1357 | mv_fill_sg(qc); |
| 1358 | } |
| 1359 | |
| 1360 | /** |
| 1361 | * mv_qc_prep_iie - Host specific command preparation. |
| 1362 | * @qc: queued command to prepare |
| 1363 | * |
| 1364 | * This routine simply redirects to the general purpose routine |
| 1365 | * if command is not DMA. Else, it handles prep of the CRQB |
| 1366 | * (command request block), does some sanity checking, and calls |
| 1367 | * the SG load routine. |
| 1368 | * |
| 1369 | * LOCKING: |
| 1370 | * Inherited from caller. |
| 1371 | */ |
| 1372 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc) |
| 1373 | { |
| 1374 | struct ata_port *ap = qc->ap; |
| 1375 | struct mv_port_priv *pp = ap->private_data; |
| 1376 | struct mv_crqb_iie *crqb; |
| 1377 | struct ata_taskfile *tf; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1378 | unsigned in_index; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1379 | u32 flags = 0; |
| 1380 | |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 1381 | if ((qc->tf.protocol != ATA_PROT_DMA) && |
| 1382 | (qc->tf.protocol != ATA_PROT_NCQ)) |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1383 | return; |
| 1384 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 1385 | /* Fill in Gen IIE command request block */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1386 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) |
| 1387 | flags |= CRQB_FLAG_READ; |
| 1388 | |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 1389 | WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1390 | flags |= qc->tag << CRQB_TAG_SHIFT; |
Mark Lord | 8c0aeb4 | 2008-01-26 18:31:48 -0500 | [diff] [blame] | 1391 | flags |= qc->tag << CRQB_HOSTQ_SHIFT; |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1392 | flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1393 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1394 | /* get current queue index from software */ |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 1395 | in_index = pp->req_idx; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1396 | |
| 1397 | crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; |
Mark Lord | eb73d55 | 2008-01-29 13:24:00 -0500 | [diff] [blame] | 1398 | crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); |
| 1399 | crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1400 | crqb->flags = cpu_to_le32(flags); |
| 1401 | |
| 1402 | tf = &qc->tf; |
| 1403 | crqb->ata_cmd[0] = cpu_to_le32( |
| 1404 | (tf->command << 16) | |
| 1405 | (tf->feature << 24) |
| 1406 | ); |
| 1407 | crqb->ata_cmd[1] = cpu_to_le32( |
| 1408 | (tf->lbal << 0) | |
| 1409 | (tf->lbam << 8) | |
| 1410 | (tf->lbah << 16) | |
| 1411 | (tf->device << 24) |
| 1412 | ); |
| 1413 | crqb->ata_cmd[2] = cpu_to_le32( |
| 1414 | (tf->hob_lbal << 0) | |
| 1415 | (tf->hob_lbam << 8) | |
| 1416 | (tf->hob_lbah << 16) | |
| 1417 | (tf->hob_feature << 24) |
| 1418 | ); |
| 1419 | crqb->ata_cmd[3] = cpu_to_le32( |
| 1420 | (tf->nsect << 0) | |
| 1421 | (tf->hob_nsect << 8) |
| 1422 | ); |
| 1423 | |
| 1424 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
| 1425 | return; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1426 | mv_fill_sg(qc); |
| 1427 | } |
| 1428 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1429 | /** |
| 1430 | * mv_qc_issue - Initiate a command to the host |
| 1431 | * @qc: queued command to start |
| 1432 | * |
| 1433 | * This routine simply redirects to the general purpose routine |
| 1434 | * if command is not DMA. Else, it sanity checks our local |
| 1435 | * caches of the request producer/consumer indices then enables |
| 1436 | * DMA and bumps the request producer index. |
| 1437 | * |
| 1438 | * LOCKING: |
| 1439 | * Inherited from caller. |
| 1440 | */ |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 1441 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1442 | { |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 1443 | struct ata_port *ap = qc->ap; |
| 1444 | void __iomem *port_mmio = mv_ap_base(ap); |
| 1445 | struct mv_port_priv *pp = ap->private_data; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1446 | u32 in_index; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1447 | |
Mark Lord | 138bfdd | 2008-01-26 18:33:18 -0500 | [diff] [blame] | 1448 | if ((qc->tf.protocol != ATA_PROT_DMA) && |
| 1449 | (qc->tf.protocol != ATA_PROT_NCQ)) { |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 1450 | /* |
| 1451 | * We're about to send a non-EDMA capable command to the |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1452 | * port. Turn off EDMA so there won't be problems accessing |
| 1453 | * shadow block, etc registers. |
| 1454 | */ |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 1455 | mv_stop_edma(ap); |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 1456 | mv_pmp_select(ap, qc->dev->link->pmp); |
Tejun Heo | 9363c38 | 2008-04-07 22:47:16 +0900 | [diff] [blame] | 1457 | return ata_sff_qc_issue(qc); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1458 | } |
| 1459 | |
Mark Lord | 7210916 | 2008-01-26 18:31:33 -0500 | [diff] [blame] | 1460 | mv_start_dma(ap, port_mmio, pp, qc->tf.protocol); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1461 | |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 1462 | pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; |
| 1463 | in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1464 | |
| 1465 | /* and write the request in pointer to kick the EDMA to life */ |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1466 | writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, |
| 1467 | port_mmio + EDMA_REQ_Q_IN_PTR_OFS); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1468 | |
| 1469 | return 0; |
| 1470 | } |
| 1471 | |
Mark Lord | 8f767f8 | 2008-04-19 14:53:07 -0400 | [diff] [blame] | 1472 | static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) |
| 1473 | { |
| 1474 | struct mv_port_priv *pp = ap->private_data; |
| 1475 | struct ata_queued_cmd *qc; |
| 1476 | |
| 1477 | if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) |
| 1478 | return NULL; |
| 1479 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
| 1480 | if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) |
| 1481 | qc = NULL; |
| 1482 | return qc; |
| 1483 | } |
| 1484 | |
| 1485 | static void mv_unexpected_intr(struct ata_port *ap) |
| 1486 | { |
| 1487 | struct mv_port_priv *pp = ap->private_data; |
| 1488 | struct ata_eh_info *ehi = &ap->link.eh_info; |
| 1489 | char *when = ""; |
| 1490 | |
| 1491 | /* |
| 1492 | * We got a device interrupt from something that |
| 1493 | * was supposed to be using EDMA or polling. |
| 1494 | */ |
| 1495 | ata_ehi_clear_desc(ehi); |
| 1496 | if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { |
| 1497 | when = " while EDMA enabled"; |
| 1498 | } else { |
| 1499 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); |
| 1500 | if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) |
| 1501 | when = " while polling"; |
| 1502 | } |
| 1503 | ata_ehi_push_desc(ehi, "unexpected device interrupt%s", when); |
| 1504 | ehi->err_mask |= AC_ERR_OTHER; |
| 1505 | ehi->action |= ATA_EH_RESET; |
| 1506 | ata_port_freeze(ap); |
| 1507 | } |
| 1508 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1509 | /** |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1510 | * mv_err_intr - Handle error interrupts on the port |
| 1511 | * @ap: ATA channel to manipulate |
Mark Lord | 8d07379 | 2008-04-19 15:07:49 -0400 | [diff] [blame] | 1512 | * @qc: affected command (non-NCQ), or NULL |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1513 | * |
Mark Lord | 8d07379 | 2008-04-19 15:07:49 -0400 | [diff] [blame] | 1514 | * Most cases require a full reset of the chip's state machine, |
| 1515 | * which also performs a COMRESET. |
| 1516 | * Also, if the port disabled DMA, update our cached copy to match. |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1517 | * |
| 1518 | * LOCKING: |
| 1519 | * Inherited from caller. |
| 1520 | */ |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1521 | static void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1522 | { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1523 | void __iomem *port_mmio = mv_ap_base(ap); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1524 | u32 edma_err_cause, eh_freeze_mask, serr = 0; |
| 1525 | struct mv_port_priv *pp = ap->private_data; |
| 1526 | struct mv_host_priv *hpriv = ap->host->private_data; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1527 | unsigned int action = 0, err_mask = 0; |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 1528 | struct ata_eh_info *ehi = &ap->link.eh_info; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1529 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1530 | ata_ehi_clear_desc(ehi); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1531 | |
Mark Lord | 8d07379 | 2008-04-19 15:07:49 -0400 | [diff] [blame] | 1532 | /* |
| 1533 | * Read and clear the err_cause bits. This won't actually |
| 1534 | * clear for some errors (eg. SError), but we will be doing |
| 1535 | * a hard reset in those cases regardless, which *will* clear it. |
| 1536 | */ |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1537 | edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
Mark Lord | 8d07379 | 2008-04-19 15:07:49 -0400 | [diff] [blame] | 1538 | writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1539 | |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 1540 | ata_ehi_push_desc(ehi, "edma_err_cause=%08x", edma_err_cause); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1541 | |
| 1542 | /* |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 1543 | * All generations share these EDMA error cause bits: |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1544 | */ |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1545 | if (edma_err_cause & EDMA_ERR_DEV) |
| 1546 | err_mask |= AC_ERR_DEV; |
| 1547 | if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 1548 | EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1549 | EDMA_ERR_INTRL_PAR)) { |
| 1550 | err_mask |= AC_ERR_ATA_BUS; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 1551 | action |= ATA_EH_RESET; |
Tejun Heo | b64bbc3 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1552 | ata_ehi_push_desc(ehi, "parity error"); |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 1553 | } |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1554 | if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { |
| 1555 | ata_ehi_hotplugged(ehi); |
| 1556 | ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? |
Tejun Heo | b64bbc3 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1557 | "dev disconnect" : "dev connect"); |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 1558 | action |= ATA_EH_RESET; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1559 | } |
| 1560 | |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 1561 | /* |
| 1562 | * Gen-I has a different SELF_DIS bit, |
| 1563 | * different FREEZE bits, and no SERR bit: |
| 1564 | */ |
Jeff Garzik | ee9ccdf | 2007-07-12 15:51:22 -0400 | [diff] [blame] | 1565 | if (IS_GEN_I(hpriv)) { |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1566 | eh_freeze_mask = EDMA_EH_FREEZE_5; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1567 | if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1568 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
Tejun Heo | b64bbc3 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1569 | ata_ehi_push_desc(ehi, "EDMA self-disable"); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1570 | } |
| 1571 | } else { |
| 1572 | eh_freeze_mask = EDMA_EH_FREEZE; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1573 | if (edma_err_cause & EDMA_ERR_SELF_DIS) { |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1574 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
Tejun Heo | b64bbc3 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1575 | ata_ehi_push_desc(ehi, "EDMA self-disable"); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1576 | } |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1577 | if (edma_err_cause & EDMA_ERR_SERR) { |
Mark Lord | 8d07379 | 2008-04-19 15:07:49 -0400 | [diff] [blame] | 1578 | /* |
| 1579 | * Ensure that we read our own SCR, not a pmp link SCR: |
| 1580 | */ |
| 1581 | ap->ops->scr_read(ap, SCR_ERROR, &serr); |
| 1582 | /* |
| 1583 | * Don't clear SError here; leave it for libata-eh: |
| 1584 | */ |
| 1585 | ata_ehi_push_desc(ehi, "SError=%08x", serr); |
| 1586 | err_mask |= AC_ERR_ATA_BUS; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 1587 | action |= ATA_EH_RESET; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1588 | } |
| 1589 | } |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1590 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1591 | if (!err_mask) { |
| 1592 | err_mask = AC_ERR_OTHER; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 1593 | action |= ATA_EH_RESET; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1594 | } |
| 1595 | |
| 1596 | ehi->serror |= serr; |
| 1597 | ehi->action |= action; |
| 1598 | |
| 1599 | if (qc) |
| 1600 | qc->err_mask |= err_mask; |
| 1601 | else |
| 1602 | ehi->err_mask |= err_mask; |
| 1603 | |
| 1604 | if (edma_err_cause & eh_freeze_mask) |
| 1605 | ata_port_freeze(ap); |
| 1606 | else |
| 1607 | ata_port_abort(ap); |
| 1608 | } |
| 1609 | |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 1610 | static void mv_process_crpb_response(struct ata_port *ap, |
| 1611 | struct mv_crpb *response, unsigned int tag, int ncq_enabled) |
| 1612 | { |
| 1613 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); |
| 1614 | |
| 1615 | if (qc) { |
| 1616 | u8 ata_status; |
| 1617 | u16 edma_status = le16_to_cpu(response->flags); |
| 1618 | /* |
| 1619 | * edma_status from a response queue entry: |
| 1620 | * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only). |
| 1621 | * MSB is saved ATA status from command completion. |
| 1622 | */ |
| 1623 | if (!ncq_enabled) { |
| 1624 | u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; |
| 1625 | if (err_cause) { |
| 1626 | /* |
| 1627 | * Error will be seen/handled by mv_err_intr(). |
| 1628 | * So do nothing at all here. |
| 1629 | */ |
| 1630 | return; |
| 1631 | } |
| 1632 | } |
| 1633 | ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; |
| 1634 | qc->err_mask |= ac_err_mask(ata_status); |
| 1635 | ata_qc_complete(qc); |
| 1636 | } else { |
| 1637 | ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", |
| 1638 | __func__, tag); |
| 1639 | } |
| 1640 | } |
| 1641 | |
| 1642 | static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1643 | { |
| 1644 | void __iomem *port_mmio = mv_ap_base(ap); |
| 1645 | struct mv_host_priv *hpriv = ap->host->private_data; |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 1646 | u32 in_index; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1647 | bool work_done = false; |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 1648 | int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1649 | |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 1650 | /* Get the hardware queue position index */ |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1651 | in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) |
| 1652 | >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; |
| 1653 | |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 1654 | /* Process new responses from since the last time we looked */ |
| 1655 | while (in_index != pp->resp_idx) { |
Jeff Garzik | 6c1153e | 2007-07-13 15:20:15 -0400 | [diff] [blame] | 1656 | unsigned int tag; |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 1657 | struct mv_crpb *response = &pp->crpb[pp->resp_idx]; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1658 | |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 1659 | pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1660 | |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 1661 | if (IS_GEN_I(hpriv)) { |
| 1662 | /* 50xx: no NCQ, only one command active at a time */ |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 1663 | tag = ap->link.active_tag; |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 1664 | } else { |
| 1665 | /* Gen II/IIE: get command tag from CRPB entry */ |
| 1666 | tag = le16_to_cpu(response->id) & 0x1f; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1667 | } |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 1668 | mv_process_crpb_response(ap, response, tag, ncq_enabled); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1669 | work_done = true; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1670 | } |
| 1671 | |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 1672 | /* Update the software queue position index in hardware */ |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1673 | if (work_done) |
| 1674 | writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 1675 | (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1676 | port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1677 | } |
| 1678 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1679 | /** |
| 1680 | * mv_host_intr - Handle all interrupts on the given host controller |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1681 | * @host: host specific structure |
Mark Lord | 8f767f8 | 2008-04-19 14:53:07 -0400 | [diff] [blame] | 1682 | * @main_cause: Main interrupt cause register for the chip. |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1683 | * |
| 1684 | * LOCKING: |
| 1685 | * Inherited from caller. |
| 1686 | */ |
Mark Lord | a3718c1 | 2008-04-19 15:07:18 -0400 | [diff] [blame] | 1687 | static int mv_host_intr(struct ata_host *host, u32 main_cause) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1688 | { |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 1689 | struct mv_host_priv *hpriv = host->private_data; |
Mark Lord | a3718c1 | 2008-04-19 15:07:18 -0400 | [diff] [blame] | 1690 | void __iomem *mmio = hpriv->base, *hc_mmio = NULL; |
| 1691 | u32 hc_irq_cause = 0; |
| 1692 | unsigned int handled = 0, port; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1693 | |
Mark Lord | a3718c1 | 2008-04-19 15:07:18 -0400 | [diff] [blame] | 1694 | for (port = 0; port < hpriv->n_ports; port++) { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1695 | struct ata_port *ap = host->ports[port]; |
Yinghai Lu | 8f71efe | 2008-02-07 15:06:17 -0800 | [diff] [blame] | 1696 | struct mv_port_priv *pp; |
Mark Lord | a3718c1 | 2008-04-19 15:07:18 -0400 | [diff] [blame] | 1697 | unsigned int shift, hardport, port_cause; |
| 1698 | /* |
| 1699 | * When we move to the second hc, flag our cached |
| 1700 | * copies of hc_mmio (and hc_irq_cause) as invalid again. |
| 1701 | */ |
| 1702 | if (port == MV_PORTS_PER_HC) |
| 1703 | hc_mmio = NULL; |
| 1704 | /* |
| 1705 | * Do nothing if port is not interrupting or is disabled: |
| 1706 | */ |
| 1707 | MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); |
| 1708 | port_cause = (main_cause >> shift) & (DONE_IRQ | ERR_IRQ); |
| 1709 | if (!port_cause || !ap || (ap->flags & ATA_FLAG_DISABLED)) |
Jeff Garzik | a2c91a8 | 2005-11-17 05:44:44 -0500 | [diff] [blame] | 1710 | continue; |
Mark Lord | a3718c1 | 2008-04-19 15:07:18 -0400 | [diff] [blame] | 1711 | /* |
| 1712 | * Each hc within the host has its own hc_irq_cause register. |
| 1713 | * We defer reading it until we know we need it, right now: |
| 1714 | * |
| 1715 | * FIXME later: we don't really need to read this register |
| 1716 | * (some logic changes required below if we go that way), |
| 1717 | * because it doesn't tell us anything new. But we do need |
| 1718 | * to write to it, outside the top of this loop, |
| 1719 | * to reset the interrupt triggers for next time. |
| 1720 | */ |
| 1721 | if (!hc_mmio) { |
| 1722 | hc_mmio = mv_hc_base_from_port(mmio, port); |
| 1723 | hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); |
| 1724 | writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); |
| 1725 | handled = 1; |
| 1726 | } |
Mark Lord | 8f767f8 | 2008-04-19 14:53:07 -0400 | [diff] [blame] | 1727 | /* |
| 1728 | * Process completed CRPB response(s) before other events. |
| 1729 | */ |
Mark Lord | a3718c1 | 2008-04-19 15:07:18 -0400 | [diff] [blame] | 1730 | pp = ap->private_data; |
Mark Lord | 8f767f8 | 2008-04-19 14:53:07 -0400 | [diff] [blame] | 1731 | if (hc_irq_cause & (DMA_IRQ << hardport)) { |
| 1732 | if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) |
Mark Lord | fcfb1f7 | 2008-04-19 15:06:40 -0400 | [diff] [blame] | 1733 | mv_process_crpb_entries(ap, pp); |
Mark Lord | 8f767f8 | 2008-04-19 14:53:07 -0400 | [diff] [blame] | 1734 | } |
| 1735 | /* |
| 1736 | * Handle chip-reported errors, or continue on to handle PIO. |
| 1737 | */ |
| 1738 | if (unlikely(port_cause & ERR_IRQ)) { |
| 1739 | mv_err_intr(ap, mv_get_active_qc(ap)); |
| 1740 | } else if (hc_irq_cause & (DEV_IRQ << hardport)) { |
| 1741 | if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { |
| 1742 | struct ata_queued_cmd *qc = mv_get_active_qc(ap); |
| 1743 | if (qc) { |
| 1744 | ata_sff_host_intr(ap, qc); |
| 1745 | continue; |
| 1746 | } |
| 1747 | } |
| 1748 | mv_unexpected_intr(ap); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1749 | } |
| 1750 | } |
Mark Lord | a3718c1 | 2008-04-19 15:07:18 -0400 | [diff] [blame] | 1751 | return handled; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1752 | } |
| 1753 | |
Mark Lord | a3718c1 | 2008-04-19 15:07:18 -0400 | [diff] [blame] | 1754 | static int mv_pci_error(struct ata_host *host, void __iomem *mmio) |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1755 | { |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 1756 | struct mv_host_priv *hpriv = host->private_data; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1757 | struct ata_port *ap; |
| 1758 | struct ata_queued_cmd *qc; |
| 1759 | struct ata_eh_info *ehi; |
| 1760 | unsigned int i, err_mask, printed = 0; |
| 1761 | u32 err_cause; |
| 1762 | |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 1763 | err_cause = readl(mmio + hpriv->irq_cause_ofs); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1764 | |
| 1765 | dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", |
| 1766 | err_cause); |
| 1767 | |
| 1768 | DPRINTK("All regs @ PCI error\n"); |
| 1769 | mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); |
| 1770 | |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 1771 | writelfl(0, mmio + hpriv->irq_cause_ofs); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1772 | |
| 1773 | for (i = 0; i < host->n_ports; i++) { |
| 1774 | ap = host->ports[i]; |
Tejun Heo | 936fd73 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1775 | if (!ata_link_offline(&ap->link)) { |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 1776 | ehi = &ap->link.eh_info; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1777 | ata_ehi_clear_desc(ehi); |
| 1778 | if (!printed++) |
| 1779 | ata_ehi_push_desc(ehi, |
| 1780 | "PCI err cause 0x%08x", err_cause); |
| 1781 | err_mask = AC_ERR_HOST_BUS; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 1782 | ehi->action = ATA_EH_RESET; |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 1783 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1784 | if (qc) |
| 1785 | qc->err_mask |= err_mask; |
| 1786 | else |
| 1787 | ehi->err_mask |= err_mask; |
| 1788 | |
| 1789 | ata_port_freeze(ap); |
| 1790 | } |
| 1791 | } |
Mark Lord | a3718c1 | 2008-04-19 15:07:18 -0400 | [diff] [blame] | 1792 | return 1; /* handled */ |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1793 | } |
| 1794 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1795 | /** |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 1796 | * mv_interrupt - Main interrupt event handler |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1797 | * @irq: unused |
| 1798 | * @dev_instance: private data; in this case the host structure |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1799 | * |
| 1800 | * Read the read only register to determine if any host |
| 1801 | * controllers have pending interrupts. If so, call lower level |
| 1802 | * routine to handle. Also check for PCI errors which are only |
| 1803 | * reported here. |
| 1804 | * |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 1805 | * LOCKING: |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1806 | * This routine holds the host lock while processing pending |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1807 | * interrupts. |
| 1808 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1809 | static irqreturn_t mv_interrupt(int irq, void *dev_instance) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1810 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1811 | struct ata_host *host = dev_instance; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 1812 | struct mv_host_priv *hpriv = host->private_data; |
Mark Lord | a3718c1 | 2008-04-19 15:07:18 -0400 | [diff] [blame] | 1813 | unsigned int handled = 0; |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 1814 | u32 main_cause, main_mask; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1815 | |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 1816 | spin_lock(&host->lock); |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 1817 | main_cause = readl(hpriv->main_cause_reg_addr); |
| 1818 | main_mask = readl(hpriv->main_mask_reg_addr); |
| 1819 | /* |
| 1820 | * Deal with cases where we either have nothing pending, or have read |
| 1821 | * a bogus register value which can indicate HW removal or PCI fault. |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1822 | */ |
Mark Lord | a3718c1 | 2008-04-19 15:07:18 -0400 | [diff] [blame] | 1823 | if ((main_cause & main_mask) && (main_cause != 0xffffffffU)) { |
| 1824 | if (unlikely((main_cause & PCI_ERR) && HAS_PCI(host))) |
| 1825 | handled = mv_pci_error(host, hpriv->base); |
| 1826 | else |
| 1827 | handled = mv_host_intr(host, main_cause); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 1828 | } |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1829 | spin_unlock(&host->lock); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1830 | return IRQ_RETVAL(handled); |
| 1831 | } |
| 1832 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1833 | static unsigned int mv5_scr_offset(unsigned int sc_reg_in) |
| 1834 | { |
| 1835 | unsigned int ofs; |
| 1836 | |
| 1837 | switch (sc_reg_in) { |
| 1838 | case SCR_STATUS: |
| 1839 | case SCR_ERROR: |
| 1840 | case SCR_CONTROL: |
| 1841 | ofs = sc_reg_in * sizeof(u32); |
| 1842 | break; |
| 1843 | default: |
| 1844 | ofs = 0xffffffffU; |
| 1845 | break; |
| 1846 | } |
| 1847 | return ofs; |
| 1848 | } |
| 1849 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1850 | static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1851 | { |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 1852 | struct mv_host_priv *hpriv = ap->host->private_data; |
| 1853 | void __iomem *mmio = hpriv->base; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1854 | void __iomem *addr = mv5_phy_base(mmio, ap->port_no); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1855 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
| 1856 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1857 | if (ofs != 0xffffffffU) { |
| 1858 | *val = readl(addr + ofs); |
| 1859 | return 0; |
| 1860 | } else |
| 1861 | return -EINVAL; |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1862 | } |
| 1863 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1864 | static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1865 | { |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 1866 | struct mv_host_priv *hpriv = ap->host->private_data; |
| 1867 | void __iomem *mmio = hpriv->base; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1868 | void __iomem *addr = mv5_phy_base(mmio, ap->port_no); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1869 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
| 1870 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1871 | if (ofs != 0xffffffffU) { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1872 | writelfl(val, addr + ofs); |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1873 | return 0; |
| 1874 | } else |
| 1875 | return -EINVAL; |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1876 | } |
| 1877 | |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 1878 | static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 1879 | { |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 1880 | struct pci_dev *pdev = to_pci_dev(host->dev); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 1881 | int early_5080; |
| 1882 | |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 1883 | early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 1884 | |
| 1885 | if (!early_5080) { |
| 1886 | u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); |
| 1887 | tmp |= (1 << 0); |
| 1888 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); |
| 1889 | } |
| 1890 | |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 1891 | mv_reset_pci_bus(host, mmio); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 1892 | } |
| 1893 | |
| 1894 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) |
| 1895 | { |
| 1896 | writel(0x0fcfffff, mmio + MV_FLASH_CTL); |
| 1897 | } |
| 1898 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1899 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1900 | void __iomem *mmio) |
| 1901 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1902 | void __iomem *phy_mmio = mv5_phy_base(mmio, idx); |
| 1903 | u32 tmp; |
| 1904 | |
| 1905 | tmp = readl(phy_mmio + MV5_PHY_MODE); |
| 1906 | |
| 1907 | hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ |
| 1908 | hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1909 | } |
| 1910 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1911 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1912 | { |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 1913 | u32 tmp; |
| 1914 | |
| 1915 | writel(0, mmio + MV_GPIO_PORT_CTL); |
| 1916 | |
| 1917 | /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ |
| 1918 | |
| 1919 | tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); |
| 1920 | tmp |= ~(1 << 0); |
| 1921 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1922 | } |
| 1923 | |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 1924 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1925 | unsigned int port) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1926 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1927 | void __iomem *phy_mmio = mv5_phy_base(mmio, port); |
| 1928 | const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); |
| 1929 | u32 tmp; |
| 1930 | int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); |
| 1931 | |
| 1932 | if (fix_apm_sq) { |
| 1933 | tmp = readl(phy_mmio + MV5_LT_MODE); |
| 1934 | tmp |= (1 << 19); |
| 1935 | writel(tmp, phy_mmio + MV5_LT_MODE); |
| 1936 | |
| 1937 | tmp = readl(phy_mmio + MV5_PHY_CTL); |
| 1938 | tmp &= ~0x3; |
| 1939 | tmp |= 0x1; |
| 1940 | writel(tmp, phy_mmio + MV5_PHY_CTL); |
| 1941 | } |
| 1942 | |
| 1943 | tmp = readl(phy_mmio + MV5_PHY_MODE); |
| 1944 | tmp &= ~mask; |
| 1945 | tmp |= hpriv->signal[port].pre; |
| 1946 | tmp |= hpriv->signal[port].amps; |
| 1947 | writel(tmp, phy_mmio + MV5_PHY_MODE); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1948 | } |
| 1949 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1950 | |
| 1951 | #undef ZERO |
| 1952 | #define ZERO(reg) writel(0, port_mmio + (reg)) |
| 1953 | static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1954 | unsigned int port) |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1955 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1956 | void __iomem *port_mmio = mv_port_base(mmio, port); |
| 1957 | |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 1958 | /* |
| 1959 | * The datasheet warns against setting ATA_RST when EDMA is active |
| 1960 | * (but doesn't say what the problem might be). So we first try |
| 1961 | * to disable the EDMA engine before doing the ATA_RST operation. |
| 1962 | */ |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 1963 | mv_reset_channel(hpriv, mmio, port); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1964 | |
| 1965 | ZERO(0x028); /* command */ |
| 1966 | writel(0x11f, port_mmio + EDMA_CFG_OFS); |
| 1967 | ZERO(0x004); /* timer */ |
| 1968 | ZERO(0x008); /* irq err cause */ |
| 1969 | ZERO(0x00c); /* irq err mask */ |
| 1970 | ZERO(0x010); /* rq bah */ |
| 1971 | ZERO(0x014); /* rq inp */ |
| 1972 | ZERO(0x018); /* rq outp */ |
| 1973 | ZERO(0x01c); /* respq bah */ |
| 1974 | ZERO(0x024); /* respq outp */ |
| 1975 | ZERO(0x020); /* respq inp */ |
| 1976 | ZERO(0x02c); /* test control */ |
| 1977 | writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); |
| 1978 | } |
| 1979 | #undef ZERO |
| 1980 | |
| 1981 | #define ZERO(reg) writel(0, hc_mmio + (reg)) |
| 1982 | static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1983 | unsigned int hc) |
| 1984 | { |
| 1985 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
| 1986 | u32 tmp; |
| 1987 | |
| 1988 | ZERO(0x00c); |
| 1989 | ZERO(0x010); |
| 1990 | ZERO(0x014); |
| 1991 | ZERO(0x018); |
| 1992 | |
| 1993 | tmp = readl(hc_mmio + 0x20); |
| 1994 | tmp &= 0x1c1c1c1c; |
| 1995 | tmp |= 0x03030303; |
| 1996 | writel(tmp, hc_mmio + 0x20); |
| 1997 | } |
| 1998 | #undef ZERO |
| 1999 | |
| 2000 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 2001 | unsigned int n_hc) |
| 2002 | { |
| 2003 | unsigned int hc, port; |
| 2004 | |
| 2005 | for (hc = 0; hc < n_hc; hc++) { |
| 2006 | for (port = 0; port < MV_PORTS_PER_HC; port++) |
| 2007 | mv5_reset_hc_port(hpriv, mmio, |
| 2008 | (hc * MV_PORTS_PER_HC) + port); |
| 2009 | |
| 2010 | mv5_reset_one_hc(hpriv, mmio, hc); |
| 2011 | } |
| 2012 | |
| 2013 | return 0; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2014 | } |
| 2015 | |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 2016 | #undef ZERO |
| 2017 | #define ZERO(reg) writel(0, mmio + (reg)) |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 2018 | static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 2019 | { |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 2020 | struct mv_host_priv *hpriv = host->private_data; |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 2021 | u32 tmp; |
| 2022 | |
| 2023 | tmp = readl(mmio + MV_PCI_MODE); |
| 2024 | tmp &= 0xff00ffff; |
| 2025 | writel(tmp, mmio + MV_PCI_MODE); |
| 2026 | |
| 2027 | ZERO(MV_PCI_DISC_TIMER); |
| 2028 | ZERO(MV_PCI_MSI_TRIGGER); |
| 2029 | writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); |
| 2030 | ZERO(HC_MAIN_IRQ_MASK_OFS); |
| 2031 | ZERO(MV_PCI_SERR_MASK); |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 2032 | ZERO(hpriv->irq_cause_ofs); |
| 2033 | ZERO(hpriv->irq_mask_ofs); |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 2034 | ZERO(MV_PCI_ERR_LOW_ADDRESS); |
| 2035 | ZERO(MV_PCI_ERR_HIGH_ADDRESS); |
| 2036 | ZERO(MV_PCI_ERR_ATTRIBUTE); |
| 2037 | ZERO(MV_PCI_ERR_COMMAND); |
| 2038 | } |
| 2039 | #undef ZERO |
| 2040 | |
| 2041 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) |
| 2042 | { |
| 2043 | u32 tmp; |
| 2044 | |
| 2045 | mv5_reset_flash(hpriv, mmio); |
| 2046 | |
| 2047 | tmp = readl(mmio + MV_GPIO_PORT_CTL); |
| 2048 | tmp &= 0x3; |
| 2049 | tmp |= (1 << 5) | (1 << 6); |
| 2050 | writel(tmp, mmio + MV_GPIO_PORT_CTL); |
| 2051 | } |
| 2052 | |
| 2053 | /** |
| 2054 | * mv6_reset_hc - Perform the 6xxx global soft reset |
| 2055 | * @mmio: base address of the HBA |
| 2056 | * |
| 2057 | * This routine only applies to 6xxx parts. |
| 2058 | * |
| 2059 | * LOCKING: |
| 2060 | * Inherited from caller. |
| 2061 | */ |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2062 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 2063 | unsigned int n_hc) |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 2064 | { |
| 2065 | void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; |
| 2066 | int i, rc = 0; |
| 2067 | u32 t; |
| 2068 | |
| 2069 | /* Following procedure defined in PCI "main command and status |
| 2070 | * register" table. |
| 2071 | */ |
| 2072 | t = readl(reg); |
| 2073 | writel(t | STOP_PCI_MASTER, reg); |
| 2074 | |
| 2075 | for (i = 0; i < 1000; i++) { |
| 2076 | udelay(1); |
| 2077 | t = readl(reg); |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 2078 | if (PCI_MASTER_EMPTY & t) |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 2079 | break; |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 2080 | } |
| 2081 | if (!(PCI_MASTER_EMPTY & t)) { |
| 2082 | printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); |
| 2083 | rc = 1; |
| 2084 | goto done; |
| 2085 | } |
| 2086 | |
| 2087 | /* set reset */ |
| 2088 | i = 5; |
| 2089 | do { |
| 2090 | writel(t | GLOB_SFT_RST, reg); |
| 2091 | t = readl(reg); |
| 2092 | udelay(1); |
| 2093 | } while (!(GLOB_SFT_RST & t) && (i-- > 0)); |
| 2094 | |
| 2095 | if (!(GLOB_SFT_RST & t)) { |
| 2096 | printk(KERN_ERR DRV_NAME ": can't set global reset\n"); |
| 2097 | rc = 1; |
| 2098 | goto done; |
| 2099 | } |
| 2100 | |
| 2101 | /* clear reset and *reenable the PCI master* (not mentioned in spec) */ |
| 2102 | i = 5; |
| 2103 | do { |
| 2104 | writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); |
| 2105 | t = readl(reg); |
| 2106 | udelay(1); |
| 2107 | } while ((GLOB_SFT_RST & t) && (i-- > 0)); |
| 2108 | |
| 2109 | if (GLOB_SFT_RST & t) { |
| 2110 | printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); |
| 2111 | rc = 1; |
| 2112 | } |
| 2113 | done: |
| 2114 | return rc; |
| 2115 | } |
| 2116 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2117 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 2118 | void __iomem *mmio) |
| 2119 | { |
| 2120 | void __iomem *port_mmio; |
| 2121 | u32 tmp; |
| 2122 | |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 2123 | tmp = readl(mmio + MV_RESET_CFG); |
| 2124 | if ((tmp & (1 << 0)) == 0) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2125 | hpriv->signal[idx].amps = 0x7 << 8; |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 2126 | hpriv->signal[idx].pre = 0x1 << 5; |
| 2127 | return; |
| 2128 | } |
| 2129 | |
| 2130 | port_mmio = mv_port_base(mmio, idx); |
| 2131 | tmp = readl(port_mmio + PHY_MODE2); |
| 2132 | |
| 2133 | hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ |
| 2134 | hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ |
| 2135 | } |
| 2136 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2137 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 2138 | { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2139 | writel(0x00000060, mmio + MV_GPIO_PORT_CTL); |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 2140 | } |
| 2141 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2142 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 2143 | unsigned int port) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2144 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2145 | void __iomem *port_mmio = mv_port_base(mmio, port); |
| 2146 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2147 | u32 hp_flags = hpriv->hp_flags; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2148 | int fix_phy_mode2 = |
| 2149 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2150 | int fix_phy_mode4 = |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2151 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); |
| 2152 | u32 m2, tmp; |
| 2153 | |
| 2154 | if (fix_phy_mode2) { |
| 2155 | m2 = readl(port_mmio + PHY_MODE2); |
| 2156 | m2 &= ~(1 << 16); |
| 2157 | m2 |= (1 << 31); |
| 2158 | writel(m2, port_mmio + PHY_MODE2); |
| 2159 | |
| 2160 | udelay(200); |
| 2161 | |
| 2162 | m2 = readl(port_mmio + PHY_MODE2); |
| 2163 | m2 &= ~((1 << 16) | (1 << 31)); |
| 2164 | writel(m2, port_mmio + PHY_MODE2); |
| 2165 | |
| 2166 | udelay(200); |
| 2167 | } |
| 2168 | |
| 2169 | /* who knows what this magic does */ |
| 2170 | tmp = readl(port_mmio + PHY_MODE3); |
| 2171 | tmp &= ~0x7F800000; |
| 2172 | tmp |= 0x2A800000; |
| 2173 | writel(tmp, port_mmio + PHY_MODE3); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2174 | |
| 2175 | if (fix_phy_mode4) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2176 | u32 m4; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2177 | |
| 2178 | m4 = readl(port_mmio + PHY_MODE4); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2179 | |
| 2180 | if (hp_flags & MV_HP_ERRATA_60X1B2) |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 2181 | tmp = readl(port_mmio + PHY_MODE3); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2182 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 2183 | /* workaround for errata FEr SATA#10 (part 1) */ |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2184 | m4 = (m4 & ~(1 << 1)) | (1 << 0); |
| 2185 | |
| 2186 | writel(m4, port_mmio + PHY_MODE4); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2187 | |
| 2188 | if (hp_flags & MV_HP_ERRATA_60X1B2) |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 2189 | writel(tmp, port_mmio + PHY_MODE3); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2190 | } |
| 2191 | |
| 2192 | /* Revert values of pre-emphasis and signal amps to the saved ones */ |
| 2193 | m2 = readl(port_mmio + PHY_MODE2); |
| 2194 | |
| 2195 | m2 &= ~MV_M2_PREAMP_MASK; |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 2196 | m2 |= hpriv->signal[port].amps; |
| 2197 | m2 |= hpriv->signal[port].pre; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2198 | m2 &= ~(1 << 16); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2199 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 2200 | /* according to mvSata 3.6.1, some IIE values are fixed */ |
| 2201 | if (IS_GEN_IIE(hpriv)) { |
| 2202 | m2 &= ~0xC30FF01F; |
| 2203 | m2 |= 0x0000900F; |
| 2204 | } |
| 2205 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2206 | writel(m2, port_mmio + PHY_MODE2); |
| 2207 | } |
| 2208 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2209 | /* TODO: use the generic LED interface to configure the SATA Presence */ |
| 2210 | /* & Acitivy LEDs on the board */ |
| 2211 | static void mv_soc_enable_leds(struct mv_host_priv *hpriv, |
| 2212 | void __iomem *mmio) |
| 2213 | { |
| 2214 | return; |
| 2215 | } |
| 2216 | |
| 2217 | static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, |
| 2218 | void __iomem *mmio) |
| 2219 | { |
| 2220 | void __iomem *port_mmio; |
| 2221 | u32 tmp; |
| 2222 | |
| 2223 | port_mmio = mv_port_base(mmio, idx); |
| 2224 | tmp = readl(port_mmio + PHY_MODE2); |
| 2225 | |
| 2226 | hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ |
| 2227 | hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ |
| 2228 | } |
| 2229 | |
| 2230 | #undef ZERO |
| 2231 | #define ZERO(reg) writel(0, port_mmio + (reg)) |
| 2232 | static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, |
| 2233 | void __iomem *mmio, unsigned int port) |
| 2234 | { |
| 2235 | void __iomem *port_mmio = mv_port_base(mmio, port); |
| 2236 | |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 2237 | /* |
| 2238 | * The datasheet warns against setting ATA_RST when EDMA is active |
| 2239 | * (but doesn't say what the problem might be). So we first try |
| 2240 | * to disable the EDMA engine before doing the ATA_RST operation. |
| 2241 | */ |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 2242 | mv_reset_channel(hpriv, mmio, port); |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2243 | |
| 2244 | ZERO(0x028); /* command */ |
| 2245 | writel(0x101f, port_mmio + EDMA_CFG_OFS); |
| 2246 | ZERO(0x004); /* timer */ |
| 2247 | ZERO(0x008); /* irq err cause */ |
| 2248 | ZERO(0x00c); /* irq err mask */ |
| 2249 | ZERO(0x010); /* rq bah */ |
| 2250 | ZERO(0x014); /* rq inp */ |
| 2251 | ZERO(0x018); /* rq outp */ |
| 2252 | ZERO(0x01c); /* respq bah */ |
| 2253 | ZERO(0x024); /* respq outp */ |
| 2254 | ZERO(0x020); /* respq inp */ |
| 2255 | ZERO(0x02c); /* test control */ |
| 2256 | writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); |
| 2257 | } |
| 2258 | |
| 2259 | #undef ZERO |
| 2260 | |
| 2261 | #define ZERO(reg) writel(0, hc_mmio + (reg)) |
| 2262 | static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, |
| 2263 | void __iomem *mmio) |
| 2264 | { |
| 2265 | void __iomem *hc_mmio = mv_hc_base(mmio, 0); |
| 2266 | |
| 2267 | ZERO(0x00c); |
| 2268 | ZERO(0x010); |
| 2269 | ZERO(0x014); |
| 2270 | |
| 2271 | } |
| 2272 | |
| 2273 | #undef ZERO |
| 2274 | |
| 2275 | static int mv_soc_reset_hc(struct mv_host_priv *hpriv, |
| 2276 | void __iomem *mmio, unsigned int n_hc) |
| 2277 | { |
| 2278 | unsigned int port; |
| 2279 | |
| 2280 | for (port = 0; port < hpriv->n_ports; port++) |
| 2281 | mv_soc_reset_hc_port(hpriv, mmio, port); |
| 2282 | |
| 2283 | mv_soc_reset_one_hc(hpriv, mmio); |
| 2284 | |
| 2285 | return 0; |
| 2286 | } |
| 2287 | |
| 2288 | static void mv_soc_reset_flash(struct mv_host_priv *hpriv, |
| 2289 | void __iomem *mmio) |
| 2290 | { |
| 2291 | return; |
| 2292 | } |
| 2293 | |
| 2294 | static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) |
| 2295 | { |
| 2296 | return; |
| 2297 | } |
| 2298 | |
Mark Lord | b67a106 | 2008-03-31 19:35:13 -0400 | [diff] [blame] | 2299 | static void mv_setup_ifctl(void __iomem *port_mmio, int want_gen2i) |
| 2300 | { |
| 2301 | u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG); |
| 2302 | |
| 2303 | ifctl = (ifctl & 0xf7f) | 0x9b1000; /* from chip spec */ |
| 2304 | if (want_gen2i) |
| 2305 | ifctl |= (1 << 7); /* enable gen2i speed */ |
| 2306 | writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG); |
| 2307 | } |
| 2308 | |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 2309 | /* |
| 2310 | * Caller must ensure that EDMA is not active, |
| 2311 | * by first doing mv_stop_edma() where needed. |
| 2312 | */ |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 2313 | static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2314 | unsigned int port_no) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2315 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2316 | void __iomem *port_mmio = mv_port_base(mmio, port_no); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2317 | |
Mark Lord | 0d8be5c | 2008-04-16 14:56:12 -0400 | [diff] [blame] | 2318 | mv_stop_edma_engine(port_mmio); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2319 | writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2320 | |
Mark Lord | b67a106 | 2008-03-31 19:35:13 -0400 | [diff] [blame] | 2321 | if (!IS_GEN_I(hpriv)) { |
| 2322 | /* Enable 3.0gb/s link speed */ |
| 2323 | mv_setup_ifctl(port_mmio, 1); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2324 | } |
Mark Lord | b67a106 | 2008-03-31 19:35:13 -0400 | [diff] [blame] | 2325 | /* |
| 2326 | * Strobing ATA_RST here causes a hard reset of the SATA transport, |
| 2327 | * link, and physical layers. It resets all SATA interface registers |
| 2328 | * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2329 | */ |
Mark Lord | b67a106 | 2008-03-31 19:35:13 -0400 | [diff] [blame] | 2330 | writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); |
| 2331 | udelay(25); /* allow reset propagation */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2332 | writelfl(0, port_mmio + EDMA_CMD_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2333 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2334 | hpriv->ops->phy_errata(hpriv, mmio, port_no); |
| 2335 | |
Jeff Garzik | ee9ccdf | 2007-07-12 15:51:22 -0400 | [diff] [blame] | 2336 | if (IS_GEN_I(hpriv)) |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2337 | mdelay(1); |
| 2338 | } |
| 2339 | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 2340 | static void mv_pmp_select(struct ata_port *ap, int pmp) |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2341 | { |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 2342 | if (sata_pmp_supported(ap)) { |
| 2343 | void __iomem *port_mmio = mv_ap_base(ap); |
| 2344 | u32 reg = readl(port_mmio + SATA_IFCTL_OFS); |
| 2345 | int old = reg & 0xf; |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2346 | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 2347 | if (old != pmp) { |
| 2348 | reg = (reg & ~0xf) | pmp; |
| 2349 | writelfl(reg, port_mmio + SATA_IFCTL_OFS); |
| 2350 | } |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 2351 | } |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2352 | } |
| 2353 | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 2354 | static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, |
| 2355 | unsigned long deadline) |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 2356 | { |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 2357 | mv_pmp_select(link->ap, sata_srst_pmp(link)); |
| 2358 | return sata_std_hardreset(link, class, deadline); |
| 2359 | } |
Jeff Garzik | 0ea9e17 | 2007-07-13 17:06:45 -0400 | [diff] [blame] | 2360 | |
Mark Lord | e49856d | 2008-04-16 14:59:07 -0400 | [diff] [blame] | 2361 | static int mv_softreset(struct ata_link *link, unsigned int *class, |
| 2362 | unsigned long deadline) |
| 2363 | { |
| 2364 | mv_pmp_select(link->ap, sata_srst_pmp(link)); |
| 2365 | return ata_sff_softreset(link, class, deadline); |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 2366 | } |
| 2367 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 2368 | static int mv_hardreset(struct ata_link *link, unsigned int *class, |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2369 | unsigned long deadline) |
| 2370 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 2371 | struct ata_port *ap = link->ap; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2372 | struct mv_host_priv *hpriv = ap->host->private_data; |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 2373 | struct mv_port_priv *pp = ap->private_data; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2374 | void __iomem *mmio = hpriv->base; |
Mark Lord | 0d8be5c | 2008-04-16 14:56:12 -0400 | [diff] [blame] | 2375 | int rc, attempts = 0, extra = 0; |
| 2376 | u32 sstatus; |
| 2377 | bool online; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2378 | |
Mark Lord | e12bef5 | 2008-03-31 19:33:56 -0400 | [diff] [blame] | 2379 | mv_reset_channel(hpriv, mmio, ap->port_no); |
Mark Lord | b562468 | 2008-03-31 19:34:40 -0400 | [diff] [blame] | 2380 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2381 | |
Mark Lord | 0d8be5c | 2008-04-16 14:56:12 -0400 | [diff] [blame] | 2382 | /* Workaround for errata FEr SATA#10 (part 2) */ |
| 2383 | do { |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 2384 | const unsigned long *timing = |
| 2385 | sata_ehc_deb_timing(&link->eh_context); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2386 | |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 2387 | rc = sata_link_hardreset(link, timing, deadline + extra, |
| 2388 | &online, NULL); |
| 2389 | if (rc) |
Mark Lord | 0d8be5c | 2008-04-16 14:56:12 -0400 | [diff] [blame] | 2390 | return rc; |
Mark Lord | 0d8be5c | 2008-04-16 14:56:12 -0400 | [diff] [blame] | 2391 | sata_scr_read(link, SCR_STATUS, &sstatus); |
| 2392 | if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { |
| 2393 | /* Force 1.5gb/s link speed and try again */ |
| 2394 | mv_setup_ifctl(mv_ap_base(ap), 0); |
| 2395 | if (time_after(jiffies + HZ, deadline)) |
| 2396 | extra = HZ; /* only extend it once, max */ |
| 2397 | } |
| 2398 | } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2399 | |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 2400 | return rc; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2401 | } |
| 2402 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2403 | static void mv_eh_freeze(struct ata_port *ap) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2404 | { |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2405 | struct mv_host_priv *hpriv = ap->host->private_data; |
Mark Lord | 1cfd19a | 2008-04-19 15:05:50 -0400 | [diff] [blame] | 2406 | unsigned int shift, hardport, port = ap->port_no; |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 2407 | u32 main_mask; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2408 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2409 | /* FIXME: handle coalescing completion events properly */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2410 | |
Mark Lord | 1cfd19a | 2008-04-19 15:05:50 -0400 | [diff] [blame] | 2411 | mv_stop_edma(ap); |
| 2412 | MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2413 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2414 | /* disable assertion of portN err, done events */ |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 2415 | main_mask = readl(hpriv->main_mask_reg_addr); |
| 2416 | main_mask &= ~((DONE_IRQ | ERR_IRQ) << shift); |
| 2417 | writelfl(main_mask, hpriv->main_mask_reg_addr); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2418 | } |
| 2419 | |
| 2420 | static void mv_eh_thaw(struct ata_port *ap) |
| 2421 | { |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2422 | struct mv_host_priv *hpriv = ap->host->private_data; |
Mark Lord | 1cfd19a | 2008-04-19 15:05:50 -0400 | [diff] [blame] | 2423 | unsigned int shift, hardport, port = ap->port_no; |
| 2424 | void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2425 | void __iomem *port_mmio = mv_ap_base(ap); |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 2426 | u32 main_mask, hc_irq_cause; |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2427 | |
| 2428 | /* FIXME: handle coalescing completion events properly */ |
| 2429 | |
Mark Lord | 1cfd19a | 2008-04-19 15:05:50 -0400 | [diff] [blame] | 2430 | MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2431 | |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2432 | /* clear EDMA errors on this port */ |
| 2433 | writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
| 2434 | |
| 2435 | /* clear pending irq events */ |
| 2436 | hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); |
Mark Lord | 1cfd19a | 2008-04-19 15:05:50 -0400 | [diff] [blame] | 2437 | hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport); |
| 2438 | writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); |
Jeff Garzik | bdd4ddd | 2007-07-12 14:34:26 -0400 | [diff] [blame] | 2439 | |
| 2440 | /* enable assertion of portN err, done events */ |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 2441 | main_mask = readl(hpriv->main_mask_reg_addr); |
| 2442 | main_mask |= ((DONE_IRQ | ERR_IRQ) << shift); |
| 2443 | writelfl(main_mask, hpriv->main_mask_reg_addr); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2444 | } |
| 2445 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2446 | /** |
| 2447 | * mv_port_init - Perform some early initialization on a single port. |
| 2448 | * @port: libata data structure storing shadow register addresses |
| 2449 | * @port_mmio: base address of the port |
| 2450 | * |
| 2451 | * Initialize shadow register mmio addresses, clear outstanding |
| 2452 | * interrupts on the port, and unmask interrupts for the future |
| 2453 | * start of the port. |
| 2454 | * |
| 2455 | * LOCKING: |
| 2456 | * Inherited from caller. |
| 2457 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2458 | static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) |
| 2459 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2460 | void __iomem *shd_base = port_mmio + SHD_BLK_OFS; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2461 | unsigned serr_ofs; |
| 2462 | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2463 | /* PIO related setup |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2464 | */ |
| 2465 | port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2466 | port->error_addr = |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2467 | port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); |
| 2468 | port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); |
| 2469 | port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); |
| 2470 | port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); |
| 2471 | port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); |
| 2472 | port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2473 | port->status_addr = |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2474 | port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); |
| 2475 | /* special case: control/altstatus doesn't have ATA_REG_ address */ |
| 2476 | port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; |
| 2477 | |
| 2478 | /* unused: */ |
Randy Dunlap | 8d9db2d | 2007-02-16 01:40:06 -0800 | [diff] [blame] | 2479 | port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2480 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2481 | /* Clear any currently outstanding port interrupt conditions */ |
| 2482 | serr_ofs = mv_scr_offset(SCR_ERROR); |
| 2483 | writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); |
| 2484 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
| 2485 | |
Mark Lord | 646a4da | 2008-01-26 18:30:37 -0500 | [diff] [blame] | 2486 | /* unmask all non-transient EDMA error interrupts */ |
| 2487 | writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2488 | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2489 | VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2490 | readl(port_mmio + EDMA_CFG_OFS), |
| 2491 | readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), |
| 2492 | readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2493 | } |
| 2494 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2495 | static int mv_chip_id(struct ata_host *host, unsigned int board_idx) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2496 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2497 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 2498 | struct mv_host_priv *hpriv = host->private_data; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2499 | u32 hp_flags = hpriv->hp_flags; |
| 2500 | |
Jeff Garzik | 5796d1c | 2007-10-26 00:03:37 -0400 | [diff] [blame] | 2501 | switch (board_idx) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2502 | case chip_5080: |
| 2503 | hpriv->ops = &mv5xxx_ops; |
Jeff Garzik | ee9ccdf | 2007-07-12 15:51:22 -0400 | [diff] [blame] | 2504 | hp_flags |= MV_HP_GEN_I; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2505 | |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 2506 | switch (pdev->revision) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2507 | case 0x1: |
| 2508 | hp_flags |= MV_HP_ERRATA_50XXB0; |
| 2509 | break; |
| 2510 | case 0x3: |
| 2511 | hp_flags |= MV_HP_ERRATA_50XXB2; |
| 2512 | break; |
| 2513 | default: |
| 2514 | dev_printk(KERN_WARNING, &pdev->dev, |
| 2515 | "Applying 50XXB2 workarounds to unknown rev\n"); |
| 2516 | hp_flags |= MV_HP_ERRATA_50XXB2; |
| 2517 | break; |
| 2518 | } |
| 2519 | break; |
| 2520 | |
| 2521 | case chip_504x: |
| 2522 | case chip_508x: |
| 2523 | hpriv->ops = &mv5xxx_ops; |
Jeff Garzik | ee9ccdf | 2007-07-12 15:51:22 -0400 | [diff] [blame] | 2524 | hp_flags |= MV_HP_GEN_I; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2525 | |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 2526 | switch (pdev->revision) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2527 | case 0x0: |
| 2528 | hp_flags |= MV_HP_ERRATA_50XXB0; |
| 2529 | break; |
| 2530 | case 0x3: |
| 2531 | hp_flags |= MV_HP_ERRATA_50XXB2; |
| 2532 | break; |
| 2533 | default: |
| 2534 | dev_printk(KERN_WARNING, &pdev->dev, |
| 2535 | "Applying B2 workarounds to unknown rev\n"); |
| 2536 | hp_flags |= MV_HP_ERRATA_50XXB2; |
| 2537 | break; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2538 | } |
| 2539 | break; |
| 2540 | |
| 2541 | case chip_604x: |
| 2542 | case chip_608x: |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2543 | hpriv->ops = &mv6xxx_ops; |
Jeff Garzik | ee9ccdf | 2007-07-12 15:51:22 -0400 | [diff] [blame] | 2544 | hp_flags |= MV_HP_GEN_II; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2545 | |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 2546 | switch (pdev->revision) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2547 | case 0x7: |
| 2548 | hp_flags |= MV_HP_ERRATA_60X1B2; |
| 2549 | break; |
| 2550 | case 0x9: |
| 2551 | hp_flags |= MV_HP_ERRATA_60X1C0; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2552 | break; |
| 2553 | default: |
| 2554 | dev_printk(KERN_WARNING, &pdev->dev, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2555 | "Applying B2 workarounds to unknown rev\n"); |
| 2556 | hp_flags |= MV_HP_ERRATA_60X1B2; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2557 | break; |
| 2558 | } |
| 2559 | break; |
| 2560 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 2561 | case chip_7042: |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 2562 | hp_flags |= MV_HP_PCIE; |
Mark Lord | 306b30f | 2007-12-04 14:07:52 -0500 | [diff] [blame] | 2563 | if (pdev->vendor == PCI_VENDOR_ID_TTI && |
| 2564 | (pdev->device == 0x2300 || pdev->device == 0x2310)) |
| 2565 | { |
Mark Lord | 4e52003 | 2007-12-11 12:58:05 -0500 | [diff] [blame] | 2566 | /* |
| 2567 | * Highpoint RocketRAID PCIe 23xx series cards: |
| 2568 | * |
| 2569 | * Unconfigured drives are treated as "Legacy" |
| 2570 | * by the BIOS, and it overwrites sector 8 with |
| 2571 | * a "Lgcy" metadata block prior to Linux boot. |
| 2572 | * |
| 2573 | * Configured drives (RAID or JBOD) leave sector 8 |
| 2574 | * alone, but instead overwrite a high numbered |
| 2575 | * sector for the RAID metadata. This sector can |
| 2576 | * be determined exactly, by truncating the physical |
| 2577 | * drive capacity to a nice even GB value. |
| 2578 | * |
| 2579 | * RAID metadata is at: (dev->n_sectors & ~0xfffff) |
| 2580 | * |
| 2581 | * Warn the user, lest they think we're just buggy. |
| 2582 | */ |
| 2583 | printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" |
| 2584 | " BIOS CORRUPTS DATA on all attached drives," |
| 2585 | " regardless of if/how they are configured." |
| 2586 | " BEWARE!\n"); |
| 2587 | printk(KERN_WARNING DRV_NAME ": For data safety, do not" |
| 2588 | " use sectors 8-9 on \"Legacy\" drives," |
| 2589 | " and avoid the final two gigabytes on" |
| 2590 | " all RocketRAID BIOS initialized drives.\n"); |
Mark Lord | 306b30f | 2007-12-04 14:07:52 -0500 | [diff] [blame] | 2591 | } |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 2592 | case chip_6042: |
| 2593 | hpriv->ops = &mv6xxx_ops; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 2594 | hp_flags |= MV_HP_GEN_IIE; |
| 2595 | |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 2596 | switch (pdev->revision) { |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 2597 | case 0x0: |
| 2598 | hp_flags |= MV_HP_ERRATA_XX42A0; |
| 2599 | break; |
| 2600 | case 0x1: |
| 2601 | hp_flags |= MV_HP_ERRATA_60X1C0; |
| 2602 | break; |
| 2603 | default: |
| 2604 | dev_printk(KERN_WARNING, &pdev->dev, |
| 2605 | "Applying 60X1C0 workarounds to unknown rev\n"); |
| 2606 | hp_flags |= MV_HP_ERRATA_60X1C0; |
| 2607 | break; |
| 2608 | } |
| 2609 | break; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2610 | case chip_soc: |
| 2611 | hpriv->ops = &mv_soc_ops; |
| 2612 | hp_flags |= MV_HP_ERRATA_60X1C0; |
| 2613 | break; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 2614 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2615 | default: |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2616 | dev_printk(KERN_ERR, host->dev, |
Jeff Garzik | 5796d1c | 2007-10-26 00:03:37 -0400 | [diff] [blame] | 2617 | "BUG: invalid board index %u\n", board_idx); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2618 | return 1; |
| 2619 | } |
| 2620 | |
| 2621 | hpriv->hp_flags = hp_flags; |
Mark Lord | 02a121d | 2007-12-01 13:07:22 -0500 | [diff] [blame] | 2622 | if (hp_flags & MV_HP_PCIE) { |
| 2623 | hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; |
| 2624 | hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; |
| 2625 | hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; |
| 2626 | } else { |
| 2627 | hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; |
| 2628 | hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; |
| 2629 | hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; |
| 2630 | } |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2631 | |
| 2632 | return 0; |
| 2633 | } |
| 2634 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2635 | /** |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2636 | * mv_init_host - Perform some early initialization of the host. |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2637 | * @host: ATA host to initialize |
| 2638 | * @board_idx: controller index |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2639 | * |
| 2640 | * If possible, do an early global reset of the host. Then do |
| 2641 | * our port init and clear/unmask all/relevant host interrupts. |
| 2642 | * |
| 2643 | * LOCKING: |
| 2644 | * Inherited from caller. |
| 2645 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2646 | static int mv_init_host(struct ata_host *host, unsigned int board_idx) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2647 | { |
| 2648 | int rc = 0, n_hc, port, hc; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2649 | struct mv_host_priv *hpriv = host->private_data; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2650 | void __iomem *mmio = hpriv->base; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2651 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2652 | rc = mv_chip_id(host, board_idx); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2653 | if (rc) |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 2654 | goto done; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2655 | |
| 2656 | if (HAS_PCI(host)) { |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 2657 | hpriv->main_cause_reg_addr = mmio + HC_MAIN_IRQ_CAUSE_OFS; |
| 2658 | hpriv->main_mask_reg_addr = mmio + HC_MAIN_IRQ_MASK_OFS; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2659 | } else { |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 2660 | hpriv->main_cause_reg_addr = mmio + HC_SOC_MAIN_IRQ_CAUSE_OFS; |
| 2661 | hpriv->main_mask_reg_addr = mmio + HC_SOC_MAIN_IRQ_MASK_OFS; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2662 | } |
Mark Lord | 352fab7 | 2008-04-19 14:43:42 -0400 | [diff] [blame] | 2663 | |
| 2664 | /* global interrupt mask: 0 == mask everything */ |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2665 | writel(0, hpriv->main_mask_reg_addr); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2666 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2667 | n_hc = mv_get_hc_count(host->ports[0]->flags); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2668 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2669 | for (port = 0; port < host->n_ports; port++) |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2670 | hpriv->ops->read_preamp(hpriv, port, mmio); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2671 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2672 | rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2673 | if (rc) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2674 | goto done; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2675 | |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 2676 | hpriv->ops->reset_flash(hpriv, mmio); |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 2677 | hpriv->ops->reset_bus(host, mmio); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2678 | hpriv->ops->enable_leds(hpriv, mmio); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2679 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2680 | for (port = 0; port < host->n_ports; port++) { |
Tejun Heo | cbcdd87 | 2007-08-18 13:14:55 +0900 | [diff] [blame] | 2681 | struct ata_port *ap = host->ports[port]; |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 2682 | void __iomem *port_mmio = mv_port_base(mmio, port); |
Tejun Heo | cbcdd87 | 2007-08-18 13:14:55 +0900 | [diff] [blame] | 2683 | |
| 2684 | mv_port_init(&ap->ioaddr, port_mmio); |
| 2685 | |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 2686 | #ifdef CONFIG_PCI |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2687 | if (HAS_PCI(host)) { |
| 2688 | unsigned int offset = port_mmio - mmio; |
| 2689 | ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); |
| 2690 | ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); |
| 2691 | } |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 2692 | #endif |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2693 | } |
| 2694 | |
| 2695 | for (hc = 0; hc < n_hc; hc++) { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2696 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
| 2697 | |
| 2698 | VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " |
| 2699 | "(before clear)=0x%08x\n", hc, |
| 2700 | readl(hc_mmio + HC_CFG_OFS), |
| 2701 | readl(hc_mmio + HC_IRQ_CAUSE_OFS)); |
| 2702 | |
| 2703 | /* Clear any currently outstanding hc interrupt conditions */ |
| 2704 | writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2705 | } |
| 2706 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2707 | if (HAS_PCI(host)) { |
| 2708 | /* Clear any currently outstanding host interrupt conditions */ |
| 2709 | writelfl(0, mmio + hpriv->irq_cause_ofs); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2710 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2711 | /* and unmask interrupt generation for host regs */ |
| 2712 | writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); |
| 2713 | if (IS_GEN_I(hpriv)) |
| 2714 | writelfl(~HC_MAIN_MASKED_IRQS_5, |
| 2715 | hpriv->main_mask_reg_addr); |
| 2716 | else |
| 2717 | writelfl(~HC_MAIN_MASKED_IRQS, |
| 2718 | hpriv->main_mask_reg_addr); |
Jeff Garzik | fb621e2 | 2007-02-25 04:19:45 -0500 | [diff] [blame] | 2719 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2720 | VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " |
| 2721 | "PCI int cause/mask=0x%08x/0x%08x\n", |
| 2722 | readl(hpriv->main_cause_reg_addr), |
| 2723 | readl(hpriv->main_mask_reg_addr), |
| 2724 | readl(mmio + hpriv->irq_cause_ofs), |
| 2725 | readl(mmio + hpriv->irq_mask_ofs)); |
| 2726 | } else { |
| 2727 | writelfl(~HC_MAIN_MASKED_IRQS_SOC, |
| 2728 | hpriv->main_mask_reg_addr); |
| 2729 | VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n", |
| 2730 | readl(hpriv->main_cause_reg_addr), |
| 2731 | readl(hpriv->main_mask_reg_addr)); |
| 2732 | } |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2733 | done: |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2734 | return rc; |
| 2735 | } |
| 2736 | |
Byron Bradley | fbf14e2 | 2008-02-10 21:17:30 +0000 | [diff] [blame] | 2737 | static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) |
| 2738 | { |
| 2739 | hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, |
| 2740 | MV_CRQB_Q_SZ, 0); |
| 2741 | if (!hpriv->crqb_pool) |
| 2742 | return -ENOMEM; |
| 2743 | |
| 2744 | hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, |
| 2745 | MV_CRPB_Q_SZ, 0); |
| 2746 | if (!hpriv->crpb_pool) |
| 2747 | return -ENOMEM; |
| 2748 | |
| 2749 | hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, |
| 2750 | MV_SG_TBL_SZ, 0); |
| 2751 | if (!hpriv->sg_tbl_pool) |
| 2752 | return -ENOMEM; |
| 2753 | |
| 2754 | return 0; |
| 2755 | } |
| 2756 | |
Lennert Buytenhek | 15a3263 | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 2757 | static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, |
| 2758 | struct mbus_dram_target_info *dram) |
| 2759 | { |
| 2760 | int i; |
| 2761 | |
| 2762 | for (i = 0; i < 4; i++) { |
| 2763 | writel(0, hpriv->base + WINDOW_CTRL(i)); |
| 2764 | writel(0, hpriv->base + WINDOW_BASE(i)); |
| 2765 | } |
| 2766 | |
| 2767 | for (i = 0; i < dram->num_cs; i++) { |
| 2768 | struct mbus_dram_window *cs = dram->cs + i; |
| 2769 | |
| 2770 | writel(((cs->size - 1) & 0xffff0000) | |
| 2771 | (cs->mbus_attr << 8) | |
| 2772 | (dram->mbus_dram_target_id << 4) | 1, |
| 2773 | hpriv->base + WINDOW_CTRL(i)); |
| 2774 | writel(cs->base, hpriv->base + WINDOW_BASE(i)); |
| 2775 | } |
| 2776 | } |
| 2777 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2778 | /** |
| 2779 | * mv_platform_probe - handle a positive probe of an soc Marvell |
| 2780 | * host |
| 2781 | * @pdev: platform device found |
| 2782 | * |
| 2783 | * LOCKING: |
| 2784 | * Inherited from caller. |
| 2785 | */ |
| 2786 | static int mv_platform_probe(struct platform_device *pdev) |
| 2787 | { |
| 2788 | static int printed_version; |
| 2789 | const struct mv_sata_platform_data *mv_platform_data; |
| 2790 | const struct ata_port_info *ppi[] = |
| 2791 | { &mv_port_info[chip_soc], NULL }; |
| 2792 | struct ata_host *host; |
| 2793 | struct mv_host_priv *hpriv; |
| 2794 | struct resource *res; |
| 2795 | int n_ports, rc; |
| 2796 | |
| 2797 | if (!printed_version++) |
| 2798 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); |
| 2799 | |
| 2800 | /* |
| 2801 | * Simple resource validation .. |
| 2802 | */ |
| 2803 | if (unlikely(pdev->num_resources != 2)) { |
| 2804 | dev_err(&pdev->dev, "invalid number of resources\n"); |
| 2805 | return -EINVAL; |
| 2806 | } |
| 2807 | |
| 2808 | /* |
| 2809 | * Get the register base first |
| 2810 | */ |
| 2811 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 2812 | if (res == NULL) |
| 2813 | return -EINVAL; |
| 2814 | |
| 2815 | /* allocate host */ |
| 2816 | mv_platform_data = pdev->dev.platform_data; |
| 2817 | n_ports = mv_platform_data->n_ports; |
| 2818 | |
| 2819 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
| 2820 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); |
| 2821 | |
| 2822 | if (!host || !hpriv) |
| 2823 | return -ENOMEM; |
| 2824 | host->private_data = hpriv; |
| 2825 | hpriv->n_ports = n_ports; |
| 2826 | |
| 2827 | host->iomap = NULL; |
Saeed Bishara | f1cb0ea | 2008-02-18 07:42:28 -1100 | [diff] [blame] | 2828 | hpriv->base = devm_ioremap(&pdev->dev, res->start, |
| 2829 | res->end - res->start + 1); |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2830 | hpriv->base -= MV_SATAHC0_REG_BASE; |
| 2831 | |
Lennert Buytenhek | 15a3263 | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 2832 | /* |
| 2833 | * (Re-)program MBUS remapping windows if we are asked to. |
| 2834 | */ |
| 2835 | if (mv_platform_data->dram != NULL) |
| 2836 | mv_conf_mbus_windows(hpriv, mv_platform_data->dram); |
| 2837 | |
Byron Bradley | fbf14e2 | 2008-02-10 21:17:30 +0000 | [diff] [blame] | 2838 | rc = mv_create_dma_pools(hpriv, &pdev->dev); |
| 2839 | if (rc) |
| 2840 | return rc; |
| 2841 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2842 | /* initialize adapter */ |
| 2843 | rc = mv_init_host(host, chip_soc); |
| 2844 | if (rc) |
| 2845 | return rc; |
| 2846 | |
| 2847 | dev_printk(KERN_INFO, &pdev->dev, |
| 2848 | "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, |
| 2849 | host->n_ports); |
| 2850 | |
| 2851 | return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, |
| 2852 | IRQF_SHARED, &mv6_sht); |
| 2853 | } |
| 2854 | |
| 2855 | /* |
| 2856 | * |
| 2857 | * mv_platform_remove - unplug a platform interface |
| 2858 | * @pdev: platform device |
| 2859 | * |
| 2860 | * A platform bus SATA device has been unplugged. Perform the needed |
| 2861 | * cleanup. Also called on module unload for any active devices. |
| 2862 | */ |
| 2863 | static int __devexit mv_platform_remove(struct platform_device *pdev) |
| 2864 | { |
| 2865 | struct device *dev = &pdev->dev; |
| 2866 | struct ata_host *host = dev_get_drvdata(dev); |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2867 | |
| 2868 | ata_host_detach(host); |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2869 | return 0; |
| 2870 | } |
| 2871 | |
| 2872 | static struct platform_driver mv_platform_driver = { |
| 2873 | .probe = mv_platform_probe, |
| 2874 | .remove = __devexit_p(mv_platform_remove), |
| 2875 | .driver = { |
| 2876 | .name = DRV_NAME, |
| 2877 | .owner = THIS_MODULE, |
| 2878 | }, |
| 2879 | }; |
| 2880 | |
| 2881 | |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 2882 | #ifdef CONFIG_PCI |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2883 | static int mv_pci_init_one(struct pci_dev *pdev, |
| 2884 | const struct pci_device_id *ent); |
| 2885 | |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 2886 | |
| 2887 | static struct pci_driver mv_pci_driver = { |
| 2888 | .name = DRV_NAME, |
| 2889 | .id_table = mv_pci_tbl, |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2890 | .probe = mv_pci_init_one, |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 2891 | .remove = ata_pci_remove_one, |
| 2892 | }; |
| 2893 | |
| 2894 | /* |
| 2895 | * module options |
| 2896 | */ |
| 2897 | static int msi; /* Use PCI msi; either zero (off, default) or non-zero */ |
| 2898 | |
| 2899 | |
| 2900 | /* move to PCI layer or libata core? */ |
| 2901 | static int pci_go_64(struct pci_dev *pdev) |
| 2902 | { |
| 2903 | int rc; |
| 2904 | |
| 2905 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
| 2906 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
| 2907 | if (rc) { |
| 2908 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 2909 | if (rc) { |
| 2910 | dev_printk(KERN_ERR, &pdev->dev, |
| 2911 | "64-bit DMA enable failed\n"); |
| 2912 | return rc; |
| 2913 | } |
| 2914 | } |
| 2915 | } else { |
| 2916 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
| 2917 | if (rc) { |
| 2918 | dev_printk(KERN_ERR, &pdev->dev, |
| 2919 | "32-bit DMA enable failed\n"); |
| 2920 | return rc; |
| 2921 | } |
| 2922 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 2923 | if (rc) { |
| 2924 | dev_printk(KERN_ERR, &pdev->dev, |
| 2925 | "32-bit consistent DMA enable failed\n"); |
| 2926 | return rc; |
| 2927 | } |
| 2928 | } |
| 2929 | |
| 2930 | return rc; |
| 2931 | } |
| 2932 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2933 | /** |
| 2934 | * mv_print_info - Dump key info to kernel log for perusal. |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2935 | * @host: ATA host to print info about |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2936 | * |
| 2937 | * FIXME: complete this. |
| 2938 | * |
| 2939 | * LOCKING: |
| 2940 | * Inherited from caller. |
| 2941 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2942 | static void mv_print_info(struct ata_host *host) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2943 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2944 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 2945 | struct mv_host_priv *hpriv = host->private_data; |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 2946 | u8 scc; |
Jeff Garzik | c1e4fe7 | 2007-07-09 12:29:31 -0400 | [diff] [blame] | 2947 | const char *scc_s, *gen; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2948 | |
| 2949 | /* Use this to determine the HW stepping of the chip so we know |
| 2950 | * what errata to workaround |
| 2951 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2952 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); |
| 2953 | if (scc == 0) |
| 2954 | scc_s = "SCSI"; |
| 2955 | else if (scc == 0x01) |
| 2956 | scc_s = "RAID"; |
| 2957 | else |
Jeff Garzik | c1e4fe7 | 2007-07-09 12:29:31 -0400 | [diff] [blame] | 2958 | scc_s = "?"; |
| 2959 | |
| 2960 | if (IS_GEN_I(hpriv)) |
| 2961 | gen = "I"; |
| 2962 | else if (IS_GEN_II(hpriv)) |
| 2963 | gen = "II"; |
| 2964 | else if (IS_GEN_IIE(hpriv)) |
| 2965 | gen = "IIE"; |
| 2966 | else |
| 2967 | gen = "?"; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2968 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2969 | dev_printk(KERN_INFO, &pdev->dev, |
Jeff Garzik | c1e4fe7 | 2007-07-09 12:29:31 -0400 | [diff] [blame] | 2970 | "Gen-%s %u slots %u ports %s mode IRQ via %s\n", |
| 2971 | gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2972 | scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); |
| 2973 | } |
| 2974 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2975 | /** |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2976 | * mv_pci_init_one - handle a positive probe of a PCI Marvell host |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2977 | * @pdev: PCI device found |
| 2978 | * @ent: PCI device ID entry for the matched host |
| 2979 | * |
| 2980 | * LOCKING: |
| 2981 | * Inherited from caller. |
| 2982 | */ |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 2983 | static int mv_pci_init_one(struct pci_dev *pdev, |
| 2984 | const struct pci_device_id *ent) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2985 | { |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 2986 | static int printed_version; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2987 | unsigned int board_idx = (unsigned int)ent->driver_data; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2988 | const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; |
| 2989 | struct ata_host *host; |
| 2990 | struct mv_host_priv *hpriv; |
| 2991 | int n_ports, rc; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2992 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2993 | if (!printed_version++) |
| 2994 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2995 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2996 | /* allocate host */ |
| 2997 | n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; |
| 2998 | |
| 2999 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
| 3000 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); |
| 3001 | if (!host || !hpriv) |
| 3002 | return -ENOMEM; |
| 3003 | host->private_data = hpriv; |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 3004 | hpriv->n_ports = n_ports; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3005 | |
| 3006 | /* acquire resources */ |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 3007 | rc = pcim_enable_device(pdev); |
| 3008 | if (rc) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3009 | return rc; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3010 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 3011 | rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); |
| 3012 | if (rc == -EBUSY) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 3013 | pcim_pin_device(pdev); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 3014 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 3015 | return rc; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3016 | host->iomap = pcim_iomap_table(pdev); |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 3017 | hpriv->base = host->iomap[MV_PRIMARY_BAR]; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3018 | |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 3019 | rc = pci_go_64(pdev); |
| 3020 | if (rc) |
| 3021 | return rc; |
| 3022 | |
Mark Lord | da2fa9b | 2008-01-26 18:32:45 -0500 | [diff] [blame] | 3023 | rc = mv_create_dma_pools(hpriv, &pdev->dev); |
| 3024 | if (rc) |
| 3025 | return rc; |
| 3026 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3027 | /* initialize adapter */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3028 | rc = mv_init_host(host, board_idx); |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 3029 | if (rc) |
| 3030 | return rc; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3031 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 3032 | /* Enable interrupts */ |
Tejun Heo | 6a59dcf | 2007-02-24 15:12:31 +0900 | [diff] [blame] | 3033 | if (msi && pci_enable_msi(pdev)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 3034 | pci_intx(pdev, 1); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3035 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 3036 | mv_dump_pci_cfg(pdev, 0x68); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3037 | mv_print_info(host); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3038 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3039 | pci_set_master(pdev); |
Jeff Garzik | ea8b4db | 2007-07-17 02:21:50 -0400 | [diff] [blame] | 3040 | pci_try_set_mwi(pdev); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 3041 | return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, |
Jeff Garzik | c5d3e45 | 2007-07-11 18:30:50 -0400 | [diff] [blame] | 3042 | IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3043 | } |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 3044 | #endif |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3045 | |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 3046 | static int mv_platform_probe(struct platform_device *pdev); |
| 3047 | static int __devexit mv_platform_remove(struct platform_device *pdev); |
| 3048 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3049 | static int __init mv_init(void) |
| 3050 | { |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 3051 | int rc = -ENODEV; |
| 3052 | #ifdef CONFIG_PCI |
| 3053 | rc = pci_register_driver(&mv_pci_driver); |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 3054 | if (rc < 0) |
| 3055 | return rc; |
| 3056 | #endif |
| 3057 | rc = platform_driver_register(&mv_platform_driver); |
| 3058 | |
| 3059 | #ifdef CONFIG_PCI |
| 3060 | if (rc < 0) |
| 3061 | pci_unregister_driver(&mv_pci_driver); |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 3062 | #endif |
| 3063 | return rc; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3064 | } |
| 3065 | |
| 3066 | static void __exit mv_exit(void) |
| 3067 | { |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 3068 | #ifdef CONFIG_PCI |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3069 | pci_unregister_driver(&mv_pci_driver); |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 3070 | #endif |
Saeed Bishara | f351b2d | 2008-02-01 18:08:03 -0500 | [diff] [blame] | 3071 | platform_driver_unregister(&mv_platform_driver); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3072 | } |
| 3073 | |
| 3074 | MODULE_AUTHOR("Brett Russ"); |
| 3075 | MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); |
| 3076 | MODULE_LICENSE("GPL"); |
| 3077 | MODULE_DEVICE_TABLE(pci, mv_pci_tbl); |
| 3078 | MODULE_VERSION(DRV_VERSION); |
Mark Lord | 17c5aab | 2008-04-16 14:56:51 -0400 | [diff] [blame] | 3079 | MODULE_ALIAS("platform:" DRV_NAME); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3080 | |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 3081 | #ifdef CONFIG_PCI |
Jeff Garzik | ddef9bb | 2006-02-02 16:17:06 -0500 | [diff] [blame] | 3082 | module_param(msi, int, 0444); |
| 3083 | MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); |
Saeed Bishara | 7bb3c52 | 2008-01-30 11:50:45 -1100 | [diff] [blame] | 3084 | #endif |
Jeff Garzik | ddef9bb | 2006-02-02 16:17:06 -0500 | [diff] [blame] | 3085 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 3086 | module_init(mv_init); |
| 3087 | module_exit(mv_exit); |