Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Synopsys DesignWare Multimedia Card Interface driver |
| 3 | * (Based on NXP driver for lpc 31xx) |
| 4 | * |
| 5 | * Copyright (C) 2009 NXP Semiconductors |
| 6 | * Copyright (C) 2009, 2010 Imagination Technologies Ltd. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #ifndef _DW_MMC_H_ |
| 15 | #define _DW_MMC_H_ |
| 16 | |
Jaehoon Chung | 4e0a5ad | 2011-10-17 19:36:23 +0900 | [diff] [blame] | 17 | #define DW_MMC_240A 0x240a |
| 18 | |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 19 | #define SDMMC_CTRL 0x000 |
| 20 | #define SDMMC_PWREN 0x004 |
| 21 | #define SDMMC_CLKDIV 0x008 |
| 22 | #define SDMMC_CLKSRC 0x00c |
| 23 | #define SDMMC_CLKENA 0x010 |
| 24 | #define SDMMC_TMOUT 0x014 |
| 25 | #define SDMMC_CTYPE 0x018 |
| 26 | #define SDMMC_BLKSIZ 0x01c |
| 27 | #define SDMMC_BYTCNT 0x020 |
| 28 | #define SDMMC_INTMASK 0x024 |
| 29 | #define SDMMC_CMDARG 0x028 |
| 30 | #define SDMMC_CMD 0x02c |
| 31 | #define SDMMC_RESP0 0x030 |
| 32 | #define SDMMC_RESP1 0x034 |
| 33 | #define SDMMC_RESP2 0x038 |
| 34 | #define SDMMC_RESP3 0x03c |
| 35 | #define SDMMC_MINTSTS 0x040 |
| 36 | #define SDMMC_RINTSTS 0x044 |
| 37 | #define SDMMC_STATUS 0x048 |
| 38 | #define SDMMC_FIFOTH 0x04c |
| 39 | #define SDMMC_CDETECT 0x050 |
| 40 | #define SDMMC_WRTPRT 0x054 |
| 41 | #define SDMMC_GPIO 0x058 |
| 42 | #define SDMMC_TCBCNT 0x05c |
| 43 | #define SDMMC_TBBCNT 0x060 |
| 44 | #define SDMMC_DEBNCE 0x064 |
| 45 | #define SDMMC_USRID 0x068 |
| 46 | #define SDMMC_VERID 0x06c |
| 47 | #define SDMMC_HCON 0x070 |
Jaehoon Chung | 41babf7 | 2011-02-24 13:46:11 +0900 | [diff] [blame] | 48 | #define SDMMC_UHS_REG 0x074 |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 49 | #define SDMMC_BMOD 0x080 |
| 50 | #define SDMMC_PLDMND 0x084 |
| 51 | #define SDMMC_DBADDR 0x088 |
| 52 | #define SDMMC_IDSTS 0x08c |
| 53 | #define SDMMC_IDINTEN 0x090 |
| 54 | #define SDMMC_DSCADDR 0x094 |
| 55 | #define SDMMC_BUFADDR 0x098 |
Seungwon Jeon | f1d2736 | 2013-08-31 00:13:55 +0900 | [diff] [blame] | 56 | #define SDMMC_CDTHRCTL 0x100 |
Jaehoon Chung | 4e0a5ad | 2011-10-17 19:36:23 +0900 | [diff] [blame] | 57 | #define SDMMC_DATA(x) (x) |
| 58 | |
| 59 | /* |
| 60 | * Data offset is difference according to Version |
| 61 | * Lower than 2.40a : data register offest is 0x100 |
| 62 | */ |
| 63 | #define DATA_OFFSET 0x100 |
| 64 | #define DATA_240A_OFFSET 0x200 |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 65 | |
| 66 | /* shift bit field */ |
| 67 | #define _SBF(f, v) ((v) << (f)) |
| 68 | |
| 69 | /* Control register defines */ |
| 70 | #define SDMMC_CTRL_USE_IDMAC BIT(25) |
| 71 | #define SDMMC_CTRL_CEATA_INT_EN BIT(11) |
| 72 | #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) |
| 73 | #define SDMMC_CTRL_SEND_CCSD BIT(9) |
| 74 | #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) |
| 75 | #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) |
| 76 | #define SDMMC_CTRL_READ_WAIT BIT(6) |
| 77 | #define SDMMC_CTRL_DMA_ENABLE BIT(5) |
| 78 | #define SDMMC_CTRL_INT_ENABLE BIT(4) |
| 79 | #define SDMMC_CTRL_DMA_RESET BIT(2) |
| 80 | #define SDMMC_CTRL_FIFO_RESET BIT(1) |
| 81 | #define SDMMC_CTRL_RESET BIT(0) |
| 82 | /* Clock Enable register defines */ |
| 83 | #define SDMMC_CLKEN_LOW_PWR BIT(16) |
| 84 | #define SDMMC_CLKEN_ENABLE BIT(0) |
| 85 | /* time-out register defines */ |
| 86 | #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) |
| 87 | #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 |
| 88 | #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) |
| 89 | #define SDMMC_TMOUT_RESP_MSK 0xFF |
| 90 | /* card-type register defines */ |
| 91 | #define SDMMC_CTYPE_8BIT BIT(16) |
| 92 | #define SDMMC_CTYPE_4BIT BIT(0) |
| 93 | #define SDMMC_CTYPE_1BIT 0 |
| 94 | /* Interrupt status & mask register defines */ |
Shashidhar Hiremath | 1a5c8e1 | 2011-08-29 13:11:46 +0530 | [diff] [blame] | 95 | #define SDMMC_INT_SDIO(n) BIT(16 + (n)) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 96 | #define SDMMC_INT_EBE BIT(15) |
| 97 | #define SDMMC_INT_ACD BIT(14) |
| 98 | #define SDMMC_INT_SBE BIT(13) |
| 99 | #define SDMMC_INT_HLE BIT(12) |
| 100 | #define SDMMC_INT_FRUN BIT(11) |
| 101 | #define SDMMC_INT_HTO BIT(10) |
Jaehoon Chung | 3f7eec6 | 2013-05-27 13:47:57 +0900 | [diff] [blame] | 102 | #define SDMMC_INT_DRTO BIT(9) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 103 | #define SDMMC_INT_RTO BIT(8) |
| 104 | #define SDMMC_INT_DCRC BIT(7) |
| 105 | #define SDMMC_INT_RCRC BIT(6) |
| 106 | #define SDMMC_INT_RXDR BIT(5) |
| 107 | #define SDMMC_INT_TXDR BIT(4) |
| 108 | #define SDMMC_INT_DATA_OVER BIT(3) |
| 109 | #define SDMMC_INT_CMD_DONE BIT(2) |
| 110 | #define SDMMC_INT_RESP_ERR BIT(1) |
| 111 | #define SDMMC_INT_CD BIT(0) |
| 112 | #define SDMMC_INT_ERROR 0xbfc2 |
| 113 | /* Command register defines */ |
| 114 | #define SDMMC_CMD_START BIT(31) |
Dinh Nguyen | eede211 | 2013-06-12 10:18:51 -0500 | [diff] [blame] | 115 | #define SDMMC_CMD_USE_HOLD_REG BIT(29) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 116 | #define SDMMC_CMD_CCS_EXP BIT(23) |
| 117 | #define SDMMC_CMD_CEATA_RD BIT(22) |
| 118 | #define SDMMC_CMD_UPD_CLK BIT(21) |
| 119 | #define SDMMC_CMD_INIT BIT(15) |
| 120 | #define SDMMC_CMD_STOP BIT(14) |
| 121 | #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) |
| 122 | #define SDMMC_CMD_SEND_STOP BIT(12) |
| 123 | #define SDMMC_CMD_STRM_MODE BIT(11) |
| 124 | #define SDMMC_CMD_DAT_WR BIT(10) |
| 125 | #define SDMMC_CMD_DAT_EXP BIT(9) |
| 126 | #define SDMMC_CMD_RESP_CRC BIT(8) |
| 127 | #define SDMMC_CMD_RESP_LONG BIT(7) |
| 128 | #define SDMMC_CMD_RESP_EXP BIT(6) |
| 129 | #define SDMMC_CMD_INDX(n) ((n) & 0x1F) |
| 130 | /* Status register defines */ |
Jaehoon Chung | ee5d19b | 2012-01-05 19:12:57 +0900 | [diff] [blame] | 131 | #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) |
Seungwon Jeon | 5242689 | 2013-08-31 00:13:42 +0900 | [diff] [blame] | 132 | /* FIFOTH register defines */ |
| 133 | #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ |
| 134 | ((r) & 0xFFF) << 16 | \ |
| 135 | ((t) & 0xFFF)) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 136 | /* Internal DMAC interrupt defines */ |
| 137 | #define SDMMC_IDMAC_INT_AI BIT(9) |
| 138 | #define SDMMC_IDMAC_INT_NI BIT(8) |
| 139 | #define SDMMC_IDMAC_INT_CES BIT(5) |
| 140 | #define SDMMC_IDMAC_INT_DU BIT(4) |
| 141 | #define SDMMC_IDMAC_INT_FBE BIT(2) |
| 142 | #define SDMMC_IDMAC_INT_RI BIT(1) |
| 143 | #define SDMMC_IDMAC_INT_TI BIT(0) |
| 144 | /* Internal DMAC bus mode bits */ |
| 145 | #define SDMMC_IDMAC_ENABLE BIT(7) |
| 146 | #define SDMMC_IDMAC_FB BIT(1) |
| 147 | #define SDMMC_IDMAC_SWRESET BIT(0) |
Jaehoon Chung | 4e0a5ad | 2011-10-17 19:36:23 +0900 | [diff] [blame] | 148 | /* Version ID register define */ |
| 149 | #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) |
Seungwon Jeon | f1d2736 | 2013-08-31 00:13:55 +0900 | [diff] [blame] | 150 | /* Card read threshold */ |
| 151 | #define SDMMC_SET_RD_THLD(v, x) (((v) & 0x1FFF) << 16 | (x)) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 152 | |
| 153 | /* Register access macros */ |
| 154 | #define mci_readl(dev, reg) \ |
James Hogan | 892b1e3 | 2011-06-24 13:56:38 +0100 | [diff] [blame] | 155 | __raw_readl((dev)->regs + SDMMC_##reg) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 156 | #define mci_writel(dev, reg, value) \ |
James Hogan | 892b1e3 | 2011-06-24 13:56:38 +0100 | [diff] [blame] | 157 | __raw_writel((value), (dev)->regs + SDMMC_##reg) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 158 | |
| 159 | /* 16-bit FIFO access macros */ |
| 160 | #define mci_readw(dev, reg) \ |
James Hogan | 892b1e3 | 2011-06-24 13:56:38 +0100 | [diff] [blame] | 161 | __raw_readw((dev)->regs + SDMMC_##reg) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 162 | #define mci_writew(dev, reg, value) \ |
James Hogan | 892b1e3 | 2011-06-24 13:56:38 +0100 | [diff] [blame] | 163 | __raw_writew((value), (dev)->regs + SDMMC_##reg) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 164 | |
| 165 | /* 64-bit FIFO access macros */ |
| 166 | #ifdef readq |
| 167 | #define mci_readq(dev, reg) \ |
James Hogan | 892b1e3 | 2011-06-24 13:56:38 +0100 | [diff] [blame] | 168 | __raw_readq((dev)->regs + SDMMC_##reg) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 169 | #define mci_writeq(dev, reg, value) \ |
James Hogan | 892b1e3 | 2011-06-24 13:56:38 +0100 | [diff] [blame] | 170 | __raw_writeq((value), (dev)->regs + SDMMC_##reg) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 171 | #else |
| 172 | /* |
| 173 | * Dummy readq implementation for architectures that don't define it. |
| 174 | * |
| 175 | * We would assume that none of these architectures would configure |
| 176 | * the IP block with a 64bit FIFO width, so this code will never be |
| 177 | * executed on those machines. Defining these macros here keeps the |
| 178 | * rest of the code free from ifdefs. |
| 179 | */ |
| 180 | #define mci_readq(dev, reg) \ |
James Hogan | 892b1e3 | 2011-06-24 13:56:38 +0100 | [diff] [blame] | 181 | (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 182 | #define mci_writeq(dev, reg, value) \ |
James Hogan | 892b1e3 | 2011-06-24 13:56:38 +0100 | [diff] [blame] | 183 | (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 184 | #endif |
| 185 | |
Shashidhar Hiremath | 62ca803 | 2012-01-13 16:04:57 +0530 | [diff] [blame] | 186 | extern int dw_mci_probe(struct dw_mci *host); |
| 187 | extern void dw_mci_remove(struct dw_mci *host); |
| 188 | #ifdef CONFIG_PM |
| 189 | extern int dw_mci_suspend(struct dw_mci *host); |
| 190 | extern int dw_mci_resume(struct dw_mci *host); |
| 191 | #endif |
| 192 | |
Thomas Abraham | 800d78b | 2012-09-17 18:16:42 +0000 | [diff] [blame] | 193 | /** |
Seungwon Jeon | 0976f16 | 2013-08-31 00:12:42 +0900 | [diff] [blame] | 194 | * struct dw_mci_slot - MMC slot state |
| 195 | * @mmc: The mmc_host representing this slot. |
| 196 | * @host: The MMC controller this slot is using. |
| 197 | * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX) |
| 198 | * @wp_gpio: If gpio_is_valid() we'll use this to read write protect. |
| 199 | * @ctype: Card type for this slot. |
| 200 | * @mrq: mmc_request currently being processed or waiting to be |
| 201 | * processed, or NULL when the slot is idle. |
| 202 | * @queue_node: List node for placing this node in the @queue list of |
| 203 | * &struct dw_mci. |
| 204 | * @clock: Clock rate configured by set_ios(). Protected by host->lock. |
| 205 | * @__clk_old: The last updated clock with reflecting clock divider. |
| 206 | * Keeping track of this helps us to avoid spamming the console |
| 207 | * with CONFIG_MMC_CLKGATE. |
| 208 | * @flags: Random state bits associated with the slot. |
| 209 | * @id: Number of this slot. |
| 210 | * @last_detect_state: Most recently observed card detect state. |
| 211 | */ |
| 212 | struct dw_mci_slot { |
| 213 | struct mmc_host *mmc; |
| 214 | struct dw_mci *host; |
| 215 | |
| 216 | int quirks; |
| 217 | int wp_gpio; |
| 218 | |
| 219 | u32 ctype; |
| 220 | |
| 221 | struct mmc_request *mrq; |
| 222 | struct list_head queue_node; |
| 223 | |
| 224 | unsigned int clock; |
| 225 | unsigned int __clk_old; |
| 226 | |
| 227 | unsigned long flags; |
| 228 | #define DW_MMC_CARD_PRESENT 0 |
| 229 | #define DW_MMC_CARD_NEED_INIT 1 |
| 230 | int id; |
| 231 | int last_detect_state; |
| 232 | }; |
| 233 | |
| 234 | struct dw_mci_tuning_data { |
| 235 | const u8 *blk_pattern; |
| 236 | unsigned int blksz; |
| 237 | }; |
| 238 | |
| 239 | /** |
Thomas Abraham | 800d78b | 2012-09-17 18:16:42 +0000 | [diff] [blame] | 240 | * dw_mci driver data - dw-mshc implementation specific driver data. |
| 241 | * @caps: mmc subsystem specified capabilities of the controller(s). |
| 242 | * @init: early implementation specific initialization. |
| 243 | * @setup_clock: implementation specific clock configuration. |
| 244 | * @prepare_command: handle CMD register extensions. |
| 245 | * @set_ios: handle bus specific extensions. |
| 246 | * @parse_dt: parse implementation specific device tree properties. |
Thomas Abraham | 800d78b | 2012-09-17 18:16:42 +0000 | [diff] [blame] | 247 | * |
| 248 | * Provide controller implementation specific extensions. The usage of this |
| 249 | * data structure is fully optional and usage of each member in this structure |
| 250 | * is optional as well. |
| 251 | */ |
| 252 | struct dw_mci_drv_data { |
| 253 | unsigned long *caps; |
| 254 | int (*init)(struct dw_mci *host); |
| 255 | int (*setup_clock)(struct dw_mci *host); |
| 256 | void (*prepare_command)(struct dw_mci *host, u32 *cmdr); |
| 257 | void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); |
| 258 | int (*parse_dt)(struct dw_mci *host); |
Seungwon Jeon | 0976f16 | 2013-08-31 00:12:42 +0900 | [diff] [blame] | 259 | int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode, |
| 260 | struct dw_mci_tuning_data *tuning_data); |
Thomas Abraham | 800d78b | 2012-09-17 18:16:42 +0000 | [diff] [blame] | 261 | }; |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 262 | #endif /* _DW_MMC_H_ */ |