Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Freescale eSDHC controller driver. |
| 3 | * |
Jerry Huang | f060bc9 | 2012-02-14 14:05:37 +0800 | [diff] [blame] | 4 | * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 5 | * Copyright (c) 2009 MontaVista Software, Inc. |
| 6 | * |
| 7 | * Authors: Xiaobo Xie <X.Xie@freescale.com> |
| 8 | * Anton Vorontsov <avorontsov@ru.mvista.com> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or (at |
| 13 | * your option) any later version. |
| 14 | */ |
| 15 | |
Oded Gabbay | 66b50a0 | 2013-06-27 12:00:05 -0400 | [diff] [blame] | 16 | #include <linux/err.h> |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 17 | #include <linux/io.h> |
Jerry Huang | f060bc9 | 2012-02-14 14:05:37 +0800 | [diff] [blame] | 18 | #include <linux/of.h> |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 19 | #include <linux/delay.h> |
Paul Gortmaker | 88b4767 | 2011-07-03 15:15:51 -0400 | [diff] [blame] | 20 | #include <linux/module.h> |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 21 | #include <linux/mmc/host.h> |
Shawn Guo | 38576af | 2011-05-27 23:48:14 +0800 | [diff] [blame] | 22 | #include "sdhci-pltfm.h" |
Wolfram Sang | 80872e2 | 2010-10-15 12:21:03 +0200 | [diff] [blame] | 23 | #include "sdhci-esdhc.h" |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 24 | |
Jerry Huang | 137ccd4 | 2012-03-08 11:25:02 +0800 | [diff] [blame] | 25 | #define VENDOR_V_22 0x12 |
Haijun Zhang | a4071fb | 2012-12-04 10:41:28 +0800 | [diff] [blame] | 26 | #define VENDOR_V_23 0x13 |
Jerry Huang | 137ccd4 | 2012-03-08 11:25:02 +0800 | [diff] [blame] | 27 | static u32 esdhc_readl(struct sdhci_host *host, int reg) |
| 28 | { |
| 29 | u32 ret; |
| 30 | |
| 31 | ret = in_be32(host->ioaddr + reg); |
| 32 | /* |
| 33 | * The bit of ADMA flag in eSDHC is not compatible with standard |
| 34 | * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is |
| 35 | * supported by eSDHC. |
| 36 | * And for many FSL eSDHC controller, the reset value of field |
| 37 | * SDHCI_CAN_DO_ADMA1 is one, but some of them can't support ADMA, |
| 38 | * only these vendor version is greater than 2.2/0x12 support ADMA. |
| 39 | * For FSL eSDHC, must aligned 4-byte, so use 0xFC to read the |
| 40 | * the verdor version number, oxFE is SDHCI_HOST_VERSION. |
| 41 | */ |
| 42 | if ((reg == SDHCI_CAPABILITIES) && (ret & SDHCI_CAN_DO_ADMA1)) { |
| 43 | u32 tmp = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS); |
| 44 | tmp = (tmp & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT; |
| 45 | if (tmp > VENDOR_V_22) |
| 46 | ret |= SDHCI_CAN_DO_ADMA2; |
| 47 | } |
| 48 | |
| 49 | return ret; |
| 50 | } |
| 51 | |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 52 | static u16 esdhc_readw(struct sdhci_host *host, int reg) |
| 53 | { |
| 54 | u16 ret; |
Xu lei | e51cbc9 | 2011-09-09 20:05:46 +0800 | [diff] [blame] | 55 | int base = reg & ~0x3; |
| 56 | int shift = (reg & 0x2) * 8; |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 57 | |
| 58 | if (unlikely(reg == SDHCI_HOST_VERSION)) |
Xu lei | e51cbc9 | 2011-09-09 20:05:46 +0800 | [diff] [blame] | 59 | ret = in_be32(host->ioaddr + base) & 0xffff; |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 60 | else |
Xu lei | e51cbc9 | 2011-09-09 20:05:46 +0800 | [diff] [blame] | 61 | ret = (in_be32(host->ioaddr + base) >> shift) & 0xffff; |
| 62 | return ret; |
| 63 | } |
| 64 | |
| 65 | static u8 esdhc_readb(struct sdhci_host *host, int reg) |
| 66 | { |
| 67 | int base = reg & ~0x3; |
| 68 | int shift = (reg & 0x3) * 8; |
| 69 | u8 ret = (in_be32(host->ioaddr + base) >> shift) & 0xff; |
Roy Zang | ba8c4dc | 2012-01-13 15:02:01 +0800 | [diff] [blame] | 70 | |
| 71 | /* |
| 72 | * "DMA select" locates at offset 0x28 in SD specification, but on |
| 73 | * P5020 or P3041, it locates at 0x29. |
| 74 | */ |
| 75 | if (reg == SDHCI_HOST_CONTROL) { |
| 76 | u32 dma_bits; |
| 77 | |
| 78 | dma_bits = in_be32(host->ioaddr + reg); |
| 79 | /* DMA select is 22,23 bits in Protocol Control Register */ |
| 80 | dma_bits = (dma_bits >> 5) & SDHCI_CTRL_DMA_MASK; |
| 81 | |
| 82 | /* fixup the result */ |
| 83 | ret &= ~SDHCI_CTRL_DMA_MASK; |
| 84 | ret |= dma_bits; |
| 85 | } |
| 86 | |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 87 | return ret; |
| 88 | } |
| 89 | |
Haijun Zhang | a4071fb | 2012-12-04 10:41:28 +0800 | [diff] [blame] | 90 | static void esdhc_writel(struct sdhci_host *host, u32 val, int reg) |
| 91 | { |
| 92 | /* |
| 93 | * Enable IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] |
| 94 | * when SYSCTL[RSTD]) is set for some special operations. |
| 95 | * No any impact other operation. |
| 96 | */ |
| 97 | if (reg == SDHCI_INT_ENABLE) |
| 98 | val |= SDHCI_INT_BLK_GAP; |
| 99 | sdhci_be32bs_writel(host, val, reg); |
| 100 | } |
| 101 | |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 102 | static void esdhc_writew(struct sdhci_host *host, u16 val, int reg) |
| 103 | { |
| 104 | if (reg == SDHCI_BLOCK_SIZE) { |
| 105 | /* |
| 106 | * Two last DMA bits are reserved, and first one is used for |
| 107 | * non-standard blksz of 4096 bytes that we don't support |
| 108 | * yet. So clear the DMA boundary bits. |
| 109 | */ |
| 110 | val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); |
| 111 | } |
| 112 | sdhci_be32bs_writew(host, val, reg); |
| 113 | } |
| 114 | |
| 115 | static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg) |
| 116 | { |
Roy Zang | ba8c4dc | 2012-01-13 15:02:01 +0800 | [diff] [blame] | 117 | /* |
| 118 | * "DMA select" location is offset 0x28 in SD specification, but on |
| 119 | * P5020 or P3041, it's located at 0x29. |
| 120 | */ |
| 121 | if (reg == SDHCI_HOST_CONTROL) { |
| 122 | u32 dma_bits; |
| 123 | |
Oded Gabbay | dcaff04 | 2013-07-05 12:48:35 -0400 | [diff] [blame] | 124 | /* |
| 125 | * If host control register is not standard, exit |
| 126 | * this function |
| 127 | */ |
| 128 | if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) |
| 129 | return; |
| 130 | |
Roy Zang | ba8c4dc | 2012-01-13 15:02:01 +0800 | [diff] [blame] | 131 | /* DMA select is 22,23 bits in Protocol Control Register */ |
| 132 | dma_bits = (val & SDHCI_CTRL_DMA_MASK) << 5; |
| 133 | clrsetbits_be32(host->ioaddr + reg , SDHCI_CTRL_DMA_MASK << 5, |
| 134 | dma_bits); |
| 135 | val &= ~SDHCI_CTRL_DMA_MASK; |
| 136 | val |= in_be32(host->ioaddr + reg) & SDHCI_CTRL_DMA_MASK; |
| 137 | } |
| 138 | |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 139 | /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */ |
| 140 | if (reg == SDHCI_HOST_CONTROL) |
| 141 | val &= ~ESDHC_HOST_CONTROL_RES; |
| 142 | sdhci_be32bs_writeb(host, val, reg); |
| 143 | } |
| 144 | |
Haijun Zhang | a4071fb | 2012-12-04 10:41:28 +0800 | [diff] [blame] | 145 | /* |
| 146 | * For Abort or Suspend after Stop at Block Gap, ignore the ADMA |
| 147 | * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) |
| 148 | * and Block Gap Event(IRQSTAT[BGE]) are also set. |
| 149 | * For Continue, apply soft reset for data(SYSCTL[RSTD]); |
| 150 | * and re-issue the entire read transaction from beginning. |
| 151 | */ |
| 152 | static void esdhci_of_adma_workaround(struct sdhci_host *host, u32 intmask) |
| 153 | { |
| 154 | u32 tmp; |
| 155 | bool applicable; |
| 156 | dma_addr_t dmastart; |
| 157 | dma_addr_t dmanow; |
| 158 | |
| 159 | tmp = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS); |
| 160 | tmp = (tmp & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT; |
| 161 | |
| 162 | applicable = (intmask & SDHCI_INT_DATA_END) && |
| 163 | (intmask & SDHCI_INT_BLK_GAP) && |
| 164 | (tmp == VENDOR_V_23); |
| 165 | if (!applicable) |
| 166 | return; |
| 167 | |
| 168 | host->data->error = 0; |
| 169 | dmastart = sg_dma_address(host->data->sg); |
| 170 | dmanow = dmastart + host->data->bytes_xfered; |
| 171 | /* |
| 172 | * Force update to the next DMA block boundary. |
| 173 | */ |
| 174 | dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + |
| 175 | SDHCI_DEFAULT_BOUNDARY_SIZE; |
| 176 | host->data->bytes_xfered = dmanow - dmastart; |
| 177 | sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); |
| 178 | } |
| 179 | |
Wolfram Sang | 80872e2 | 2010-10-15 12:21:03 +0200 | [diff] [blame] | 180 | static int esdhc_of_enable_dma(struct sdhci_host *host) |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 181 | { |
| 182 | setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP); |
| 183 | return 0; |
| 184 | } |
| 185 | |
Wolfram Sang | 80872e2 | 2010-10-15 12:21:03 +0200 | [diff] [blame] | 186 | static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 187 | { |
Shawn Guo | e307148 | 2011-07-20 17:13:36 -0400 | [diff] [blame] | 188 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 189 | |
Shawn Guo | e307148 | 2011-07-20 17:13:36 -0400 | [diff] [blame] | 190 | return pltfm_host->clock; |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 191 | } |
| 192 | |
Wolfram Sang | 80872e2 | 2010-10-15 12:21:03 +0200 | [diff] [blame] | 193 | static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 194 | { |
Shawn Guo | e307148 | 2011-07-20 17:13:36 -0400 | [diff] [blame] | 195 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 196 | |
Shawn Guo | e307148 | 2011-07-20 17:13:36 -0400 | [diff] [blame] | 197 | return pltfm_host->clock / 256 / 16; |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 198 | } |
| 199 | |
Jerry Huang | f060bc9 | 2012-02-14 14:05:37 +0800 | [diff] [blame] | 200 | static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) |
| 201 | { |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 202 | |
| 203 | int pre_div = 2; |
| 204 | int div = 1; |
| 205 | u32 temp; |
| 206 | |
| 207 | if (clock == 0) |
| 208 | goto out; |
| 209 | |
Jerry Huang | f060bc9 | 2012-02-14 14:05:37 +0800 | [diff] [blame] | 210 | /* Workaround to reduce the clock frequency for p1010 esdhc */ |
| 211 | if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) { |
| 212 | if (clock > 20000000) |
| 213 | clock -= 5000000; |
| 214 | if (clock > 40000000) |
| 215 | clock -= 5000000; |
| 216 | } |
| 217 | |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 218 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); |
| 219 | temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
| 220 | | ESDHC_CLOCK_MASK); |
| 221 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); |
| 222 | |
| 223 | while (host->max_clk / pre_div / 16 > clock && pre_div < 256) |
| 224 | pre_div *= 2; |
| 225 | |
| 226 | while (host->max_clk / pre_div / div > clock && div < 16) |
| 227 | div++; |
| 228 | |
| 229 | dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", |
Dong Aisheng | e76b855 | 2013-09-13 19:11:37 +0800 | [diff] [blame] | 230 | clock, host->max_clk / pre_div / div); |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 231 | |
| 232 | pre_div >>= 1; |
| 233 | div--; |
| 234 | |
| 235 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); |
| 236 | temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
| 237 | | (div << ESDHC_DIVIDER_SHIFT) |
| 238 | | (pre_div << ESDHC_PREDIV_SHIFT)); |
| 239 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); |
| 240 | mdelay(1); |
| 241 | out: |
| 242 | host->clock = clock; |
Jerry Huang | f060bc9 | 2012-02-14 14:05:37 +0800 | [diff] [blame] | 243 | } |
| 244 | |
Jerry Huang | 192b537 | 2012-02-04 17:13:13 -0500 | [diff] [blame] | 245 | #ifdef CONFIG_PM |
| 246 | static u32 esdhc_proctl; |
| 247 | static void esdhc_of_suspend(struct sdhci_host *host) |
| 248 | { |
| 249 | esdhc_proctl = sdhci_be32bs_readl(host, SDHCI_HOST_CONTROL); |
| 250 | } |
| 251 | |
| 252 | static void esdhc_of_resume(struct sdhci_host *host) |
| 253 | { |
| 254 | esdhc_of_enable_dma(host); |
| 255 | sdhci_be32bs_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); |
| 256 | } |
| 257 | #endif |
| 258 | |
Jerry Huang | 63ef5d8 | 2012-10-25 13:47:19 +0800 | [diff] [blame] | 259 | static void esdhc_of_platform_init(struct sdhci_host *host) |
| 260 | { |
| 261 | u32 vvn; |
| 262 | |
| 263 | vvn = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS); |
| 264 | vvn = (vvn & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT; |
| 265 | if (vvn == VENDOR_V_22) |
| 266 | host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; |
Jerry Huang | 3cf3883 | 2012-11-23 17:25:03 +0800 | [diff] [blame] | 267 | |
| 268 | if (vvn > VENDOR_V_22) |
| 269 | host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; |
Jerry Huang | 63ef5d8 | 2012-10-25 13:47:19 +0800 | [diff] [blame] | 270 | } |
| 271 | |
Oded Gabbay | 66b50a0 | 2013-06-27 12:00:05 -0400 | [diff] [blame] | 272 | static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width) |
| 273 | { |
| 274 | u32 ctrl; |
| 275 | |
| 276 | switch (width) { |
| 277 | case MMC_BUS_WIDTH_8: |
| 278 | ctrl = ESDHC_CTRL_8BITBUS; |
| 279 | break; |
| 280 | |
| 281 | case MMC_BUS_WIDTH_4: |
| 282 | ctrl = ESDHC_CTRL_4BITBUS; |
| 283 | break; |
| 284 | |
| 285 | default: |
| 286 | ctrl = 0; |
| 287 | break; |
| 288 | } |
| 289 | |
| 290 | clrsetbits_be32(host->ioaddr + SDHCI_HOST_CONTROL, |
| 291 | ESDHC_CTRL_BUSWIDTH_MASK, ctrl); |
| 292 | |
| 293 | return 0; |
| 294 | } |
| 295 | |
Lars-Peter Clausen | c915568 | 2013-03-13 19:26:05 +0100 | [diff] [blame] | 296 | static const struct sdhci_ops sdhci_esdhc_ops = { |
Jerry Huang | 137ccd4 | 2012-03-08 11:25:02 +0800 | [diff] [blame] | 297 | .read_l = esdhc_readl, |
Shawn Guo | e307148 | 2011-07-20 17:13:36 -0400 | [diff] [blame] | 298 | .read_w = esdhc_readw, |
Xu lei | e51cbc9 | 2011-09-09 20:05:46 +0800 | [diff] [blame] | 299 | .read_b = esdhc_readb, |
Haijun Zhang | a4071fb | 2012-12-04 10:41:28 +0800 | [diff] [blame] | 300 | .write_l = esdhc_writel, |
Shawn Guo | e307148 | 2011-07-20 17:13:36 -0400 | [diff] [blame] | 301 | .write_w = esdhc_writew, |
| 302 | .write_b = esdhc_writeb, |
Jerry Huang | f060bc9 | 2012-02-14 14:05:37 +0800 | [diff] [blame] | 303 | .set_clock = esdhc_of_set_clock, |
Shawn Guo | e307148 | 2011-07-20 17:13:36 -0400 | [diff] [blame] | 304 | .enable_dma = esdhc_of_enable_dma, |
| 305 | .get_max_clock = esdhc_of_get_max_clock, |
| 306 | .get_min_clock = esdhc_of_get_min_clock, |
Jerry Huang | 63ef5d8 | 2012-10-25 13:47:19 +0800 | [diff] [blame] | 307 | .platform_init = esdhc_of_platform_init, |
Jerry Huang | 192b537 | 2012-02-04 17:13:13 -0500 | [diff] [blame] | 308 | #ifdef CONFIG_PM |
| 309 | .platform_suspend = esdhc_of_suspend, |
| 310 | .platform_resume = esdhc_of_resume, |
| 311 | #endif |
Haijun Zhang | a4071fb | 2012-12-04 10:41:28 +0800 | [diff] [blame] | 312 | .adma_workaround = esdhci_of_adma_workaround, |
Oded Gabbay | 66b50a0 | 2013-06-27 12:00:05 -0400 | [diff] [blame] | 313 | .platform_bus_width = esdhc_pltfm_bus_width, |
Shawn Guo | e307148 | 2011-07-20 17:13:36 -0400 | [diff] [blame] | 314 | }; |
| 315 | |
Lars-Peter Clausen | 1db5eeb | 2013-03-13 19:26:03 +0100 | [diff] [blame] | 316 | static const struct sdhci_pltfm_data sdhci_esdhc_pdata = { |
Jerry Huang | 137ccd4 | 2012-03-08 11:25:02 +0800 | [diff] [blame] | 317 | /* |
| 318 | * card detection could be handled via GPIO |
| 319 | * eSDHC cannot support End Attribute in NOP ADMA descriptor |
| 320 | */ |
Richard Zhu | e481e45 | 2011-03-21 13:22:13 +0800 | [diff] [blame] | 321 | .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION |
Jerry Huang | 137ccd4 | 2012-03-08 11:25:02 +0800 | [diff] [blame] | 322 | | SDHCI_QUIRK_NO_CARD_NO_RESET |
| 323 | | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
Shawn Guo | e307148 | 2011-07-20 17:13:36 -0400 | [diff] [blame] | 324 | .ops = &sdhci_esdhc_ops, |
Albert Herranz | 7657c3a | 2009-12-17 15:27:20 -0800 | [diff] [blame] | 325 | }; |
Shawn Guo | 38576af | 2011-05-27 23:48:14 +0800 | [diff] [blame] | 326 | |
Bill Pemberton | c3be1ef | 2012-11-19 13:23:06 -0500 | [diff] [blame] | 327 | static int sdhci_esdhc_probe(struct platform_device *pdev) |
Shawn Guo | 38576af | 2011-05-27 23:48:14 +0800 | [diff] [blame] | 328 | { |
Oded Gabbay | 66b50a0 | 2013-06-27 12:00:05 -0400 | [diff] [blame] | 329 | struct sdhci_host *host; |
Oded Gabbay | dcaff04 | 2013-07-05 12:48:35 -0400 | [diff] [blame] | 330 | struct device_node *np; |
Oded Gabbay | 66b50a0 | 2013-06-27 12:00:05 -0400 | [diff] [blame] | 331 | int ret; |
| 332 | |
| 333 | host = sdhci_pltfm_init(pdev, &sdhci_esdhc_pdata, 0); |
| 334 | if (IS_ERR(host)) |
| 335 | return PTR_ERR(host); |
| 336 | |
| 337 | sdhci_get_of_property(pdev); |
| 338 | |
Oded Gabbay | dcaff04 | 2013-07-05 12:48:35 -0400 | [diff] [blame] | 339 | np = pdev->dev.of_node; |
| 340 | if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { |
| 341 | /* |
| 342 | * Freescale messed up with P2020 as it has a non-standard |
| 343 | * host control register |
| 344 | */ |
| 345 | host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; |
| 346 | } |
| 347 | |
Oded Gabbay | 66b50a0 | 2013-06-27 12:00:05 -0400 | [diff] [blame] | 348 | /* call to generic mmc_of_parse to support additional capabilities */ |
| 349 | mmc_of_parse(host->mmc); |
Haijun Zhang | 490104a | 2013-08-26 09:19:24 +0800 | [diff] [blame] | 350 | mmc_of_parse_voltage(np, &host->ocr_mask); |
Oded Gabbay | 66b50a0 | 2013-06-27 12:00:05 -0400 | [diff] [blame] | 351 | |
| 352 | ret = sdhci_add_host(host); |
| 353 | if (ret) |
| 354 | sdhci_pltfm_free(pdev); |
| 355 | |
| 356 | return ret; |
Shawn Guo | 38576af | 2011-05-27 23:48:14 +0800 | [diff] [blame] | 357 | } |
| 358 | |
Bill Pemberton | 6e0ee71 | 2012-11-19 13:26:03 -0500 | [diff] [blame] | 359 | static int sdhci_esdhc_remove(struct platform_device *pdev) |
Shawn Guo | 38576af | 2011-05-27 23:48:14 +0800 | [diff] [blame] | 360 | { |
| 361 | return sdhci_pltfm_unregister(pdev); |
| 362 | } |
| 363 | |
| 364 | static const struct of_device_id sdhci_esdhc_of_match[] = { |
| 365 | { .compatible = "fsl,mpc8379-esdhc" }, |
| 366 | { .compatible = "fsl,mpc8536-esdhc" }, |
| 367 | { .compatible = "fsl,esdhc" }, |
| 368 | { } |
| 369 | }; |
| 370 | MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); |
| 371 | |
| 372 | static struct platform_driver sdhci_esdhc_driver = { |
| 373 | .driver = { |
| 374 | .name = "sdhci-esdhc", |
| 375 | .owner = THIS_MODULE, |
| 376 | .of_match_table = sdhci_esdhc_of_match, |
Manuel Lauss | 29495aa | 2011-11-03 11:09:45 +0100 | [diff] [blame] | 377 | .pm = SDHCI_PLTFM_PMOPS, |
Shawn Guo | 38576af | 2011-05-27 23:48:14 +0800 | [diff] [blame] | 378 | }, |
| 379 | .probe = sdhci_esdhc_probe, |
Bill Pemberton | 0433c14 | 2012-11-19 13:20:26 -0500 | [diff] [blame] | 380 | .remove = sdhci_esdhc_remove, |
Shawn Guo | 38576af | 2011-05-27 23:48:14 +0800 | [diff] [blame] | 381 | }; |
| 382 | |
Axel Lin | d1f81a6 | 2011-11-26 12:55:43 +0800 | [diff] [blame] | 383 | module_platform_driver(sdhci_esdhc_driver); |
Shawn Guo | 38576af | 2011-05-27 23:48:14 +0800 | [diff] [blame] | 384 | |
| 385 | MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); |
| 386 | MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " |
| 387 | "Anton Vorontsov <avorontsov@ru.mvista.com>"); |
| 388 | MODULE_LICENSE("GPL v2"); |