Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Hash algorithms supported by the CESA: MD5, SHA1 and SHA256. |
| 3 | * |
| 4 | * Author: Boris Brezillon <boris.brezillon@free-electrons.com> |
| 5 | * Author: Arnaud Ebalard <arno@natisbad.org> |
| 6 | * |
| 7 | * This work is based on an initial version written by |
| 8 | * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc > |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License version 2 as published |
| 12 | * by the Free Software Foundation. |
| 13 | */ |
| 14 | |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 15 | #include <crypto/md5.h> |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 16 | #include <crypto/sha.h> |
| 17 | |
| 18 | #include "cesa.h" |
| 19 | |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 20 | struct mv_cesa_ahash_dma_iter { |
| 21 | struct mv_cesa_dma_iter base; |
| 22 | struct mv_cesa_sg_dma_iter src; |
| 23 | }; |
| 24 | |
| 25 | static inline void |
| 26 | mv_cesa_ahash_req_iter_init(struct mv_cesa_ahash_dma_iter *iter, |
| 27 | struct ahash_request *req) |
| 28 | { |
| 29 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
Russell King | bd274b1 | 2015-10-18 17:24:26 +0100 | [diff] [blame] | 30 | unsigned int len = req->nbytes + creq->cache_ptr; |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 31 | |
| 32 | if (!creq->last_req) |
Russell King | bd274b1 | 2015-10-18 17:24:26 +0100 | [diff] [blame] | 33 | len &= ~CESA_HASH_BLOCK_SIZE_MSK; |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 34 | |
| 35 | mv_cesa_req_dma_iter_init(&iter->base, len); |
| 36 | mv_cesa_sg_dma_iter_init(&iter->src, req->src, DMA_TO_DEVICE); |
| 37 | iter->src.op_offset = creq->cache_ptr; |
| 38 | } |
| 39 | |
| 40 | static inline bool |
| 41 | mv_cesa_ahash_req_iter_next_op(struct mv_cesa_ahash_dma_iter *iter) |
| 42 | { |
| 43 | iter->src.op_offset = 0; |
| 44 | |
| 45 | return mv_cesa_req_dma_iter_next_op(&iter->base); |
| 46 | } |
| 47 | |
Boris BREZILLON | 7850c91 | 2016-03-17 10:21:34 +0100 | [diff] [blame] | 48 | static inline int |
| 49 | mv_cesa_ahash_dma_alloc_cache(struct mv_cesa_ahash_dma_req *req, gfp_t flags) |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 50 | { |
Boris BREZILLON | 7850c91 | 2016-03-17 10:21:34 +0100 | [diff] [blame] | 51 | req->cache = dma_pool_alloc(cesa_dev->dma->cache_pool, flags, |
| 52 | &req->cache_dma); |
| 53 | if (!req->cache) |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 54 | return -ENOMEM; |
| 55 | |
| 56 | return 0; |
| 57 | } |
| 58 | |
Boris BREZILLON | 7850c91 | 2016-03-17 10:21:34 +0100 | [diff] [blame] | 59 | static inline void |
| 60 | mv_cesa_ahash_dma_free_cache(struct mv_cesa_ahash_dma_req *req) |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 61 | { |
Boris BREZILLON | 7850c91 | 2016-03-17 10:21:34 +0100 | [diff] [blame] | 62 | if (!req->cache) |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 63 | return; |
| 64 | |
Boris BREZILLON | 7850c91 | 2016-03-17 10:21:34 +0100 | [diff] [blame] | 65 | dma_pool_free(cesa_dev->dma->cache_pool, req->cache, |
| 66 | req->cache_dma); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 67 | } |
| 68 | |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 69 | static int mv_cesa_ahash_dma_alloc_padding(struct mv_cesa_ahash_dma_req *req, |
| 70 | gfp_t flags) |
| 71 | { |
| 72 | if (req->padding) |
| 73 | return 0; |
| 74 | |
| 75 | req->padding = dma_pool_alloc(cesa_dev->dma->padding_pool, flags, |
| 76 | &req->padding_dma); |
| 77 | if (!req->padding) |
| 78 | return -ENOMEM; |
| 79 | |
| 80 | return 0; |
| 81 | } |
| 82 | |
| 83 | static void mv_cesa_ahash_dma_free_padding(struct mv_cesa_ahash_dma_req *req) |
| 84 | { |
| 85 | if (!req->padding) |
| 86 | return; |
| 87 | |
| 88 | dma_pool_free(cesa_dev->dma->padding_pool, req->padding, |
| 89 | req->padding_dma); |
| 90 | req->padding = NULL; |
| 91 | } |
| 92 | |
| 93 | static inline void mv_cesa_ahash_dma_last_cleanup(struct ahash_request *req) |
| 94 | { |
| 95 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
| 96 | |
| 97 | mv_cesa_ahash_dma_free_padding(&creq->req.dma); |
| 98 | } |
| 99 | |
| 100 | static inline void mv_cesa_ahash_dma_cleanup(struct ahash_request *req) |
| 101 | { |
| 102 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
| 103 | |
| 104 | dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE); |
Boris BREZILLON | 7850c91 | 2016-03-17 10:21:34 +0100 | [diff] [blame] | 105 | mv_cesa_ahash_dma_free_cache(&creq->req.dma); |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 106 | mv_cesa_dma_cleanup(&creq->base); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 107 | } |
| 108 | |
| 109 | static inline void mv_cesa_ahash_cleanup(struct ahash_request *req) |
| 110 | { |
| 111 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
| 112 | |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 113 | if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 114 | mv_cesa_ahash_dma_cleanup(req); |
| 115 | } |
| 116 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 117 | static void mv_cesa_ahash_last_cleanup(struct ahash_request *req) |
| 118 | { |
| 119 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
| 120 | |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 121 | if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 122 | mv_cesa_ahash_dma_last_cleanup(req); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 123 | } |
| 124 | |
| 125 | static int mv_cesa_ahash_pad_len(struct mv_cesa_ahash_req *creq) |
| 126 | { |
| 127 | unsigned int index, padlen; |
| 128 | |
| 129 | index = creq->len & CESA_HASH_BLOCK_SIZE_MSK; |
| 130 | padlen = (index < 56) ? (56 - index) : (64 + 56 - index); |
| 131 | |
| 132 | return padlen; |
| 133 | } |
| 134 | |
| 135 | static int mv_cesa_ahash_pad_req(struct mv_cesa_ahash_req *creq, u8 *buf) |
| 136 | { |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 137 | unsigned int index, padlen; |
| 138 | |
| 139 | buf[0] = 0x80; |
| 140 | /* Pad out to 56 mod 64 */ |
| 141 | index = creq->len & CESA_HASH_BLOCK_SIZE_MSK; |
| 142 | padlen = mv_cesa_ahash_pad_len(creq); |
| 143 | memset(buf + 1, 0, padlen - 1); |
Russell King | 51954a9 | 2015-10-18 17:23:46 +0100 | [diff] [blame] | 144 | |
| 145 | if (creq->algo_le) { |
| 146 | __le64 bits = cpu_to_le64(creq->len << 3); |
| 147 | memcpy(buf + padlen, &bits, sizeof(bits)); |
| 148 | } else { |
| 149 | __be64 bits = cpu_to_be64(creq->len << 3); |
| 150 | memcpy(buf + padlen, &bits, sizeof(bits)); |
| 151 | } |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 152 | |
| 153 | return padlen + 8; |
| 154 | } |
| 155 | |
| 156 | static void mv_cesa_ahash_std_step(struct ahash_request *req) |
| 157 | { |
| 158 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
| 159 | struct mv_cesa_ahash_std_req *sreq = &creq->req.std; |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 160 | struct mv_cesa_engine *engine = creq->base.engine; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 161 | struct mv_cesa_op_ctx *op; |
| 162 | unsigned int new_cache_ptr = 0; |
| 163 | u32 frag_mode; |
| 164 | size_t len; |
Romain Perier | 2786cee | 2016-06-21 10:08:37 +0200 | [diff] [blame] | 165 | unsigned int digsize; |
| 166 | int i; |
| 167 | |
| 168 | mv_cesa_adjust_op(engine, &creq->op_tmpl); |
| 169 | memcpy_toio(engine->sram, &creq->op_tmpl, sizeof(creq->op_tmpl)); |
| 170 | |
Romain Perier | 9e5f7a1 | 2016-12-05 09:56:39 +0100 | [diff] [blame] | 171 | if (!sreq->offset) { |
| 172 | digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(req)); |
| 173 | for (i = 0; i < digsize / 4; i++) |
| 174 | writel_relaxed(creq->state[i], engine->regs + CESA_IVDIG(i)); |
| 175 | } |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 176 | |
| 177 | if (creq->cache_ptr) |
Russell King | 0f3304d | 2015-10-18 18:31:15 +0100 | [diff] [blame] | 178 | memcpy_toio(engine->sram + CESA_SA_DATA_SRAM_OFFSET, |
| 179 | creq->cache, creq->cache_ptr); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 180 | |
| 181 | len = min_t(size_t, req->nbytes + creq->cache_ptr - sreq->offset, |
| 182 | CESA_SA_SRAM_PAYLOAD_SIZE); |
| 183 | |
| 184 | if (!creq->last_req) { |
| 185 | new_cache_ptr = len & CESA_HASH_BLOCK_SIZE_MSK; |
| 186 | len &= ~CESA_HASH_BLOCK_SIZE_MSK; |
| 187 | } |
| 188 | |
| 189 | if (len - creq->cache_ptr) |
| 190 | sreq->offset += sg_pcopy_to_buffer(req->src, creq->src_nents, |
| 191 | engine->sram + |
| 192 | CESA_SA_DATA_SRAM_OFFSET + |
| 193 | creq->cache_ptr, |
| 194 | len - creq->cache_ptr, |
| 195 | sreq->offset); |
| 196 | |
| 197 | op = &creq->op_tmpl; |
| 198 | |
| 199 | frag_mode = mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK; |
| 200 | |
| 201 | if (creq->last_req && sreq->offset == req->nbytes && |
| 202 | creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) { |
| 203 | if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG) |
| 204 | frag_mode = CESA_SA_DESC_CFG_NOT_FRAG; |
| 205 | else if (frag_mode == CESA_SA_DESC_CFG_MID_FRAG) |
| 206 | frag_mode = CESA_SA_DESC_CFG_LAST_FRAG; |
| 207 | } |
| 208 | |
| 209 | if (frag_mode == CESA_SA_DESC_CFG_NOT_FRAG || |
| 210 | frag_mode == CESA_SA_DESC_CFG_LAST_FRAG) { |
| 211 | if (len && |
| 212 | creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) { |
| 213 | mv_cesa_set_mac_op_total_len(op, creq->len); |
| 214 | } else { |
| 215 | int trailerlen = mv_cesa_ahash_pad_len(creq) + 8; |
| 216 | |
| 217 | if (len + trailerlen > CESA_SA_SRAM_PAYLOAD_SIZE) { |
| 218 | len &= CESA_HASH_BLOCK_SIZE_MSK; |
| 219 | new_cache_ptr = 64 - trailerlen; |
Russell King | 0f3304d | 2015-10-18 18:31:15 +0100 | [diff] [blame] | 220 | memcpy_fromio(creq->cache, |
| 221 | engine->sram + |
| 222 | CESA_SA_DATA_SRAM_OFFSET + len, |
| 223 | new_cache_ptr); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 224 | } else { |
| 225 | len += mv_cesa_ahash_pad_req(creq, |
| 226 | engine->sram + len + |
| 227 | CESA_SA_DATA_SRAM_OFFSET); |
| 228 | } |
| 229 | |
| 230 | if (frag_mode == CESA_SA_DESC_CFG_LAST_FRAG) |
| 231 | frag_mode = CESA_SA_DESC_CFG_MID_FRAG; |
| 232 | else |
| 233 | frag_mode = CESA_SA_DESC_CFG_FIRST_FRAG; |
| 234 | } |
| 235 | } |
| 236 | |
| 237 | mv_cesa_set_mac_op_frag_len(op, len); |
| 238 | mv_cesa_update_op_cfg(op, frag_mode, CESA_SA_DESC_CFG_FRAG_MSK); |
| 239 | |
| 240 | /* FIXME: only update enc_len field */ |
Russell King | 0f3304d | 2015-10-18 18:31:15 +0100 | [diff] [blame] | 241 | memcpy_toio(engine->sram, op, sizeof(*op)); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 242 | |
| 243 | if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG) |
| 244 | mv_cesa_update_op_cfg(op, CESA_SA_DESC_CFG_MID_FRAG, |
| 245 | CESA_SA_DESC_CFG_FRAG_MSK); |
| 246 | |
| 247 | creq->cache_ptr = new_cache_ptr; |
| 248 | |
| 249 | mv_cesa_set_int_mask(engine, CESA_SA_INT_ACCEL0_DONE); |
Russell King | b150856 | 2015-10-18 18:31:00 +0100 | [diff] [blame] | 250 | writel_relaxed(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG); |
Romain Perier | f628308 | 2016-06-21 10:08:32 +0200 | [diff] [blame] | 251 | BUG_ON(readl(engine->regs + CESA_SA_CMD) & |
| 252 | CESA_SA_CMD_EN_CESA_SA_ACCL0); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 253 | writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD); |
| 254 | } |
| 255 | |
| 256 | static int mv_cesa_ahash_std_process(struct ahash_request *req, u32 status) |
| 257 | { |
| 258 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
| 259 | struct mv_cesa_ahash_std_req *sreq = &creq->req.std; |
| 260 | |
| 261 | if (sreq->offset < (req->nbytes - creq->cache_ptr)) |
| 262 | return -EINPROGRESS; |
| 263 | |
| 264 | return 0; |
| 265 | } |
| 266 | |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 267 | static inline void mv_cesa_ahash_dma_prepare(struct ahash_request *req) |
| 268 | { |
| 269 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 270 | struct mv_cesa_req *basereq = &creq->base; |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 271 | |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 272 | mv_cesa_dma_prepare(basereq, basereq->engine); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 273 | } |
| 274 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 275 | static void mv_cesa_ahash_std_prepare(struct ahash_request *req) |
| 276 | { |
| 277 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
| 278 | struct mv_cesa_ahash_std_req *sreq = &creq->req.std; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 279 | |
| 280 | sreq->offset = 0; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 281 | } |
| 282 | |
Romain Perier | bdc2571 | 2016-12-14 15:15:07 +0100 | [diff] [blame] | 283 | static void mv_cesa_ahash_dma_step(struct ahash_request *req) |
| 284 | { |
| 285 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
| 286 | struct mv_cesa_req *base = &creq->base; |
| 287 | |
| 288 | /* We must explicitly set the digest state. */ |
| 289 | if (base->chain.first->flags & CESA_TDMA_SET_STATE) { |
| 290 | struct mv_cesa_engine *engine = base->engine; |
| 291 | int i; |
| 292 | |
| 293 | /* Set the hash state in the IVDIG regs. */ |
| 294 | for (i = 0; i < ARRAY_SIZE(creq->state); i++) |
| 295 | writel_relaxed(creq->state[i], engine->regs + |
| 296 | CESA_IVDIG(i)); |
| 297 | } |
| 298 | |
| 299 | mv_cesa_dma_step(base); |
| 300 | } |
| 301 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 302 | static void mv_cesa_ahash_step(struct crypto_async_request *req) |
| 303 | { |
| 304 | struct ahash_request *ahashreq = ahash_request_cast(req); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 305 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 306 | |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 307 | if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) |
Romain Perier | bdc2571 | 2016-12-14 15:15:07 +0100 | [diff] [blame] | 308 | mv_cesa_ahash_dma_step(ahashreq); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 309 | else |
| 310 | mv_cesa_ahash_std_step(ahashreq); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 311 | } |
| 312 | |
| 313 | static int mv_cesa_ahash_process(struct crypto_async_request *req, u32 status) |
| 314 | { |
| 315 | struct ahash_request *ahashreq = ahash_request_cast(req); |
| 316 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 317 | |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 318 | if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) |
Romain Perier | 1bf6682 | 2016-06-21 10:08:36 +0200 | [diff] [blame] | 319 | return mv_cesa_dma_process(&creq->base, status); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 320 | |
Romain Perier | 1bf6682 | 2016-06-21 10:08:36 +0200 | [diff] [blame] | 321 | return mv_cesa_ahash_std_process(ahashreq, status); |
| 322 | } |
| 323 | |
| 324 | static void mv_cesa_ahash_complete(struct crypto_async_request *req) |
| 325 | { |
| 326 | struct ahash_request *ahashreq = ahash_request_cast(req); |
| 327 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq); |
| 328 | struct mv_cesa_engine *engine = creq->base.engine; |
| 329 | unsigned int digsize; |
| 330 | int i; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 331 | |
| 332 | digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq)); |
| 333 | for (i = 0; i < digsize / 4; i++) |
Russell King | b150856 | 2015-10-18 18:31:00 +0100 | [diff] [blame] | 334 | creq->state[i] = readl_relaxed(engine->regs + CESA_IVDIG(i)); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 335 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 336 | if (creq->last_req) { |
Russell King | 4c2b130 | 2015-10-18 17:23:35 +0100 | [diff] [blame] | 337 | /* |
| 338 | * Hardware's MD5 digest is in little endian format, but |
| 339 | * SHA in big endian format |
| 340 | */ |
Russell King | a9eb678 | 2015-10-18 17:23:40 +0100 | [diff] [blame] | 341 | if (creq->algo_le) { |
Russell King | 4c2b130 | 2015-10-18 17:23:35 +0100 | [diff] [blame] | 342 | __le32 *result = (void *)ahashreq->result; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 343 | |
Russell King | 4c2b130 | 2015-10-18 17:23:35 +0100 | [diff] [blame] | 344 | for (i = 0; i < digsize / 4; i++) |
| 345 | result[i] = cpu_to_le32(creq->state[i]); |
| 346 | } else { |
| 347 | __be32 *result = (void *)ahashreq->result; |
| 348 | |
| 349 | for (i = 0; i < digsize / 4; i++) |
| 350 | result[i] = cpu_to_be32(creq->state[i]); |
| 351 | } |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 352 | } |
Romain Perier | bf8f91e | 2016-06-21 10:08:38 +0200 | [diff] [blame] | 353 | |
| 354 | atomic_sub(ahashreq->nbytes, &engine->load); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 355 | } |
| 356 | |
| 357 | static void mv_cesa_ahash_prepare(struct crypto_async_request *req, |
| 358 | struct mv_cesa_engine *engine) |
| 359 | { |
| 360 | struct ahash_request *ahashreq = ahash_request_cast(req); |
| 361 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 362 | |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 363 | creq->base.engine = engine; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 364 | |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 365 | if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 366 | mv_cesa_ahash_dma_prepare(ahashreq); |
| 367 | else |
| 368 | mv_cesa_ahash_std_prepare(ahashreq); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 369 | } |
| 370 | |
| 371 | static void mv_cesa_ahash_req_cleanup(struct crypto_async_request *req) |
| 372 | { |
| 373 | struct ahash_request *ahashreq = ahash_request_cast(req); |
| 374 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq); |
| 375 | |
| 376 | if (creq->last_req) |
| 377 | mv_cesa_ahash_last_cleanup(ahashreq); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 378 | |
| 379 | mv_cesa_ahash_cleanup(ahashreq); |
Romain Perier | 64ec6cc | 2016-07-22 15:46:24 +0200 | [diff] [blame] | 380 | |
| 381 | if (creq->cache_ptr) |
| 382 | sg_pcopy_to_buffer(ahashreq->src, creq->src_nents, |
| 383 | creq->cache, |
| 384 | creq->cache_ptr, |
| 385 | ahashreq->nbytes - creq->cache_ptr); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 386 | } |
| 387 | |
| 388 | static const struct mv_cesa_req_ops mv_cesa_ahash_req_ops = { |
| 389 | .step = mv_cesa_ahash_step, |
| 390 | .process = mv_cesa_ahash_process, |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 391 | .cleanup = mv_cesa_ahash_req_cleanup, |
Romain Perier | 1bf6682 | 2016-06-21 10:08:36 +0200 | [diff] [blame] | 392 | .complete = mv_cesa_ahash_complete, |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 393 | }; |
| 394 | |
Thomas Petazzoni | 3e5c66c | 2016-08-09 11:03:16 +0200 | [diff] [blame] | 395 | static void mv_cesa_ahash_init(struct ahash_request *req, |
Russell King | a9eb678 | 2015-10-18 17:23:40 +0100 | [diff] [blame] | 396 | struct mv_cesa_op_ctx *tmpl, bool algo_le) |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 397 | { |
| 398 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
| 399 | |
| 400 | memset(creq, 0, sizeof(*creq)); |
| 401 | mv_cesa_update_op_cfg(tmpl, |
| 402 | CESA_SA_DESC_CFG_OP_MAC_ONLY | |
| 403 | CESA_SA_DESC_CFG_FIRST_FRAG, |
| 404 | CESA_SA_DESC_CFG_OP_MSK | |
| 405 | CESA_SA_DESC_CFG_FRAG_MSK); |
| 406 | mv_cesa_set_mac_op_total_len(tmpl, 0); |
| 407 | mv_cesa_set_mac_op_frag_len(tmpl, 0); |
| 408 | creq->op_tmpl = *tmpl; |
| 409 | creq->len = 0; |
Russell King | a9eb678 | 2015-10-18 17:23:40 +0100 | [diff] [blame] | 410 | creq->algo_le = algo_le; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 411 | } |
| 412 | |
| 413 | static inline int mv_cesa_ahash_cra_init(struct crypto_tfm *tfm) |
| 414 | { |
| 415 | struct mv_cesa_hash_ctx *ctx = crypto_tfm_ctx(tfm); |
| 416 | |
| 417 | ctx->base.ops = &mv_cesa_ahash_req_ops; |
| 418 | |
| 419 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), |
| 420 | sizeof(struct mv_cesa_ahash_req)); |
| 421 | return 0; |
| 422 | } |
| 423 | |
Thomas Petazzoni | 6dc156f | 2016-08-09 11:03:17 +0200 | [diff] [blame] | 424 | static bool mv_cesa_ahash_cache_req(struct ahash_request *req) |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 425 | { |
| 426 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
Thomas Petazzoni | 6dc156f | 2016-08-09 11:03:17 +0200 | [diff] [blame] | 427 | bool cached = false; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 428 | |
Romain Perier | 4785620 | 2016-08-09 11:03:20 +0200 | [diff] [blame] | 429 | if (creq->cache_ptr + req->nbytes < CESA_MAX_HASH_BLOCK_SIZE && !creq->last_req) { |
Thomas Petazzoni | 6dc156f | 2016-08-09 11:03:17 +0200 | [diff] [blame] | 430 | cached = true; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 431 | |
| 432 | if (!req->nbytes) |
Thomas Petazzoni | 6dc156f | 2016-08-09 11:03:17 +0200 | [diff] [blame] | 433 | return cached; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 434 | |
| 435 | sg_pcopy_to_buffer(req->src, creq->src_nents, |
| 436 | creq->cache + creq->cache_ptr, |
| 437 | req->nbytes, 0); |
| 438 | |
| 439 | creq->cache_ptr += req->nbytes; |
| 440 | } |
| 441 | |
Thomas Petazzoni | 6dc156f | 2016-08-09 11:03:17 +0200 | [diff] [blame] | 442 | return cached; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 443 | } |
| 444 | |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 445 | static struct mv_cesa_op_ctx * |
Russell King | 9621288 | 2015-10-18 17:24:06 +0100 | [diff] [blame] | 446 | mv_cesa_dma_add_frag(struct mv_cesa_tdma_chain *chain, |
| 447 | struct mv_cesa_op_ctx *tmpl, unsigned int frag_len, |
| 448 | gfp_t flags) |
| 449 | { |
| 450 | struct mv_cesa_op_ctx *op; |
| 451 | int ret; |
| 452 | |
| 453 | op = mv_cesa_dma_add_op(chain, tmpl, false, flags); |
| 454 | if (IS_ERR(op)) |
| 455 | return op; |
| 456 | |
| 457 | /* Set the operation block fragment length. */ |
| 458 | mv_cesa_set_mac_op_frag_len(op, frag_len); |
| 459 | |
| 460 | /* Append dummy desc to launch operation */ |
| 461 | ret = mv_cesa_dma_add_dummy_launch(chain, flags); |
| 462 | if (ret) |
| 463 | return ERR_PTR(ret); |
| 464 | |
Russell King | 2f396a9 | 2015-10-18 17:24:11 +0100 | [diff] [blame] | 465 | if (mv_cesa_mac_op_is_first_frag(tmpl)) |
| 466 | mv_cesa_update_op_cfg(tmpl, |
| 467 | CESA_SA_DESC_CFG_MID_FRAG, |
| 468 | CESA_SA_DESC_CFG_FRAG_MSK); |
| 469 | |
Russell King | 9621288 | 2015-10-18 17:24:06 +0100 | [diff] [blame] | 470 | return op; |
| 471 | } |
| 472 | |
Russell King | 0971d09 | 2015-10-18 17:24:16 +0100 | [diff] [blame] | 473 | static int |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 474 | mv_cesa_ahash_dma_add_cache(struct mv_cesa_tdma_chain *chain, |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 475 | struct mv_cesa_ahash_req *creq, |
| 476 | gfp_t flags) |
| 477 | { |
| 478 | struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma; |
Boris BREZILLON | 7850c91 | 2016-03-17 10:21:34 +0100 | [diff] [blame] | 479 | int ret; |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 480 | |
| 481 | if (!creq->cache_ptr) |
Russell King | 0971d09 | 2015-10-18 17:24:16 +0100 | [diff] [blame] | 482 | return 0; |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 483 | |
Boris BREZILLON | 7850c91 | 2016-03-17 10:21:34 +0100 | [diff] [blame] | 484 | ret = mv_cesa_ahash_dma_alloc_cache(ahashdreq, flags); |
| 485 | if (ret) |
| 486 | return ret; |
| 487 | |
| 488 | memcpy(ahashdreq->cache, creq->cache, creq->cache_ptr); |
| 489 | |
Russell King | 0971d09 | 2015-10-18 17:24:16 +0100 | [diff] [blame] | 490 | return mv_cesa_dma_add_data_transfer(chain, |
| 491 | CESA_SA_DATA_SRAM_OFFSET, |
| 492 | ahashdreq->cache_dma, |
| 493 | creq->cache_ptr, |
| 494 | CESA_TDMA_DST_IN_SRAM, |
| 495 | flags); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 496 | } |
| 497 | |
| 498 | static struct mv_cesa_op_ctx * |
| 499 | mv_cesa_ahash_dma_last_req(struct mv_cesa_tdma_chain *chain, |
| 500 | struct mv_cesa_ahash_dma_iter *dma_iter, |
| 501 | struct mv_cesa_ahash_req *creq, |
Russell King | 58953e1 | 2015-10-18 17:24:37 +0100 | [diff] [blame] | 502 | unsigned int frag_len, gfp_t flags) |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 503 | { |
| 504 | struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma; |
| 505 | unsigned int len, trailerlen, padoff = 0; |
Russell King | 58953e1 | 2015-10-18 17:24:37 +0100 | [diff] [blame] | 506 | struct mv_cesa_op_ctx *op; |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 507 | int ret; |
| 508 | |
Russell King | aee84a7 | 2015-10-18 17:24:42 +0100 | [diff] [blame] | 509 | /* |
| 510 | * If the transfer is smaller than our maximum length, and we have |
| 511 | * some data outstanding, we can ask the engine to finish the hash. |
| 512 | */ |
| 513 | if (creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX && frag_len) { |
| 514 | op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len, |
| 515 | flags); |
| 516 | if (IS_ERR(op)) |
| 517 | return op; |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 518 | |
Russell King | aee84a7 | 2015-10-18 17:24:42 +0100 | [diff] [blame] | 519 | mv_cesa_set_mac_op_total_len(op, creq->len); |
| 520 | mv_cesa_update_op_cfg(op, mv_cesa_mac_op_is_first_frag(op) ? |
| 521 | CESA_SA_DESC_CFG_NOT_FRAG : |
| 522 | CESA_SA_DESC_CFG_LAST_FRAG, |
| 523 | CESA_SA_DESC_CFG_FRAG_MSK); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 524 | |
| 525 | return op; |
| 526 | } |
| 527 | |
Russell King | aee84a7 | 2015-10-18 17:24:42 +0100 | [diff] [blame] | 528 | /* |
| 529 | * The request is longer than the engine can handle, or we have |
| 530 | * no data outstanding. Manually generate the padding, adding it |
| 531 | * as a "mid" fragment. |
| 532 | */ |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 533 | ret = mv_cesa_ahash_dma_alloc_padding(ahashdreq, flags); |
| 534 | if (ret) |
| 535 | return ERR_PTR(ret); |
| 536 | |
| 537 | trailerlen = mv_cesa_ahash_pad_req(creq, ahashdreq->padding); |
| 538 | |
Russell King | ab270e7 | 2015-10-18 17:24:47 +0100 | [diff] [blame] | 539 | len = min(CESA_SA_SRAM_PAYLOAD_SIZE - frag_len, trailerlen); |
| 540 | if (len) { |
| 541 | ret = mv_cesa_dma_add_data_transfer(chain, |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 542 | CESA_SA_DATA_SRAM_OFFSET + |
Russell King | ab270e7 | 2015-10-18 17:24:47 +0100 | [diff] [blame] | 543 | frag_len, |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 544 | ahashdreq->padding_dma, |
| 545 | len, CESA_TDMA_DST_IN_SRAM, |
| 546 | flags); |
Russell King | ab270e7 | 2015-10-18 17:24:47 +0100 | [diff] [blame] | 547 | if (ret) |
| 548 | return ERR_PTR(ret); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 549 | |
Russell King | ab270e7 | 2015-10-18 17:24:47 +0100 | [diff] [blame] | 550 | op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len + len, |
| 551 | flags); |
| 552 | if (IS_ERR(op)) |
| 553 | return op; |
| 554 | |
Russell King | ab270e7 | 2015-10-18 17:24:47 +0100 | [diff] [blame] | 555 | if (len == trailerlen) |
| 556 | return op; |
| 557 | |
| 558 | padoff += len; |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 559 | } |
| 560 | |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 561 | ret = mv_cesa_dma_add_data_transfer(chain, |
| 562 | CESA_SA_DATA_SRAM_OFFSET, |
| 563 | ahashdreq->padding_dma + |
| 564 | padoff, |
| 565 | trailerlen - padoff, |
| 566 | CESA_TDMA_DST_IN_SRAM, |
| 567 | flags); |
| 568 | if (ret) |
| 569 | return ERR_PTR(ret); |
| 570 | |
Russell King | 9621288 | 2015-10-18 17:24:06 +0100 | [diff] [blame] | 571 | return mv_cesa_dma_add_frag(chain, &creq->op_tmpl, trailerlen - padoff, |
| 572 | flags); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 573 | } |
| 574 | |
| 575 | static int mv_cesa_ahash_dma_req_init(struct ahash_request *req) |
| 576 | { |
| 577 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
| 578 | gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? |
| 579 | GFP_KERNEL : GFP_ATOMIC; |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 580 | struct mv_cesa_req *basereq = &creq->base; |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 581 | struct mv_cesa_ahash_dma_iter iter; |
| 582 | struct mv_cesa_op_ctx *op = NULL; |
Russell King | e41bbeb | 2015-10-18 17:24:32 +0100 | [diff] [blame] | 583 | unsigned int frag_len; |
Romain Perier | bdc2571 | 2016-12-14 15:15:07 +0100 | [diff] [blame] | 584 | bool set_state = false; |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 585 | int ret; |
| 586 | |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 587 | basereq->chain.first = NULL; |
| 588 | basereq->chain.last = NULL; |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 589 | |
Romain Perier | bdc2571 | 2016-12-14 15:15:07 +0100 | [diff] [blame] | 590 | if (!mv_cesa_mac_op_is_first_frag(&creq->op_tmpl)) |
| 591 | set_state = true; |
| 592 | |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 593 | if (creq->src_nents) { |
| 594 | ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents, |
| 595 | DMA_TO_DEVICE); |
| 596 | if (!ret) { |
| 597 | ret = -ENOMEM; |
| 598 | goto err; |
| 599 | } |
| 600 | } |
| 601 | |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 602 | mv_cesa_tdma_desc_iter_init(&basereq->chain); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 603 | mv_cesa_ahash_req_iter_init(&iter, req); |
| 604 | |
Russell King | 0971d09 | 2015-10-18 17:24:16 +0100 | [diff] [blame] | 605 | /* |
| 606 | * Add the cache (left-over data from a previous block) first. |
| 607 | * This will never overflow the SRAM size. |
| 608 | */ |
Thomas Petazzoni | 2a8a785 | 2016-08-09 11:03:15 +0200 | [diff] [blame] | 609 | ret = mv_cesa_ahash_dma_add_cache(&basereq->chain, creq, flags); |
Russell King | 0971d09 | 2015-10-18 17:24:16 +0100 | [diff] [blame] | 610 | if (ret) |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 611 | goto err_free_tdma; |
Russell King | 0971d09 | 2015-10-18 17:24:16 +0100 | [diff] [blame] | 612 | |
Russell King | d9bba4c | 2015-10-18 17:24:21 +0100 | [diff] [blame] | 613 | if (iter.src.sg) { |
| 614 | /* |
| 615 | * Add all the new data, inserting an operation block and |
| 616 | * launch command between each full SRAM block-worth of |
Russell King | e41bbeb | 2015-10-18 17:24:32 +0100 | [diff] [blame] | 617 | * data. We intentionally do not add the final op block. |
Russell King | d9bba4c | 2015-10-18 17:24:21 +0100 | [diff] [blame] | 618 | */ |
Russell King | e41bbeb | 2015-10-18 17:24:32 +0100 | [diff] [blame] | 619 | while (true) { |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 620 | ret = mv_cesa_dma_add_op_transfers(&basereq->chain, |
Boris Brezillon | 8c07f3a | 2015-10-18 17:24:57 +0100 | [diff] [blame] | 621 | &iter.base, |
Russell King | d9bba4c | 2015-10-18 17:24:21 +0100 | [diff] [blame] | 622 | &iter.src, flags); |
| 623 | if (ret) |
| 624 | goto err_free_tdma; |
| 625 | |
Russell King | e41bbeb | 2015-10-18 17:24:32 +0100 | [diff] [blame] | 626 | frag_len = iter.base.op_len; |
| 627 | |
| 628 | if (!mv_cesa_ahash_req_iter_next_op(&iter)) |
| 629 | break; |
| 630 | |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 631 | op = mv_cesa_dma_add_frag(&basereq->chain, &creq->op_tmpl, |
Russell King | e41bbeb | 2015-10-18 17:24:32 +0100 | [diff] [blame] | 632 | frag_len, flags); |
Russell King | d9bba4c | 2015-10-18 17:24:21 +0100 | [diff] [blame] | 633 | if (IS_ERR(op)) { |
| 634 | ret = PTR_ERR(op); |
| 635 | goto err_free_tdma; |
| 636 | } |
Russell King | e41bbeb | 2015-10-18 17:24:32 +0100 | [diff] [blame] | 637 | } |
| 638 | } else { |
Russell King | d9bba4c | 2015-10-18 17:24:21 +0100 | [diff] [blame] | 639 | /* Account for the data that was in the cache. */ |
Russell King | e41bbeb | 2015-10-18 17:24:32 +0100 | [diff] [blame] | 640 | frag_len = iter.base.op_len; |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 641 | } |
| 642 | |
Russell King | 58953e1 | 2015-10-18 17:24:37 +0100 | [diff] [blame] | 643 | /* |
| 644 | * At this point, frag_len indicates whether we have any data |
| 645 | * outstanding which needs an operation. Queue up the final |
| 646 | * operation, which depends whether this is the final request. |
| 647 | */ |
| 648 | if (creq->last_req) |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 649 | op = mv_cesa_ahash_dma_last_req(&basereq->chain, &iter, creq, |
Boris Brezillon | 8c07f3a | 2015-10-18 17:24:57 +0100 | [diff] [blame] | 650 | frag_len, flags); |
Russell King | 58953e1 | 2015-10-18 17:24:37 +0100 | [diff] [blame] | 651 | else if (frag_len) |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 652 | op = mv_cesa_dma_add_frag(&basereq->chain, &creq->op_tmpl, |
Boris Brezillon | 8c07f3a | 2015-10-18 17:24:57 +0100 | [diff] [blame] | 653 | frag_len, flags); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 654 | |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 655 | if (IS_ERR(op)) { |
| 656 | ret = PTR_ERR(op); |
| 657 | goto err_free_tdma; |
| 658 | } |
| 659 | |
| 660 | if (op) { |
| 661 | /* Add dummy desc to wait for crypto operation end */ |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 662 | ret = mv_cesa_dma_add_dummy_end(&basereq->chain, flags); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 663 | if (ret) |
| 664 | goto err_free_tdma; |
| 665 | } |
| 666 | |
| 667 | if (!creq->last_req) |
| 668 | creq->cache_ptr = req->nbytes + creq->cache_ptr - |
| 669 | iter.base.len; |
| 670 | else |
| 671 | creq->cache_ptr = 0; |
| 672 | |
Romain Perier | 85030c5 | 2016-06-21 10:08:39 +0200 | [diff] [blame] | 673 | basereq->chain.last->flags |= (CESA_TDMA_END_OF_REQ | |
| 674 | CESA_TDMA_BREAK_CHAIN); |
| 675 | |
Romain Perier | bdc2571 | 2016-12-14 15:15:07 +0100 | [diff] [blame] | 676 | if (set_state) { |
| 677 | /* |
| 678 | * Put the CESA_TDMA_SET_STATE flag on the first tdma desc to |
| 679 | * let the step logic know that the IVDIG registers should be |
| 680 | * explicitly set before launching a TDMA chain. |
| 681 | */ |
| 682 | basereq->chain.first->flags |= CESA_TDMA_SET_STATE; |
| 683 | } |
| 684 | |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 685 | return 0; |
| 686 | |
| 687 | err_free_tdma: |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 688 | mv_cesa_dma_cleanup(basereq); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 689 | dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE); |
| 690 | |
| 691 | err: |
| 692 | mv_cesa_ahash_last_cleanup(req); |
| 693 | |
| 694 | return ret; |
| 695 | } |
| 696 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 697 | static int mv_cesa_ahash_req_init(struct ahash_request *req, bool *cached) |
| 698 | { |
| 699 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
| 700 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 701 | creq->src_nents = sg_nents_for_len(req->src, req->nbytes); |
LABBE Corentin | c22dafb | 2015-11-04 21:13:33 +0100 | [diff] [blame] | 702 | if (creq->src_nents < 0) { |
| 703 | dev_err(cesa_dev->dev, "Invalid number of src SG"); |
| 704 | return creq->src_nents; |
| 705 | } |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 706 | |
Thomas Petazzoni | 6dc156f | 2016-08-09 11:03:17 +0200 | [diff] [blame] | 707 | *cached = mv_cesa_ahash_cache_req(req); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 708 | |
| 709 | if (*cached) |
| 710 | return 0; |
| 711 | |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 712 | if (cesa_dev->caps->has_tdma) |
Thomas Petazzoni | 6dc156f | 2016-08-09 11:03:17 +0200 | [diff] [blame] | 713 | return mv_cesa_ahash_dma_req_init(req); |
| 714 | else |
| 715 | return 0; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 716 | } |
| 717 | |
Romain Perier | bf8f91e | 2016-06-21 10:08:38 +0200 | [diff] [blame] | 718 | static int mv_cesa_ahash_queue_req(struct ahash_request *req) |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 719 | { |
| 720 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
Romain Perier | bf8f91e | 2016-06-21 10:08:38 +0200 | [diff] [blame] | 721 | struct mv_cesa_engine *engine; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 722 | bool cached = false; |
| 723 | int ret; |
| 724 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 725 | ret = mv_cesa_ahash_req_init(req, &cached); |
| 726 | if (ret) |
| 727 | return ret; |
| 728 | |
| 729 | if (cached) |
| 730 | return 0; |
| 731 | |
Romain Perier | bf8f91e | 2016-06-21 10:08:38 +0200 | [diff] [blame] | 732 | engine = mv_cesa_select_engine(req->nbytes); |
| 733 | mv_cesa_ahash_prepare(&req->base, engine); |
| 734 | |
Romain Perier | 53da740 | 2016-06-21 10:08:35 +0200 | [diff] [blame] | 735 | ret = mv_cesa_queue_req(&req->base, &creq->base); |
Romain Perier | bf8f91e | 2016-06-21 10:08:38 +0200 | [diff] [blame] | 736 | |
Thomas Petazzoni | cfcd227 | 2015-09-18 17:25:36 +0200 | [diff] [blame] | 737 | if (mv_cesa_req_needs_cleanup(&req->base, ret)) |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 738 | mv_cesa_ahash_cleanup(req); |
Boris BREZILLON | db509a4 | 2015-06-18 15:46:21 +0200 | [diff] [blame] | 739 | |
| 740 | return ret; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 741 | } |
| 742 | |
Romain Perier | bf8f91e | 2016-06-21 10:08:38 +0200 | [diff] [blame] | 743 | static int mv_cesa_ahash_update(struct ahash_request *req) |
| 744 | { |
| 745 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
| 746 | |
| 747 | creq->len += req->nbytes; |
| 748 | |
| 749 | return mv_cesa_ahash_queue_req(req); |
| 750 | } |
| 751 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 752 | static int mv_cesa_ahash_final(struct ahash_request *req) |
| 753 | { |
| 754 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
| 755 | struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 756 | |
| 757 | mv_cesa_set_mac_op_total_len(tmpl, creq->len); |
| 758 | creq->last_req = true; |
| 759 | req->nbytes = 0; |
| 760 | |
Romain Perier | bf8f91e | 2016-06-21 10:08:38 +0200 | [diff] [blame] | 761 | return mv_cesa_ahash_queue_req(req); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 762 | } |
| 763 | |
| 764 | static int mv_cesa_ahash_finup(struct ahash_request *req) |
| 765 | { |
| 766 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
| 767 | struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 768 | |
| 769 | creq->len += req->nbytes; |
| 770 | mv_cesa_set_mac_op_total_len(tmpl, creq->len); |
| 771 | creq->last_req = true; |
| 772 | |
Romain Perier | bf8f91e | 2016-06-21 10:08:38 +0200 | [diff] [blame] | 773 | return mv_cesa_ahash_queue_req(req); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 774 | } |
| 775 | |
Russell King | a6479ea | 2015-10-09 21:14:22 +0100 | [diff] [blame] | 776 | static int mv_cesa_ahash_export(struct ahash_request *req, void *hash, |
| 777 | u64 *len, void *cache) |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 778 | { |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 779 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); |
| 780 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
| 781 | unsigned int digsize = crypto_ahash_digestsize(ahash); |
Russell King | a6479ea | 2015-10-09 21:14:22 +0100 | [diff] [blame] | 782 | unsigned int blocksize; |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 783 | |
Russell King | 8075453 | 2015-10-18 17:23:30 +0100 | [diff] [blame] | 784 | blocksize = crypto_ahash_blocksize(ahash); |
Russell King | a6479ea | 2015-10-09 21:14:22 +0100 | [diff] [blame] | 785 | |
| 786 | *len = creq->len; |
| 787 | memcpy(hash, creq->state, digsize); |
| 788 | memset(cache, 0, blocksize); |
Dan Carpenter | 063327f | 2016-03-21 12:03:43 +0300 | [diff] [blame] | 789 | memcpy(cache, creq->cache, creq->cache_ptr); |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 790 | |
| 791 | return 0; |
| 792 | } |
| 793 | |
Russell King | a6479ea | 2015-10-09 21:14:22 +0100 | [diff] [blame] | 794 | static int mv_cesa_ahash_import(struct ahash_request *req, const void *hash, |
| 795 | u64 len, const void *cache) |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 796 | { |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 797 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); |
| 798 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
| 799 | unsigned int digsize = crypto_ahash_digestsize(ahash); |
Russell King | a6479ea | 2015-10-09 21:14:22 +0100 | [diff] [blame] | 800 | unsigned int blocksize; |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 801 | unsigned int cache_ptr; |
| 802 | int ret; |
| 803 | |
Russell King | a6479ea | 2015-10-09 21:14:22 +0100 | [diff] [blame] | 804 | ret = crypto_ahash_init(req); |
| 805 | if (ret) |
| 806 | return ret; |
| 807 | |
Russell King | 8075453 | 2015-10-18 17:23:30 +0100 | [diff] [blame] | 808 | blocksize = crypto_ahash_blocksize(ahash); |
Russell King | a6479ea | 2015-10-09 21:14:22 +0100 | [diff] [blame] | 809 | if (len >= blocksize) |
| 810 | mv_cesa_update_op_cfg(&creq->op_tmpl, |
| 811 | CESA_SA_DESC_CFG_MID_FRAG, |
| 812 | CESA_SA_DESC_CFG_FRAG_MSK); |
| 813 | |
| 814 | creq->len = len; |
| 815 | memcpy(creq->state, hash, digsize); |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 816 | creq->cache_ptr = 0; |
| 817 | |
Russell King | a6479ea | 2015-10-09 21:14:22 +0100 | [diff] [blame] | 818 | cache_ptr = do_div(len, blocksize); |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 819 | if (!cache_ptr) |
| 820 | return 0; |
| 821 | |
Russell King | a6479ea | 2015-10-09 21:14:22 +0100 | [diff] [blame] | 822 | memcpy(creq->cache, cache, cache_ptr); |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 823 | creq->cache_ptr = cache_ptr; |
| 824 | |
| 825 | return 0; |
| 826 | } |
| 827 | |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 828 | static int mv_cesa_md5_init(struct ahash_request *req) |
| 829 | { |
Boris BREZILLON | b0ef510 | 2016-03-17 10:21:35 +0100 | [diff] [blame] | 830 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
Russell King | d30cb2f | 2015-10-18 17:23:51 +0100 | [diff] [blame] | 831 | struct mv_cesa_op_ctx tmpl = { }; |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 832 | |
| 833 | mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_MD5); |
Romain Perier | 57cfda1 | 2016-08-09 11:03:19 +0200 | [diff] [blame] | 834 | |
| 835 | mv_cesa_ahash_init(req, &tmpl, true); |
| 836 | |
Boris BREZILLON | b0ef510 | 2016-03-17 10:21:35 +0100 | [diff] [blame] | 837 | creq->state[0] = MD5_H0; |
| 838 | creq->state[1] = MD5_H1; |
| 839 | creq->state[2] = MD5_H2; |
| 840 | creq->state[3] = MD5_H3; |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 841 | |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 842 | return 0; |
| 843 | } |
| 844 | |
| 845 | static int mv_cesa_md5_export(struct ahash_request *req, void *out) |
| 846 | { |
| 847 | struct md5_state *out_state = out; |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 848 | |
Russell King | a6479ea | 2015-10-09 21:14:22 +0100 | [diff] [blame] | 849 | return mv_cesa_ahash_export(req, out_state->hash, |
| 850 | &out_state->byte_count, out_state->block); |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 851 | } |
| 852 | |
| 853 | static int mv_cesa_md5_import(struct ahash_request *req, const void *in) |
| 854 | { |
| 855 | const struct md5_state *in_state = in; |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 856 | |
Russell King | a6479ea | 2015-10-09 21:14:22 +0100 | [diff] [blame] | 857 | return mv_cesa_ahash_import(req, in_state->hash, in_state->byte_count, |
| 858 | in_state->block); |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 859 | } |
| 860 | |
| 861 | static int mv_cesa_md5_digest(struct ahash_request *req) |
| 862 | { |
| 863 | int ret; |
| 864 | |
| 865 | ret = mv_cesa_md5_init(req); |
| 866 | if (ret) |
| 867 | return ret; |
| 868 | |
| 869 | return mv_cesa_ahash_finup(req); |
| 870 | } |
| 871 | |
| 872 | struct ahash_alg mv_md5_alg = { |
| 873 | .init = mv_cesa_md5_init, |
| 874 | .update = mv_cesa_ahash_update, |
| 875 | .final = mv_cesa_ahash_final, |
| 876 | .finup = mv_cesa_ahash_finup, |
| 877 | .digest = mv_cesa_md5_digest, |
| 878 | .export = mv_cesa_md5_export, |
| 879 | .import = mv_cesa_md5_import, |
| 880 | .halg = { |
| 881 | .digestsize = MD5_DIGEST_SIZE, |
Russell King | 9f5594c | 2015-10-09 20:43:38 +0100 | [diff] [blame] | 882 | .statesize = sizeof(struct md5_state), |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 883 | .base = { |
| 884 | .cra_name = "md5", |
| 885 | .cra_driver_name = "mv-md5", |
| 886 | .cra_priority = 300, |
| 887 | .cra_flags = CRYPTO_ALG_ASYNC | |
| 888 | CRYPTO_ALG_KERN_DRIVER_ONLY, |
| 889 | .cra_blocksize = MD5_HMAC_BLOCK_SIZE, |
| 890 | .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx), |
| 891 | .cra_init = mv_cesa_ahash_cra_init, |
| 892 | .cra_module = THIS_MODULE, |
| 893 | } |
| 894 | } |
| 895 | }; |
| 896 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 897 | static int mv_cesa_sha1_init(struct ahash_request *req) |
| 898 | { |
Boris BREZILLON | b0ef510 | 2016-03-17 10:21:35 +0100 | [diff] [blame] | 899 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
Russell King | d30cb2f | 2015-10-18 17:23:51 +0100 | [diff] [blame] | 900 | struct mv_cesa_op_ctx tmpl = { }; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 901 | |
| 902 | mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA1); |
Romain Perier | 57cfda1 | 2016-08-09 11:03:19 +0200 | [diff] [blame] | 903 | |
| 904 | mv_cesa_ahash_init(req, &tmpl, false); |
| 905 | |
Boris BREZILLON | b0ef510 | 2016-03-17 10:21:35 +0100 | [diff] [blame] | 906 | creq->state[0] = SHA1_H0; |
| 907 | creq->state[1] = SHA1_H1; |
| 908 | creq->state[2] = SHA1_H2; |
| 909 | creq->state[3] = SHA1_H3; |
| 910 | creq->state[4] = SHA1_H4; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 911 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 912 | return 0; |
| 913 | } |
| 914 | |
| 915 | static int mv_cesa_sha1_export(struct ahash_request *req, void *out) |
| 916 | { |
| 917 | struct sha1_state *out_state = out; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 918 | |
Russell King | a6479ea | 2015-10-09 21:14:22 +0100 | [diff] [blame] | 919 | return mv_cesa_ahash_export(req, out_state->state, &out_state->count, |
| 920 | out_state->buffer); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 921 | } |
| 922 | |
| 923 | static int mv_cesa_sha1_import(struct ahash_request *req, const void *in) |
| 924 | { |
| 925 | const struct sha1_state *in_state = in; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 926 | |
Russell King | a6479ea | 2015-10-09 21:14:22 +0100 | [diff] [blame] | 927 | return mv_cesa_ahash_import(req, in_state->state, in_state->count, |
| 928 | in_state->buffer); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 929 | } |
| 930 | |
| 931 | static int mv_cesa_sha1_digest(struct ahash_request *req) |
| 932 | { |
| 933 | int ret; |
| 934 | |
| 935 | ret = mv_cesa_sha1_init(req); |
| 936 | if (ret) |
| 937 | return ret; |
| 938 | |
| 939 | return mv_cesa_ahash_finup(req); |
| 940 | } |
| 941 | |
| 942 | struct ahash_alg mv_sha1_alg = { |
| 943 | .init = mv_cesa_sha1_init, |
| 944 | .update = mv_cesa_ahash_update, |
| 945 | .final = mv_cesa_ahash_final, |
| 946 | .finup = mv_cesa_ahash_finup, |
| 947 | .digest = mv_cesa_sha1_digest, |
| 948 | .export = mv_cesa_sha1_export, |
| 949 | .import = mv_cesa_sha1_import, |
| 950 | .halg = { |
| 951 | .digestsize = SHA1_DIGEST_SIZE, |
Russell King | 9f5594c | 2015-10-09 20:43:38 +0100 | [diff] [blame] | 952 | .statesize = sizeof(struct sha1_state), |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 953 | .base = { |
| 954 | .cra_name = "sha1", |
| 955 | .cra_driver_name = "mv-sha1", |
| 956 | .cra_priority = 300, |
| 957 | .cra_flags = CRYPTO_ALG_ASYNC | |
| 958 | CRYPTO_ALG_KERN_DRIVER_ONLY, |
| 959 | .cra_blocksize = SHA1_BLOCK_SIZE, |
| 960 | .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx), |
| 961 | .cra_init = mv_cesa_ahash_cra_init, |
| 962 | .cra_module = THIS_MODULE, |
| 963 | } |
| 964 | } |
| 965 | }; |
| 966 | |
Arnaud Ebalard | f85a762 | 2015-06-18 15:46:25 +0200 | [diff] [blame] | 967 | static int mv_cesa_sha256_init(struct ahash_request *req) |
| 968 | { |
Boris BREZILLON | b0ef510 | 2016-03-17 10:21:35 +0100 | [diff] [blame] | 969 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
Russell King | d30cb2f | 2015-10-18 17:23:51 +0100 | [diff] [blame] | 970 | struct mv_cesa_op_ctx tmpl = { }; |
Arnaud Ebalard | f85a762 | 2015-06-18 15:46:25 +0200 | [diff] [blame] | 971 | |
| 972 | mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA256); |
Romain Perier | 57cfda1 | 2016-08-09 11:03:19 +0200 | [diff] [blame] | 973 | |
| 974 | mv_cesa_ahash_init(req, &tmpl, false); |
| 975 | |
Boris BREZILLON | b0ef510 | 2016-03-17 10:21:35 +0100 | [diff] [blame] | 976 | creq->state[0] = SHA256_H0; |
| 977 | creq->state[1] = SHA256_H1; |
| 978 | creq->state[2] = SHA256_H2; |
| 979 | creq->state[3] = SHA256_H3; |
| 980 | creq->state[4] = SHA256_H4; |
| 981 | creq->state[5] = SHA256_H5; |
| 982 | creq->state[6] = SHA256_H6; |
| 983 | creq->state[7] = SHA256_H7; |
Arnaud Ebalard | f85a762 | 2015-06-18 15:46:25 +0200 | [diff] [blame] | 984 | |
Arnaud Ebalard | f85a762 | 2015-06-18 15:46:25 +0200 | [diff] [blame] | 985 | return 0; |
| 986 | } |
| 987 | |
| 988 | static int mv_cesa_sha256_digest(struct ahash_request *req) |
| 989 | { |
| 990 | int ret; |
| 991 | |
| 992 | ret = mv_cesa_sha256_init(req); |
| 993 | if (ret) |
| 994 | return ret; |
| 995 | |
| 996 | return mv_cesa_ahash_finup(req); |
| 997 | } |
| 998 | |
| 999 | static int mv_cesa_sha256_export(struct ahash_request *req, void *out) |
| 1000 | { |
| 1001 | struct sha256_state *out_state = out; |
Arnaud Ebalard | f85a762 | 2015-06-18 15:46:25 +0200 | [diff] [blame] | 1002 | |
Russell King | a6479ea | 2015-10-09 21:14:22 +0100 | [diff] [blame] | 1003 | return mv_cesa_ahash_export(req, out_state->state, &out_state->count, |
| 1004 | out_state->buf); |
Arnaud Ebalard | f85a762 | 2015-06-18 15:46:25 +0200 | [diff] [blame] | 1005 | } |
| 1006 | |
| 1007 | static int mv_cesa_sha256_import(struct ahash_request *req, const void *in) |
| 1008 | { |
| 1009 | const struct sha256_state *in_state = in; |
Arnaud Ebalard | f85a762 | 2015-06-18 15:46:25 +0200 | [diff] [blame] | 1010 | |
Russell King | a6479ea | 2015-10-09 21:14:22 +0100 | [diff] [blame] | 1011 | return mv_cesa_ahash_import(req, in_state->state, in_state->count, |
| 1012 | in_state->buf); |
Arnaud Ebalard | f85a762 | 2015-06-18 15:46:25 +0200 | [diff] [blame] | 1013 | } |
| 1014 | |
| 1015 | struct ahash_alg mv_sha256_alg = { |
| 1016 | .init = mv_cesa_sha256_init, |
| 1017 | .update = mv_cesa_ahash_update, |
| 1018 | .final = mv_cesa_ahash_final, |
| 1019 | .finup = mv_cesa_ahash_finup, |
| 1020 | .digest = mv_cesa_sha256_digest, |
| 1021 | .export = mv_cesa_sha256_export, |
| 1022 | .import = mv_cesa_sha256_import, |
| 1023 | .halg = { |
| 1024 | .digestsize = SHA256_DIGEST_SIZE, |
Russell King | 9f5594c | 2015-10-09 20:43:38 +0100 | [diff] [blame] | 1025 | .statesize = sizeof(struct sha256_state), |
Arnaud Ebalard | f85a762 | 2015-06-18 15:46:25 +0200 | [diff] [blame] | 1026 | .base = { |
| 1027 | .cra_name = "sha256", |
| 1028 | .cra_driver_name = "mv-sha256", |
| 1029 | .cra_priority = 300, |
| 1030 | .cra_flags = CRYPTO_ALG_ASYNC | |
| 1031 | CRYPTO_ALG_KERN_DRIVER_ONLY, |
| 1032 | .cra_blocksize = SHA256_BLOCK_SIZE, |
| 1033 | .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx), |
| 1034 | .cra_init = mv_cesa_ahash_cra_init, |
| 1035 | .cra_module = THIS_MODULE, |
| 1036 | } |
| 1037 | } |
| 1038 | }; |
| 1039 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 1040 | struct mv_cesa_ahash_result { |
| 1041 | struct completion completion; |
| 1042 | int error; |
| 1043 | }; |
| 1044 | |
| 1045 | static void mv_cesa_hmac_ahash_complete(struct crypto_async_request *req, |
| 1046 | int error) |
| 1047 | { |
| 1048 | struct mv_cesa_ahash_result *result = req->data; |
| 1049 | |
| 1050 | if (error == -EINPROGRESS) |
| 1051 | return; |
| 1052 | |
| 1053 | result->error = error; |
| 1054 | complete(&result->completion); |
| 1055 | } |
| 1056 | |
| 1057 | static int mv_cesa_ahmac_iv_state_init(struct ahash_request *req, u8 *pad, |
| 1058 | void *state, unsigned int blocksize) |
| 1059 | { |
| 1060 | struct mv_cesa_ahash_result result; |
| 1061 | struct scatterlist sg; |
| 1062 | int ret; |
| 1063 | |
| 1064 | ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, |
| 1065 | mv_cesa_hmac_ahash_complete, &result); |
| 1066 | sg_init_one(&sg, pad, blocksize); |
| 1067 | ahash_request_set_crypt(req, &sg, pad, blocksize); |
| 1068 | init_completion(&result.completion); |
| 1069 | |
| 1070 | ret = crypto_ahash_init(req); |
| 1071 | if (ret) |
| 1072 | return ret; |
| 1073 | |
| 1074 | ret = crypto_ahash_update(req); |
| 1075 | if (ret && ret != -EINPROGRESS) |
| 1076 | return ret; |
| 1077 | |
| 1078 | wait_for_completion_interruptible(&result.completion); |
| 1079 | if (result.error) |
| 1080 | return result.error; |
| 1081 | |
| 1082 | ret = crypto_ahash_export(req, state); |
| 1083 | if (ret) |
| 1084 | return ret; |
| 1085 | |
| 1086 | return 0; |
| 1087 | } |
| 1088 | |
| 1089 | static int mv_cesa_ahmac_pad_init(struct ahash_request *req, |
| 1090 | const u8 *key, unsigned int keylen, |
| 1091 | u8 *ipad, u8 *opad, |
| 1092 | unsigned int blocksize) |
| 1093 | { |
| 1094 | struct mv_cesa_ahash_result result; |
| 1095 | struct scatterlist sg; |
| 1096 | int ret; |
| 1097 | int i; |
| 1098 | |
| 1099 | if (keylen <= blocksize) { |
| 1100 | memcpy(ipad, key, keylen); |
| 1101 | } else { |
| 1102 | u8 *keydup = kmemdup(key, keylen, GFP_KERNEL); |
| 1103 | |
| 1104 | if (!keydup) |
| 1105 | return -ENOMEM; |
| 1106 | |
| 1107 | ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, |
| 1108 | mv_cesa_hmac_ahash_complete, |
| 1109 | &result); |
| 1110 | sg_init_one(&sg, keydup, keylen); |
| 1111 | ahash_request_set_crypt(req, &sg, ipad, keylen); |
| 1112 | init_completion(&result.completion); |
| 1113 | |
| 1114 | ret = crypto_ahash_digest(req); |
| 1115 | if (ret == -EINPROGRESS) { |
| 1116 | wait_for_completion_interruptible(&result.completion); |
| 1117 | ret = result.error; |
| 1118 | } |
| 1119 | |
| 1120 | /* Set the memory region to 0 to avoid any leak. */ |
| 1121 | memset(keydup, 0, keylen); |
| 1122 | kfree(keydup); |
| 1123 | |
| 1124 | if (ret) |
| 1125 | return ret; |
| 1126 | |
| 1127 | keylen = crypto_ahash_digestsize(crypto_ahash_reqtfm(req)); |
| 1128 | } |
| 1129 | |
| 1130 | memset(ipad + keylen, 0, blocksize - keylen); |
| 1131 | memcpy(opad, ipad, blocksize); |
| 1132 | |
| 1133 | for (i = 0; i < blocksize; i++) { |
| 1134 | ipad[i] ^= 0x36; |
| 1135 | opad[i] ^= 0x5c; |
| 1136 | } |
| 1137 | |
| 1138 | return 0; |
| 1139 | } |
| 1140 | |
| 1141 | static int mv_cesa_ahmac_setkey(const char *hash_alg_name, |
| 1142 | const u8 *key, unsigned int keylen, |
| 1143 | void *istate, void *ostate) |
| 1144 | { |
| 1145 | struct ahash_request *req; |
| 1146 | struct crypto_ahash *tfm; |
| 1147 | unsigned int blocksize; |
| 1148 | u8 *ipad = NULL; |
| 1149 | u8 *opad; |
| 1150 | int ret; |
| 1151 | |
| 1152 | tfm = crypto_alloc_ahash(hash_alg_name, CRYPTO_ALG_TYPE_AHASH, |
| 1153 | CRYPTO_ALG_TYPE_AHASH_MASK); |
| 1154 | if (IS_ERR(tfm)) |
| 1155 | return PTR_ERR(tfm); |
| 1156 | |
| 1157 | req = ahash_request_alloc(tfm, GFP_KERNEL); |
| 1158 | if (!req) { |
| 1159 | ret = -ENOMEM; |
| 1160 | goto free_ahash; |
| 1161 | } |
| 1162 | |
| 1163 | crypto_ahash_clear_flags(tfm, ~0); |
| 1164 | |
| 1165 | blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); |
| 1166 | |
| 1167 | ipad = kzalloc(2 * blocksize, GFP_KERNEL); |
| 1168 | if (!ipad) { |
| 1169 | ret = -ENOMEM; |
| 1170 | goto free_req; |
| 1171 | } |
| 1172 | |
| 1173 | opad = ipad + blocksize; |
| 1174 | |
| 1175 | ret = mv_cesa_ahmac_pad_init(req, key, keylen, ipad, opad, blocksize); |
| 1176 | if (ret) |
| 1177 | goto free_ipad; |
| 1178 | |
| 1179 | ret = mv_cesa_ahmac_iv_state_init(req, ipad, istate, blocksize); |
| 1180 | if (ret) |
| 1181 | goto free_ipad; |
| 1182 | |
| 1183 | ret = mv_cesa_ahmac_iv_state_init(req, opad, ostate, blocksize); |
| 1184 | |
| 1185 | free_ipad: |
| 1186 | kfree(ipad); |
| 1187 | free_req: |
| 1188 | ahash_request_free(req); |
| 1189 | free_ahash: |
| 1190 | crypto_free_ahash(tfm); |
| 1191 | |
| 1192 | return ret; |
| 1193 | } |
| 1194 | |
| 1195 | static int mv_cesa_ahmac_cra_init(struct crypto_tfm *tfm) |
| 1196 | { |
| 1197 | struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(tfm); |
| 1198 | |
| 1199 | ctx->base.ops = &mv_cesa_ahash_req_ops; |
| 1200 | |
| 1201 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), |
| 1202 | sizeof(struct mv_cesa_ahash_req)); |
| 1203 | return 0; |
| 1204 | } |
| 1205 | |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 1206 | static int mv_cesa_ahmac_md5_init(struct ahash_request *req) |
| 1207 | { |
| 1208 | struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm); |
Russell King | d30cb2f | 2015-10-18 17:23:51 +0100 | [diff] [blame] | 1209 | struct mv_cesa_op_ctx tmpl = { }; |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 1210 | |
| 1211 | mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_MD5); |
| 1212 | memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv)); |
| 1213 | |
Russell King | a9eb678 | 2015-10-18 17:23:40 +0100 | [diff] [blame] | 1214 | mv_cesa_ahash_init(req, &tmpl, true); |
Arnaud Ebalard | 7aeef69 | 2015-06-18 15:46:24 +0200 | [diff] [blame] | 1215 | |
| 1216 | return 0; |
| 1217 | } |
| 1218 | |
| 1219 | static int mv_cesa_ahmac_md5_setkey(struct crypto_ahash *tfm, const u8 *key, |
| 1220 | unsigned int keylen) |
| 1221 | { |
| 1222 | struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm)); |
| 1223 | struct md5_state istate, ostate; |
| 1224 | int ret, i; |
| 1225 | |
| 1226 | ret = mv_cesa_ahmac_setkey("mv-md5", key, keylen, &istate, &ostate); |
| 1227 | if (ret) |
| 1228 | return ret; |
| 1229 | |
| 1230 | for (i = 0; i < ARRAY_SIZE(istate.hash); i++) |
| 1231 | ctx->iv[i] = be32_to_cpu(istate.hash[i]); |
| 1232 | |
| 1233 | for (i = 0; i < ARRAY_SIZE(ostate.hash); i++) |
| 1234 | ctx->iv[i + 8] = be32_to_cpu(ostate.hash[i]); |
| 1235 | |
| 1236 | return 0; |
| 1237 | } |
| 1238 | |
| 1239 | static int mv_cesa_ahmac_md5_digest(struct ahash_request *req) |
| 1240 | { |
| 1241 | int ret; |
| 1242 | |
| 1243 | ret = mv_cesa_ahmac_md5_init(req); |
| 1244 | if (ret) |
| 1245 | return ret; |
| 1246 | |
| 1247 | return mv_cesa_ahash_finup(req); |
| 1248 | } |
| 1249 | |
| 1250 | struct ahash_alg mv_ahmac_md5_alg = { |
| 1251 | .init = mv_cesa_ahmac_md5_init, |
| 1252 | .update = mv_cesa_ahash_update, |
| 1253 | .final = mv_cesa_ahash_final, |
| 1254 | .finup = mv_cesa_ahash_finup, |
| 1255 | .digest = mv_cesa_ahmac_md5_digest, |
| 1256 | .setkey = mv_cesa_ahmac_md5_setkey, |
| 1257 | .export = mv_cesa_md5_export, |
| 1258 | .import = mv_cesa_md5_import, |
| 1259 | .halg = { |
| 1260 | .digestsize = MD5_DIGEST_SIZE, |
| 1261 | .statesize = sizeof(struct md5_state), |
| 1262 | .base = { |
| 1263 | .cra_name = "hmac(md5)", |
| 1264 | .cra_driver_name = "mv-hmac-md5", |
| 1265 | .cra_priority = 300, |
| 1266 | .cra_flags = CRYPTO_ALG_ASYNC | |
| 1267 | CRYPTO_ALG_KERN_DRIVER_ONLY, |
| 1268 | .cra_blocksize = MD5_HMAC_BLOCK_SIZE, |
| 1269 | .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx), |
| 1270 | .cra_init = mv_cesa_ahmac_cra_init, |
| 1271 | .cra_module = THIS_MODULE, |
| 1272 | } |
| 1273 | } |
| 1274 | }; |
| 1275 | |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 1276 | static int mv_cesa_ahmac_sha1_init(struct ahash_request *req) |
| 1277 | { |
| 1278 | struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm); |
Russell King | d30cb2f | 2015-10-18 17:23:51 +0100 | [diff] [blame] | 1279 | struct mv_cesa_op_ctx tmpl = { }; |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 1280 | |
| 1281 | mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA1); |
| 1282 | memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv)); |
| 1283 | |
Russell King | a9eb678 | 2015-10-18 17:23:40 +0100 | [diff] [blame] | 1284 | mv_cesa_ahash_init(req, &tmpl, false); |
Boris BREZILLON | f63601f | 2015-06-18 15:46:20 +0200 | [diff] [blame] | 1285 | |
| 1286 | return 0; |
| 1287 | } |
| 1288 | |
| 1289 | static int mv_cesa_ahmac_sha1_setkey(struct crypto_ahash *tfm, const u8 *key, |
| 1290 | unsigned int keylen) |
| 1291 | { |
| 1292 | struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm)); |
| 1293 | struct sha1_state istate, ostate; |
| 1294 | int ret, i; |
| 1295 | |
| 1296 | ret = mv_cesa_ahmac_setkey("mv-sha1", key, keylen, &istate, &ostate); |
| 1297 | if (ret) |
| 1298 | return ret; |
| 1299 | |
| 1300 | for (i = 0; i < ARRAY_SIZE(istate.state); i++) |
| 1301 | ctx->iv[i] = be32_to_cpu(istate.state[i]); |
| 1302 | |
| 1303 | for (i = 0; i < ARRAY_SIZE(ostate.state); i++) |
| 1304 | ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]); |
| 1305 | |
| 1306 | return 0; |
| 1307 | } |
| 1308 | |
| 1309 | static int mv_cesa_ahmac_sha1_digest(struct ahash_request *req) |
| 1310 | { |
| 1311 | int ret; |
| 1312 | |
| 1313 | ret = mv_cesa_ahmac_sha1_init(req); |
| 1314 | if (ret) |
| 1315 | return ret; |
| 1316 | |
| 1317 | return mv_cesa_ahash_finup(req); |
| 1318 | } |
| 1319 | |
| 1320 | struct ahash_alg mv_ahmac_sha1_alg = { |
| 1321 | .init = mv_cesa_ahmac_sha1_init, |
| 1322 | .update = mv_cesa_ahash_update, |
| 1323 | .final = mv_cesa_ahash_final, |
| 1324 | .finup = mv_cesa_ahash_finup, |
| 1325 | .digest = mv_cesa_ahmac_sha1_digest, |
| 1326 | .setkey = mv_cesa_ahmac_sha1_setkey, |
| 1327 | .export = mv_cesa_sha1_export, |
| 1328 | .import = mv_cesa_sha1_import, |
| 1329 | .halg = { |
| 1330 | .digestsize = SHA1_DIGEST_SIZE, |
| 1331 | .statesize = sizeof(struct sha1_state), |
| 1332 | .base = { |
| 1333 | .cra_name = "hmac(sha1)", |
| 1334 | .cra_driver_name = "mv-hmac-sha1", |
| 1335 | .cra_priority = 300, |
| 1336 | .cra_flags = CRYPTO_ALG_ASYNC | |
| 1337 | CRYPTO_ALG_KERN_DRIVER_ONLY, |
| 1338 | .cra_blocksize = SHA1_BLOCK_SIZE, |
| 1339 | .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx), |
| 1340 | .cra_init = mv_cesa_ahmac_cra_init, |
| 1341 | .cra_module = THIS_MODULE, |
| 1342 | } |
| 1343 | } |
| 1344 | }; |
Arnaud Ebalard | f85a762 | 2015-06-18 15:46:25 +0200 | [diff] [blame] | 1345 | |
| 1346 | static int mv_cesa_ahmac_sha256_setkey(struct crypto_ahash *tfm, const u8 *key, |
| 1347 | unsigned int keylen) |
| 1348 | { |
| 1349 | struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm)); |
| 1350 | struct sha256_state istate, ostate; |
| 1351 | int ret, i; |
| 1352 | |
| 1353 | ret = mv_cesa_ahmac_setkey("mv-sha256", key, keylen, &istate, &ostate); |
| 1354 | if (ret) |
| 1355 | return ret; |
| 1356 | |
| 1357 | for (i = 0; i < ARRAY_SIZE(istate.state); i++) |
| 1358 | ctx->iv[i] = be32_to_cpu(istate.state[i]); |
| 1359 | |
| 1360 | for (i = 0; i < ARRAY_SIZE(ostate.state); i++) |
| 1361 | ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]); |
| 1362 | |
| 1363 | return 0; |
| 1364 | } |
| 1365 | |
| 1366 | static int mv_cesa_ahmac_sha256_init(struct ahash_request *req) |
| 1367 | { |
| 1368 | struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm); |
Russell King | d30cb2f | 2015-10-18 17:23:51 +0100 | [diff] [blame] | 1369 | struct mv_cesa_op_ctx tmpl = { }; |
Arnaud Ebalard | f85a762 | 2015-06-18 15:46:25 +0200 | [diff] [blame] | 1370 | |
| 1371 | mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA256); |
| 1372 | memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv)); |
| 1373 | |
Russell King | a9eb678 | 2015-10-18 17:23:40 +0100 | [diff] [blame] | 1374 | mv_cesa_ahash_init(req, &tmpl, false); |
Arnaud Ebalard | f85a762 | 2015-06-18 15:46:25 +0200 | [diff] [blame] | 1375 | |
| 1376 | return 0; |
| 1377 | } |
| 1378 | |
| 1379 | static int mv_cesa_ahmac_sha256_digest(struct ahash_request *req) |
| 1380 | { |
| 1381 | int ret; |
| 1382 | |
| 1383 | ret = mv_cesa_ahmac_sha256_init(req); |
| 1384 | if (ret) |
| 1385 | return ret; |
| 1386 | |
| 1387 | return mv_cesa_ahash_finup(req); |
| 1388 | } |
| 1389 | |
| 1390 | struct ahash_alg mv_ahmac_sha256_alg = { |
| 1391 | .init = mv_cesa_ahmac_sha256_init, |
| 1392 | .update = mv_cesa_ahash_update, |
| 1393 | .final = mv_cesa_ahash_final, |
| 1394 | .finup = mv_cesa_ahash_finup, |
| 1395 | .digest = mv_cesa_ahmac_sha256_digest, |
| 1396 | .setkey = mv_cesa_ahmac_sha256_setkey, |
| 1397 | .export = mv_cesa_sha256_export, |
| 1398 | .import = mv_cesa_sha256_import, |
| 1399 | .halg = { |
| 1400 | .digestsize = SHA256_DIGEST_SIZE, |
| 1401 | .statesize = sizeof(struct sha256_state), |
| 1402 | .base = { |
| 1403 | .cra_name = "hmac(sha256)", |
| 1404 | .cra_driver_name = "mv-hmac-sha256", |
| 1405 | .cra_priority = 300, |
| 1406 | .cra_flags = CRYPTO_ALG_ASYNC | |
| 1407 | CRYPTO_ALG_KERN_DRIVER_ONLY, |
| 1408 | .cra_blocksize = SHA256_BLOCK_SIZE, |
| 1409 | .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx), |
| 1410 | .cra_init = mv_cesa_ahmac_cra_init, |
| 1411 | .cra_module = THIS_MODULE, |
| 1412 | } |
| 1413 | } |
| 1414 | }; |