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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Cache flushing routines.
3 *
David Mosberger-Tang20746152005-02-18 19:09:00 -07004 * Copyright (C) 1999-2001, 2005 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
Zoltan Menyhart08357f82005-06-03 05:36:00 -07006 *
7 * 05/28/05 Zoltan Menyhart Dynamic stride size
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 */
Zoltan Menyhart08357f82005-06-03 05:36:00 -07009
Linus Torvalds1da177e2005-04-16 15:20:36 -070010#include <asm/asmmacro.h>
Zoltan Menyhart08357f82005-06-03 05:36:00 -070011
Linus Torvalds1da177e2005-04-16 15:20:36 -070012
13 /*
14 * flush_icache_range(start,end)
Zoltan Menyhart08357f82005-06-03 05:36:00 -070015 *
16 * Make i-cache(s) coherent with d-caches.
17 *
18 * Must deal with range from start to end-1 but nothing else (need to
Linus Torvalds1da177e2005-04-16 15:20:36 -070019 * be careful not to touch addresses that may be unmapped).
Zoltan Menyhart08357f82005-06-03 05:36:00 -070020 *
21 * Note: "in0" and "in1" are preserved for debugging purposes.
Linus Torvalds1da177e2005-04-16 15:20:36 -070022 */
Prasanna S Panchamukhi1f7ad572005-09-06 15:19:30 -070023 .section .kprobes.text,"ax"
Linus Torvalds1da177e2005-04-16 15:20:36 -070024GLOBAL_ENTRY(flush_icache_range)
Zoltan Menyhart08357f82005-06-03 05:36:00 -070025
Linus Torvalds1da177e2005-04-16 15:20:36 -070026 .prologue
Zoltan Menyhart08357f82005-06-03 05:36:00 -070027 alloc r2=ar.pfs,2,0,0,0
28 movl r3=ia64_i_cache_stride_shift
29 mov r21=1
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 ;;
Zoltan Menyhart08357f82005-06-03 05:36:00 -070031 ld8 r20=[r3] // r20: stride shift
32 sub r22=in1,r0,1 // last byte address
33 ;;
34 shr.u r23=in0,r20 // start / (stride size)
35 shr.u r22=r22,r20 // (last byte address) / (stride size)
36 shl r21=r21,r20 // r21: stride size of the i-cache(s)
37 ;;
38 sub r8=r22,r23 // number of strides - 1
39 shl r24=r23,r20 // r24: addresses for "fc.i" =
40 // "start" rounded down to stride boundary
41 .save ar.lc,r3
42 mov r3=ar.lc // save ar.lc
Linus Torvalds1da177e2005-04-16 15:20:36 -070043 ;;
44
45 .body
Zoltan Menyhart08357f82005-06-03 05:36:00 -070046 mov ar.lc=r8
Linus Torvalds1da177e2005-04-16 15:20:36 -070047 ;;
Zoltan Menyhart08357f82005-06-03 05:36:00 -070048 /*
49 * 32 byte aligned loop, even number of (actually 2) bundles
50 */
51.Loop: fc.i r24 // issuable on M0 only
52 add r24=r21,r24 // we flush "stride size" bytes per iteration
53 nop.i 0
Linus Torvalds1da177e2005-04-16 15:20:36 -070054 br.cloop.sptk.few .Loop
55 ;;
56 sync.i
57 ;;
58 srlz.i
59 ;;
Zoltan Menyhart08357f82005-06-03 05:36:00 -070060 mov ar.lc=r3 // restore ar.lc
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 br.ret.sptk.many rp
62END(flush_icache_range)