blob: 43eb72af894823d294cbf3ca951b9a3e498088c2 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -06001/dts-v1/;
2
Grant Likely8e267f32011-07-19 17:26:54 -06003/include/ "tegra20.dtsi"
4
5/ {
6 model = "NVIDIA Tegra2 Harmony evaluation board";
7 compatible = "nvidia,harmony", "nvidia,tegra20";
8
Stephen Warrenf9eb26a2012-05-11 16:17:47 -06009 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060010 reg = <0x00000000 0x40000000>;
Grant Likely8e267f32011-07-19 17:26:54 -060011 };
12
Stephen Warren20ffbd72012-11-09 16:58:11 -070013 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060025 pinmux {
Stephen Warrenecc295b2012-03-15 16:27:36 -060026 pinctrl-names = "default";
27 pinctrl-0 = <&state_default>;
28
29 state_default: pinmux {
30 ata {
31 nvidia,pins = "ata";
32 nvidia,function = "ide";
33 };
34 atb {
35 nvidia,pins = "atb", "gma", "gme";
36 nvidia,function = "sdio4";
37 };
38 atc {
39 nvidia,pins = "atc";
40 nvidia,function = "nand";
41 };
42 atd {
43 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
44 "spia", "spib", "spic";
45 nvidia,function = "gmi";
46 };
47 cdev1 {
48 nvidia,pins = "cdev1";
49 nvidia,function = "plla_out";
50 };
51 cdev2 {
52 nvidia,pins = "cdev2";
53 nvidia,function = "pllp_out4";
54 };
55 crtp {
56 nvidia,pins = "crtp";
57 nvidia,function = "crt";
58 };
59 csus {
60 nvidia,pins = "csus";
61 nvidia,function = "vi_sensor_clk";
62 };
63 dap1 {
64 nvidia,pins = "dap1";
65 nvidia,function = "dap1";
66 };
67 dap2 {
68 nvidia,pins = "dap2";
69 nvidia,function = "dap2";
70 };
71 dap3 {
72 nvidia,pins = "dap3";
73 nvidia,function = "dap3";
74 };
75 dap4 {
76 nvidia,pins = "dap4";
77 nvidia,function = "dap4";
78 };
79 ddc {
80 nvidia,pins = "ddc";
81 nvidia,function = "i2c2";
82 };
83 dta {
84 nvidia,pins = "dta", "dtd";
85 nvidia,function = "sdio2";
86 };
87 dtb {
88 nvidia,pins = "dtb", "dtc", "dte";
89 nvidia,function = "rsvd1";
90 };
91 dtf {
92 nvidia,pins = "dtf";
93 nvidia,function = "i2c3";
94 };
95 gmc {
96 nvidia,pins = "gmc";
97 nvidia,function = "uartd";
98 };
99 gpu7 {
100 nvidia,pins = "gpu7";
101 nvidia,function = "rtck";
102 };
103 gpv {
104 nvidia,pins = "gpv", "slxa", "slxk";
105 nvidia,function = "pcie";
106 };
107 hdint {
108 nvidia,pins = "hdint", "pta";
109 nvidia,function = "hdmi";
110 };
111 i2cp {
112 nvidia,pins = "i2cp";
113 nvidia,function = "i2cp";
114 };
115 irrx {
116 nvidia,pins = "irrx", "irtx";
117 nvidia,function = "uarta";
118 };
119 kbca {
120 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
121 "kbce", "kbcf";
122 nvidia,function = "kbc";
123 };
124 lcsn {
125 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
126 "ld3", "ld4", "ld5", "ld6", "ld7",
127 "ld8", "ld9", "ld10", "ld11", "ld12",
128 "ld13", "ld14", "ld15", "ld16", "ld17",
129 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
130 "lhs", "lm0", "lm1", "lpp", "lpw0",
131 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
132 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
133 "lvs";
134 nvidia,function = "displaya";
135 };
136 owc {
137 nvidia,pins = "owc", "spdi", "spdo", "uac";
138 nvidia,function = "rsvd2";
139 };
140 pmc {
141 nvidia,pins = "pmc";
142 nvidia,function = "pwr_on";
143 };
144 rm {
145 nvidia,pins = "rm";
146 nvidia,function = "i2c1";
147 };
148 sdb {
149 nvidia,pins = "sdb", "sdc", "sdd";
150 nvidia,function = "pwm";
151 };
152 sdio1 {
153 nvidia,pins = "sdio1";
154 nvidia,function = "sdio1";
155 };
156 slxc {
157 nvidia,pins = "slxc", "slxd";
158 nvidia,function = "spdif";
159 };
160 spid {
161 nvidia,pins = "spid", "spie", "spif";
162 nvidia,function = "spi1";
163 };
164 spig {
165 nvidia,pins = "spig", "spih";
166 nvidia,function = "spi2_alt";
167 };
168 uaa {
169 nvidia,pins = "uaa", "uab", "uda";
170 nvidia,function = "ulpi";
171 };
172 uad {
173 nvidia,pins = "uad";
174 nvidia,function = "irda";
175 };
176 uca {
177 nvidia,pins = "uca", "ucb";
178 nvidia,function = "uartc";
179 };
180 conf_ata {
181 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
Stephen Warren563da212012-04-13 16:35:20 -0600182 "cdev1", "cdev2", "dap1", "dtb", "gma",
183 "gmb", "gmc", "gmd", "gme", "gpu7",
184 "gpv", "i2cp", "pta", "rm", "slxa",
185 "slxk", "spia", "spib", "uac";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600186 nvidia,pull = <0>;
187 nvidia,tristate = <0>;
188 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600189 conf_ck32 {
190 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
191 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
192 nvidia,pull = <0>;
193 };
Stephen Warren563da212012-04-13 16:35:20 -0600194 conf_csus {
195 nvidia,pins = "csus", "spid", "spif";
196 nvidia,pull = <1>;
197 nvidia,tristate = <1>;
198 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600199 conf_crtp {
200 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
201 "dtc", "dte", "dtf", "gpu", "sdio1",
202 "slxc", "slxd", "spdi", "spdo", "spig",
Stephen Warren563da212012-04-13 16:35:20 -0600203 "uda";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600204 nvidia,pull = <0>;
205 nvidia,tristate = <1>;
206 };
207 conf_ddc {
208 nvidia,pins = "ddc", "dta", "dtd", "kbca",
209 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
210 "sdc";
211 nvidia,pull = <2>;
212 nvidia,tristate = <0>;
213 };
214 conf_hdint {
215 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
216 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
217 "lvp0", "owc", "sdb";
218 nvidia,tristate = <1>;
219 };
220 conf_irrx {
221 nvidia,pins = "irrx", "irtx", "sdd", "spic",
222 "spie", "spih", "uaa", "uab", "uad",
223 "uca", "ucb";
224 nvidia,pull = <2>;
225 nvidia,tristate = <1>;
226 };
227 conf_lc {
228 nvidia,pins = "lc", "ls";
229 nvidia,pull = <2>;
230 };
231 conf_ld0 {
232 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
233 "ld5", "ld6", "ld7", "ld8", "ld9",
234 "ld10", "ld11", "ld12", "ld13", "ld14",
235 "ld15", "ld16", "ld17", "ldi", "lhp0",
236 "lhp1", "lhp2", "lhs", "lm0", "lpp",
237 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
238 "lvs", "pmc";
239 nvidia,tristate = <0>;
240 };
241 conf_ld17_0 {
242 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
243 "ld23_22";
244 nvidia,pull = <1>;
245 };
246 };
247 };
248
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600249 i2s@70002800 {
250 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600251 };
252
253 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600254 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600255 clock-frequency = <216000000>;
256 };
257
Grant Likely8e267f32011-07-19 17:26:54 -0600258 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600259 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600260 clock-frequency = <400000>;
261
Stephen Warren797acf72012-01-11 16:09:57 -0700262 wm8903: wm8903@1a {
Grant Likely8e267f32011-07-19 17:26:54 -0600263 compatible = "wlf,wm8903";
264 reg = <0x1a>;
Stephen Warren797acf72012-01-11 16:09:57 -0700265 interrupt-parent = <&gpio>;
Stephen Warren95decf82012-05-11 16:11:38 -0600266 interrupts = <187 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600267
268 gpio-controller;
269 #gpio-cells = <2>;
270
Stephen Warren797acf72012-01-11 16:09:57 -0700271 micdet-cfg = <0>;
272 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600273 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Grant Likely8e267f32011-07-19 17:26:54 -0600274 };
275 };
276
Stephen Warren20ffbd72012-11-09 16:58:11 -0700277 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600278 status = "okay";
Stephen Warren20ffbd72012-11-09 16:58:11 -0700279 clock-frequency = <100000>;
Grant Likely8e267f32011-07-19 17:26:54 -0600280 };
281
282 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600283 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600284 clock-frequency = <400000>;
285 };
286
287 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600288 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600289 clock-frequency = <400000>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000290
291 pmic: tps6586x@34 {
292 compatible = "ti,tps6586x";
293 reg = <0x34>;
294 interrupts = <0 86 0x4>;
295
Stephen Warrenbe972c32012-09-11 11:40:04 -0600296 ti,system-power-controller;
297
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000298 #gpio-cells = <2>;
299 gpio-controller;
300
301 sys-supply = <&vdd_5v0_reg>;
302 vin-sm0-supply = <&sys_reg>;
303 vin-sm1-supply = <&sys_reg>;
304 vin-sm2-supply = <&sys_reg>;
305 vinldo01-supply = <&sm2_reg>;
306 vinldo23-supply = <&sm2_reg>;
307 vinldo4-supply = <&sm2_reg>;
308 vinldo678-supply = <&sm2_reg>;
309 vinldo9-supply = <&sm2_reg>;
310
311 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600312 sys_reg: sys {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000313 regulator-name = "vdd_sys";
314 regulator-always-on;
315 };
316
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600317 sm0 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000318 regulator-name = "vdd_sm0,vdd_core";
319 regulator-min-microvolt = <1200000>;
320 regulator-max-microvolt = <1200000>;
321 regulator-always-on;
322 };
323
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600324 sm1 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000325 regulator-name = "vdd_sm1,vdd_cpu";
326 regulator-min-microvolt = <1000000>;
327 regulator-max-microvolt = <1000000>;
328 regulator-always-on;
329 };
330
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600331 sm2_reg: sm2 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000332 regulator-name = "vdd_sm2,vin_ldo*";
333 regulator-min-microvolt = <3700000>;
334 regulator-max-microvolt = <3700000>;
335 regulator-always-on;
336 };
337
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600338 ldo0 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000339 regulator-name = "vdd_ldo0,vddio_pex_clk";
340 regulator-min-microvolt = <3300000>;
341 regulator-max-microvolt = <3300000>;
342 };
343
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600344 ldo1 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000345 regulator-name = "vdd_ldo1,avdd_pll*";
346 regulator-min-microvolt = <1100000>;
347 regulator-max-microvolt = <1100000>;
348 regulator-always-on;
349 };
350
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600351 ldo2 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000352 regulator-name = "vdd_ldo2,vdd_rtc";
353 regulator-min-microvolt = <1200000>;
354 regulator-max-microvolt = <1200000>;
355 };
356
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600357 ldo3 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000358 regulator-name = "vdd_ldo3,avdd_usb*";
359 regulator-min-microvolt = <3300000>;
360 regulator-max-microvolt = <3300000>;
361 regulator-always-on;
362 };
363
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600364 ldo4 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000365 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
366 regulator-min-microvolt = <1800000>;
367 regulator-max-microvolt = <1800000>;
368 regulator-always-on;
369 };
370
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600371 ldo5 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000372 regulator-name = "vdd_ldo5,vcore_mmc";
373 regulator-min-microvolt = <2850000>;
374 regulator-max-microvolt = <2850000>;
375 regulator-always-on;
376 };
377
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600378 ldo6 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000379 regulator-name = "vdd_ldo6,avdd_vdac";
380 regulator-min-microvolt = <1800000>;
381 regulator-max-microvolt = <1800000>;
382 };
383
Stephen Warren20ffbd72012-11-09 16:58:11 -0700384 hdmi_vdd_reg: ldo7 {
Stephen Warren740418e2012-09-20 15:20:39 -0600385 regulator-name = "vdd_ldo7,avdd_hdmi";
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000386 regulator-min-microvolt = <3300000>;
387 regulator-max-microvolt = <3300000>;
388 };
389
Stephen Warren20ffbd72012-11-09 16:58:11 -0700390 hdmi_pll_reg: ldo8 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000391 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
392 regulator-min-microvolt = <1800000>;
393 regulator-max-microvolt = <1800000>;
394 };
395
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600396 ldo9 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000397 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
398 regulator-min-microvolt = <2850000>;
399 regulator-max-microvolt = <2850000>;
400 regulator-always-on;
401 };
402
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600403 ldo_rtc {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000404 regulator-name = "vdd_rtc_out,vdd_cell";
405 regulator-min-microvolt = <3300000>;
406 regulator-max-microvolt = <3300000>;
407 regulator-always-on;
408 };
409 };
410 };
Thierry Reding42d25342012-11-09 22:58:43 +0100411
412 temperature-sensor@4c {
413 compatible = "adi,adt7461";
414 reg = <0x4c>;
415 };
Grant Likely8e267f32011-07-19 17:26:54 -0600416 };
417
Stephen Warrenc04abb32012-05-11 17:03:26 -0600418 pmc {
419 nvidia,invert-interrupt;
420 };
421
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600422 usb@c5000000 {
423 status = "okay";
424 };
425
Stephen Warrenc04abb32012-05-11 17:03:26 -0600426 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600427 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600428 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
429 };
430
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600431 usb@c5008000 {
432 status = "okay";
Stephen Warren797acf72012-01-11 16:09:57 -0700433 };
Grant Likely8e267f32011-07-19 17:26:54 -0600434
Stephen Warrenc04abb32012-05-11 17:03:26 -0600435 sdhci@c8000200 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600436 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600437 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
438 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
439 power-gpios = <&gpio 155 0>; /* gpio PT3 */
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200440 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600441 };
442
Stephen Warrenc04abb32012-05-11 17:03:26 -0600443 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600444 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600445 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
446 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
447 power-gpios = <&gpio 70 0>; /* gpio PI6 */
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200448 bus-width = <8>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600449 };
450
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000451 regulators {
452 compatible = "simple-bus";
453 #address-cells = <1>;
454 #size-cells = <0>;
455
456 vdd_5v0_reg: regulator@0 {
457 compatible = "regulator-fixed";
458 reg = <0>;
459 regulator-name = "vdd_5v0";
460 regulator-min-microvolt = <5000000>;
461 regulator-max-microvolt = <5000000>;
462 regulator-always-on;
463 };
464
465 regulator@1 {
466 compatible = "regulator-fixed";
467 reg = <1>;
468 regulator-name = "vdd_1v5";
469 regulator-min-microvolt = <1500000>;
470 regulator-max-microvolt = <1500000>;
471 gpio = <&pmic 0 0>;
472 };
473
474 regulator@2 {
475 compatible = "regulator-fixed";
476 reg = <2>;
477 regulator-name = "vdd_1v2";
478 regulator-min-microvolt = <1200000>;
479 regulator-max-microvolt = <1200000>;
480 gpio = <&pmic 1 0>;
481 enable-active-high;
482 };
483
484 regulator@3 {
485 compatible = "regulator-fixed";
486 reg = <3>;
487 regulator-name = "vdd_1v05";
488 regulator-min-microvolt = <1050000>;
489 regulator-max-microvolt = <1050000>;
490 gpio = <&pmic 2 0>;
491 enable-active-high;
492 /* Hack until board-harmony-pcie.c is removed */
493 status = "disabled";
494 };
495
496 regulator@4 {
497 compatible = "regulator-fixed";
498 reg = <4>;
499 regulator-name = "vdd_pnl";
500 regulator-min-microvolt = <2800000>;
501 regulator-max-microvolt = <2800000>;
502 gpio = <&gpio 22 0>; /* gpio PC6 */
503 enable-active-high;
504 };
505
506 regulator@5 {
507 compatible = "regulator-fixed";
508 reg = <5>;
509 regulator-name = "vdd_bl";
510 regulator-min-microvolt = <2800000>;
511 regulator-max-microvolt = <2800000>;
512 gpio = <&gpio 176 0>; /* gpio PW0 */
513 enable-active-high;
514 };
515 };
516
Stephen Warren797acf72012-01-11 16:09:57 -0700517 sound {
518 compatible = "nvidia,tegra-audio-wm8903-harmony",
519 "nvidia,tegra-audio-wm8903";
520 nvidia,model = "NVIDIA Tegra Harmony";
521
522 nvidia,audio-routing =
523 "Headphone Jack", "HPOUTR",
524 "Headphone Jack", "HPOUTL",
525 "Int Spk", "ROP",
526 "Int Spk", "RON",
527 "Int Spk", "LOP",
528 "Int Spk", "LON",
529 "Mic Jack", "MICBIAS",
530 "IN1L", "Mic Jack";
531
532 nvidia,i2s-controller = <&tegra_i2s1>;
533 nvidia,audio-codec = <&wm8903>;
534
535 nvidia,spkr-en-gpios = <&wm8903 2 0>;
536 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
537 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
538 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
Grant Likely8e267f32011-07-19 17:26:54 -0600539 };
Grant Likely8e267f32011-07-19 17:26:54 -0600540};