Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1 | /* Xilinx CAN device driver |
| 2 | * |
| 3 | * Copyright (C) 2012 - 2014 Xilinx, Inc. |
| 4 | * Copyright (C) 2009 PetaLogix. All rights reserved. |
| 5 | * |
| 6 | * Description: |
| 7 | * This driver is developed for Axi CAN IP and for Zynq CANPS Controller. |
| 8 | * This program is free software: you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation, either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <linux/clk.h> |
| 20 | #include <linux/errno.h> |
| 21 | #include <linux/init.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/io.h> |
| 24 | #include <linux/kernel.h> |
| 25 | #include <linux/module.h> |
| 26 | #include <linux/netdevice.h> |
| 27 | #include <linux/of.h> |
| 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/skbuff.h> |
| 30 | #include <linux/string.h> |
| 31 | #include <linux/types.h> |
| 32 | #include <linux/can/dev.h> |
| 33 | #include <linux/can/error.h> |
| 34 | #include <linux/can/led.h> |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 35 | #include <linux/pm_runtime.h> |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 36 | |
| 37 | #define DRIVER_NAME "xilinx_can" |
| 38 | |
| 39 | /* CAN registers set */ |
| 40 | enum xcan_reg { |
| 41 | XCAN_SRR_OFFSET = 0x00, /* Software reset */ |
| 42 | XCAN_MSR_OFFSET = 0x04, /* Mode select */ |
| 43 | XCAN_BRPR_OFFSET = 0x08, /* Baud rate prescaler */ |
| 44 | XCAN_BTR_OFFSET = 0x0C, /* Bit timing */ |
| 45 | XCAN_ECR_OFFSET = 0x10, /* Error counter */ |
| 46 | XCAN_ESR_OFFSET = 0x14, /* Error status */ |
| 47 | XCAN_SR_OFFSET = 0x18, /* Status */ |
| 48 | XCAN_ISR_OFFSET = 0x1C, /* Interrupt status */ |
| 49 | XCAN_IER_OFFSET = 0x20, /* Interrupt enable */ |
| 50 | XCAN_ICR_OFFSET = 0x24, /* Interrupt clear */ |
| 51 | XCAN_TXFIFO_ID_OFFSET = 0x30,/* TX FIFO ID */ |
| 52 | XCAN_TXFIFO_DLC_OFFSET = 0x34, /* TX FIFO DLC */ |
| 53 | XCAN_TXFIFO_DW1_OFFSET = 0x38, /* TX FIFO Data Word 1 */ |
| 54 | XCAN_TXFIFO_DW2_OFFSET = 0x3C, /* TX FIFO Data Word 2 */ |
| 55 | XCAN_RXFIFO_ID_OFFSET = 0x50, /* RX FIFO ID */ |
| 56 | XCAN_RXFIFO_DLC_OFFSET = 0x54, /* RX FIFO DLC */ |
| 57 | XCAN_RXFIFO_DW1_OFFSET = 0x58, /* RX FIFO Data Word 1 */ |
| 58 | XCAN_RXFIFO_DW2_OFFSET = 0x5C, /* RX FIFO Data Word 2 */ |
| 59 | }; |
| 60 | |
| 61 | /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */ |
| 62 | #define XCAN_SRR_CEN_MASK 0x00000002 /* CAN enable */ |
| 63 | #define XCAN_SRR_RESET_MASK 0x00000001 /* Soft Reset the CAN core */ |
| 64 | #define XCAN_MSR_LBACK_MASK 0x00000002 /* Loop back mode select */ |
| 65 | #define XCAN_MSR_SLEEP_MASK 0x00000001 /* Sleep mode select */ |
| 66 | #define XCAN_BRPR_BRP_MASK 0x000000FF /* Baud rate prescaler */ |
| 67 | #define XCAN_BTR_SJW_MASK 0x00000180 /* Synchronous jump width */ |
| 68 | #define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */ |
| 69 | #define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */ |
| 70 | #define XCAN_ECR_REC_MASK 0x0000FF00 /* Receive error counter */ |
| 71 | #define XCAN_ECR_TEC_MASK 0x000000FF /* Transmit error counter */ |
| 72 | #define XCAN_ESR_ACKER_MASK 0x00000010 /* ACK error */ |
| 73 | #define XCAN_ESR_BERR_MASK 0x00000008 /* Bit error */ |
| 74 | #define XCAN_ESR_STER_MASK 0x00000004 /* Stuff error */ |
| 75 | #define XCAN_ESR_FMER_MASK 0x00000002 /* Form error */ |
| 76 | #define XCAN_ESR_CRCER_MASK 0x00000001 /* CRC error */ |
| 77 | #define XCAN_SR_TXFLL_MASK 0x00000400 /* TX FIFO is full */ |
| 78 | #define XCAN_SR_ESTAT_MASK 0x00000180 /* Error status */ |
| 79 | #define XCAN_SR_ERRWRN_MASK 0x00000040 /* Error warning */ |
| 80 | #define XCAN_SR_NORMAL_MASK 0x00000008 /* Normal mode */ |
| 81 | #define XCAN_SR_LBACK_MASK 0x00000002 /* Loop back mode */ |
| 82 | #define XCAN_SR_CONFIG_MASK 0x00000001 /* Configuration mode */ |
| 83 | #define XCAN_IXR_TXFEMP_MASK 0x00004000 /* TX FIFO Empty */ |
| 84 | #define XCAN_IXR_WKUP_MASK 0x00000800 /* Wake up interrupt */ |
| 85 | #define XCAN_IXR_SLP_MASK 0x00000400 /* Sleep interrupt */ |
| 86 | #define XCAN_IXR_BSOFF_MASK 0x00000200 /* Bus off interrupt */ |
| 87 | #define XCAN_IXR_ERROR_MASK 0x00000100 /* Error interrupt */ |
| 88 | #define XCAN_IXR_RXNEMP_MASK 0x00000080 /* RX FIFO NotEmpty intr */ |
| 89 | #define XCAN_IXR_RXOFLW_MASK 0x00000040 /* RX FIFO Overflow intr */ |
| 90 | #define XCAN_IXR_RXOK_MASK 0x00000010 /* Message received intr */ |
| 91 | #define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */ |
| 92 | #define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */ |
| 93 | #define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */ |
| 94 | #define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */ |
| 95 | #define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */ |
| 96 | #define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */ |
| 97 | #define XCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */ |
| 98 | #define XCAN_IDR_RTR_MASK 0x00000001 /* Remote TX request */ |
| 99 | #define XCAN_DLCR_DLC_MASK 0xF0000000 /* Data length code */ |
| 100 | |
| 101 | #define XCAN_INTR_ALL (XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK |\ |
| 102 | XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | \ |
| 103 | XCAN_IXR_RXNEMP_MASK | XCAN_IXR_ERROR_MASK | \ |
| 104 | XCAN_IXR_ARBLST_MASK | XCAN_IXR_RXOK_MASK) |
| 105 | |
| 106 | /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */ |
| 107 | #define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */ |
| 108 | #define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */ |
| 109 | #define XCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */ |
| 110 | #define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */ |
| 111 | #define XCAN_DLCR_DLC_SHIFT 28 /* Data length code */ |
| 112 | #define XCAN_ESR_REC_SHIFT 8 /* Rx Error Count */ |
| 113 | |
| 114 | /* CAN frame length constants */ |
| 115 | #define XCAN_FRAME_MAX_DATA_LEN 8 |
| 116 | #define XCAN_TIMEOUT (1 * HZ) |
| 117 | |
| 118 | /** |
| 119 | * struct xcan_priv - This definition define CAN driver instance |
| 120 | * @can: CAN private data structure. |
| 121 | * @tx_head: Tx CAN packets ready to send on the queue |
| 122 | * @tx_tail: Tx CAN packets successfully sended on the queue |
| 123 | * @tx_max: Maximum number packets the driver can send |
| 124 | * @napi: NAPI structure |
| 125 | * @read_reg: For reading data from CAN registers |
| 126 | * @write_reg: For writing data to CAN registers |
| 127 | * @dev: Network device data structure |
| 128 | * @reg_base: Ioremapped address to registers |
| 129 | * @irq_flags: For request_irq() |
| 130 | * @bus_clk: Pointer to struct clk |
| 131 | * @can_clk: Pointer to struct clk |
| 132 | */ |
| 133 | struct xcan_priv { |
| 134 | struct can_priv can; |
| 135 | unsigned int tx_head; |
| 136 | unsigned int tx_tail; |
| 137 | unsigned int tx_max; |
| 138 | struct napi_struct napi; |
| 139 | u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg); |
| 140 | void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg, |
| 141 | u32 val); |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 142 | struct device *dev; |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 143 | void __iomem *reg_base; |
| 144 | unsigned long irq_flags; |
| 145 | struct clk *bus_clk; |
| 146 | struct clk *can_clk; |
| 147 | }; |
| 148 | |
| 149 | /* CAN Bittiming constants as per Xilinx CAN specs */ |
| 150 | static const struct can_bittiming_const xcan_bittiming_const = { |
| 151 | .name = DRIVER_NAME, |
| 152 | .tseg1_min = 1, |
| 153 | .tseg1_max = 16, |
| 154 | .tseg2_min = 1, |
| 155 | .tseg2_max = 8, |
| 156 | .sjw_max = 4, |
| 157 | .brp_min = 1, |
| 158 | .brp_max = 256, |
| 159 | .brp_inc = 1, |
| 160 | }; |
| 161 | |
| 162 | /** |
| 163 | * xcan_write_reg_le - Write a value to the device register little endian |
| 164 | * @priv: Driver private data structure |
| 165 | * @reg: Register offset |
| 166 | * @val: Value to write at the Register offset |
| 167 | * |
| 168 | * Write data to the paricular CAN register |
| 169 | */ |
| 170 | static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg, |
| 171 | u32 val) |
| 172 | { |
| 173 | iowrite32(val, priv->reg_base + reg); |
| 174 | } |
| 175 | |
| 176 | /** |
| 177 | * xcan_read_reg_le - Read a value from the device register little endian |
| 178 | * @priv: Driver private data structure |
| 179 | * @reg: Register offset |
| 180 | * |
| 181 | * Read data from the particular CAN register |
| 182 | * Return: value read from the CAN register |
| 183 | */ |
| 184 | static u32 xcan_read_reg_le(const struct xcan_priv *priv, enum xcan_reg reg) |
| 185 | { |
| 186 | return ioread32(priv->reg_base + reg); |
| 187 | } |
| 188 | |
| 189 | /** |
| 190 | * xcan_write_reg_be - Write a value to the device register big endian |
| 191 | * @priv: Driver private data structure |
| 192 | * @reg: Register offset |
| 193 | * @val: Value to write at the Register offset |
| 194 | * |
| 195 | * Write data to the paricular CAN register |
| 196 | */ |
| 197 | static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg, |
| 198 | u32 val) |
| 199 | { |
| 200 | iowrite32be(val, priv->reg_base + reg); |
| 201 | } |
| 202 | |
| 203 | /** |
| 204 | * xcan_read_reg_be - Read a value from the device register big endian |
| 205 | * @priv: Driver private data structure |
| 206 | * @reg: Register offset |
| 207 | * |
| 208 | * Read data from the particular CAN register |
| 209 | * Return: value read from the CAN register |
| 210 | */ |
| 211 | static u32 xcan_read_reg_be(const struct xcan_priv *priv, enum xcan_reg reg) |
| 212 | { |
| 213 | return ioread32be(priv->reg_base + reg); |
| 214 | } |
| 215 | |
| 216 | /** |
| 217 | * set_reset_mode - Resets the CAN device mode |
| 218 | * @ndev: Pointer to net_device structure |
| 219 | * |
| 220 | * This is the driver reset mode routine.The driver |
| 221 | * enters into configuration mode. |
| 222 | * |
| 223 | * Return: 0 on success and failure value on error |
| 224 | */ |
| 225 | static int set_reset_mode(struct net_device *ndev) |
| 226 | { |
| 227 | struct xcan_priv *priv = netdev_priv(ndev); |
| 228 | unsigned long timeout; |
| 229 | |
| 230 | priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); |
| 231 | |
| 232 | timeout = jiffies + XCAN_TIMEOUT; |
| 233 | while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) { |
| 234 | if (time_after(jiffies, timeout)) { |
| 235 | netdev_warn(ndev, "timed out for config mode\n"); |
| 236 | return -ETIMEDOUT; |
| 237 | } |
| 238 | usleep_range(500, 10000); |
| 239 | } |
| 240 | |
| 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | /** |
| 245 | * xcan_set_bittiming - CAN set bit timing routine |
| 246 | * @ndev: Pointer to net_device structure |
| 247 | * |
| 248 | * This is the driver set bittiming routine. |
| 249 | * Return: 0 on success and failure value on error |
| 250 | */ |
| 251 | static int xcan_set_bittiming(struct net_device *ndev) |
| 252 | { |
| 253 | struct xcan_priv *priv = netdev_priv(ndev); |
| 254 | struct can_bittiming *bt = &priv->can.bittiming; |
| 255 | u32 btr0, btr1; |
| 256 | u32 is_config_mode; |
| 257 | |
| 258 | /* Check whether Xilinx CAN is in configuration mode. |
| 259 | * It cannot set bit timing if Xilinx CAN is not in configuration mode. |
| 260 | */ |
| 261 | is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) & |
| 262 | XCAN_SR_CONFIG_MASK; |
| 263 | if (!is_config_mode) { |
| 264 | netdev_alert(ndev, |
| 265 | "BUG! Cannot set bittiming - CAN is not in config mode\n"); |
| 266 | return -EPERM; |
| 267 | } |
| 268 | |
| 269 | /* Setting Baud Rate prescalar value in BRPR Register */ |
| 270 | btr0 = (bt->brp - 1); |
| 271 | |
| 272 | /* Setting Time Segment 1 in BTR Register */ |
| 273 | btr1 = (bt->prop_seg + bt->phase_seg1 - 1); |
| 274 | |
| 275 | /* Setting Time Segment 2 in BTR Register */ |
| 276 | btr1 |= (bt->phase_seg2 - 1) << XCAN_BTR_TS2_SHIFT; |
| 277 | |
| 278 | /* Setting Synchronous jump width in BTR Register */ |
| 279 | btr1 |= (bt->sjw - 1) << XCAN_BTR_SJW_SHIFT; |
| 280 | |
| 281 | priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0); |
| 282 | priv->write_reg(priv, XCAN_BTR_OFFSET, btr1); |
| 283 | |
| 284 | netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n", |
| 285 | priv->read_reg(priv, XCAN_BRPR_OFFSET), |
| 286 | priv->read_reg(priv, XCAN_BTR_OFFSET)); |
| 287 | |
| 288 | return 0; |
| 289 | } |
| 290 | |
| 291 | /** |
| 292 | * xcan_chip_start - This the drivers start routine |
| 293 | * @ndev: Pointer to net_device structure |
| 294 | * |
| 295 | * This is the drivers start routine. |
| 296 | * Based on the State of the CAN device it puts |
| 297 | * the CAN device into a proper mode. |
| 298 | * |
| 299 | * Return: 0 on success and failure value on error |
| 300 | */ |
| 301 | static int xcan_chip_start(struct net_device *ndev) |
| 302 | { |
| 303 | struct xcan_priv *priv = netdev_priv(ndev); |
Sudip Mukherjee | fb3ec7b | 2014-11-18 19:17:07 +0530 | [diff] [blame] | 304 | u32 reg_msr, reg_sr_mask; |
| 305 | int err; |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 306 | unsigned long timeout; |
| 307 | |
| 308 | /* Check if it is in reset mode */ |
| 309 | err = set_reset_mode(ndev); |
| 310 | if (err < 0) |
| 311 | return err; |
| 312 | |
| 313 | err = xcan_set_bittiming(ndev); |
| 314 | if (err < 0) |
| 315 | return err; |
| 316 | |
| 317 | /* Enable interrupts */ |
| 318 | priv->write_reg(priv, XCAN_IER_OFFSET, XCAN_INTR_ALL); |
| 319 | |
| 320 | /* Check whether it is loopback mode or normal mode */ |
| 321 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { |
| 322 | reg_msr = XCAN_MSR_LBACK_MASK; |
| 323 | reg_sr_mask = XCAN_SR_LBACK_MASK; |
| 324 | } else { |
| 325 | reg_msr = 0x0; |
| 326 | reg_sr_mask = XCAN_SR_NORMAL_MASK; |
| 327 | } |
| 328 | |
| 329 | priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr); |
| 330 | priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK); |
| 331 | |
| 332 | timeout = jiffies + XCAN_TIMEOUT; |
| 333 | while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & reg_sr_mask)) { |
| 334 | if (time_after(jiffies, timeout)) { |
| 335 | netdev_warn(ndev, |
| 336 | "timed out for correct mode\n"); |
| 337 | return -ETIMEDOUT; |
| 338 | } |
| 339 | } |
| 340 | netdev_dbg(ndev, "status:#x%08x\n", |
| 341 | priv->read_reg(priv, XCAN_SR_OFFSET)); |
| 342 | |
| 343 | priv->can.state = CAN_STATE_ERROR_ACTIVE; |
| 344 | return 0; |
| 345 | } |
| 346 | |
| 347 | /** |
| 348 | * xcan_do_set_mode - This sets the mode of the driver |
| 349 | * @ndev: Pointer to net_device structure |
| 350 | * @mode: Tells the mode of the driver |
| 351 | * |
| 352 | * This check the drivers state and calls the |
| 353 | * the corresponding modes to set. |
| 354 | * |
| 355 | * Return: 0 on success and failure value on error |
| 356 | */ |
| 357 | static int xcan_do_set_mode(struct net_device *ndev, enum can_mode mode) |
| 358 | { |
| 359 | int ret; |
| 360 | |
| 361 | switch (mode) { |
| 362 | case CAN_MODE_START: |
| 363 | ret = xcan_chip_start(ndev); |
| 364 | if (ret < 0) { |
| 365 | netdev_err(ndev, "xcan_chip_start failed!\n"); |
| 366 | return ret; |
| 367 | } |
| 368 | netif_wake_queue(ndev); |
| 369 | break; |
| 370 | default: |
| 371 | ret = -EOPNOTSUPP; |
| 372 | break; |
| 373 | } |
| 374 | |
| 375 | return ret; |
| 376 | } |
| 377 | |
| 378 | /** |
| 379 | * xcan_start_xmit - Starts the transmission |
| 380 | * @skb: sk_buff pointer that contains data to be Txed |
| 381 | * @ndev: Pointer to net_device structure |
| 382 | * |
| 383 | * This function is invoked from upper layers to initiate transmission. This |
| 384 | * function uses the next available free txbuff and populates their fields to |
| 385 | * start the transmission. |
| 386 | * |
| 387 | * Return: 0 on success and failure value on error |
| 388 | */ |
| 389 | static int xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
| 390 | { |
| 391 | struct xcan_priv *priv = netdev_priv(ndev); |
| 392 | struct net_device_stats *stats = &ndev->stats; |
| 393 | struct can_frame *cf = (struct can_frame *)skb->data; |
| 394 | u32 id, dlc, data[2] = {0, 0}; |
| 395 | |
| 396 | if (can_dropped_invalid_skb(ndev, skb)) |
| 397 | return NETDEV_TX_OK; |
| 398 | |
| 399 | /* Check if the TX buffer is full */ |
| 400 | if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) & |
| 401 | XCAN_SR_TXFLL_MASK)) { |
| 402 | netif_stop_queue(ndev); |
| 403 | netdev_err(ndev, "BUG!, TX FIFO full when queue awake!\n"); |
| 404 | return NETDEV_TX_BUSY; |
| 405 | } |
| 406 | |
| 407 | /* Watch carefully on the bit sequence */ |
| 408 | if (cf->can_id & CAN_EFF_FLAG) { |
| 409 | /* Extended CAN ID format */ |
| 410 | id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) & |
| 411 | XCAN_IDR_ID2_MASK; |
| 412 | id |= (((cf->can_id & CAN_EFF_MASK) >> |
| 413 | (CAN_EFF_ID_BITS-CAN_SFF_ID_BITS)) << |
| 414 | XCAN_IDR_ID1_SHIFT) & XCAN_IDR_ID1_MASK; |
| 415 | |
| 416 | /* The substibute remote TX request bit should be "1" |
| 417 | * for extended frames as in the Xilinx CAN datasheet |
| 418 | */ |
| 419 | id |= XCAN_IDR_IDE_MASK | XCAN_IDR_SRR_MASK; |
| 420 | |
| 421 | if (cf->can_id & CAN_RTR_FLAG) |
| 422 | /* Extended frames remote TX request */ |
| 423 | id |= XCAN_IDR_RTR_MASK; |
| 424 | } else { |
| 425 | /* Standard CAN ID format */ |
| 426 | id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) & |
| 427 | XCAN_IDR_ID1_MASK; |
| 428 | |
| 429 | if (cf->can_id & CAN_RTR_FLAG) |
| 430 | /* Standard frames remote TX request */ |
| 431 | id |= XCAN_IDR_SRR_MASK; |
| 432 | } |
| 433 | |
| 434 | dlc = cf->can_dlc << XCAN_DLCR_DLC_SHIFT; |
| 435 | |
| 436 | if (cf->can_dlc > 0) |
| 437 | data[0] = be32_to_cpup((__be32 *)(cf->data + 0)); |
| 438 | if (cf->can_dlc > 4) |
| 439 | data[1] = be32_to_cpup((__be32 *)(cf->data + 4)); |
| 440 | |
| 441 | can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max); |
| 442 | priv->tx_head++; |
| 443 | |
| 444 | /* Write the Frame to Xilinx CAN TX FIFO */ |
| 445 | priv->write_reg(priv, XCAN_TXFIFO_ID_OFFSET, id); |
| 446 | /* If the CAN frame is RTR frame this write triggers tranmission */ |
| 447 | priv->write_reg(priv, XCAN_TXFIFO_DLC_OFFSET, dlc); |
| 448 | if (!(cf->can_id & CAN_RTR_FLAG)) { |
| 449 | priv->write_reg(priv, XCAN_TXFIFO_DW1_OFFSET, data[0]); |
| 450 | /* If the CAN frame is Standard/Extended frame this |
| 451 | * write triggers tranmission |
| 452 | */ |
| 453 | priv->write_reg(priv, XCAN_TXFIFO_DW2_OFFSET, data[1]); |
| 454 | stats->tx_bytes += cf->can_dlc; |
| 455 | } |
| 456 | |
| 457 | /* Check if the TX buffer is full */ |
| 458 | if ((priv->tx_head - priv->tx_tail) == priv->tx_max) |
| 459 | netif_stop_queue(ndev); |
| 460 | |
| 461 | return NETDEV_TX_OK; |
| 462 | } |
| 463 | |
| 464 | /** |
| 465 | * xcan_rx - Is called from CAN isr to complete the received |
| 466 | * frame processing |
| 467 | * @ndev: Pointer to net_device structure |
| 468 | * |
| 469 | * This function is invoked from the CAN isr(poll) to process the Rx frames. It |
| 470 | * does minimal processing and invokes "netif_receive_skb" to complete further |
| 471 | * processing. |
| 472 | * Return: 1 on success and 0 on failure. |
| 473 | */ |
| 474 | static int xcan_rx(struct net_device *ndev) |
| 475 | { |
| 476 | struct xcan_priv *priv = netdev_priv(ndev); |
| 477 | struct net_device_stats *stats = &ndev->stats; |
| 478 | struct can_frame *cf; |
| 479 | struct sk_buff *skb; |
| 480 | u32 id_xcan, dlc, data[2] = {0, 0}; |
| 481 | |
| 482 | skb = alloc_can_skb(ndev, &cf); |
| 483 | if (unlikely(!skb)) { |
| 484 | stats->rx_dropped++; |
| 485 | return 0; |
| 486 | } |
| 487 | |
| 488 | /* Read a frame from Xilinx zynq CANPS */ |
| 489 | id_xcan = priv->read_reg(priv, XCAN_RXFIFO_ID_OFFSET); |
| 490 | dlc = priv->read_reg(priv, XCAN_RXFIFO_DLC_OFFSET) >> |
| 491 | XCAN_DLCR_DLC_SHIFT; |
| 492 | |
| 493 | /* Change Xilinx CAN data length format to socketCAN data format */ |
| 494 | cf->can_dlc = get_can_dlc(dlc); |
| 495 | |
| 496 | /* Change Xilinx CAN ID format to socketCAN ID format */ |
| 497 | if (id_xcan & XCAN_IDR_IDE_MASK) { |
| 498 | /* The received frame is an Extended format frame */ |
| 499 | cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3; |
| 500 | cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >> |
| 501 | XCAN_IDR_ID2_SHIFT; |
| 502 | cf->can_id |= CAN_EFF_FLAG; |
| 503 | if (id_xcan & XCAN_IDR_RTR_MASK) |
| 504 | cf->can_id |= CAN_RTR_FLAG; |
| 505 | } else { |
| 506 | /* The received frame is a standard format frame */ |
| 507 | cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> |
| 508 | XCAN_IDR_ID1_SHIFT; |
| 509 | if (id_xcan & XCAN_IDR_SRR_MASK) |
| 510 | cf->can_id |= CAN_RTR_FLAG; |
| 511 | } |
| 512 | |
Jeppe Ledet-Pedersen | 5793aff | 2015-04-29 17:05:01 +0200 | [diff] [blame] | 513 | /* DW1/DW2 must always be read to remove message from RXFIFO */ |
| 514 | data[0] = priv->read_reg(priv, XCAN_RXFIFO_DW1_OFFSET); |
| 515 | data[1] = priv->read_reg(priv, XCAN_RXFIFO_DW2_OFFSET); |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 516 | |
Jeppe Ledet-Pedersen | 5793aff | 2015-04-29 17:05:01 +0200 | [diff] [blame] | 517 | if (!(cf->can_id & CAN_RTR_FLAG)) { |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 518 | /* Change Xilinx CAN data format to socketCAN data format */ |
| 519 | if (cf->can_dlc > 0) |
| 520 | *(__be32 *)(cf->data) = cpu_to_be32(data[0]); |
| 521 | if (cf->can_dlc > 4) |
| 522 | *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]); |
| 523 | } |
| 524 | |
| 525 | stats->rx_bytes += cf->can_dlc; |
| 526 | stats->rx_packets++; |
| 527 | netif_receive_skb(skb); |
| 528 | |
| 529 | return 1; |
| 530 | } |
| 531 | |
| 532 | /** |
| 533 | * xcan_err_interrupt - error frame Isr |
| 534 | * @ndev: net_device pointer |
| 535 | * @isr: interrupt status register value |
| 536 | * |
| 537 | * This is the CAN error interrupt and it will |
| 538 | * check the the type of error and forward the error |
| 539 | * frame to upper layers. |
| 540 | */ |
| 541 | static void xcan_err_interrupt(struct net_device *ndev, u32 isr) |
| 542 | { |
| 543 | struct xcan_priv *priv = netdev_priv(ndev); |
| 544 | struct net_device_stats *stats = &ndev->stats; |
| 545 | struct can_frame *cf; |
| 546 | struct sk_buff *skb; |
| 547 | u32 err_status, status, txerr = 0, rxerr = 0; |
| 548 | |
| 549 | skb = alloc_can_err_skb(ndev, &cf); |
| 550 | |
| 551 | err_status = priv->read_reg(priv, XCAN_ESR_OFFSET); |
| 552 | priv->write_reg(priv, XCAN_ESR_OFFSET, err_status); |
| 553 | txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK; |
| 554 | rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) & |
| 555 | XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT); |
| 556 | status = priv->read_reg(priv, XCAN_SR_OFFSET); |
| 557 | |
| 558 | if (isr & XCAN_IXR_BSOFF_MASK) { |
| 559 | priv->can.state = CAN_STATE_BUS_OFF; |
| 560 | priv->can.can_stats.bus_off++; |
| 561 | /* Leave device in Config Mode in bus-off state */ |
| 562 | priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); |
| 563 | can_bus_off(ndev); |
| 564 | if (skb) |
| 565 | cf->can_id |= CAN_ERR_BUSOFF; |
| 566 | } else if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK) { |
| 567 | priv->can.state = CAN_STATE_ERROR_PASSIVE; |
| 568 | priv->can.can_stats.error_passive++; |
| 569 | if (skb) { |
| 570 | cf->can_id |= CAN_ERR_CRTL; |
| 571 | cf->data[1] = (rxerr > 127) ? |
| 572 | CAN_ERR_CRTL_RX_PASSIVE : |
| 573 | CAN_ERR_CRTL_TX_PASSIVE; |
| 574 | cf->data[6] = txerr; |
| 575 | cf->data[7] = rxerr; |
| 576 | } |
| 577 | } else if (status & XCAN_SR_ERRWRN_MASK) { |
| 578 | priv->can.state = CAN_STATE_ERROR_WARNING; |
| 579 | priv->can.can_stats.error_warning++; |
| 580 | if (skb) { |
| 581 | cf->can_id |= CAN_ERR_CRTL; |
| 582 | cf->data[1] |= (txerr > rxerr) ? |
| 583 | CAN_ERR_CRTL_TX_WARNING : |
| 584 | CAN_ERR_CRTL_RX_WARNING; |
| 585 | cf->data[6] = txerr; |
| 586 | cf->data[7] = rxerr; |
| 587 | } |
| 588 | } |
| 589 | |
| 590 | /* Check for Arbitration lost interrupt */ |
| 591 | if (isr & XCAN_IXR_ARBLST_MASK) { |
| 592 | priv->can.can_stats.arbitration_lost++; |
| 593 | if (skb) { |
| 594 | cf->can_id |= CAN_ERR_LOSTARB; |
| 595 | cf->data[0] = CAN_ERR_LOSTARB_UNSPEC; |
| 596 | } |
| 597 | } |
| 598 | |
| 599 | /* Check for RX FIFO Overflow interrupt */ |
| 600 | if (isr & XCAN_IXR_RXOFLW_MASK) { |
| 601 | stats->rx_over_errors++; |
| 602 | stats->rx_errors++; |
| 603 | priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); |
| 604 | if (skb) { |
| 605 | cf->can_id |= CAN_ERR_CRTL; |
| 606 | cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; |
| 607 | } |
| 608 | } |
| 609 | |
| 610 | /* Check for error interrupt */ |
| 611 | if (isr & XCAN_IXR_ERROR_MASK) { |
Oliver Hartkopp | a2ec19f | 2015-11-21 18:41:21 +0100 | [diff] [blame] | 612 | if (skb) |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 613 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 614 | |
| 615 | /* Check for Ack error interrupt */ |
| 616 | if (err_status & XCAN_ESR_ACKER_MASK) { |
| 617 | stats->tx_errors++; |
| 618 | if (skb) { |
| 619 | cf->can_id |= CAN_ERR_ACK; |
Oliver Hartkopp | ffd461f | 2015-11-21 18:41:20 +0100 | [diff] [blame] | 620 | cf->data[3] = CAN_ERR_PROT_LOC_ACK; |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 621 | } |
| 622 | } |
| 623 | |
| 624 | /* Check for Bit error interrupt */ |
| 625 | if (err_status & XCAN_ESR_BERR_MASK) { |
| 626 | stats->tx_errors++; |
| 627 | if (skb) { |
| 628 | cf->can_id |= CAN_ERR_PROT; |
| 629 | cf->data[2] = CAN_ERR_PROT_BIT; |
| 630 | } |
| 631 | } |
| 632 | |
| 633 | /* Check for Stuff error interrupt */ |
| 634 | if (err_status & XCAN_ESR_STER_MASK) { |
| 635 | stats->rx_errors++; |
| 636 | if (skb) { |
| 637 | cf->can_id |= CAN_ERR_PROT; |
| 638 | cf->data[2] = CAN_ERR_PROT_STUFF; |
| 639 | } |
| 640 | } |
| 641 | |
| 642 | /* Check for Form error interrupt */ |
| 643 | if (err_status & XCAN_ESR_FMER_MASK) { |
| 644 | stats->rx_errors++; |
| 645 | if (skb) { |
| 646 | cf->can_id |= CAN_ERR_PROT; |
| 647 | cf->data[2] = CAN_ERR_PROT_FORM; |
| 648 | } |
| 649 | } |
| 650 | |
| 651 | /* Check for CRC error interrupt */ |
| 652 | if (err_status & XCAN_ESR_CRCER_MASK) { |
| 653 | stats->rx_errors++; |
| 654 | if (skb) { |
| 655 | cf->can_id |= CAN_ERR_PROT; |
Oliver Hartkopp | ffd461f | 2015-11-21 18:41:20 +0100 | [diff] [blame] | 656 | cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 657 | } |
| 658 | } |
| 659 | priv->can.can_stats.bus_error++; |
| 660 | } |
| 661 | |
| 662 | if (skb) { |
| 663 | stats->rx_packets++; |
| 664 | stats->rx_bytes += cf->can_dlc; |
| 665 | netif_rx(skb); |
| 666 | } |
| 667 | |
| 668 | netdev_dbg(ndev, "%s: error status register:0x%x\n", |
| 669 | __func__, priv->read_reg(priv, XCAN_ESR_OFFSET)); |
| 670 | } |
| 671 | |
| 672 | /** |
| 673 | * xcan_state_interrupt - It will check the state of the CAN device |
| 674 | * @ndev: net_device pointer |
| 675 | * @isr: interrupt status register value |
| 676 | * |
| 677 | * This will checks the state of the CAN device |
| 678 | * and puts the device into appropriate state. |
| 679 | */ |
| 680 | static void xcan_state_interrupt(struct net_device *ndev, u32 isr) |
| 681 | { |
| 682 | struct xcan_priv *priv = netdev_priv(ndev); |
| 683 | |
| 684 | /* Check for Sleep interrupt if set put CAN device in sleep state */ |
| 685 | if (isr & XCAN_IXR_SLP_MASK) |
| 686 | priv->can.state = CAN_STATE_SLEEPING; |
| 687 | |
| 688 | /* Check for Wake up interrupt if set put CAN device in Active state */ |
| 689 | if (isr & XCAN_IXR_WKUP_MASK) |
| 690 | priv->can.state = CAN_STATE_ERROR_ACTIVE; |
| 691 | } |
| 692 | |
| 693 | /** |
| 694 | * xcan_rx_poll - Poll routine for rx packets (NAPI) |
| 695 | * @napi: napi structure pointer |
| 696 | * @quota: Max number of rx packets to be processed. |
| 697 | * |
| 698 | * This is the poll routine for rx part. |
| 699 | * It will process the packets maximux quota value. |
| 700 | * |
| 701 | * Return: number of packets received |
| 702 | */ |
| 703 | static int xcan_rx_poll(struct napi_struct *napi, int quota) |
| 704 | { |
| 705 | struct net_device *ndev = napi->dev; |
| 706 | struct xcan_priv *priv = netdev_priv(ndev); |
| 707 | u32 isr, ier; |
| 708 | int work_done = 0; |
| 709 | |
| 710 | isr = priv->read_reg(priv, XCAN_ISR_OFFSET); |
| 711 | while ((isr & XCAN_IXR_RXNEMP_MASK) && (work_done < quota)) { |
| 712 | if (isr & XCAN_IXR_RXOK_MASK) { |
| 713 | priv->write_reg(priv, XCAN_ICR_OFFSET, |
| 714 | XCAN_IXR_RXOK_MASK); |
| 715 | work_done += xcan_rx(ndev); |
| 716 | } else { |
| 717 | priv->write_reg(priv, XCAN_ICR_OFFSET, |
| 718 | XCAN_IXR_RXNEMP_MASK); |
| 719 | break; |
| 720 | } |
| 721 | priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXNEMP_MASK); |
| 722 | isr = priv->read_reg(priv, XCAN_ISR_OFFSET); |
| 723 | } |
| 724 | |
| 725 | if (work_done) |
| 726 | can_led_event(ndev, CAN_LED_EVENT_RX); |
| 727 | |
| 728 | if (work_done < quota) { |
| 729 | napi_complete(napi); |
| 730 | ier = priv->read_reg(priv, XCAN_IER_OFFSET); |
| 731 | ier |= (XCAN_IXR_RXOK_MASK | XCAN_IXR_RXNEMP_MASK); |
| 732 | priv->write_reg(priv, XCAN_IER_OFFSET, ier); |
| 733 | } |
| 734 | return work_done; |
| 735 | } |
| 736 | |
| 737 | /** |
| 738 | * xcan_tx_interrupt - Tx Done Isr |
| 739 | * @ndev: net_device pointer |
| 740 | * @isr: Interrupt status register value |
| 741 | */ |
| 742 | static void xcan_tx_interrupt(struct net_device *ndev, u32 isr) |
| 743 | { |
| 744 | struct xcan_priv *priv = netdev_priv(ndev); |
| 745 | struct net_device_stats *stats = &ndev->stats; |
| 746 | |
| 747 | while ((priv->tx_head - priv->tx_tail > 0) && |
| 748 | (isr & XCAN_IXR_TXOK_MASK)) { |
| 749 | priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); |
| 750 | can_get_echo_skb(ndev, priv->tx_tail % |
| 751 | priv->tx_max); |
| 752 | priv->tx_tail++; |
| 753 | stats->tx_packets++; |
| 754 | isr = priv->read_reg(priv, XCAN_ISR_OFFSET); |
| 755 | } |
| 756 | can_led_event(ndev, CAN_LED_EVENT_TX); |
| 757 | netif_wake_queue(ndev); |
| 758 | } |
| 759 | |
| 760 | /** |
| 761 | * xcan_interrupt - CAN Isr |
| 762 | * @irq: irq number |
| 763 | * @dev_id: device id poniter |
| 764 | * |
| 765 | * This is the xilinx CAN Isr. It checks for the type of interrupt |
| 766 | * and invokes the corresponding ISR. |
| 767 | * |
| 768 | * Return: |
| 769 | * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise |
| 770 | */ |
| 771 | static irqreturn_t xcan_interrupt(int irq, void *dev_id) |
| 772 | { |
| 773 | struct net_device *ndev = (struct net_device *)dev_id; |
| 774 | struct xcan_priv *priv = netdev_priv(ndev); |
| 775 | u32 isr, ier; |
| 776 | |
| 777 | /* Get the interrupt status from Xilinx CAN */ |
| 778 | isr = priv->read_reg(priv, XCAN_ISR_OFFSET); |
| 779 | if (!isr) |
| 780 | return IRQ_NONE; |
| 781 | |
| 782 | /* Check for the type of interrupt and Processing it */ |
| 783 | if (isr & (XCAN_IXR_SLP_MASK | XCAN_IXR_WKUP_MASK)) { |
| 784 | priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK | |
| 785 | XCAN_IXR_WKUP_MASK)); |
| 786 | xcan_state_interrupt(ndev, isr); |
| 787 | } |
| 788 | |
| 789 | /* Check for Tx interrupt and Processing it */ |
| 790 | if (isr & XCAN_IXR_TXOK_MASK) |
| 791 | xcan_tx_interrupt(ndev, isr); |
| 792 | |
| 793 | /* Check for the type of error interrupt and Processing it */ |
| 794 | if (isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | |
| 795 | XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK)) { |
| 796 | priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_ERROR_MASK | |
| 797 | XCAN_IXR_RXOFLW_MASK | XCAN_IXR_BSOFF_MASK | |
| 798 | XCAN_IXR_ARBLST_MASK)); |
| 799 | xcan_err_interrupt(ndev, isr); |
| 800 | } |
| 801 | |
| 802 | /* Check for the type of receive interrupt and Processing it */ |
| 803 | if (isr & (XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK)) { |
| 804 | ier = priv->read_reg(priv, XCAN_IER_OFFSET); |
| 805 | ier &= ~(XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK); |
| 806 | priv->write_reg(priv, XCAN_IER_OFFSET, ier); |
| 807 | napi_schedule(&priv->napi); |
| 808 | } |
| 809 | return IRQ_HANDLED; |
| 810 | } |
| 811 | |
| 812 | /** |
| 813 | * xcan_chip_stop - Driver stop routine |
| 814 | * @ndev: Pointer to net_device structure |
| 815 | * |
| 816 | * This is the drivers stop routine. It will disable the |
| 817 | * interrupts and put the device into configuration mode. |
| 818 | */ |
| 819 | static void xcan_chip_stop(struct net_device *ndev) |
| 820 | { |
| 821 | struct xcan_priv *priv = netdev_priv(ndev); |
| 822 | u32 ier; |
| 823 | |
| 824 | /* Disable interrupts and leave the can in configuration mode */ |
| 825 | ier = priv->read_reg(priv, XCAN_IER_OFFSET); |
| 826 | ier &= ~XCAN_INTR_ALL; |
| 827 | priv->write_reg(priv, XCAN_IER_OFFSET, ier); |
| 828 | priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); |
| 829 | priv->can.state = CAN_STATE_STOPPED; |
| 830 | } |
| 831 | |
| 832 | /** |
| 833 | * xcan_open - Driver open routine |
| 834 | * @ndev: Pointer to net_device structure |
| 835 | * |
| 836 | * This is the driver open routine. |
| 837 | * Return: 0 on success and failure value on error |
| 838 | */ |
| 839 | static int xcan_open(struct net_device *ndev) |
| 840 | { |
| 841 | struct xcan_priv *priv = netdev_priv(ndev); |
| 842 | int ret; |
| 843 | |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 844 | ret = pm_runtime_get_sync(priv->dev); |
| 845 | if (ret < 0) { |
| 846 | netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", |
| 847 | __func__, ret); |
| 848 | return ret; |
| 849 | } |
| 850 | |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 851 | ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags, |
| 852 | ndev->name, ndev); |
| 853 | if (ret < 0) { |
| 854 | netdev_err(ndev, "irq allocation for CAN failed\n"); |
| 855 | goto err; |
| 856 | } |
| 857 | |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 858 | /* Set chip into reset mode */ |
| 859 | ret = set_reset_mode(ndev); |
| 860 | if (ret < 0) { |
| 861 | netdev_err(ndev, "mode resetting failed!\n"); |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 862 | goto err_irq; |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 863 | } |
| 864 | |
| 865 | /* Common open */ |
| 866 | ret = open_candev(ndev); |
| 867 | if (ret) |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 868 | goto err_irq; |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 869 | |
| 870 | ret = xcan_chip_start(ndev); |
| 871 | if (ret < 0) { |
| 872 | netdev_err(ndev, "xcan_chip_start failed!\n"); |
| 873 | goto err_candev; |
| 874 | } |
| 875 | |
| 876 | can_led_event(ndev, CAN_LED_EVENT_OPEN); |
| 877 | napi_enable(&priv->napi); |
| 878 | netif_start_queue(ndev); |
| 879 | |
| 880 | return 0; |
| 881 | |
| 882 | err_candev: |
| 883 | close_candev(ndev); |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 884 | err_irq: |
| 885 | free_irq(ndev->irq, ndev); |
| 886 | err: |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 887 | pm_runtime_put(priv->dev); |
| 888 | |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 889 | return ret; |
| 890 | } |
| 891 | |
| 892 | /** |
| 893 | * xcan_close - Driver close routine |
| 894 | * @ndev: Pointer to net_device structure |
| 895 | * |
| 896 | * Return: 0 always |
| 897 | */ |
| 898 | static int xcan_close(struct net_device *ndev) |
| 899 | { |
| 900 | struct xcan_priv *priv = netdev_priv(ndev); |
| 901 | |
| 902 | netif_stop_queue(ndev); |
| 903 | napi_disable(&priv->napi); |
| 904 | xcan_chip_stop(ndev); |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 905 | free_irq(ndev->irq, ndev); |
| 906 | close_candev(ndev); |
| 907 | |
| 908 | can_led_event(ndev, CAN_LED_EVENT_STOP); |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 909 | pm_runtime_put(priv->dev); |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 910 | |
| 911 | return 0; |
| 912 | } |
| 913 | |
| 914 | /** |
| 915 | * xcan_get_berr_counter - error counter routine |
| 916 | * @ndev: Pointer to net_device structure |
| 917 | * @bec: Pointer to can_berr_counter structure |
| 918 | * |
| 919 | * This is the driver error counter routine. |
| 920 | * Return: 0 on success and failure value on error |
| 921 | */ |
| 922 | static int xcan_get_berr_counter(const struct net_device *ndev, |
| 923 | struct can_berr_counter *bec) |
| 924 | { |
| 925 | struct xcan_priv *priv = netdev_priv(ndev); |
| 926 | int ret; |
| 927 | |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 928 | ret = pm_runtime_get_sync(priv->dev); |
| 929 | if (ret < 0) { |
| 930 | netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", |
| 931 | __func__, ret); |
| 932 | return ret; |
| 933 | } |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 934 | |
| 935 | bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK; |
| 936 | bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) & |
| 937 | XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT); |
| 938 | |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 939 | pm_runtime_put(priv->dev); |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 940 | |
| 941 | return 0; |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 942 | } |
| 943 | |
| 944 | |
| 945 | static const struct net_device_ops xcan_netdev_ops = { |
| 946 | .ndo_open = xcan_open, |
| 947 | .ndo_stop = xcan_close, |
| 948 | .ndo_start_xmit = xcan_start_xmit, |
Marc Kleine-Budde | 92593a0 | 2014-11-18 13:16:13 +0100 | [diff] [blame] | 949 | .ndo_change_mtu = can_change_mtu, |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 950 | }; |
| 951 | |
| 952 | /** |
| 953 | * xcan_suspend - Suspend method for the driver |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 954 | * @dev: Address of the device structure |
| 955 | * |
| 956 | * Put the driver into low power mode. |
| 957 | * Return: 0 on success and failure value on error |
| 958 | */ |
| 959 | static int __maybe_unused xcan_suspend(struct device *dev) |
| 960 | { |
| 961 | if (!device_may_wakeup(dev)) |
| 962 | return pm_runtime_force_suspend(dev); |
| 963 | |
| 964 | return 0; |
| 965 | } |
| 966 | |
| 967 | /** |
| 968 | * xcan_resume - Resume from suspend |
| 969 | * @dev: Address of the device structure |
| 970 | * |
| 971 | * Resume operation after suspend. |
| 972 | * Return: 0 on success and failure value on error |
| 973 | */ |
| 974 | static int __maybe_unused xcan_resume(struct device *dev) |
| 975 | { |
| 976 | if (!device_may_wakeup(dev)) |
| 977 | return pm_runtime_force_resume(dev); |
| 978 | |
| 979 | return 0; |
| 980 | |
| 981 | } |
| 982 | |
| 983 | /** |
| 984 | * xcan_runtime_suspend - Runtime suspend method for the driver |
| 985 | * @dev: Address of the device structure |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 986 | * |
| 987 | * Put the driver into low power mode. |
| 988 | * Return: 0 always |
| 989 | */ |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 990 | static int __maybe_unused xcan_runtime_suspend(struct device *dev) |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 991 | { |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 992 | struct net_device *ndev = dev_get_drvdata(dev); |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 993 | struct xcan_priv *priv = netdev_priv(ndev); |
| 994 | |
| 995 | if (netif_running(ndev)) { |
| 996 | netif_stop_queue(ndev); |
| 997 | netif_device_detach(ndev); |
| 998 | } |
| 999 | |
| 1000 | priv->write_reg(priv, XCAN_MSR_OFFSET, XCAN_MSR_SLEEP_MASK); |
| 1001 | priv->can.state = CAN_STATE_SLEEPING; |
| 1002 | |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 1003 | clk_disable_unprepare(priv->bus_clk); |
| 1004 | clk_disable_unprepare(priv->can_clk); |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1005 | |
| 1006 | return 0; |
| 1007 | } |
| 1008 | |
| 1009 | /** |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 1010 | * xcan_runtime_resume - Runtime resume from suspend |
| 1011 | * @dev: Address of the device structure |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1012 | * |
| 1013 | * Resume operation after suspend. |
| 1014 | * Return: 0 on success and failure value on error |
| 1015 | */ |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 1016 | static int __maybe_unused xcan_runtime_resume(struct device *dev) |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1017 | { |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 1018 | struct net_device *ndev = dev_get_drvdata(dev); |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1019 | struct xcan_priv *priv = netdev_priv(ndev); |
| 1020 | int ret; |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 1021 | u32 isr, status; |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1022 | |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 1023 | ret = clk_prepare_enable(priv->bus_clk); |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1024 | if (ret) { |
| 1025 | dev_err(dev, "Cannot enable clock.\n"); |
| 1026 | return ret; |
| 1027 | } |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 1028 | ret = clk_prepare_enable(priv->can_clk); |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1029 | if (ret) { |
| 1030 | dev_err(dev, "Cannot enable clock.\n"); |
| 1031 | clk_disable_unprepare(priv->bus_clk); |
| 1032 | return ret; |
| 1033 | } |
| 1034 | |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 1035 | priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); |
| 1036 | isr = priv->read_reg(priv, XCAN_ISR_OFFSET); |
| 1037 | status = priv->read_reg(priv, XCAN_SR_OFFSET); |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1038 | |
| 1039 | if (netif_running(ndev)) { |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 1040 | if (isr & XCAN_IXR_BSOFF_MASK) { |
| 1041 | priv->can.state = CAN_STATE_BUS_OFF; |
| 1042 | priv->write_reg(priv, XCAN_SRR_OFFSET, |
| 1043 | XCAN_SRR_RESET_MASK); |
| 1044 | } else if ((status & XCAN_SR_ESTAT_MASK) == |
| 1045 | XCAN_SR_ESTAT_MASK) { |
| 1046 | priv->can.state = CAN_STATE_ERROR_PASSIVE; |
| 1047 | } else if (status & XCAN_SR_ERRWRN_MASK) { |
| 1048 | priv->can.state = CAN_STATE_ERROR_WARNING; |
| 1049 | } else { |
| 1050 | priv->can.state = CAN_STATE_ERROR_ACTIVE; |
| 1051 | } |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1052 | netif_device_attach(ndev); |
| 1053 | netif_start_queue(ndev); |
| 1054 | } |
| 1055 | |
| 1056 | return 0; |
| 1057 | } |
| 1058 | |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 1059 | static const struct dev_pm_ops xcan_dev_pm_ops = { |
| 1060 | SET_SYSTEM_SLEEP_PM_OPS(xcan_suspend, xcan_resume) |
| 1061 | SET_RUNTIME_PM_OPS(xcan_runtime_suspend, xcan_runtime_resume, NULL) |
| 1062 | }; |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1063 | |
| 1064 | /** |
| 1065 | * xcan_probe - Platform registration call |
| 1066 | * @pdev: Handle to the platform device structure |
| 1067 | * |
| 1068 | * This function does all the memory allocation and registration for the CAN |
| 1069 | * device. |
| 1070 | * |
| 1071 | * Return: 0 on success and failure value on error |
| 1072 | */ |
| 1073 | static int xcan_probe(struct platform_device *pdev) |
| 1074 | { |
| 1075 | struct resource *res; /* IO mem resources */ |
| 1076 | struct net_device *ndev; |
| 1077 | struct xcan_priv *priv; |
| 1078 | void __iomem *addr; |
| 1079 | int ret, rx_max, tx_max; |
| 1080 | |
| 1081 | /* Get the virtual base address for the device */ |
| 1082 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1083 | addr = devm_ioremap_resource(&pdev->dev, res); |
| 1084 | if (IS_ERR(addr)) { |
| 1085 | ret = PTR_ERR(addr); |
| 1086 | goto err; |
| 1087 | } |
| 1088 | |
| 1089 | ret = of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth", &tx_max); |
| 1090 | if (ret < 0) |
| 1091 | goto err; |
| 1092 | |
| 1093 | ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", &rx_max); |
| 1094 | if (ret < 0) |
| 1095 | goto err; |
| 1096 | |
| 1097 | /* Create a CAN device instance */ |
| 1098 | ndev = alloc_candev(sizeof(struct xcan_priv), tx_max); |
| 1099 | if (!ndev) |
| 1100 | return -ENOMEM; |
| 1101 | |
| 1102 | priv = netdev_priv(ndev); |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 1103 | priv->dev = &pdev->dev; |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1104 | priv->can.bittiming_const = &xcan_bittiming_const; |
| 1105 | priv->can.do_set_mode = xcan_do_set_mode; |
| 1106 | priv->can.do_get_berr_counter = xcan_get_berr_counter; |
| 1107 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | |
| 1108 | CAN_CTRLMODE_BERR_REPORTING; |
| 1109 | priv->reg_base = addr; |
| 1110 | priv->tx_max = tx_max; |
| 1111 | |
| 1112 | /* Get IRQ for the device */ |
| 1113 | ndev->irq = platform_get_irq(pdev, 0); |
| 1114 | ndev->flags |= IFF_ECHO; /* We support local echo */ |
| 1115 | |
| 1116 | platform_set_drvdata(pdev, ndev); |
| 1117 | SET_NETDEV_DEV(ndev, &pdev->dev); |
| 1118 | ndev->netdev_ops = &xcan_netdev_ops; |
| 1119 | |
| 1120 | /* Getting the CAN can_clk info */ |
| 1121 | priv->can_clk = devm_clk_get(&pdev->dev, "can_clk"); |
| 1122 | if (IS_ERR(priv->can_clk)) { |
| 1123 | dev_err(&pdev->dev, "Device clock not found.\n"); |
| 1124 | ret = PTR_ERR(priv->can_clk); |
| 1125 | goto err_free; |
| 1126 | } |
| 1127 | /* Check for type of CAN device */ |
| 1128 | if (of_device_is_compatible(pdev->dev.of_node, |
| 1129 | "xlnx,zynq-can-1.0")) { |
| 1130 | priv->bus_clk = devm_clk_get(&pdev->dev, "pclk"); |
| 1131 | if (IS_ERR(priv->bus_clk)) { |
| 1132 | dev_err(&pdev->dev, "bus clock not found\n"); |
| 1133 | ret = PTR_ERR(priv->bus_clk); |
| 1134 | goto err_free; |
| 1135 | } |
| 1136 | } else { |
| 1137 | priv->bus_clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); |
| 1138 | if (IS_ERR(priv->bus_clk)) { |
| 1139 | dev_err(&pdev->dev, "bus clock not found\n"); |
| 1140 | ret = PTR_ERR(priv->bus_clk); |
| 1141 | goto err_free; |
| 1142 | } |
| 1143 | } |
| 1144 | |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1145 | priv->write_reg = xcan_write_reg_le; |
| 1146 | priv->read_reg = xcan_read_reg_le; |
| 1147 | |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 1148 | pm_runtime_enable(&pdev->dev); |
| 1149 | ret = pm_runtime_get_sync(&pdev->dev); |
| 1150 | if (ret < 0) { |
| 1151 | netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", |
| 1152 | __func__, ret); |
| 1153 | goto err_pmdisable; |
| 1154 | } |
| 1155 | |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1156 | if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) { |
| 1157 | priv->write_reg = xcan_write_reg_be; |
| 1158 | priv->read_reg = xcan_read_reg_be; |
| 1159 | } |
| 1160 | |
| 1161 | priv->can.clock.freq = clk_get_rate(priv->can_clk); |
| 1162 | |
| 1163 | netif_napi_add(ndev, &priv->napi, xcan_rx_poll, rx_max); |
| 1164 | |
| 1165 | ret = register_candev(ndev); |
| 1166 | if (ret) { |
| 1167 | dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret); |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 1168 | goto err_disableclks; |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1169 | } |
| 1170 | |
| 1171 | devm_can_led_init(ndev); |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 1172 | |
| 1173 | pm_runtime_put(&pdev->dev); |
| 1174 | |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1175 | netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx fifo depth:%d\n", |
| 1176 | priv->reg_base, ndev->irq, priv->can.clock.freq, |
| 1177 | priv->tx_max); |
| 1178 | |
| 1179 | return 0; |
| 1180 | |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 1181 | err_disableclks: |
| 1182 | pm_runtime_put(priv->dev); |
| 1183 | err_pmdisable: |
| 1184 | pm_runtime_disable(&pdev->dev); |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1185 | err_free: |
| 1186 | free_candev(ndev); |
| 1187 | err: |
| 1188 | return ret; |
| 1189 | } |
| 1190 | |
| 1191 | /** |
| 1192 | * xcan_remove - Unregister the device after releasing the resources |
| 1193 | * @pdev: Handle to the platform device structure |
| 1194 | * |
| 1195 | * This function frees all the resources allocated to the device. |
| 1196 | * Return: 0 always |
| 1197 | */ |
| 1198 | static int xcan_remove(struct platform_device *pdev) |
| 1199 | { |
| 1200 | struct net_device *ndev = platform_get_drvdata(pdev); |
| 1201 | struct xcan_priv *priv = netdev_priv(ndev); |
| 1202 | |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1203 | unregister_candev(ndev); |
Kedareswara rao Appana | 4716620 | 2015-10-26 11:41:54 +0530 | [diff] [blame] | 1204 | pm_runtime_disable(&pdev->dev); |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1205 | netif_napi_del(&priv->napi); |
| 1206 | free_candev(ndev); |
| 1207 | |
| 1208 | return 0; |
| 1209 | } |
| 1210 | |
| 1211 | /* Match table for OF platform binding */ |
Fabian Frederick | 486e957 | 2015-03-17 19:40:24 +0100 | [diff] [blame] | 1212 | static const struct of_device_id xcan_of_match[] = { |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1213 | { .compatible = "xlnx,zynq-can-1.0", }, |
| 1214 | { .compatible = "xlnx,axi-can-1.00.a", }, |
| 1215 | { /* end of list */ }, |
| 1216 | }; |
| 1217 | MODULE_DEVICE_TABLE(of, xcan_of_match); |
| 1218 | |
| 1219 | static struct platform_driver xcan_driver = { |
| 1220 | .probe = xcan_probe, |
| 1221 | .remove = xcan_remove, |
| 1222 | .driver = { |
Kedareswara rao Appana | b1201e44 | 2014-05-21 12:30:59 +0530 | [diff] [blame] | 1223 | .name = DRIVER_NAME, |
| 1224 | .pm = &xcan_dev_pm_ops, |
| 1225 | .of_match_table = xcan_of_match, |
| 1226 | }, |
| 1227 | }; |
| 1228 | |
| 1229 | module_platform_driver(xcan_driver); |
| 1230 | |
| 1231 | MODULE_LICENSE("GPL"); |
| 1232 | MODULE_AUTHOR("Xilinx Inc"); |
| 1233 | MODULE_DESCRIPTION("Xilinx CAN interface"); |