Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * Driver for AMBA serial ports |
| 3 | * |
| 4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. |
| 5 | * |
| 6 | * Copyright 1999 ARM Limited |
| 7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 8 | * Copyright (C) 2010 ST-Ericsson SA |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 23 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | * This is a generic driver for ARM AMBA-type serial ports. They |
| 25 | * have a lot of 16550-like features, but are not register compatible. |
| 26 | * Note that although they do have CTS, DCD and DSR inputs, they do |
| 27 | * not have an RI input, nor do they have DTR or RTS outputs. If |
| 28 | * required, these have to be supplied via some other means (eg, GPIO) |
| 29 | * and hooked into this driver. |
| 30 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 32 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
| 34 | #define SUPPORT_SYSRQ |
| 35 | #endif |
| 36 | |
| 37 | #include <linux/module.h> |
| 38 | #include <linux/ioport.h> |
| 39 | #include <linux/init.h> |
| 40 | #include <linux/console.h> |
| 41 | #include <linux/sysrq.h> |
| 42 | #include <linux/device.h> |
| 43 | #include <linux/tty.h> |
| 44 | #include <linux/tty_flip.h> |
| 45 | #include <linux/serial_core.h> |
| 46 | #include <linux/serial.h> |
Russell King | a62c80e | 2006-01-07 13:52:45 +0000 | [diff] [blame] | 47 | #include <linux/amba/bus.h> |
| 48 | #include <linux/amba/serial.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 49 | #include <linux/clk.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 50 | #include <linux/slab.h> |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 51 | #include <linux/dmaengine.h> |
| 52 | #include <linux/dma-mapping.h> |
| 53 | #include <linux/scatterlist.h> |
Shreshtha Kumar Sahu | c16d51a | 2011-06-13 10:11:33 +0200 | [diff] [blame] | 54 | #include <linux/delay.h> |
Viresh Kumar | 258aea7 | 2012-02-01 16:12:19 +0530 | [diff] [blame] | 55 | #include <linux/types.h> |
Matthew Leach | 32614aa | 2012-08-28 16:41:28 +0100 | [diff] [blame] | 56 | #include <linux/of.h> |
| 57 | #include <linux/of_device.h> |
Shawn Guo | 258e055 | 2012-05-06 22:53:35 +0800 | [diff] [blame] | 58 | #include <linux/pinctrl/consumer.h> |
Alessandro Rubini | cb70706 | 2012-06-24 12:46:37 +0100 | [diff] [blame] | 59 | #include <linux/sizes.h> |
Linus Walleij | de60958 | 2012-10-15 13:36:01 +0200 | [diff] [blame] | 60 | #include <linux/io.h> |
Graeme Gregory | 3db9ab0 | 2015-05-21 17:26:24 +0100 | [diff] [blame] | 61 | #include <linux/acpi.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 63 | #include "amba-pl011.h" |
| 64 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 65 | #define UART_NR 14 |
| 66 | |
| 67 | #define SERIAL_AMBA_MAJOR 204 |
| 68 | #define SERIAL_AMBA_MINOR 64 |
| 69 | #define SERIAL_AMBA_NR UART_NR |
| 70 | |
| 71 | #define AMBA_ISR_PASS_LIMIT 256 |
| 72 | |
Russell King | b63d4f0 | 2005-11-19 11:10:35 +0000 | [diff] [blame] | 73 | #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) |
| 74 | #define UART_DUMMY_DR_RX (1 << 16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | |
Russell King | debb7f6 | 2015-11-16 17:40:26 +0000 | [diff] [blame] | 76 | static u16 pl011_std_offsets[REG_ARRAY_SIZE] = { |
| 77 | [REG_DR] = UART01x_DR, |
Russell King | debb7f6 | 2015-11-16 17:40:26 +0000 | [diff] [blame] | 78 | [REG_FR] = UART01x_FR, |
Russell King | e4df9a8 | 2015-11-16 17:40:41 +0000 | [diff] [blame] | 79 | [REG_LCRH_RX] = UART011_LCRH, |
| 80 | [REG_LCRH_TX] = UART011_LCRH, |
Russell King | debb7f6 | 2015-11-16 17:40:26 +0000 | [diff] [blame] | 81 | [REG_IBRD] = UART011_IBRD, |
| 82 | [REG_FBRD] = UART011_FBRD, |
Russell King | debb7f6 | 2015-11-16 17:40:26 +0000 | [diff] [blame] | 83 | [REG_CR] = UART011_CR, |
| 84 | [REG_IFLS] = UART011_IFLS, |
| 85 | [REG_IMSC] = UART011_IMSC, |
| 86 | [REG_RIS] = UART011_RIS, |
| 87 | [REG_MIS] = UART011_MIS, |
| 88 | [REG_ICR] = UART011_ICR, |
| 89 | [REG_DMACR] = UART011_DMACR, |
Russell King | debb7f6 | 2015-11-16 17:40:26 +0000 | [diff] [blame] | 90 | }; |
| 91 | |
Alessandro Rubini | 5926a29 | 2009-06-04 17:43:04 +0100 | [diff] [blame] | 92 | /* There is by now at least one vendor with differing details, so handle it */ |
| 93 | struct vendor_data { |
Russell King | 439403b | 2015-11-16 17:40:31 +0000 | [diff] [blame] | 94 | const u16 *reg_offset; |
Alessandro Rubini | 5926a29 | 2009-06-04 17:43:04 +0100 | [diff] [blame] | 95 | unsigned int ifls; |
Russell King | 84c3e03 | 2015-11-16 17:40:52 +0000 | [diff] [blame] | 96 | bool access_32b; |
Linus Walleij | ac3e3fb | 2010-06-02 20:40:22 +0100 | [diff] [blame] | 97 | bool oversampling; |
Russell King | 38d6243 | 2010-12-22 17:59:16 +0000 | [diff] [blame] | 98 | bool dma_threshold; |
Rajanikanth H.V | 4fd0690 | 2012-03-26 11:17:02 +0200 | [diff] [blame] | 99 | bool cts_event_workaround; |
Andre Przywara | 71eec48 | 2015-05-21 17:26:21 +0100 | [diff] [blame] | 100 | bool always_enabled; |
Andre Przywara | cefc2d1 | 2015-05-21 17:26:22 +0100 | [diff] [blame] | 101 | bool fixed_options; |
Jongsung Kim | 78506f2 | 2013-04-15 14:45:25 +0900 | [diff] [blame] | 102 | |
Jongsung Kim | ea33640 | 2013-05-10 18:05:35 +0900 | [diff] [blame] | 103 | unsigned int (*get_fifosize)(struct amba_device *dev); |
Alessandro Rubini | 5926a29 | 2009-06-04 17:43:04 +0100 | [diff] [blame] | 104 | }; |
| 105 | |
Jongsung Kim | ea33640 | 2013-05-10 18:05:35 +0900 | [diff] [blame] | 106 | static unsigned int get_fifosize_arm(struct amba_device *dev) |
Jongsung Kim | 78506f2 | 2013-04-15 14:45:25 +0900 | [diff] [blame] | 107 | { |
Jongsung Kim | ea33640 | 2013-05-10 18:05:35 +0900 | [diff] [blame] | 108 | return amba_rev(dev) < 3 ? 16 : 32; |
Jongsung Kim | 78506f2 | 2013-04-15 14:45:25 +0900 | [diff] [blame] | 109 | } |
| 110 | |
Alessandro Rubini | 5926a29 | 2009-06-04 17:43:04 +0100 | [diff] [blame] | 111 | static struct vendor_data vendor_arm = { |
Russell King | 439403b | 2015-11-16 17:40:31 +0000 | [diff] [blame] | 112 | .reg_offset = pl011_std_offsets, |
Alessandro Rubini | 5926a29 | 2009-06-04 17:43:04 +0100 | [diff] [blame] | 113 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, |
Linus Walleij | ac3e3fb | 2010-06-02 20:40:22 +0100 | [diff] [blame] | 114 | .oversampling = false, |
Russell King | 38d6243 | 2010-12-22 17:59:16 +0000 | [diff] [blame] | 115 | .dma_threshold = false, |
Rajanikanth H.V | 4fd0690 | 2012-03-26 11:17:02 +0200 | [diff] [blame] | 116 | .cts_event_workaround = false, |
Andre Przywara | 71eec48 | 2015-05-21 17:26:21 +0100 | [diff] [blame] | 117 | .always_enabled = false, |
Andre Przywara | cefc2d1 | 2015-05-21 17:26:22 +0100 | [diff] [blame] | 118 | .fixed_options = false, |
Jongsung Kim | 78506f2 | 2013-04-15 14:45:25 +0900 | [diff] [blame] | 119 | .get_fifosize = get_fifosize_arm, |
Alessandro Rubini | 5926a29 | 2009-06-04 17:43:04 +0100 | [diff] [blame] | 120 | }; |
| 121 | |
Andre Przywara | 0dd1e24 | 2015-05-21 17:26:23 +0100 | [diff] [blame] | 122 | static struct vendor_data vendor_sbsa = { |
Russell King | 439403b | 2015-11-16 17:40:31 +0000 | [diff] [blame] | 123 | .reg_offset = pl011_std_offsets, |
Christopher Covington | 1aabf52 | 2016-04-01 17:23:58 -0400 | [diff] [blame] | 124 | .access_32b = true, |
Andre Przywara | 0dd1e24 | 2015-05-21 17:26:23 +0100 | [diff] [blame] | 125 | .oversampling = false, |
| 126 | .dma_threshold = false, |
| 127 | .cts_event_workaround = false, |
| 128 | .always_enabled = true, |
| 129 | .fixed_options = true, |
| 130 | }; |
| 131 | |
Russell King | bf69ff8 | 2015-11-16 17:40:36 +0000 | [diff] [blame] | 132 | static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { |
| 133 | [REG_DR] = UART01x_DR, |
| 134 | [REG_ST_DMAWM] = ST_UART011_DMAWM, |
| 135 | [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, |
| 136 | [REG_FR] = UART01x_FR, |
Russell King | e4df9a8 | 2015-11-16 17:40:41 +0000 | [diff] [blame] | 137 | [REG_LCRH_RX] = ST_UART011_LCRH_RX, |
| 138 | [REG_LCRH_TX] = ST_UART011_LCRH_TX, |
Russell King | bf69ff8 | 2015-11-16 17:40:36 +0000 | [diff] [blame] | 139 | [REG_IBRD] = UART011_IBRD, |
| 140 | [REG_FBRD] = UART011_FBRD, |
Russell King | bf69ff8 | 2015-11-16 17:40:36 +0000 | [diff] [blame] | 141 | [REG_CR] = UART011_CR, |
| 142 | [REG_IFLS] = UART011_IFLS, |
| 143 | [REG_IMSC] = UART011_IMSC, |
| 144 | [REG_RIS] = UART011_RIS, |
| 145 | [REG_MIS] = UART011_MIS, |
| 146 | [REG_ICR] = UART011_ICR, |
| 147 | [REG_DMACR] = UART011_DMACR, |
| 148 | [REG_ST_XFCR] = ST_UART011_XFCR, |
| 149 | [REG_ST_XON1] = ST_UART011_XON1, |
| 150 | [REG_ST_XON2] = ST_UART011_XON2, |
| 151 | [REG_ST_XOFF1] = ST_UART011_XOFF1, |
| 152 | [REG_ST_XOFF2] = ST_UART011_XOFF2, |
| 153 | [REG_ST_ITCR] = ST_UART011_ITCR, |
| 154 | [REG_ST_ITIP] = ST_UART011_ITIP, |
| 155 | [REG_ST_ABCR] = ST_UART011_ABCR, |
| 156 | [REG_ST_ABIMSC] = ST_UART011_ABIMSC, |
| 157 | }; |
| 158 | |
Jongsung Kim | ea33640 | 2013-05-10 18:05:35 +0900 | [diff] [blame] | 159 | static unsigned int get_fifosize_st(struct amba_device *dev) |
Jongsung Kim | 78506f2 | 2013-04-15 14:45:25 +0900 | [diff] [blame] | 160 | { |
| 161 | return 64; |
| 162 | } |
| 163 | |
Alessandro Rubini | 5926a29 | 2009-06-04 17:43:04 +0100 | [diff] [blame] | 164 | static struct vendor_data vendor_st = { |
Russell King | bf69ff8 | 2015-11-16 17:40:36 +0000 | [diff] [blame] | 165 | .reg_offset = pl011_st_offsets, |
Alessandro Rubini | 5926a29 | 2009-06-04 17:43:04 +0100 | [diff] [blame] | 166 | .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, |
Linus Walleij | ac3e3fb | 2010-06-02 20:40:22 +0100 | [diff] [blame] | 167 | .oversampling = true, |
Russell King | 38d6243 | 2010-12-22 17:59:16 +0000 | [diff] [blame] | 168 | .dma_threshold = true, |
Rajanikanth H.V | 4fd0690 | 2012-03-26 11:17:02 +0200 | [diff] [blame] | 169 | .cts_event_workaround = true, |
Andre Przywara | 71eec48 | 2015-05-21 17:26:21 +0100 | [diff] [blame] | 170 | .always_enabled = false, |
Andre Przywara | cefc2d1 | 2015-05-21 17:26:22 +0100 | [diff] [blame] | 171 | .fixed_options = false, |
Jongsung Kim | 78506f2 | 2013-04-15 14:45:25 +0900 | [diff] [blame] | 172 | .get_fifosize = get_fifosize_st, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 173 | }; |
| 174 | |
Russell King | 7ec7587 | 2015-11-16 17:40:57 +0000 | [diff] [blame] | 175 | static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = { |
| 176 | [REG_DR] = ZX_UART011_DR, |
| 177 | [REG_FR] = ZX_UART011_FR, |
| 178 | [REG_LCRH_RX] = ZX_UART011_LCRH, |
| 179 | [REG_LCRH_TX] = ZX_UART011_LCRH, |
| 180 | [REG_IBRD] = ZX_UART011_IBRD, |
| 181 | [REG_FBRD] = ZX_UART011_FBRD, |
| 182 | [REG_CR] = ZX_UART011_CR, |
| 183 | [REG_IFLS] = ZX_UART011_IFLS, |
| 184 | [REG_IMSC] = ZX_UART011_IMSC, |
| 185 | [REG_RIS] = ZX_UART011_RIS, |
| 186 | [REG_MIS] = ZX_UART011_MIS, |
| 187 | [REG_ICR] = ZX_UART011_ICR, |
| 188 | [REG_DMACR] = ZX_UART011_DMACR, |
| 189 | }; |
| 190 | |
Arnd Bergmann | ff52a9a | 2016-01-20 11:40:03 +0100 | [diff] [blame] | 191 | static struct vendor_data vendor_zte __maybe_unused = { |
Russell King | 7ec7587 | 2015-11-16 17:40:57 +0000 | [diff] [blame] | 192 | .reg_offset = pl011_zte_offsets, |
| 193 | .access_32b = true, |
| 194 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, |
| 195 | .get_fifosize = get_fifosize_arm, |
| 196 | }; |
| 197 | |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 198 | /* Deals with DMA transactions */ |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 199 | |
| 200 | struct pl011_sgbuf { |
| 201 | struct scatterlist sg; |
| 202 | char *buf; |
| 203 | }; |
| 204 | |
| 205 | struct pl011_dmarx_data { |
| 206 | struct dma_chan *chan; |
| 207 | struct completion complete; |
| 208 | bool use_buf_b; |
| 209 | struct pl011_sgbuf sgbuf_a; |
| 210 | struct pl011_sgbuf sgbuf_b; |
| 211 | dma_cookie_t cookie; |
| 212 | bool running; |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 213 | struct timer_list timer; |
| 214 | unsigned int last_residue; |
| 215 | unsigned long last_jiffies; |
| 216 | bool auto_poll_rate; |
| 217 | unsigned int poll_rate; |
| 218 | unsigned int poll_timeout; |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 219 | }; |
| 220 | |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 221 | struct pl011_dmatx_data { |
| 222 | struct dma_chan *chan; |
| 223 | struct scatterlist sg; |
| 224 | char *buf; |
| 225 | bool queued; |
| 226 | }; |
| 227 | |
Russell King | c19f12b | 2010-12-22 17:48:26 +0000 | [diff] [blame] | 228 | /* |
| 229 | * We wrap our port structure around the generic uart_port. |
| 230 | */ |
| 231 | struct uart_amba_port { |
| 232 | struct uart_port port; |
Russell King | debb7f6 | 2015-11-16 17:40:26 +0000 | [diff] [blame] | 233 | const u16 *reg_offset; |
Russell King | c19f12b | 2010-12-22 17:48:26 +0000 | [diff] [blame] | 234 | struct clk *clk; |
| 235 | const struct vendor_data *vendor; |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 236 | unsigned int dmacr; /* dma control reg */ |
Russell King | c19f12b | 2010-12-22 17:48:26 +0000 | [diff] [blame] | 237 | unsigned int im; /* interrupt mask */ |
| 238 | unsigned int old_status; |
Russell King | ffca2b1 | 2010-12-22 17:13:05 +0000 | [diff] [blame] | 239 | unsigned int fifosize; /* vendor-specific */ |
Shreshtha Kumar Sahu | d8d8ffa | 2012-01-18 15:53:59 +0530 | [diff] [blame] | 240 | unsigned int old_cr; /* state during shutdown */ |
Russell King | c19f12b | 2010-12-22 17:48:26 +0000 | [diff] [blame] | 241 | bool autorts; |
Andre Przywara | cefc2d1 | 2015-05-21 17:26:22 +0100 | [diff] [blame] | 242 | unsigned int fixed_baud; /* vendor-set fixed baud rate */ |
Russell King | c19f12b | 2010-12-22 17:48:26 +0000 | [diff] [blame] | 243 | char type[12]; |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 244 | #ifdef CONFIG_DMA_ENGINE |
| 245 | /* DMA stuff */ |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 246 | bool using_tx_dma; |
| 247 | bool using_rx_dma; |
| 248 | struct pl011_dmarx_data dmarx; |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 249 | struct pl011_dmatx_data dmatx; |
Jorge Ramirez-Ortiz | 1c9be31 | 2015-03-06 13:05:40 -0500 | [diff] [blame] | 250 | bool dma_probed; |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 251 | #endif |
Russell King | c19f12b | 2010-12-22 17:48:26 +0000 | [diff] [blame] | 252 | }; |
| 253 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 254 | static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, |
| 255 | unsigned int reg) |
| 256 | { |
Russell King | debb7f6 | 2015-11-16 17:40:26 +0000 | [diff] [blame] | 257 | return uap->reg_offset[reg]; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 258 | } |
| 259 | |
Russell King | b2a4e24 | 2015-11-03 14:51:03 +0000 | [diff] [blame] | 260 | static unsigned int pl011_read(const struct uart_amba_port *uap, |
| 261 | unsigned int reg) |
Russell King | 7583633 | 2015-11-03 14:50:58 +0000 | [diff] [blame] | 262 | { |
Russell King | 84c3e03 | 2015-11-16 17:40:52 +0000 | [diff] [blame] | 263 | void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); |
| 264 | |
Timur Tabi | 3b78fae | 2016-01-04 15:37:42 -0600 | [diff] [blame] | 265 | return (uap->port.iotype == UPIO_MEM32) ? |
| 266 | readl_relaxed(addr) : readw_relaxed(addr); |
Russell King | 7583633 | 2015-11-03 14:50:58 +0000 | [diff] [blame] | 267 | } |
| 268 | |
Russell King | b2a4e24 | 2015-11-03 14:51:03 +0000 | [diff] [blame] | 269 | static void pl011_write(unsigned int val, const struct uart_amba_port *uap, |
| 270 | unsigned int reg) |
Russell King | 7583633 | 2015-11-03 14:50:58 +0000 | [diff] [blame] | 271 | { |
Russell King | 84c3e03 | 2015-11-16 17:40:52 +0000 | [diff] [blame] | 272 | void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); |
| 273 | |
Timur Tabi | 3b78fae | 2016-01-04 15:37:42 -0600 | [diff] [blame] | 274 | if (uap->port.iotype == UPIO_MEM32) |
Russell King | f5ce6ed | 2015-11-16 17:41:02 +0000 | [diff] [blame] | 275 | writel_relaxed(val, addr); |
Russell King | 84c3e03 | 2015-11-16 17:40:52 +0000 | [diff] [blame] | 276 | else |
Russell King | f5ce6ed | 2015-11-16 17:41:02 +0000 | [diff] [blame] | 277 | writew_relaxed(val, addr); |
Russell King | 7583633 | 2015-11-03 14:50:58 +0000 | [diff] [blame] | 278 | } |
| 279 | |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 280 | /* |
Linus Walleij | 29772c4 | 2011-02-24 13:21:36 +0100 | [diff] [blame] | 281 | * Reads up to 256 characters from the FIFO or until it's empty and |
| 282 | * inserts them into the TTY layer. Returns the number of characters |
| 283 | * read from the FIFO. |
| 284 | */ |
| 285 | static int pl011_fifo_to_tty(struct uart_amba_port *uap) |
| 286 | { |
Timur Tabi | 71a5cd8 | 2015-10-07 15:27:16 -0500 | [diff] [blame] | 287 | u16 status; |
| 288 | unsigned int ch, flag, max_count = 256; |
Linus Walleij | 29772c4 | 2011-02-24 13:21:36 +0100 | [diff] [blame] | 289 | int fifotaken = 0; |
| 290 | |
| 291 | while (max_count--) { |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 292 | status = pl011_read(uap, REG_FR); |
Linus Walleij | 29772c4 | 2011-02-24 13:21:36 +0100 | [diff] [blame] | 293 | if (status & UART01x_FR_RXFE) |
| 294 | break; |
| 295 | |
| 296 | /* Take chars from the FIFO and update status */ |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 297 | ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; |
Linus Walleij | 29772c4 | 2011-02-24 13:21:36 +0100 | [diff] [blame] | 298 | flag = TTY_NORMAL; |
| 299 | uap->port.icount.rx++; |
| 300 | fifotaken++; |
| 301 | |
| 302 | if (unlikely(ch & UART_DR_ERROR)) { |
| 303 | if (ch & UART011_DR_BE) { |
| 304 | ch &= ~(UART011_DR_FE | UART011_DR_PE); |
| 305 | uap->port.icount.brk++; |
| 306 | if (uart_handle_break(&uap->port)) |
| 307 | continue; |
| 308 | } else if (ch & UART011_DR_PE) |
| 309 | uap->port.icount.parity++; |
| 310 | else if (ch & UART011_DR_FE) |
| 311 | uap->port.icount.frame++; |
| 312 | if (ch & UART011_DR_OE) |
| 313 | uap->port.icount.overrun++; |
| 314 | |
| 315 | ch &= uap->port.read_status_mask; |
| 316 | |
| 317 | if (ch & UART011_DR_BE) |
| 318 | flag = TTY_BREAK; |
| 319 | else if (ch & UART011_DR_PE) |
| 320 | flag = TTY_PARITY; |
| 321 | else if (ch & UART011_DR_FE) |
| 322 | flag = TTY_FRAME; |
| 323 | } |
| 324 | |
| 325 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) |
| 326 | continue; |
| 327 | |
| 328 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); |
| 329 | } |
| 330 | |
| 331 | return fifotaken; |
| 332 | } |
| 333 | |
| 334 | |
| 335 | /* |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 336 | * All the DMA operation mode stuff goes inside this ifdef. |
| 337 | * This assumes that you have a generic DMA device interface, |
| 338 | * no custom DMA interfaces are supported. |
| 339 | */ |
| 340 | #ifdef CONFIG_DMA_ENGINE |
| 341 | |
| 342 | #define PL011_DMA_BUFFER_SIZE PAGE_SIZE |
| 343 | |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 344 | static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, |
| 345 | enum dma_data_direction dir) |
| 346 | { |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 347 | dma_addr_t dma_addr; |
| 348 | |
| 349 | sg->buf = dma_alloc_coherent(chan->device->dev, |
| 350 | PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 351 | if (!sg->buf) |
| 352 | return -ENOMEM; |
| 353 | |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 354 | sg_init_table(&sg->sg, 1); |
| 355 | sg_set_page(&sg->sg, phys_to_page(dma_addr), |
| 356 | PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); |
| 357 | sg_dma_address(&sg->sg) = dma_addr; |
Andrew Jackson | c64be92 | 2014-11-07 14:14:43 +0000 | [diff] [blame] | 358 | sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 359 | |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 360 | return 0; |
| 361 | } |
| 362 | |
| 363 | static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, |
| 364 | enum dma_data_direction dir) |
| 365 | { |
| 366 | if (sg->buf) { |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 367 | dma_free_coherent(chan->device->dev, |
| 368 | PL011_DMA_BUFFER_SIZE, sg->buf, |
| 369 | sg_dma_address(&sg->sg)); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 370 | } |
| 371 | } |
| 372 | |
Jorge Ramirez-Ortiz | 1c9be31 | 2015-03-06 13:05:40 -0500 | [diff] [blame] | 373 | static void pl011_dma_probe(struct uart_amba_port *uap) |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 374 | { |
| 375 | /* DMA is the sole user of the platform data right now */ |
Jingoo Han | 574de55 | 2013-07-30 17:06:57 +0900 | [diff] [blame] | 376 | struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); |
Jorge Ramirez-Ortiz | 1c9be31 | 2015-03-06 13:05:40 -0500 | [diff] [blame] | 377 | struct device *dev = uap->port.dev; |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 378 | struct dma_slave_config tx_conf = { |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 379 | .dst_addr = uap->port.mapbase + |
| 380 | pl011_reg_to_offset(uap, REG_DR), |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 381 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, |
Vinod Koul | a485df4 | 2011-10-14 10:47:38 +0530 | [diff] [blame] | 382 | .direction = DMA_MEM_TO_DEV, |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 383 | .dst_maxburst = uap->fifosize >> 1, |
Viresh Kumar | 258aea7 | 2012-02-01 16:12:19 +0530 | [diff] [blame] | 384 | .device_fc = false, |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 385 | }; |
| 386 | struct dma_chan *chan; |
| 387 | dma_cap_mask_t mask; |
| 388 | |
Jorge Ramirez-Ortiz | 1c9be31 | 2015-03-06 13:05:40 -0500 | [diff] [blame] | 389 | uap->dma_probed = true; |
| 390 | chan = dma_request_slave_channel_reason(dev, "tx"); |
| 391 | if (IS_ERR(chan)) { |
| 392 | if (PTR_ERR(chan) == -EPROBE_DEFER) { |
Jorge Ramirez-Ortiz | 1c9be31 | 2015-03-06 13:05:40 -0500 | [diff] [blame] | 393 | uap->dma_probed = false; |
| 394 | return; |
| 395 | } |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 396 | |
Arnd Bergmann | 787b0c1 | 2013-01-28 16:24:37 +0000 | [diff] [blame] | 397 | /* We need platform data */ |
| 398 | if (!plat || !plat->dma_filter) { |
| 399 | dev_info(uap->port.dev, "no DMA platform data\n"); |
| 400 | return; |
| 401 | } |
| 402 | |
| 403 | /* Try to acquire a generic DMA engine slave TX channel */ |
| 404 | dma_cap_zero(mask); |
| 405 | dma_cap_set(DMA_SLAVE, mask); |
| 406 | |
| 407 | chan = dma_request_channel(mask, plat->dma_filter, |
| 408 | plat->dma_tx_param); |
| 409 | if (!chan) { |
| 410 | dev_err(uap->port.dev, "no TX DMA channel!\n"); |
| 411 | return; |
| 412 | } |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 413 | } |
| 414 | |
| 415 | dmaengine_slave_config(chan, &tx_conf); |
| 416 | uap->dmatx.chan = chan; |
| 417 | |
| 418 | dev_info(uap->port.dev, "DMA channel TX %s\n", |
| 419 | dma_chan_name(uap->dmatx.chan)); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 420 | |
| 421 | /* Optionally make use of an RX channel as well */ |
Arnd Bergmann | 787b0c1 | 2013-01-28 16:24:37 +0000 | [diff] [blame] | 422 | chan = dma_request_slave_channel(dev, "rx"); |
Rob Herring | 0d3c673 | 2014-04-18 17:19:57 -0500 | [diff] [blame] | 423 | |
Robin Murphy | d9e105c | 2016-03-03 16:35:35 +0000 | [diff] [blame] | 424 | if (!chan && plat && plat->dma_rx_param) { |
Arnd Bergmann | 787b0c1 | 2013-01-28 16:24:37 +0000 | [diff] [blame] | 425 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); |
| 426 | |
| 427 | if (!chan) { |
| 428 | dev_err(uap->port.dev, "no RX DMA channel!\n"); |
| 429 | return; |
| 430 | } |
| 431 | } |
| 432 | |
| 433 | if (chan) { |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 434 | struct dma_slave_config rx_conf = { |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 435 | .src_addr = uap->port.mapbase + |
| 436 | pl011_reg_to_offset(uap, REG_DR), |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 437 | .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, |
Vinod Koul | a485df4 | 2011-10-14 10:47:38 +0530 | [diff] [blame] | 438 | .direction = DMA_DEV_TO_MEM, |
Guennadi Liakhovetski | b2aeb77 | 2014-04-12 19:47:17 +0200 | [diff] [blame] | 439 | .src_maxburst = uap->fifosize >> 2, |
Viresh Kumar | 258aea7 | 2012-02-01 16:12:19 +0530 | [diff] [blame] | 440 | .device_fc = false, |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 441 | }; |
Andrew Jackson | 2d3b7d6 | 2014-11-07 14:14:47 +0000 | [diff] [blame] | 442 | struct dma_slave_caps caps; |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 443 | |
Andrew Jackson | 2d3b7d6 | 2014-11-07 14:14:47 +0000 | [diff] [blame] | 444 | /* |
| 445 | * Some DMA controllers provide information on their capabilities. |
| 446 | * If the controller does, check for suitable residue processing |
| 447 | * otherwise assime all is well. |
| 448 | */ |
| 449 | if (0 == dma_get_slave_caps(chan, &caps)) { |
| 450 | if (caps.residue_granularity == |
| 451 | DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { |
| 452 | dma_release_channel(chan); |
| 453 | dev_info(uap->port.dev, |
| 454 | "RX DMA disabled - no residue processing\n"); |
| 455 | return; |
| 456 | } |
| 457 | } |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 458 | dmaengine_slave_config(chan, &rx_conf); |
| 459 | uap->dmarx.chan = chan; |
| 460 | |
Andrew Jackson | 98267d3 | 2014-11-07 14:14:23 +0000 | [diff] [blame] | 461 | uap->dmarx.auto_poll_rate = false; |
Greg Kroah-Hartman | 8f898bf | 2013-12-17 09:33:18 -0800 | [diff] [blame] | 462 | if (plat && plat->dma_rx_poll_enable) { |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 463 | /* Set poll rate if specified. */ |
| 464 | if (plat->dma_rx_poll_rate) { |
| 465 | uap->dmarx.auto_poll_rate = false; |
| 466 | uap->dmarx.poll_rate = plat->dma_rx_poll_rate; |
| 467 | } else { |
| 468 | /* |
| 469 | * 100 ms defaults to poll rate if not |
| 470 | * specified. This will be adjusted with |
| 471 | * the baud rate at set_termios. |
| 472 | */ |
| 473 | uap->dmarx.auto_poll_rate = true; |
| 474 | uap->dmarx.poll_rate = 100; |
| 475 | } |
| 476 | /* 3 secs defaults poll_timeout if not specified. */ |
| 477 | if (plat->dma_rx_poll_timeout) |
| 478 | uap->dmarx.poll_timeout = |
| 479 | plat->dma_rx_poll_timeout; |
| 480 | else |
| 481 | uap->dmarx.poll_timeout = 3000; |
Andrew Jackson | 98267d3 | 2014-11-07 14:14:23 +0000 | [diff] [blame] | 482 | } else if (!plat && dev->of_node) { |
| 483 | uap->dmarx.auto_poll_rate = of_property_read_bool( |
| 484 | dev->of_node, "auto-poll"); |
| 485 | if (uap->dmarx.auto_poll_rate) { |
| 486 | u32 x; |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 487 | |
Andrew Jackson | 98267d3 | 2014-11-07 14:14:23 +0000 | [diff] [blame] | 488 | if (0 == of_property_read_u32(dev->of_node, |
| 489 | "poll-rate-ms", &x)) |
| 490 | uap->dmarx.poll_rate = x; |
| 491 | else |
| 492 | uap->dmarx.poll_rate = 100; |
| 493 | if (0 == of_property_read_u32(dev->of_node, |
| 494 | "poll-timeout-ms", &x)) |
| 495 | uap->dmarx.poll_timeout = x; |
| 496 | else |
| 497 | uap->dmarx.poll_timeout = 3000; |
| 498 | } |
| 499 | } |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 500 | dev_info(uap->port.dev, "DMA channel RX %s\n", |
| 501 | dma_chan_name(uap->dmarx.chan)); |
| 502 | } |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 503 | } |
| 504 | |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 505 | static void pl011_dma_remove(struct uart_amba_port *uap) |
| 506 | { |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 507 | if (uap->dmatx.chan) |
| 508 | dma_release_channel(uap->dmatx.chan); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 509 | if (uap->dmarx.chan) |
| 510 | dma_release_channel(uap->dmarx.chan); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 511 | } |
| 512 | |
Dave Martin | 734745c | 2015-03-04 12:27:33 +0000 | [diff] [blame] | 513 | /* Forward declare these for the refill routine */ |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 514 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); |
Dave Martin | 734745c | 2015-03-04 12:27:33 +0000 | [diff] [blame] | 515 | static void pl011_start_tx_pio(struct uart_amba_port *uap); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 516 | |
| 517 | /* |
| 518 | * The current DMA TX buffer has been sent. |
| 519 | * Try to queue up another DMA buffer. |
| 520 | */ |
| 521 | static void pl011_dma_tx_callback(void *data) |
| 522 | { |
| 523 | struct uart_amba_port *uap = data; |
| 524 | struct pl011_dmatx_data *dmatx = &uap->dmatx; |
| 525 | unsigned long flags; |
| 526 | u16 dmacr; |
| 527 | |
| 528 | spin_lock_irqsave(&uap->port.lock, flags); |
| 529 | if (uap->dmatx.queued) |
| 530 | dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, |
| 531 | DMA_TO_DEVICE); |
| 532 | |
| 533 | dmacr = uap->dmacr; |
| 534 | uap->dmacr = dmacr & ~UART011_TXDMAE; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 535 | pl011_write(uap->dmacr, uap, REG_DMACR); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 536 | |
| 537 | /* |
| 538 | * If TX DMA was disabled, it means that we've stopped the DMA for |
| 539 | * some reason (eg, XOFF received, or we want to send an X-char.) |
| 540 | * |
| 541 | * Note: we need to be careful here of a potential race between DMA |
| 542 | * and the rest of the driver - if the driver disables TX DMA while |
| 543 | * a TX buffer completing, we must update the tx queued status to |
| 544 | * get further refills (hence we check dmacr). |
| 545 | */ |
| 546 | if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || |
| 547 | uart_circ_empty(&uap->port.state->xmit)) { |
| 548 | uap->dmatx.queued = false; |
| 549 | spin_unlock_irqrestore(&uap->port.lock, flags); |
| 550 | return; |
| 551 | } |
| 552 | |
Dave Martin | 734745c | 2015-03-04 12:27:33 +0000 | [diff] [blame] | 553 | if (pl011_dma_tx_refill(uap) <= 0) |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 554 | /* |
| 555 | * We didn't queue a DMA buffer for some reason, but we |
| 556 | * have data pending to be sent. Re-enable the TX IRQ. |
| 557 | */ |
Dave Martin | 734745c | 2015-03-04 12:27:33 +0000 | [diff] [blame] | 558 | pl011_start_tx_pio(uap); |
| 559 | |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 560 | spin_unlock_irqrestore(&uap->port.lock, flags); |
| 561 | } |
| 562 | |
| 563 | /* |
| 564 | * Try to refill the TX DMA buffer. |
| 565 | * Locking: called with port lock held and IRQs disabled. |
| 566 | * Returns: |
| 567 | * 1 if we queued up a TX DMA buffer. |
| 568 | * 0 if we didn't want to handle this by DMA |
| 569 | * <0 on error |
| 570 | */ |
| 571 | static int pl011_dma_tx_refill(struct uart_amba_port *uap) |
| 572 | { |
| 573 | struct pl011_dmatx_data *dmatx = &uap->dmatx; |
| 574 | struct dma_chan *chan = dmatx->chan; |
| 575 | struct dma_device *dma_dev = chan->device; |
| 576 | struct dma_async_tx_descriptor *desc; |
| 577 | struct circ_buf *xmit = &uap->port.state->xmit; |
| 578 | unsigned int count; |
| 579 | |
| 580 | /* |
| 581 | * Try to avoid the overhead involved in using DMA if the |
| 582 | * transaction fits in the first half of the FIFO, by using |
| 583 | * the standard interrupt handling. This ensures that we |
| 584 | * issue a uart_write_wakeup() at the appropriate time. |
| 585 | */ |
| 586 | count = uart_circ_chars_pending(xmit); |
| 587 | if (count < (uap->fifosize >> 1)) { |
| 588 | uap->dmatx.queued = false; |
| 589 | return 0; |
| 590 | } |
| 591 | |
| 592 | /* |
| 593 | * Bodge: don't send the last character by DMA, as this |
| 594 | * will prevent XON from notifying us to restart DMA. |
| 595 | */ |
| 596 | count -= 1; |
| 597 | |
| 598 | /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ |
| 599 | if (count > PL011_DMA_BUFFER_SIZE) |
| 600 | count = PL011_DMA_BUFFER_SIZE; |
| 601 | |
| 602 | if (xmit->tail < xmit->head) |
| 603 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); |
| 604 | else { |
| 605 | size_t first = UART_XMIT_SIZE - xmit->tail; |
Andrew Jackson | e2a545a | 2014-11-07 14:14:39 +0000 | [diff] [blame] | 606 | size_t second; |
| 607 | |
| 608 | if (first > count) |
| 609 | first = count; |
| 610 | second = count - first; |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 611 | |
| 612 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); |
| 613 | if (second) |
| 614 | memcpy(&dmatx->buf[first], &xmit->buf[0], second); |
| 615 | } |
| 616 | |
| 617 | dmatx->sg.length = count; |
| 618 | |
| 619 | if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { |
| 620 | uap->dmatx.queued = false; |
| 621 | dev_dbg(uap->port.dev, "unable to map TX DMA\n"); |
| 622 | return -EBUSY; |
| 623 | } |
| 624 | |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 625 | desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 626 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 627 | if (!desc) { |
| 628 | dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); |
| 629 | uap->dmatx.queued = false; |
| 630 | /* |
| 631 | * If DMA cannot be used right now, we complete this |
| 632 | * transaction via IRQ and let the TTY layer retry. |
| 633 | */ |
| 634 | dev_dbg(uap->port.dev, "TX DMA busy\n"); |
| 635 | return -EBUSY; |
| 636 | } |
| 637 | |
| 638 | /* Some data to go along to the callback */ |
| 639 | desc->callback = pl011_dma_tx_callback; |
| 640 | desc->callback_param = uap; |
| 641 | |
| 642 | /* All errors should happen at prepare time */ |
| 643 | dmaengine_submit(desc); |
| 644 | |
| 645 | /* Fire the DMA transaction */ |
| 646 | dma_dev->device_issue_pending(chan); |
| 647 | |
| 648 | uap->dmacr |= UART011_TXDMAE; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 649 | pl011_write(uap->dmacr, uap, REG_DMACR); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 650 | uap->dmatx.queued = true; |
| 651 | |
| 652 | /* |
| 653 | * Now we know that DMA will fire, so advance the ring buffer |
| 654 | * with the stuff we just dispatched. |
| 655 | */ |
| 656 | xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); |
| 657 | uap->port.icount.tx += count; |
| 658 | |
| 659 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
| 660 | uart_write_wakeup(&uap->port); |
| 661 | |
| 662 | return 1; |
| 663 | } |
| 664 | |
| 665 | /* |
| 666 | * We received a transmit interrupt without a pending X-char but with |
| 667 | * pending characters. |
| 668 | * Locking: called with port lock held and IRQs disabled. |
| 669 | * Returns: |
| 670 | * false if we want to use PIO to transmit |
| 671 | * true if we queued a DMA buffer |
| 672 | */ |
| 673 | static bool pl011_dma_tx_irq(struct uart_amba_port *uap) |
| 674 | { |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 675 | if (!uap->using_tx_dma) |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 676 | return false; |
| 677 | |
| 678 | /* |
| 679 | * If we already have a TX buffer queued, but received a |
| 680 | * TX interrupt, it will be because we've just sent an X-char. |
| 681 | * Ensure the TX DMA is enabled and the TX IRQ is disabled. |
| 682 | */ |
| 683 | if (uap->dmatx.queued) { |
| 684 | uap->dmacr |= UART011_TXDMAE; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 685 | pl011_write(uap->dmacr, uap, REG_DMACR); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 686 | uap->im &= ~UART011_TXIM; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 687 | pl011_write(uap->im, uap, REG_IMSC); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 688 | return true; |
| 689 | } |
| 690 | |
| 691 | /* |
| 692 | * We don't have a TX buffer queued, so try to queue one. |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 693 | * If we successfully queued a buffer, mask the TX IRQ. |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 694 | */ |
| 695 | if (pl011_dma_tx_refill(uap) > 0) { |
| 696 | uap->im &= ~UART011_TXIM; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 697 | pl011_write(uap->im, uap, REG_IMSC); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 698 | return true; |
| 699 | } |
| 700 | return false; |
| 701 | } |
| 702 | |
| 703 | /* |
| 704 | * Stop the DMA transmit (eg, due to received XOFF). |
| 705 | * Locking: called with port lock held and IRQs disabled. |
| 706 | */ |
| 707 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) |
| 708 | { |
| 709 | if (uap->dmatx.queued) { |
| 710 | uap->dmacr &= ~UART011_TXDMAE; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 711 | pl011_write(uap->dmacr, uap, REG_DMACR); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 712 | } |
| 713 | } |
| 714 | |
| 715 | /* |
| 716 | * Try to start a DMA transmit, or in the case of an XON/OFF |
| 717 | * character queued for send, try to get that character out ASAP. |
| 718 | * Locking: called with port lock held and IRQs disabled. |
| 719 | * Returns: |
| 720 | * false if we want the TX IRQ to be enabled |
| 721 | * true if we have a buffer queued |
| 722 | */ |
| 723 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) |
| 724 | { |
| 725 | u16 dmacr; |
| 726 | |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 727 | if (!uap->using_tx_dma) |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 728 | return false; |
| 729 | |
| 730 | if (!uap->port.x_char) { |
| 731 | /* no X-char, try to push chars out in DMA mode */ |
| 732 | bool ret = true; |
| 733 | |
| 734 | if (!uap->dmatx.queued) { |
| 735 | if (pl011_dma_tx_refill(uap) > 0) { |
| 736 | uap->im &= ~UART011_TXIM; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 737 | pl011_write(uap->im, uap, REG_IMSC); |
Dave Martin | 734745c | 2015-03-04 12:27:33 +0000 | [diff] [blame] | 738 | } else |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 739 | ret = false; |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 740 | } else if (!(uap->dmacr & UART011_TXDMAE)) { |
| 741 | uap->dmacr |= UART011_TXDMAE; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 742 | pl011_write(uap->dmacr, uap, REG_DMACR); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 743 | } |
| 744 | return ret; |
| 745 | } |
| 746 | |
| 747 | /* |
| 748 | * We have an X-char to send. Disable DMA to prevent it loading |
| 749 | * the TX fifo, and then see if we can stuff it into the FIFO. |
| 750 | */ |
| 751 | dmacr = uap->dmacr; |
| 752 | uap->dmacr &= ~UART011_TXDMAE; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 753 | pl011_write(uap->dmacr, uap, REG_DMACR); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 754 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 755 | if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 756 | /* |
| 757 | * No space in the FIFO, so enable the transmit interrupt |
| 758 | * so we know when there is space. Note that once we've |
| 759 | * loaded the character, we should just re-enable DMA. |
| 760 | */ |
| 761 | return false; |
| 762 | } |
| 763 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 764 | pl011_write(uap->port.x_char, uap, REG_DR); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 765 | uap->port.icount.tx++; |
| 766 | uap->port.x_char = 0; |
| 767 | |
| 768 | /* Success - restore the DMA state */ |
| 769 | uap->dmacr = dmacr; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 770 | pl011_write(dmacr, uap, REG_DMACR); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 771 | |
| 772 | return true; |
| 773 | } |
| 774 | |
| 775 | /* |
| 776 | * Flush the transmit buffer. |
| 777 | * Locking: called with port lock held and IRQs disabled. |
| 778 | */ |
| 779 | static void pl011_dma_flush_buffer(struct uart_port *port) |
Fabio Estevam | b83286b | 2013-08-09 17:58:51 -0300 | [diff] [blame] | 780 | __releases(&uap->port.lock) |
| 781 | __acquires(&uap->port.lock) |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 782 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 783 | struct uart_amba_port *uap = |
| 784 | container_of(port, struct uart_amba_port, port); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 785 | |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 786 | if (!uap->using_tx_dma) |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 787 | return; |
| 788 | |
| 789 | /* Avoid deadlock with the DMA engine callback */ |
| 790 | spin_unlock(&uap->port.lock); |
| 791 | dmaengine_terminate_all(uap->dmatx.chan); |
| 792 | spin_lock(&uap->port.lock); |
| 793 | if (uap->dmatx.queued) { |
| 794 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, |
| 795 | DMA_TO_DEVICE); |
| 796 | uap->dmatx.queued = false; |
| 797 | uap->dmacr &= ~UART011_TXDMAE; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 798 | pl011_write(uap->dmacr, uap, REG_DMACR); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 799 | } |
| 800 | } |
| 801 | |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 802 | static void pl011_dma_rx_callback(void *data); |
| 803 | |
| 804 | static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) |
| 805 | { |
| 806 | struct dma_chan *rxchan = uap->dmarx.chan; |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 807 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
| 808 | struct dma_async_tx_descriptor *desc; |
| 809 | struct pl011_sgbuf *sgbuf; |
| 810 | |
| 811 | if (!rxchan) |
| 812 | return -EIO; |
| 813 | |
| 814 | /* Start the RX DMA job */ |
| 815 | sgbuf = uap->dmarx.use_buf_b ? |
| 816 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 817 | desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, |
Vinod Koul | a485df4 | 2011-10-14 10:47:38 +0530 | [diff] [blame] | 818 | DMA_DEV_TO_MEM, |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 819 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 820 | /* |
| 821 | * If the DMA engine is busy and cannot prepare a |
| 822 | * channel, no big deal, the driver will fall back |
| 823 | * to interrupt mode as a result of this error code. |
| 824 | */ |
| 825 | if (!desc) { |
| 826 | uap->dmarx.running = false; |
| 827 | dmaengine_terminate_all(rxchan); |
| 828 | return -EBUSY; |
| 829 | } |
| 830 | |
| 831 | /* Some data to go along to the callback */ |
| 832 | desc->callback = pl011_dma_rx_callback; |
| 833 | desc->callback_param = uap; |
| 834 | dmarx->cookie = dmaengine_submit(desc); |
| 835 | dma_async_issue_pending(rxchan); |
| 836 | |
| 837 | uap->dmacr |= UART011_RXDMAE; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 838 | pl011_write(uap->dmacr, uap, REG_DMACR); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 839 | uap->dmarx.running = true; |
| 840 | |
| 841 | uap->im &= ~UART011_RXIM; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 842 | pl011_write(uap->im, uap, REG_IMSC); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 843 | |
| 844 | return 0; |
| 845 | } |
| 846 | |
| 847 | /* |
| 848 | * This is called when either the DMA job is complete, or |
| 849 | * the FIFO timeout interrupt occurred. This must be called |
| 850 | * with the port spinlock uap->port.lock held. |
| 851 | */ |
| 852 | static void pl011_dma_rx_chars(struct uart_amba_port *uap, |
| 853 | u32 pending, bool use_buf_b, |
| 854 | bool readfifo) |
| 855 | { |
Jiri Slaby | 05c7cd3 | 2013-01-03 15:53:04 +0100 | [diff] [blame] | 856 | struct tty_port *port = &uap->port.state->port; |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 857 | struct pl011_sgbuf *sgbuf = use_buf_b ? |
| 858 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 859 | int dma_count = 0; |
| 860 | u32 fifotaken = 0; /* only used for vdbg() */ |
| 861 | |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 862 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
| 863 | int dmataken = 0; |
| 864 | |
| 865 | if (uap->dmarx.poll_rate) { |
| 866 | /* The data can be taken by polling */ |
| 867 | dmataken = sgbuf->sg.length - dmarx->last_residue; |
| 868 | /* Recalculate the pending size */ |
| 869 | if (pending >= dmataken) |
| 870 | pending -= dmataken; |
| 871 | } |
| 872 | |
| 873 | /* Pick the remain data from the DMA */ |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 874 | if (pending) { |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 875 | |
| 876 | /* |
| 877 | * First take all chars in the DMA pipe, then look in the FIFO. |
| 878 | * Note that tty_insert_flip_buf() tries to take as many chars |
| 879 | * as it can. |
| 880 | */ |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 881 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, |
| 882 | pending); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 883 | |
| 884 | uap->port.icount.rx += dma_count; |
| 885 | if (dma_count < pending) |
| 886 | dev_warn(uap->port.dev, |
| 887 | "couldn't insert all characters (TTY is full?)\n"); |
| 888 | } |
| 889 | |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 890 | /* Reset the last_residue for Rx DMA poll */ |
| 891 | if (uap->dmarx.poll_rate) |
| 892 | dmarx->last_residue = sgbuf->sg.length; |
| 893 | |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 894 | /* |
| 895 | * Only continue with trying to read the FIFO if all DMA chars have |
| 896 | * been taken first. |
| 897 | */ |
| 898 | if (dma_count == pending && readfifo) { |
| 899 | /* Clear any error flags */ |
Russell King | 7583633 | 2015-11-03 14:50:58 +0000 | [diff] [blame] | 900 | pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 901 | UART011_FEIS, uap, REG_ICR); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 902 | |
| 903 | /* |
| 904 | * If we read all the DMA'd characters, and we had an |
Linus Walleij | 29772c4 | 2011-02-24 13:21:36 +0100 | [diff] [blame] | 905 | * incomplete buffer, that could be due to an rx error, or |
| 906 | * maybe we just timed out. Read any pending chars and check |
| 907 | * the error status. |
| 908 | * |
| 909 | * Error conditions will only occur in the FIFO, these will |
| 910 | * trigger an immediate interrupt and stop the DMA job, so we |
| 911 | * will always find the error in the FIFO, never in the DMA |
| 912 | * buffer. |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 913 | */ |
Linus Walleij | 29772c4 | 2011-02-24 13:21:36 +0100 | [diff] [blame] | 914 | fifotaken = pl011_fifo_to_tty(uap); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 915 | } |
| 916 | |
| 917 | spin_unlock(&uap->port.lock); |
| 918 | dev_vdbg(uap->port.dev, |
| 919 | "Took %d chars from DMA buffer and %d chars from the FIFO\n", |
| 920 | dma_count, fifotaken); |
Jiri Slaby | 2e124b4 | 2013-01-03 15:53:06 +0100 | [diff] [blame] | 921 | tty_flip_buffer_push(port); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 922 | spin_lock(&uap->port.lock); |
| 923 | } |
| 924 | |
| 925 | static void pl011_dma_rx_irq(struct uart_amba_port *uap) |
| 926 | { |
| 927 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
| 928 | struct dma_chan *rxchan = dmarx->chan; |
| 929 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? |
| 930 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; |
| 931 | size_t pending; |
| 932 | struct dma_tx_state state; |
| 933 | enum dma_status dmastat; |
| 934 | |
| 935 | /* |
| 936 | * Pause the transfer so we can trust the current counter, |
| 937 | * do this before we pause the PL011 block, else we may |
| 938 | * overflow the FIFO. |
| 939 | */ |
| 940 | if (dmaengine_pause(rxchan)) |
| 941 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); |
| 942 | dmastat = rxchan->device->device_tx_status(rxchan, |
| 943 | dmarx->cookie, &state); |
| 944 | if (dmastat != DMA_PAUSED) |
| 945 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); |
| 946 | |
| 947 | /* Disable RX DMA - incoming data will wait in the FIFO */ |
| 948 | uap->dmacr &= ~UART011_RXDMAE; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 949 | pl011_write(uap->dmacr, uap, REG_DMACR); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 950 | uap->dmarx.running = false; |
| 951 | |
| 952 | pending = sgbuf->sg.length - state.residue; |
| 953 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); |
| 954 | /* Then we terminate the transfer - we now know our residue */ |
| 955 | dmaengine_terminate_all(rxchan); |
| 956 | |
| 957 | /* |
| 958 | * This will take the chars we have so far and insert |
| 959 | * into the framework. |
| 960 | */ |
| 961 | pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); |
| 962 | |
| 963 | /* Switch buffer & re-trigger DMA job */ |
| 964 | dmarx->use_buf_b = !dmarx->use_buf_b; |
| 965 | if (pl011_dma_rx_trigger_dma(uap)) { |
| 966 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " |
| 967 | "fall back to interrupt mode\n"); |
| 968 | uap->im |= UART011_RXIM; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 969 | pl011_write(uap->im, uap, REG_IMSC); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 970 | } |
| 971 | } |
| 972 | |
| 973 | static void pl011_dma_rx_callback(void *data) |
| 974 | { |
| 975 | struct uart_amba_port *uap = data; |
| 976 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
Chanho Min | 6dc01aa | 2012-02-20 10:24:40 +0900 | [diff] [blame] | 977 | struct dma_chan *rxchan = dmarx->chan; |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 978 | bool lastbuf = dmarx->use_buf_b; |
Chanho Min | 6dc01aa | 2012-02-20 10:24:40 +0900 | [diff] [blame] | 979 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? |
| 980 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; |
| 981 | size_t pending; |
| 982 | struct dma_tx_state state; |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 983 | int ret; |
| 984 | |
| 985 | /* |
| 986 | * This completion interrupt occurs typically when the |
| 987 | * RX buffer is totally stuffed but no timeout has yet |
| 988 | * occurred. When that happens, we just want the RX |
| 989 | * routine to flush out the secondary DMA buffer while |
| 990 | * we immediately trigger the next DMA job. |
| 991 | */ |
| 992 | spin_lock_irq(&uap->port.lock); |
Chanho Min | 6dc01aa | 2012-02-20 10:24:40 +0900 | [diff] [blame] | 993 | /* |
| 994 | * Rx data can be taken by the UART interrupts during |
| 995 | * the DMA irq handler. So we check the residue here. |
| 996 | */ |
| 997 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); |
| 998 | pending = sgbuf->sg.length - state.residue; |
| 999 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); |
| 1000 | /* Then we terminate the transfer - we now know our residue */ |
| 1001 | dmaengine_terminate_all(rxchan); |
| 1002 | |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1003 | uap->dmarx.running = false; |
| 1004 | dmarx->use_buf_b = !lastbuf; |
| 1005 | ret = pl011_dma_rx_trigger_dma(uap); |
| 1006 | |
Chanho Min | 6dc01aa | 2012-02-20 10:24:40 +0900 | [diff] [blame] | 1007 | pl011_dma_rx_chars(uap, pending, lastbuf, false); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1008 | spin_unlock_irq(&uap->port.lock); |
| 1009 | /* |
| 1010 | * Do this check after we picked the DMA chars so we don't |
| 1011 | * get some IRQ immediately from RX. |
| 1012 | */ |
| 1013 | if (ret) { |
| 1014 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " |
| 1015 | "fall back to interrupt mode\n"); |
| 1016 | uap->im |= UART011_RXIM; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1017 | pl011_write(uap->im, uap, REG_IMSC); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1018 | } |
| 1019 | } |
| 1020 | |
| 1021 | /* |
| 1022 | * Stop accepting received characters, when we're shutting down or |
| 1023 | * suspending this port. |
| 1024 | * Locking: called with port lock held and IRQs disabled. |
| 1025 | */ |
| 1026 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) |
| 1027 | { |
| 1028 | /* FIXME. Just disable the DMA enable */ |
| 1029 | uap->dmacr &= ~UART011_RXDMAE; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1030 | pl011_write(uap->dmacr, uap, REG_DMACR); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1031 | } |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1032 | |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 1033 | /* |
| 1034 | * Timer handler for Rx DMA polling. |
| 1035 | * Every polling, It checks the residue in the dma buffer and transfer |
| 1036 | * data to the tty. Also, last_residue is updated for the next polling. |
| 1037 | */ |
| 1038 | static void pl011_dma_rx_poll(unsigned long args) |
| 1039 | { |
| 1040 | struct uart_amba_port *uap = (struct uart_amba_port *)args; |
| 1041 | struct tty_port *port = &uap->port.state->port; |
| 1042 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
| 1043 | struct dma_chan *rxchan = uap->dmarx.chan; |
| 1044 | unsigned long flags = 0; |
| 1045 | unsigned int dmataken = 0; |
| 1046 | unsigned int size = 0; |
| 1047 | struct pl011_sgbuf *sgbuf; |
| 1048 | int dma_count; |
| 1049 | struct dma_tx_state state; |
| 1050 | |
| 1051 | sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; |
| 1052 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); |
| 1053 | if (likely(state.residue < dmarx->last_residue)) { |
| 1054 | dmataken = sgbuf->sg.length - dmarx->last_residue; |
| 1055 | size = dmarx->last_residue - state.residue; |
| 1056 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, |
| 1057 | size); |
| 1058 | if (dma_count == size) |
| 1059 | dmarx->last_residue = state.residue; |
| 1060 | dmarx->last_jiffies = jiffies; |
| 1061 | } |
| 1062 | tty_flip_buffer_push(port); |
| 1063 | |
| 1064 | /* |
| 1065 | * If no data is received in poll_timeout, the driver will fall back |
| 1066 | * to interrupt mode. We will retrigger DMA at the first interrupt. |
| 1067 | */ |
| 1068 | if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) |
| 1069 | > uap->dmarx.poll_timeout) { |
| 1070 | |
| 1071 | spin_lock_irqsave(&uap->port.lock, flags); |
| 1072 | pl011_dma_rx_stop(uap); |
Guennadi Liakhovetski | c25a1ad | 2013-12-10 14:54:47 +0100 | [diff] [blame] | 1073 | uap->im |= UART011_RXIM; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1074 | pl011_write(uap->im, uap, REG_IMSC); |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 1075 | spin_unlock_irqrestore(&uap->port.lock, flags); |
| 1076 | |
| 1077 | uap->dmarx.running = false; |
| 1078 | dmaengine_terminate_all(rxchan); |
| 1079 | del_timer(&uap->dmarx.timer); |
| 1080 | } else { |
| 1081 | mod_timer(&uap->dmarx.timer, |
| 1082 | jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); |
| 1083 | } |
| 1084 | } |
| 1085 | |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1086 | static void pl011_dma_startup(struct uart_amba_port *uap) |
| 1087 | { |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1088 | int ret; |
| 1089 | |
Jorge Ramirez-Ortiz | 1c9be31 | 2015-03-06 13:05:40 -0500 | [diff] [blame] | 1090 | if (!uap->dma_probed) |
| 1091 | pl011_dma_probe(uap); |
| 1092 | |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1093 | if (!uap->dmatx.chan) |
| 1094 | return; |
| 1095 | |
Andrew Jackson | 4c0be45 | 2014-11-07 14:14:35 +0000 | [diff] [blame] | 1096 | uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1097 | if (!uap->dmatx.buf) { |
| 1098 | dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); |
| 1099 | uap->port.fifosize = uap->fifosize; |
| 1100 | return; |
| 1101 | } |
| 1102 | |
| 1103 | sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); |
| 1104 | |
| 1105 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ |
| 1106 | uap->port.fifosize = PL011_DMA_BUFFER_SIZE; |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1107 | uap->using_tx_dma = true; |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1108 | |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1109 | if (!uap->dmarx.chan) |
| 1110 | goto skip_rx; |
| 1111 | |
| 1112 | /* Allocate and map DMA RX buffers */ |
| 1113 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, |
| 1114 | DMA_FROM_DEVICE); |
| 1115 | if (ret) { |
| 1116 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", |
| 1117 | "RX buffer A", ret); |
| 1118 | goto skip_rx; |
| 1119 | } |
| 1120 | |
| 1121 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, |
| 1122 | DMA_FROM_DEVICE); |
| 1123 | if (ret) { |
| 1124 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", |
| 1125 | "RX buffer B", ret); |
| 1126 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, |
| 1127 | DMA_FROM_DEVICE); |
| 1128 | goto skip_rx; |
| 1129 | } |
| 1130 | |
| 1131 | uap->using_rx_dma = true; |
| 1132 | |
| 1133 | skip_rx: |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1134 | /* Turn on DMA error (RX/TX will be enabled on demand) */ |
| 1135 | uap->dmacr |= UART011_DMAONERR; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1136 | pl011_write(uap->dmacr, uap, REG_DMACR); |
Russell King | 38d6243 | 2010-12-22 17:59:16 +0000 | [diff] [blame] | 1137 | |
| 1138 | /* |
| 1139 | * ST Micro variants has some specific dma burst threshold |
| 1140 | * compensation. Set this to 16 bytes, so burst will only |
| 1141 | * be issued above/below 16 bytes. |
| 1142 | */ |
| 1143 | if (uap->vendor->dma_threshold) |
Russell King | 7583633 | 2015-11-03 14:50:58 +0000 | [diff] [blame] | 1144 | pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1145 | uap, REG_ST_DMAWM); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1146 | |
| 1147 | if (uap->using_rx_dma) { |
| 1148 | if (pl011_dma_rx_trigger_dma(uap)) |
| 1149 | dev_dbg(uap->port.dev, "could not trigger initial " |
| 1150 | "RX DMA job, fall back to interrupt mode\n"); |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 1151 | if (uap->dmarx.poll_rate) { |
| 1152 | init_timer(&(uap->dmarx.timer)); |
| 1153 | uap->dmarx.timer.function = pl011_dma_rx_poll; |
| 1154 | uap->dmarx.timer.data = (unsigned long)uap; |
| 1155 | mod_timer(&uap->dmarx.timer, |
| 1156 | jiffies + |
| 1157 | msecs_to_jiffies(uap->dmarx.poll_rate)); |
| 1158 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; |
| 1159 | uap->dmarx.last_jiffies = jiffies; |
| 1160 | } |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1161 | } |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1162 | } |
| 1163 | |
| 1164 | static void pl011_dma_shutdown(struct uart_amba_port *uap) |
| 1165 | { |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1166 | if (!(uap->using_tx_dma || uap->using_rx_dma)) |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1167 | return; |
| 1168 | |
| 1169 | /* Disable RX and TX DMA */ |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1170 | while (pl011_read(uap, REG_FR) & UART01x_FR_BUSY) |
Timur Tabi | 2f2fd08 | 2016-01-15 14:32:20 -0600 | [diff] [blame] | 1171 | cpu_relax(); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1172 | |
| 1173 | spin_lock_irq(&uap->port.lock); |
| 1174 | uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1175 | pl011_write(uap->dmacr, uap, REG_DMACR); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1176 | spin_unlock_irq(&uap->port.lock); |
| 1177 | |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1178 | if (uap->using_tx_dma) { |
| 1179 | /* In theory, this should already be done by pl011_dma_flush_buffer */ |
| 1180 | dmaengine_terminate_all(uap->dmatx.chan); |
| 1181 | if (uap->dmatx.queued) { |
| 1182 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, |
| 1183 | DMA_TO_DEVICE); |
| 1184 | uap->dmatx.queued = false; |
| 1185 | } |
| 1186 | |
| 1187 | kfree(uap->dmatx.buf); |
| 1188 | uap->using_tx_dma = false; |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1189 | } |
| 1190 | |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1191 | if (uap->using_rx_dma) { |
| 1192 | dmaengine_terminate_all(uap->dmarx.chan); |
| 1193 | /* Clean up the RX DMA */ |
| 1194 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); |
| 1195 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 1196 | if (uap->dmarx.poll_rate) |
| 1197 | del_timer_sync(&uap->dmarx.timer); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1198 | uap->using_rx_dma = false; |
| 1199 | } |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1200 | } |
| 1201 | |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1202 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) |
| 1203 | { |
| 1204 | return uap->using_rx_dma; |
| 1205 | } |
| 1206 | |
| 1207 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) |
| 1208 | { |
| 1209 | return uap->using_rx_dma && uap->dmarx.running; |
| 1210 | } |
| 1211 | |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1212 | #else |
| 1213 | /* Blank functions if the DMA engine is not available */ |
Jorge Ramirez-Ortiz | 1c9be31 | 2015-03-06 13:05:40 -0500 | [diff] [blame] | 1214 | static inline void pl011_dma_probe(struct uart_amba_port *uap) |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1215 | { |
| 1216 | } |
| 1217 | |
| 1218 | static inline void pl011_dma_remove(struct uart_amba_port *uap) |
| 1219 | { |
| 1220 | } |
| 1221 | |
| 1222 | static inline void pl011_dma_startup(struct uart_amba_port *uap) |
| 1223 | { |
| 1224 | } |
| 1225 | |
| 1226 | static inline void pl011_dma_shutdown(struct uart_amba_port *uap) |
| 1227 | { |
| 1228 | } |
| 1229 | |
| 1230 | static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) |
| 1231 | { |
| 1232 | return false; |
| 1233 | } |
| 1234 | |
| 1235 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) |
| 1236 | { |
| 1237 | } |
| 1238 | |
| 1239 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) |
| 1240 | { |
| 1241 | return false; |
| 1242 | } |
| 1243 | |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1244 | static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) |
| 1245 | { |
| 1246 | } |
| 1247 | |
| 1248 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) |
| 1249 | { |
| 1250 | } |
| 1251 | |
| 1252 | static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) |
| 1253 | { |
| 1254 | return -EIO; |
| 1255 | } |
| 1256 | |
| 1257 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) |
| 1258 | { |
| 1259 | return false; |
| 1260 | } |
| 1261 | |
| 1262 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) |
| 1263 | { |
| 1264 | return false; |
| 1265 | } |
| 1266 | |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1267 | #define pl011_dma_flush_buffer NULL |
| 1268 | #endif |
| 1269 | |
Russell King | b129a8c | 2005-08-31 10:12:14 +0100 | [diff] [blame] | 1270 | static void pl011_stop_tx(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1271 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 1272 | struct uart_amba_port *uap = |
| 1273 | container_of(port, struct uart_amba_port, port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1274 | |
| 1275 | uap->im &= ~UART011_TXIM; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1276 | pl011_write(uap->im, uap, REG_IMSC); |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1277 | pl011_dma_tx_stop(uap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1278 | } |
| 1279 | |
Dave Martin | 1e84d22 | 2015-04-27 16:49:05 +0100 | [diff] [blame] | 1280 | static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); |
Dave Martin | 734745c | 2015-03-04 12:27:33 +0000 | [diff] [blame] | 1281 | |
| 1282 | /* Start TX with programmed I/O only (no DMA) */ |
| 1283 | static void pl011_start_tx_pio(struct uart_amba_port *uap) |
| 1284 | { |
| 1285 | uap->im |= UART011_TXIM; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1286 | pl011_write(uap->im, uap, REG_IMSC); |
Dave Martin | 1e84d22 | 2015-04-27 16:49:05 +0100 | [diff] [blame] | 1287 | pl011_tx_chars(uap, false); |
Dave Martin | 734745c | 2015-03-04 12:27:33 +0000 | [diff] [blame] | 1288 | } |
| 1289 | |
Russell King | b129a8c | 2005-08-31 10:12:14 +0100 | [diff] [blame] | 1290 | static void pl011_start_tx(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1291 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 1292 | struct uart_amba_port *uap = |
| 1293 | container_of(port, struct uart_amba_port, port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1294 | |
Dave Martin | 734745c | 2015-03-04 12:27:33 +0000 | [diff] [blame] | 1295 | if (!pl011_dma_tx_start(uap)) |
| 1296 | pl011_start_tx_pio(uap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1297 | } |
| 1298 | |
| 1299 | static void pl011_stop_rx(struct uart_port *port) |
| 1300 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 1301 | struct uart_amba_port *uap = |
| 1302 | container_of(port, struct uart_amba_port, port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1303 | |
| 1304 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| |
| 1305 | UART011_PEIM|UART011_BEIM|UART011_OEIM); |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1306 | pl011_write(uap->im, uap, REG_IMSC); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1307 | |
| 1308 | pl011_dma_rx_stop(uap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1309 | } |
| 1310 | |
| 1311 | static void pl011_enable_ms(struct uart_port *port) |
| 1312 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 1313 | struct uart_amba_port *uap = |
| 1314 | container_of(port, struct uart_amba_port, port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1315 | |
| 1316 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1317 | pl011_write(uap->im, uap, REG_IMSC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1318 | } |
| 1319 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1320 | static void pl011_rx_chars(struct uart_amba_port *uap) |
Fabio Estevam | b83286b | 2013-08-09 17:58:51 -0300 | [diff] [blame] | 1321 | __releases(&uap->port.lock) |
| 1322 | __acquires(&uap->port.lock) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1323 | { |
Linus Walleij | 29772c4 | 2011-02-24 13:21:36 +0100 | [diff] [blame] | 1324 | pl011_fifo_to_tty(uap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1325 | |
Thomas Gleixner | 2389b27 | 2007-05-29 21:53:50 +0100 | [diff] [blame] | 1326 | spin_unlock(&uap->port.lock); |
Jiri Slaby | 2e124b4 | 2013-01-03 15:53:06 +0100 | [diff] [blame] | 1327 | tty_flip_buffer_push(&uap->port.state->port); |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1328 | /* |
| 1329 | * If we were temporarily out of DMA mode for a while, |
| 1330 | * attempt to switch back to DMA mode again. |
| 1331 | */ |
| 1332 | if (pl011_dma_rx_available(uap)) { |
| 1333 | if (pl011_dma_rx_trigger_dma(uap)) { |
| 1334 | dev_dbg(uap->port.dev, "could not trigger RX DMA job " |
| 1335 | "fall back to interrupt mode again\n"); |
| 1336 | uap->im |= UART011_RXIM; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1337 | pl011_write(uap->im, uap, REG_IMSC); |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 1338 | } else { |
Chanho Min | 89fa28d | 2013-04-03 11:10:37 +0900 | [diff] [blame] | 1339 | #ifdef CONFIG_DMA_ENGINE |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 1340 | /* Start Rx DMA poll */ |
| 1341 | if (uap->dmarx.poll_rate) { |
| 1342 | uap->dmarx.last_jiffies = jiffies; |
| 1343 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; |
| 1344 | mod_timer(&uap->dmarx.timer, |
| 1345 | jiffies + |
| 1346 | msecs_to_jiffies(uap->dmarx.poll_rate)); |
| 1347 | } |
Chanho Min | 89fa28d | 2013-04-03 11:10:37 +0900 | [diff] [blame] | 1348 | #endif |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 1349 | } |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1350 | } |
Thomas Gleixner | 2389b27 | 2007-05-29 21:53:50 +0100 | [diff] [blame] | 1351 | spin_lock(&uap->port.lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1352 | } |
| 1353 | |
Dave Martin | 1e84d22 | 2015-04-27 16:49:05 +0100 | [diff] [blame] | 1354 | static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, |
| 1355 | bool from_irq) |
Dave Martin | 734745c | 2015-03-04 12:27:33 +0000 | [diff] [blame] | 1356 | { |
Dave Martin | 1e84d22 | 2015-04-27 16:49:05 +0100 | [diff] [blame] | 1357 | if (unlikely(!from_irq) && |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1358 | pl011_read(uap, REG_FR) & UART01x_FR_TXFF) |
Dave Martin | 1e84d22 | 2015-04-27 16:49:05 +0100 | [diff] [blame] | 1359 | return false; /* unable to transmit character */ |
| 1360 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1361 | pl011_write(c, uap, REG_DR); |
Dave Martin | 734745c | 2015-03-04 12:27:33 +0000 | [diff] [blame] | 1362 | uap->port.icount.tx++; |
| 1363 | |
Dave Martin | 1e84d22 | 2015-04-27 16:49:05 +0100 | [diff] [blame] | 1364 | return true; |
Dave Martin | 734745c | 2015-03-04 12:27:33 +0000 | [diff] [blame] | 1365 | } |
| 1366 | |
Dave Martin | 1e84d22 | 2015-04-27 16:49:05 +0100 | [diff] [blame] | 1367 | static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1368 | { |
Alan Cox | ebd2c8f | 2009-09-19 13:13:28 -0700 | [diff] [blame] | 1369 | struct circ_buf *xmit = &uap->port.state->xmit; |
Dave Martin | 1e84d22 | 2015-04-27 16:49:05 +0100 | [diff] [blame] | 1370 | int count = uap->fifosize >> 1; |
Dave Martin | 734745c | 2015-03-04 12:27:33 +0000 | [diff] [blame] | 1371 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1372 | if (uap->port.x_char) { |
Dave Martin | 1e84d22 | 2015-04-27 16:49:05 +0100 | [diff] [blame] | 1373 | if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) |
| 1374 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1375 | uap->port.x_char = 0; |
Dave Martin | 734745c | 2015-03-04 12:27:33 +0000 | [diff] [blame] | 1376 | --count; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1377 | } |
| 1378 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { |
Russell King | b129a8c | 2005-08-31 10:12:14 +0100 | [diff] [blame] | 1379 | pl011_stop_tx(&uap->port); |
Dave Martin | 1e84d22 | 2015-04-27 16:49:05 +0100 | [diff] [blame] | 1380 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1381 | } |
| 1382 | |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1383 | /* If we are using DMA mode, try to send some characters. */ |
| 1384 | if (pl011_dma_tx_irq(uap)) |
Dave Martin | 1e84d22 | 2015-04-27 16:49:05 +0100 | [diff] [blame] | 1385 | return; |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1386 | |
Dave Martin | 1e84d22 | 2015-04-27 16:49:05 +0100 | [diff] [blame] | 1387 | do { |
| 1388 | if (likely(from_irq) && count-- == 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1389 | break; |
Dave Martin | 1e84d22 | 2015-04-27 16:49:05 +0100 | [diff] [blame] | 1390 | |
| 1391 | if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) |
| 1392 | break; |
| 1393 | |
| 1394 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
| 1395 | } while (!uart_circ_empty(xmit)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1396 | |
| 1397 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
| 1398 | uart_write_wakeup(&uap->port); |
| 1399 | |
Dave Martin | 1e84d22 | 2015-04-27 16:49:05 +0100 | [diff] [blame] | 1400 | if (uart_circ_empty(xmit)) |
Russell King | b129a8c | 2005-08-31 10:12:14 +0100 | [diff] [blame] | 1401 | pl011_stop_tx(&uap->port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1402 | } |
| 1403 | |
| 1404 | static void pl011_modem_status(struct uart_amba_port *uap) |
| 1405 | { |
| 1406 | unsigned int status, delta; |
| 1407 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1408 | status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1409 | |
| 1410 | delta = status ^ uap->old_status; |
| 1411 | uap->old_status = status; |
| 1412 | |
| 1413 | if (!delta) |
| 1414 | return; |
| 1415 | |
| 1416 | if (delta & UART01x_FR_DCD) |
| 1417 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); |
| 1418 | |
Greg Kroah-Hartman | 062a68a | 2015-09-04 09:11:24 -0700 | [diff] [blame] | 1419 | if (delta & UART01x_FR_DSR) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1420 | uap->port.icount.dsr++; |
| 1421 | |
Greg Kroah-Hartman | 062a68a | 2015-09-04 09:11:24 -0700 | [diff] [blame] | 1422 | if (delta & UART01x_FR_CTS) |
| 1423 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1424 | |
Alan Cox | bdc04e3 | 2009-09-19 13:13:31 -0700 | [diff] [blame] | 1425 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1426 | } |
| 1427 | |
Andre Przywara | 9c4ef4b | 2015-05-21 17:26:20 +0100 | [diff] [blame] | 1428 | static void check_apply_cts_event_workaround(struct uart_amba_port *uap) |
| 1429 | { |
| 1430 | unsigned int dummy_read; |
| 1431 | |
| 1432 | if (!uap->vendor->cts_event_workaround) |
| 1433 | return; |
| 1434 | |
| 1435 | /* workaround to make sure that all bits are unlocked.. */ |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1436 | pl011_write(0x00, uap, REG_ICR); |
Andre Przywara | 9c4ef4b | 2015-05-21 17:26:20 +0100 | [diff] [blame] | 1437 | |
| 1438 | /* |
| 1439 | * WA: introduce 26ns(1 uart clk) delay before W1C; |
| 1440 | * single apb access will incur 2 pclk(133.12Mhz) delay, |
| 1441 | * so add 2 dummy reads |
| 1442 | */ |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1443 | dummy_read = pl011_read(uap, REG_ICR); |
| 1444 | dummy_read = pl011_read(uap, REG_ICR); |
Andre Przywara | 9c4ef4b | 2015-05-21 17:26:20 +0100 | [diff] [blame] | 1445 | } |
| 1446 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1447 | static irqreturn_t pl011_int(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1448 | { |
| 1449 | struct uart_amba_port *uap = dev_id; |
Russell King | 963cc98 | 2010-12-22 17:16:09 +0000 | [diff] [blame] | 1450 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1451 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
Andre Przywara | 075167e | 2015-05-21 17:26:19 +0100 | [diff] [blame] | 1452 | u16 imsc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1453 | int handled = 0; |
| 1454 | |
Russell King | 963cc98 | 2010-12-22 17:16:09 +0000 | [diff] [blame] | 1455 | spin_lock_irqsave(&uap->port.lock, flags); |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1456 | imsc = pl011_read(uap, REG_IMSC); |
| 1457 | status = pl011_read(uap, REG_RIS) & imsc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1458 | if (status) { |
| 1459 | do { |
Andre Przywara | 9c4ef4b | 2015-05-21 17:26:20 +0100 | [diff] [blame] | 1460 | check_apply_cts_event_workaround(uap); |
Greg Kroah-Hartman | f11c984 | 2015-09-04 09:13:39 -0700 | [diff] [blame] | 1461 | |
Russell King | 7583633 | 2015-11-03 14:50:58 +0000 | [diff] [blame] | 1462 | pl011_write(status & ~(UART011_TXIS|UART011_RTIS| |
| 1463 | UART011_RXIS), |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1464 | uap, REG_ICR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1465 | |
Linus Walleij | ead76f3 | 2011-02-24 13:21:08 +0100 | [diff] [blame] | 1466 | if (status & (UART011_RTIS|UART011_RXIS)) { |
| 1467 | if (pl011_dma_rx_running(uap)) |
| 1468 | pl011_dma_rx_irq(uap); |
| 1469 | else |
| 1470 | pl011_rx_chars(uap); |
| 1471 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1472 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
| 1473 | UART011_CTSMIS|UART011_RIMIS)) |
| 1474 | pl011_modem_status(uap); |
Dave Martin | 1e84d22 | 2015-04-27 16:49:05 +0100 | [diff] [blame] | 1475 | if (status & UART011_TXIS) |
| 1476 | pl011_tx_chars(uap, true); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1477 | |
Rajanikanth H.V | 4fd0690 | 2012-03-26 11:17:02 +0200 | [diff] [blame] | 1478 | if (pass_counter-- == 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1479 | break; |
| 1480 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1481 | status = pl011_read(uap, REG_RIS) & imsc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1482 | } while (status != 0); |
| 1483 | handled = 1; |
| 1484 | } |
| 1485 | |
Russell King | 963cc98 | 2010-12-22 17:16:09 +0000 | [diff] [blame] | 1486 | spin_unlock_irqrestore(&uap->port.lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1487 | |
| 1488 | return IRQ_RETVAL(handled); |
| 1489 | } |
| 1490 | |
Linus Walleij | e643f87 | 2012-06-17 15:44:19 +0200 | [diff] [blame] | 1491 | static unsigned int pl011_tx_empty(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1492 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 1493 | struct uart_amba_port *uap = |
| 1494 | container_of(port, struct uart_amba_port, port); |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1495 | unsigned int status = pl011_read(uap, REG_FR); |
Greg Kroah-Hartman | 062a68a | 2015-09-04 09:11:24 -0700 | [diff] [blame] | 1496 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1497 | } |
| 1498 | |
Linus Walleij | e643f87 | 2012-06-17 15:44:19 +0200 | [diff] [blame] | 1499 | static unsigned int pl011_get_mctrl(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1500 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 1501 | struct uart_amba_port *uap = |
| 1502 | container_of(port, struct uart_amba_port, port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1503 | unsigned int result = 0; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1504 | unsigned int status = pl011_read(uap, REG_FR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1505 | |
Jiri Slaby | 5159f40 | 2007-10-18 23:40:31 -0700 | [diff] [blame] | 1506 | #define TIOCMBIT(uartbit, tiocmbit) \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1507 | if (status & uartbit) \ |
| 1508 | result |= tiocmbit |
| 1509 | |
Jiri Slaby | 5159f40 | 2007-10-18 23:40:31 -0700 | [diff] [blame] | 1510 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
Greg Kroah-Hartman | 062a68a | 2015-09-04 09:11:24 -0700 | [diff] [blame] | 1511 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); |
| 1512 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); |
| 1513 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); |
Jiri Slaby | 5159f40 | 2007-10-18 23:40:31 -0700 | [diff] [blame] | 1514 | #undef TIOCMBIT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1515 | return result; |
| 1516 | } |
| 1517 | |
| 1518 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) |
| 1519 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 1520 | struct uart_amba_port *uap = |
| 1521 | container_of(port, struct uart_amba_port, port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1522 | unsigned int cr; |
| 1523 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1524 | cr = pl011_read(uap, REG_CR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1525 | |
Jiri Slaby | 5159f40 | 2007-10-18 23:40:31 -0700 | [diff] [blame] | 1526 | #define TIOCMBIT(tiocmbit, uartbit) \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1527 | if (mctrl & tiocmbit) \ |
| 1528 | cr |= uartbit; \ |
| 1529 | else \ |
| 1530 | cr &= ~uartbit |
| 1531 | |
Jiri Slaby | 5159f40 | 2007-10-18 23:40:31 -0700 | [diff] [blame] | 1532 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
| 1533 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); |
| 1534 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); |
| 1535 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); |
| 1536 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); |
Rabin Vincent | 3b43816 | 2010-02-12 06:43:11 +0100 | [diff] [blame] | 1537 | |
| 1538 | if (uap->autorts) { |
| 1539 | /* We need to disable auto-RTS if we want to turn RTS off */ |
| 1540 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); |
| 1541 | } |
Jiri Slaby | 5159f40 | 2007-10-18 23:40:31 -0700 | [diff] [blame] | 1542 | #undef TIOCMBIT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1543 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1544 | pl011_write(cr, uap, REG_CR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1545 | } |
| 1546 | |
| 1547 | static void pl011_break_ctl(struct uart_port *port, int break_state) |
| 1548 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 1549 | struct uart_amba_port *uap = |
| 1550 | container_of(port, struct uart_amba_port, port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1551 | unsigned long flags; |
| 1552 | unsigned int lcr_h; |
| 1553 | |
| 1554 | spin_lock_irqsave(&uap->port.lock, flags); |
Russell King | e4df9a8 | 2015-11-16 17:40:41 +0000 | [diff] [blame] | 1555 | lcr_h = pl011_read(uap, REG_LCRH_TX); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1556 | if (break_state == -1) |
| 1557 | lcr_h |= UART01x_LCRH_BRK; |
| 1558 | else |
| 1559 | lcr_h &= ~UART01x_LCRH_BRK; |
Russell King | e4df9a8 | 2015-11-16 17:40:41 +0000 | [diff] [blame] | 1560 | pl011_write(lcr_h, uap, REG_LCRH_TX); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1561 | spin_unlock_irqrestore(&uap->port.lock, flags); |
| 1562 | } |
| 1563 | |
Jason Wessel | 84b5ae1 | 2008-02-20 13:33:39 -0600 | [diff] [blame] | 1564 | #ifdef CONFIG_CONSOLE_POLL |
Anton Vorontsov | 5c8124a | 2012-09-24 14:27:55 -0700 | [diff] [blame] | 1565 | |
| 1566 | static void pl011_quiesce_irqs(struct uart_port *port) |
| 1567 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 1568 | struct uart_amba_port *uap = |
| 1569 | container_of(port, struct uart_amba_port, port); |
Anton Vorontsov | 5c8124a | 2012-09-24 14:27:55 -0700 | [diff] [blame] | 1570 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1571 | pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); |
Anton Vorontsov | 5c8124a | 2012-09-24 14:27:55 -0700 | [diff] [blame] | 1572 | /* |
| 1573 | * There is no way to clear TXIM as this is "ready to transmit IRQ", so |
| 1574 | * we simply mask it. start_tx() will unmask it. |
| 1575 | * |
| 1576 | * Note we can race with start_tx(), and if the race happens, the |
| 1577 | * polling user might get another interrupt just after we clear it. |
| 1578 | * But it should be OK and can happen even w/o the race, e.g. |
| 1579 | * controller immediately got some new data and raised the IRQ. |
| 1580 | * |
| 1581 | * And whoever uses polling routines assumes that it manages the device |
| 1582 | * (including tx queue), so we're also fine with start_tx()'s caller |
| 1583 | * side. |
| 1584 | */ |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1585 | pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, |
| 1586 | REG_IMSC); |
Anton Vorontsov | 5c8124a | 2012-09-24 14:27:55 -0700 | [diff] [blame] | 1587 | } |
| 1588 | |
Linus Walleij | e643f87 | 2012-06-17 15:44:19 +0200 | [diff] [blame] | 1589 | static int pl011_get_poll_char(struct uart_port *port) |
Jason Wessel | 84b5ae1 | 2008-02-20 13:33:39 -0600 | [diff] [blame] | 1590 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 1591 | struct uart_amba_port *uap = |
| 1592 | container_of(port, struct uart_amba_port, port); |
Jason Wessel | 84b5ae1 | 2008-02-20 13:33:39 -0600 | [diff] [blame] | 1593 | unsigned int status; |
| 1594 | |
Anton Vorontsov | 5c8124a | 2012-09-24 14:27:55 -0700 | [diff] [blame] | 1595 | /* |
| 1596 | * The caller might need IRQs lowered, e.g. if used with KDB NMI |
| 1597 | * debugger. |
| 1598 | */ |
| 1599 | pl011_quiesce_irqs(port); |
| 1600 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1601 | status = pl011_read(uap, REG_FR); |
Jason Wessel | f5316b4 | 2010-05-20 21:04:22 -0500 | [diff] [blame] | 1602 | if (status & UART01x_FR_RXFE) |
| 1603 | return NO_POLL_CHAR; |
Jason Wessel | 84b5ae1 | 2008-02-20 13:33:39 -0600 | [diff] [blame] | 1604 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1605 | return pl011_read(uap, REG_DR); |
Jason Wessel | 84b5ae1 | 2008-02-20 13:33:39 -0600 | [diff] [blame] | 1606 | } |
| 1607 | |
Linus Walleij | e643f87 | 2012-06-17 15:44:19 +0200 | [diff] [blame] | 1608 | static void pl011_put_poll_char(struct uart_port *port, |
Jason Wessel | 84b5ae1 | 2008-02-20 13:33:39 -0600 | [diff] [blame] | 1609 | unsigned char ch) |
| 1610 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 1611 | struct uart_amba_port *uap = |
| 1612 | container_of(port, struct uart_amba_port, port); |
Jason Wessel | 84b5ae1 | 2008-02-20 13:33:39 -0600 | [diff] [blame] | 1613 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1614 | while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) |
Timur Tabi | 2f2fd08 | 2016-01-15 14:32:20 -0600 | [diff] [blame] | 1615 | cpu_relax(); |
Jason Wessel | 84b5ae1 | 2008-02-20 13:33:39 -0600 | [diff] [blame] | 1616 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1617 | pl011_write(ch, uap, REG_DR); |
Jason Wessel | 84b5ae1 | 2008-02-20 13:33:39 -0600 | [diff] [blame] | 1618 | } |
| 1619 | |
| 1620 | #endif /* CONFIG_CONSOLE_POLL */ |
| 1621 | |
Anton Vorontsov | b3564c2 | 2012-09-24 14:27:54 -0700 | [diff] [blame] | 1622 | static int pl011_hwinit(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1623 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 1624 | struct uart_amba_port *uap = |
| 1625 | container_of(port, struct uart_amba_port, port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1626 | int retval; |
| 1627 | |
Linus Walleij | 78d80c5 | 2012-05-23 21:18:46 +0200 | [diff] [blame] | 1628 | /* Optionaly enable pins to be muxed in and configured */ |
Linus Walleij | 2b996fc | 2013-06-05 15:36:42 +0200 | [diff] [blame] | 1629 | pinctrl_pm_select_default_state(port->dev); |
Linus Walleij | 78d80c5 | 2012-05-23 21:18:46 +0200 | [diff] [blame] | 1630 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1631 | /* |
| 1632 | * Try to enable the clock producer. |
| 1633 | */ |
Julia Lawall | 1c4c439 | 2012-08-26 18:01:01 +0200 | [diff] [blame] | 1634 | retval = clk_prepare_enable(uap->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1635 | if (retval) |
Tushar Behera | 7f6d942 | 2014-06-26 15:35:35 +0530 | [diff] [blame] | 1636 | return retval; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1637 | |
| 1638 | uap->port.uartclk = clk_get_rate(uap->clk); |
| 1639 | |
Linus Walleij | 9b96fba | 2012-03-13 13:27:23 +0100 | [diff] [blame] | 1640 | /* Clear pending error and receive interrupts */ |
Russell King | 7583633 | 2015-11-03 14:50:58 +0000 | [diff] [blame] | 1641 | pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | |
| 1642 | UART011_FEIS | UART011_RTIS | UART011_RXIS, |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1643 | uap, REG_ICR); |
Linus Walleij | 9b96fba | 2012-03-13 13:27:23 +0100 | [diff] [blame] | 1644 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1645 | /* |
Anton Vorontsov | b3564c2 | 2012-09-24 14:27:54 -0700 | [diff] [blame] | 1646 | * Save interrupts enable mask, and enable RX interrupts in case if |
| 1647 | * the interrupt is used for NMI entry. |
| 1648 | */ |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1649 | uap->im = pl011_read(uap, REG_IMSC); |
| 1650 | pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); |
Anton Vorontsov | b3564c2 | 2012-09-24 14:27:54 -0700 | [diff] [blame] | 1651 | |
Jingoo Han | 574de55 | 2013-07-30 17:06:57 +0900 | [diff] [blame] | 1652 | if (dev_get_platdata(uap->port.dev)) { |
Anton Vorontsov | b3564c2 | 2012-09-24 14:27:54 -0700 | [diff] [blame] | 1653 | struct amba_pl011_data *plat; |
| 1654 | |
Jingoo Han | 574de55 | 2013-07-30 17:06:57 +0900 | [diff] [blame] | 1655 | plat = dev_get_platdata(uap->port.dev); |
Anton Vorontsov | b3564c2 | 2012-09-24 14:27:54 -0700 | [diff] [blame] | 1656 | if (plat->init) |
| 1657 | plat->init(); |
| 1658 | } |
| 1659 | return 0; |
Anton Vorontsov | b3564c2 | 2012-09-24 14:27:54 -0700 | [diff] [blame] | 1660 | } |
| 1661 | |
Russell King | 7fe9a5a | 2015-11-03 14:51:08 +0000 | [diff] [blame] | 1662 | static bool pl011_split_lcrh(const struct uart_amba_port *uap) |
| 1663 | { |
Russell King | e4df9a8 | 2015-11-16 17:40:41 +0000 | [diff] [blame] | 1664 | return pl011_reg_to_offset(uap, REG_LCRH_RX) != |
| 1665 | pl011_reg_to_offset(uap, REG_LCRH_TX); |
Russell King | 7fe9a5a | 2015-11-03 14:51:08 +0000 | [diff] [blame] | 1666 | } |
| 1667 | |
Jon Medhurst | b60f2f6 | 2013-12-10 10:18:59 +0000 | [diff] [blame] | 1668 | static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) |
| 1669 | { |
Russell King | e4df9a8 | 2015-11-16 17:40:41 +0000 | [diff] [blame] | 1670 | pl011_write(lcr_h, uap, REG_LCRH_RX); |
Russell King | 7fe9a5a | 2015-11-03 14:51:08 +0000 | [diff] [blame] | 1671 | if (pl011_split_lcrh(uap)) { |
Jon Medhurst | b60f2f6 | 2013-12-10 10:18:59 +0000 | [diff] [blame] | 1672 | int i; |
| 1673 | /* |
| 1674 | * Wait 10 PCLKs before writing LCRH_TX register, |
| 1675 | * to get this delay write read only register 10 times |
| 1676 | */ |
| 1677 | for (i = 0; i < 10; ++i) |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1678 | pl011_write(0xff, uap, REG_MIS); |
Russell King | e4df9a8 | 2015-11-16 17:40:41 +0000 | [diff] [blame] | 1679 | pl011_write(lcr_h, uap, REG_LCRH_TX); |
Jon Medhurst | b60f2f6 | 2013-12-10 10:18:59 +0000 | [diff] [blame] | 1680 | } |
| 1681 | } |
| 1682 | |
Andre Przywara | 867b8e8 | 2015-05-21 17:26:15 +0100 | [diff] [blame] | 1683 | static int pl011_allocate_irq(struct uart_amba_port *uap) |
| 1684 | { |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1685 | pl011_write(uap->im, uap, REG_IMSC); |
Andre Przywara | 867b8e8 | 2015-05-21 17:26:15 +0100 | [diff] [blame] | 1686 | |
| 1687 | return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); |
| 1688 | } |
| 1689 | |
| 1690 | /* |
| 1691 | * Enable interrupts, only timeouts when using DMA |
| 1692 | * if initial RX DMA job failed, start in interrupt mode |
| 1693 | * as well. |
| 1694 | */ |
| 1695 | static void pl011_enable_interrupts(struct uart_amba_port *uap) |
| 1696 | { |
| 1697 | spin_lock_irq(&uap->port.lock); |
| 1698 | |
| 1699 | /* Clear out any spuriously appearing RX interrupts */ |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1700 | pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); |
Andre Przywara | 867b8e8 | 2015-05-21 17:26:15 +0100 | [diff] [blame] | 1701 | uap->im = UART011_RTIM; |
| 1702 | if (!pl011_dma_rx_running(uap)) |
| 1703 | uap->im |= UART011_RXIM; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1704 | pl011_write(uap->im, uap, REG_IMSC); |
Andre Przywara | 867b8e8 | 2015-05-21 17:26:15 +0100 | [diff] [blame] | 1705 | spin_unlock_irq(&uap->port.lock); |
| 1706 | } |
| 1707 | |
Anton Vorontsov | b3564c2 | 2012-09-24 14:27:54 -0700 | [diff] [blame] | 1708 | static int pl011_startup(struct uart_port *port) |
| 1709 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 1710 | struct uart_amba_port *uap = |
| 1711 | container_of(port, struct uart_amba_port, port); |
Dave Martin | 734745c | 2015-03-04 12:27:33 +0000 | [diff] [blame] | 1712 | unsigned int cr; |
Anton Vorontsov | b3564c2 | 2012-09-24 14:27:54 -0700 | [diff] [blame] | 1713 | int retval; |
| 1714 | |
| 1715 | retval = pl011_hwinit(port); |
| 1716 | if (retval) |
| 1717 | goto clk_dis; |
| 1718 | |
Andre Przywara | 867b8e8 | 2015-05-21 17:26:15 +0100 | [diff] [blame] | 1719 | retval = pl011_allocate_irq(uap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1720 | if (retval) |
| 1721 | goto clk_dis; |
| 1722 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1723 | pl011_write(uap->vendor->ifls, uap, REG_IFLS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1724 | |
Jon Medhurst | fe43390 | 2013-12-10 10:18:58 +0000 | [diff] [blame] | 1725 | spin_lock_irq(&uap->port.lock); |
| 1726 | |
Shreshtha Kumar Sahu | d8d8ffa | 2012-01-18 15:53:59 +0530 | [diff] [blame] | 1727 | /* restore RTS and DTR */ |
| 1728 | cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); |
| 1729 | cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1730 | pl011_write(cr, uap, REG_CR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1731 | |
Jon Medhurst | fe43390 | 2013-12-10 10:18:58 +0000 | [diff] [blame] | 1732 | spin_unlock_irq(&uap->port.lock); |
| 1733 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1734 | /* |
| 1735 | * initialise the old status of the modem signals |
| 1736 | */ |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1737 | uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1738 | |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 1739 | /* Startup DMA */ |
| 1740 | pl011_dma_startup(uap); |
| 1741 | |
Andre Przywara | 867b8e8 | 2015-05-21 17:26:15 +0100 | [diff] [blame] | 1742 | pl011_enable_interrupts(uap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1743 | |
| 1744 | return 0; |
| 1745 | |
| 1746 | clk_dis: |
Julia Lawall | 1c4c439 | 2012-08-26 18:01:01 +0200 | [diff] [blame] | 1747 | clk_disable_unprepare(uap->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1748 | return retval; |
| 1749 | } |
| 1750 | |
Andre Przywara | 0dd1e24 | 2015-05-21 17:26:23 +0100 | [diff] [blame] | 1751 | static int sbsa_uart_startup(struct uart_port *port) |
| 1752 | { |
| 1753 | struct uart_amba_port *uap = |
| 1754 | container_of(port, struct uart_amba_port, port); |
| 1755 | int retval; |
| 1756 | |
| 1757 | retval = pl011_hwinit(port); |
| 1758 | if (retval) |
| 1759 | return retval; |
| 1760 | |
| 1761 | retval = pl011_allocate_irq(uap); |
| 1762 | if (retval) |
| 1763 | return retval; |
| 1764 | |
| 1765 | /* The SBSA UART does not support any modem status lines. */ |
| 1766 | uap->old_status = 0; |
| 1767 | |
| 1768 | pl011_enable_interrupts(uap); |
| 1769 | |
| 1770 | return 0; |
| 1771 | } |
| 1772 | |
Linus Walleij | ec489aa | 2010-06-02 08:13:52 +0100 | [diff] [blame] | 1773 | static void pl011_shutdown_channel(struct uart_amba_port *uap, |
| 1774 | unsigned int lcrh) |
| 1775 | { |
Greg Kroah-Hartman | f11c984 | 2015-09-04 09:13:39 -0700 | [diff] [blame] | 1776 | unsigned long val; |
Linus Walleij | ec489aa | 2010-06-02 08:13:52 +0100 | [diff] [blame] | 1777 | |
Russell King | b2a4e24 | 2015-11-03 14:51:03 +0000 | [diff] [blame] | 1778 | val = pl011_read(uap, lcrh); |
Greg Kroah-Hartman | f11c984 | 2015-09-04 09:13:39 -0700 | [diff] [blame] | 1779 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); |
Russell King | b2a4e24 | 2015-11-03 14:51:03 +0000 | [diff] [blame] | 1780 | pl011_write(val, uap, lcrh); |
Linus Walleij | ec489aa | 2010-06-02 08:13:52 +0100 | [diff] [blame] | 1781 | } |
| 1782 | |
Andre Przywara | 95166a3 | 2015-05-21 17:26:16 +0100 | [diff] [blame] | 1783 | /* |
| 1784 | * disable the port. It should not disable RTS and DTR. |
| 1785 | * Also RTS and DTR state should be preserved to restore |
| 1786 | * it during startup(). |
| 1787 | */ |
| 1788 | static void pl011_disable_uart(struct uart_amba_port *uap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1789 | { |
Shreshtha Kumar Sahu | d8d8ffa | 2012-01-18 15:53:59 +0530 | [diff] [blame] | 1790 | unsigned int cr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1791 | |
Rabin Vincent | 3b43816 | 2010-02-12 06:43:11 +0100 | [diff] [blame] | 1792 | uap->autorts = false; |
Jon Medhurst | fe43390 | 2013-12-10 10:18:58 +0000 | [diff] [blame] | 1793 | spin_lock_irq(&uap->port.lock); |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1794 | cr = pl011_read(uap, REG_CR); |
Shreshtha Kumar Sahu | d8d8ffa | 2012-01-18 15:53:59 +0530 | [diff] [blame] | 1795 | uap->old_cr = cr; |
| 1796 | cr &= UART011_CR_RTS | UART011_CR_DTR; |
| 1797 | cr |= UART01x_CR_UARTEN | UART011_CR_TXE; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1798 | pl011_write(cr, uap, REG_CR); |
Jon Medhurst | fe43390 | 2013-12-10 10:18:58 +0000 | [diff] [blame] | 1799 | spin_unlock_irq(&uap->port.lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1800 | |
| 1801 | /* |
| 1802 | * disable break condition and fifos |
| 1803 | */ |
Russell King | e4df9a8 | 2015-11-16 17:40:41 +0000 | [diff] [blame] | 1804 | pl011_shutdown_channel(uap, REG_LCRH_RX); |
Russell King | 7fe9a5a | 2015-11-03 14:51:08 +0000 | [diff] [blame] | 1805 | if (pl011_split_lcrh(uap)) |
Russell King | e4df9a8 | 2015-11-16 17:40:41 +0000 | [diff] [blame] | 1806 | pl011_shutdown_channel(uap, REG_LCRH_TX); |
Andre Przywara | 95166a3 | 2015-05-21 17:26:16 +0100 | [diff] [blame] | 1807 | } |
| 1808 | |
| 1809 | static void pl011_disable_interrupts(struct uart_amba_port *uap) |
| 1810 | { |
| 1811 | spin_lock_irq(&uap->port.lock); |
| 1812 | |
| 1813 | /* mask all interrupts and clear all pending ones */ |
| 1814 | uap->im = 0; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1815 | pl011_write(uap->im, uap, REG_IMSC); |
| 1816 | pl011_write(0xffff, uap, REG_ICR); |
Andre Przywara | 95166a3 | 2015-05-21 17:26:16 +0100 | [diff] [blame] | 1817 | |
| 1818 | spin_unlock_irq(&uap->port.lock); |
| 1819 | } |
| 1820 | |
| 1821 | static void pl011_shutdown(struct uart_port *port) |
| 1822 | { |
| 1823 | struct uart_amba_port *uap = |
| 1824 | container_of(port, struct uart_amba_port, port); |
| 1825 | |
| 1826 | pl011_disable_interrupts(uap); |
| 1827 | |
| 1828 | pl011_dma_shutdown(uap); |
| 1829 | |
| 1830 | free_irq(uap->port.irq, uap); |
| 1831 | |
| 1832 | pl011_disable_uart(uap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1833 | |
| 1834 | /* |
| 1835 | * Shut down the clock producer |
| 1836 | */ |
Julia Lawall | 1c4c439 | 2012-08-26 18:01:01 +0200 | [diff] [blame] | 1837 | clk_disable_unprepare(uap->clk); |
Linus Walleij | 78d80c5 | 2012-05-23 21:18:46 +0200 | [diff] [blame] | 1838 | /* Optionally let pins go into sleep states */ |
Linus Walleij | 2b996fc | 2013-06-05 15:36:42 +0200 | [diff] [blame] | 1839 | pinctrl_pm_select_sleep_state(port->dev); |
Shreshtha Kumar Sahu | c16d51a | 2011-06-13 10:11:33 +0200 | [diff] [blame] | 1840 | |
Jingoo Han | 574de55 | 2013-07-30 17:06:57 +0900 | [diff] [blame] | 1841 | if (dev_get_platdata(uap->port.dev)) { |
Shreshtha Kumar Sahu | c16d51a | 2011-06-13 10:11:33 +0200 | [diff] [blame] | 1842 | struct amba_pl011_data *plat; |
| 1843 | |
Jingoo Han | 574de55 | 2013-07-30 17:06:57 +0900 | [diff] [blame] | 1844 | plat = dev_get_platdata(uap->port.dev); |
Shreshtha Kumar Sahu | c16d51a | 2011-06-13 10:11:33 +0200 | [diff] [blame] | 1845 | if (plat->exit) |
| 1846 | plat->exit(); |
| 1847 | } |
| 1848 | |
Peter Hurley | 36f339d | 2014-11-06 09:06:12 -0500 | [diff] [blame] | 1849 | if (uap->port.ops->flush_buffer) |
| 1850 | uap->port.ops->flush_buffer(port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1851 | } |
| 1852 | |
Andre Przywara | 0dd1e24 | 2015-05-21 17:26:23 +0100 | [diff] [blame] | 1853 | static void sbsa_uart_shutdown(struct uart_port *port) |
| 1854 | { |
| 1855 | struct uart_amba_port *uap = |
| 1856 | container_of(port, struct uart_amba_port, port); |
| 1857 | |
| 1858 | pl011_disable_interrupts(uap); |
| 1859 | |
| 1860 | free_irq(uap->port.irq, uap); |
| 1861 | |
| 1862 | if (uap->port.ops->flush_buffer) |
| 1863 | uap->port.ops->flush_buffer(port); |
| 1864 | } |
| 1865 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1866 | static void |
Andre Przywara | ef5a935 | 2015-05-21 17:26:17 +0100 | [diff] [blame] | 1867 | pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) |
| 1868 | { |
| 1869 | port->read_status_mask = UART011_DR_OE | 255; |
| 1870 | if (termios->c_iflag & INPCK) |
| 1871 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; |
| 1872 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
| 1873 | port->read_status_mask |= UART011_DR_BE; |
| 1874 | |
| 1875 | /* |
| 1876 | * Characters to ignore |
| 1877 | */ |
| 1878 | port->ignore_status_mask = 0; |
| 1879 | if (termios->c_iflag & IGNPAR) |
| 1880 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; |
| 1881 | if (termios->c_iflag & IGNBRK) { |
| 1882 | port->ignore_status_mask |= UART011_DR_BE; |
| 1883 | /* |
| 1884 | * If we're ignoring parity and break indicators, |
| 1885 | * ignore overruns too (for real raw support). |
| 1886 | */ |
| 1887 | if (termios->c_iflag & IGNPAR) |
| 1888 | port->ignore_status_mask |= UART011_DR_OE; |
| 1889 | } |
| 1890 | |
| 1891 | /* |
| 1892 | * Ignore all characters if CREAD is not set. |
| 1893 | */ |
| 1894 | if ((termios->c_cflag & CREAD) == 0) |
| 1895 | port->ignore_status_mask |= UART_DUMMY_DR_RX; |
| 1896 | } |
| 1897 | |
| 1898 | static void |
Alan Cox | 606d099 | 2006-12-08 02:38:45 -0800 | [diff] [blame] | 1899 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
| 1900 | struct ktermios *old) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1901 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 1902 | struct uart_amba_port *uap = |
| 1903 | container_of(port, struct uart_amba_port, port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1904 | unsigned int lcr_h, old_cr; |
| 1905 | unsigned long flags; |
Russell King | c19f12b | 2010-12-22 17:48:26 +0000 | [diff] [blame] | 1906 | unsigned int baud, quot, clkdiv; |
| 1907 | |
| 1908 | if (uap->vendor->oversampling) |
| 1909 | clkdiv = 8; |
| 1910 | else |
| 1911 | clkdiv = 16; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1912 | |
| 1913 | /* |
| 1914 | * Ask the core to calculate the divisor for us. |
| 1915 | */ |
Linus Walleij | ac3e3fb | 2010-06-02 20:40:22 +0100 | [diff] [blame] | 1916 | baud = uart_get_baud_rate(port, termios, old, 0, |
Russell King | c19f12b | 2010-12-22 17:48:26 +0000 | [diff] [blame] | 1917 | port->uartclk / clkdiv); |
Chanho Min | 89fa28d | 2013-04-03 11:10:37 +0900 | [diff] [blame] | 1918 | #ifdef CONFIG_DMA_ENGINE |
Chanho Min | cb06ff1 | 2013-03-27 18:38:11 +0900 | [diff] [blame] | 1919 | /* |
| 1920 | * Adjust RX DMA polling rate with baud rate if not specified. |
| 1921 | */ |
| 1922 | if (uap->dmarx.auto_poll_rate) |
| 1923 | uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); |
Chanho Min | 89fa28d | 2013-04-03 11:10:37 +0900 | [diff] [blame] | 1924 | #endif |
Linus Walleij | ac3e3fb | 2010-06-02 20:40:22 +0100 | [diff] [blame] | 1925 | |
| 1926 | if (baud > port->uartclk/16) |
| 1927 | quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); |
| 1928 | else |
| 1929 | quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1930 | |
| 1931 | switch (termios->c_cflag & CSIZE) { |
| 1932 | case CS5: |
| 1933 | lcr_h = UART01x_LCRH_WLEN_5; |
| 1934 | break; |
| 1935 | case CS6: |
| 1936 | lcr_h = UART01x_LCRH_WLEN_6; |
| 1937 | break; |
| 1938 | case CS7: |
| 1939 | lcr_h = UART01x_LCRH_WLEN_7; |
| 1940 | break; |
| 1941 | default: // CS8 |
| 1942 | lcr_h = UART01x_LCRH_WLEN_8; |
| 1943 | break; |
| 1944 | } |
| 1945 | if (termios->c_cflag & CSTOPB) |
| 1946 | lcr_h |= UART01x_LCRH_STP2; |
| 1947 | if (termios->c_cflag & PARENB) { |
| 1948 | lcr_h |= UART01x_LCRH_PEN; |
| 1949 | if (!(termios->c_cflag & PARODD)) |
| 1950 | lcr_h |= UART01x_LCRH_EPS; |
Ed Spiridonov | bb70002 | 2016-03-04 08:11:53 +0300 | [diff] [blame] | 1951 | if (termios->c_cflag & CMSPAR) |
| 1952 | lcr_h |= UART011_LCRH_SPS; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1953 | } |
Russell King | ffca2b1 | 2010-12-22 17:13:05 +0000 | [diff] [blame] | 1954 | if (uap->fifosize > 1) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1955 | lcr_h |= UART01x_LCRH_FEN; |
| 1956 | |
| 1957 | spin_lock_irqsave(&port->lock, flags); |
| 1958 | |
| 1959 | /* |
| 1960 | * Update the per-port timeout. |
| 1961 | */ |
| 1962 | uart_update_timeout(port, termios->c_cflag, baud); |
| 1963 | |
Andre Przywara | ef5a935 | 2015-05-21 17:26:17 +0100 | [diff] [blame] | 1964 | pl011_setup_status_masks(port, termios); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1965 | |
| 1966 | if (UART_ENABLE_MS(port, termios->c_cflag)) |
| 1967 | pl011_enable_ms(port); |
| 1968 | |
| 1969 | /* first, disable everything */ |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 1970 | old_cr = pl011_read(uap, REG_CR); |
| 1971 | pl011_write(0, uap, REG_CR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1972 | |
Rabin Vincent | 3b43816 | 2010-02-12 06:43:11 +0100 | [diff] [blame] | 1973 | if (termios->c_cflag & CRTSCTS) { |
| 1974 | if (old_cr & UART011_CR_RTS) |
| 1975 | old_cr |= UART011_CR_RTSEN; |
| 1976 | |
| 1977 | old_cr |= UART011_CR_CTSEN; |
| 1978 | uap->autorts = true; |
| 1979 | } else { |
| 1980 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); |
| 1981 | uap->autorts = false; |
| 1982 | } |
| 1983 | |
Russell King | c19f12b | 2010-12-22 17:48:26 +0000 | [diff] [blame] | 1984 | if (uap->vendor->oversampling) { |
| 1985 | if (baud > port->uartclk / 16) |
Linus Walleij | ac3e3fb | 2010-06-02 20:40:22 +0100 | [diff] [blame] | 1986 | old_cr |= ST_UART011_CR_OVSFACT; |
| 1987 | else |
| 1988 | old_cr &= ~ST_UART011_CR_OVSFACT; |
| 1989 | } |
| 1990 | |
Linus Walleij | c5dd553 | 2012-09-26 17:21:36 +0200 | [diff] [blame] | 1991 | /* |
| 1992 | * Workaround for the ST Micro oversampling variants to |
| 1993 | * increase the bitrate slightly, by lowering the divisor, |
| 1994 | * to avoid delayed sampling of start bit at high speeds, |
| 1995 | * else we see data corruption. |
| 1996 | */ |
| 1997 | if (uap->vendor->oversampling) { |
| 1998 | if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) |
| 1999 | quot -= 1; |
| 2000 | else if ((baud > 3250000) && (quot > 2)) |
| 2001 | quot -= 2; |
| 2002 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2003 | /* Set baud rate */ |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 2004 | pl011_write(quot & 0x3f, uap, REG_FBRD); |
| 2005 | pl011_write(quot >> 6, uap, REG_IBRD); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2006 | |
| 2007 | /* |
| 2008 | * ----------v----------v----------v----------v----- |
Russell King | e4df9a8 | 2015-11-16 17:40:41 +0000 | [diff] [blame] | 2009 | * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 2010 | * REG_FBRD & REG_IBRD. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2011 | * ----------^----------^----------^----------^----- |
| 2012 | */ |
Jon Medhurst | b60f2f6 | 2013-12-10 10:18:59 +0000 | [diff] [blame] | 2013 | pl011_write_lcr_h(uap, lcr_h); |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 2014 | pl011_write(old_cr, uap, REG_CR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2015 | |
| 2016 | spin_unlock_irqrestore(&port->lock, flags); |
| 2017 | } |
| 2018 | |
Andre Przywara | 0dd1e24 | 2015-05-21 17:26:23 +0100 | [diff] [blame] | 2019 | static void |
| 2020 | sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, |
| 2021 | struct ktermios *old) |
| 2022 | { |
| 2023 | struct uart_amba_port *uap = |
| 2024 | container_of(port, struct uart_amba_port, port); |
| 2025 | unsigned long flags; |
| 2026 | |
| 2027 | tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); |
| 2028 | |
| 2029 | /* The SBSA UART only supports 8n1 without hardware flow control. */ |
| 2030 | termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); |
| 2031 | termios->c_cflag &= ~(CMSPAR | CRTSCTS); |
| 2032 | termios->c_cflag |= CS8 | CLOCAL; |
| 2033 | |
| 2034 | spin_lock_irqsave(&port->lock, flags); |
| 2035 | uart_update_timeout(port, CS8, uap->fixed_baud); |
| 2036 | pl011_setup_status_masks(port, termios); |
| 2037 | spin_unlock_irqrestore(&port->lock, flags); |
| 2038 | } |
| 2039 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2040 | static const char *pl011_type(struct uart_port *port) |
| 2041 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 2042 | struct uart_amba_port *uap = |
| 2043 | container_of(port, struct uart_amba_port, port); |
Russell King | e8a7ba8 | 2010-12-28 09:16:54 +0000 | [diff] [blame] | 2044 | return uap->port.type == PORT_AMBA ? uap->type : NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2045 | } |
| 2046 | |
| 2047 | /* |
| 2048 | * Release the memory region(s) being used by 'port' |
| 2049 | */ |
Linus Walleij | e643f87 | 2012-06-17 15:44:19 +0200 | [diff] [blame] | 2050 | static void pl011_release_port(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2051 | { |
| 2052 | release_mem_region(port->mapbase, SZ_4K); |
| 2053 | } |
| 2054 | |
| 2055 | /* |
| 2056 | * Request the memory region(s) being used by 'port' |
| 2057 | */ |
Linus Walleij | e643f87 | 2012-06-17 15:44:19 +0200 | [diff] [blame] | 2058 | static int pl011_request_port(struct uart_port *port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2059 | { |
| 2060 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") |
| 2061 | != NULL ? 0 : -EBUSY; |
| 2062 | } |
| 2063 | |
| 2064 | /* |
| 2065 | * Configure/autoconfigure the port. |
| 2066 | */ |
Linus Walleij | e643f87 | 2012-06-17 15:44:19 +0200 | [diff] [blame] | 2067 | static void pl011_config_port(struct uart_port *port, int flags) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2068 | { |
| 2069 | if (flags & UART_CONFIG_TYPE) { |
| 2070 | port->type = PORT_AMBA; |
Linus Walleij | e643f87 | 2012-06-17 15:44:19 +0200 | [diff] [blame] | 2071 | pl011_request_port(port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2072 | } |
| 2073 | } |
| 2074 | |
| 2075 | /* |
| 2076 | * verify the new serial_struct (for TIOCSSERIAL). |
| 2077 | */ |
Linus Walleij | e643f87 | 2012-06-17 15:44:19 +0200 | [diff] [blame] | 2078 | static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2079 | { |
| 2080 | int ret = 0; |
| 2081 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) |
| 2082 | ret = -EINVAL; |
Yinghai Lu | a62c413 | 2008-08-19 20:49:55 -0700 | [diff] [blame] | 2083 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2084 | ret = -EINVAL; |
| 2085 | if (ser->baud_base < 9600) |
| 2086 | ret = -EINVAL; |
| 2087 | return ret; |
| 2088 | } |
| 2089 | |
| 2090 | static struct uart_ops amba_pl011_pops = { |
Linus Walleij | e643f87 | 2012-06-17 15:44:19 +0200 | [diff] [blame] | 2091 | .tx_empty = pl011_tx_empty, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2092 | .set_mctrl = pl011_set_mctrl, |
Linus Walleij | e643f87 | 2012-06-17 15:44:19 +0200 | [diff] [blame] | 2093 | .get_mctrl = pl011_get_mctrl, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2094 | .stop_tx = pl011_stop_tx, |
| 2095 | .start_tx = pl011_start_tx, |
| 2096 | .stop_rx = pl011_stop_rx, |
| 2097 | .enable_ms = pl011_enable_ms, |
| 2098 | .break_ctl = pl011_break_ctl, |
| 2099 | .startup = pl011_startup, |
| 2100 | .shutdown = pl011_shutdown, |
Russell King | 68b65f7 | 2010-12-22 17:24:39 +0000 | [diff] [blame] | 2101 | .flush_buffer = pl011_dma_flush_buffer, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2102 | .set_termios = pl011_set_termios, |
| 2103 | .type = pl011_type, |
Linus Walleij | e643f87 | 2012-06-17 15:44:19 +0200 | [diff] [blame] | 2104 | .release_port = pl011_release_port, |
| 2105 | .request_port = pl011_request_port, |
| 2106 | .config_port = pl011_config_port, |
| 2107 | .verify_port = pl011_verify_port, |
Jason Wessel | 84b5ae1 | 2008-02-20 13:33:39 -0600 | [diff] [blame] | 2108 | #ifdef CONFIG_CONSOLE_POLL |
Anton Vorontsov | b3564c2 | 2012-09-24 14:27:54 -0700 | [diff] [blame] | 2109 | .poll_init = pl011_hwinit, |
Linus Walleij | e643f87 | 2012-06-17 15:44:19 +0200 | [diff] [blame] | 2110 | .poll_get_char = pl011_get_poll_char, |
| 2111 | .poll_put_char = pl011_put_poll_char, |
Jason Wessel | 84b5ae1 | 2008-02-20 13:33:39 -0600 | [diff] [blame] | 2112 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2113 | }; |
| 2114 | |
Andre Przywara | 0dd1e24 | 2015-05-21 17:26:23 +0100 | [diff] [blame] | 2115 | static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
| 2116 | { |
| 2117 | } |
| 2118 | |
| 2119 | static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) |
| 2120 | { |
| 2121 | return 0; |
| 2122 | } |
| 2123 | |
| 2124 | static const struct uart_ops sbsa_uart_pops = { |
| 2125 | .tx_empty = pl011_tx_empty, |
| 2126 | .set_mctrl = sbsa_uart_set_mctrl, |
| 2127 | .get_mctrl = sbsa_uart_get_mctrl, |
| 2128 | .stop_tx = pl011_stop_tx, |
| 2129 | .start_tx = pl011_start_tx, |
| 2130 | .stop_rx = pl011_stop_rx, |
| 2131 | .startup = sbsa_uart_startup, |
| 2132 | .shutdown = sbsa_uart_shutdown, |
| 2133 | .set_termios = sbsa_uart_set_termios, |
| 2134 | .type = pl011_type, |
| 2135 | .release_port = pl011_release_port, |
| 2136 | .request_port = pl011_request_port, |
| 2137 | .config_port = pl011_config_port, |
| 2138 | .verify_port = pl011_verify_port, |
| 2139 | #ifdef CONFIG_CONSOLE_POLL |
| 2140 | .poll_init = pl011_hwinit, |
| 2141 | .poll_get_char = pl011_get_poll_char, |
| 2142 | .poll_put_char = pl011_put_poll_char, |
| 2143 | #endif |
| 2144 | }; |
| 2145 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2146 | static struct uart_amba_port *amba_ports[UART_NR]; |
| 2147 | |
| 2148 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE |
| 2149 | |
Russell King | d358788 | 2006-03-20 20:00:09 +0000 | [diff] [blame] | 2150 | static void pl011_console_putchar(struct uart_port *port, int ch) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2151 | { |
Daniel Thompson | a5820c2 | 2014-09-03 12:51:55 +0100 | [diff] [blame] | 2152 | struct uart_amba_port *uap = |
| 2153 | container_of(port, struct uart_amba_port, port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2154 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 2155 | while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) |
Timur Tabi | 2f2fd08 | 2016-01-15 14:32:20 -0600 | [diff] [blame] | 2156 | cpu_relax(); |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 2157 | pl011_write(ch, uap, REG_DR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2158 | } |
| 2159 | |
| 2160 | static void |
| 2161 | pl011_console_write(struct console *co, const char *s, unsigned int count) |
| 2162 | { |
| 2163 | struct uart_amba_port *uap = amba_ports[co->index]; |
Timur Tabi | 2f2fd08 | 2016-01-15 14:32:20 -0600 | [diff] [blame] | 2164 | unsigned int old_cr = 0, new_cr; |
Rabin Vincent | ef605fd | 2012-01-17 11:52:28 +0100 | [diff] [blame] | 2165 | unsigned long flags; |
| 2166 | int locked = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2167 | |
| 2168 | clk_enable(uap->clk); |
| 2169 | |
Rabin Vincent | ef605fd | 2012-01-17 11:52:28 +0100 | [diff] [blame] | 2170 | local_irq_save(flags); |
| 2171 | if (uap->port.sysrq) |
| 2172 | locked = 0; |
| 2173 | else if (oops_in_progress) |
| 2174 | locked = spin_trylock(&uap->port.lock); |
| 2175 | else |
| 2176 | spin_lock(&uap->port.lock); |
| 2177 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2178 | /* |
| 2179 | * First save the CR then disable the interrupts |
| 2180 | */ |
Andre Przywara | 71eec48 | 2015-05-21 17:26:21 +0100 | [diff] [blame] | 2181 | if (!uap->vendor->always_enabled) { |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 2182 | old_cr = pl011_read(uap, REG_CR); |
Andre Przywara | 71eec48 | 2015-05-21 17:26:21 +0100 | [diff] [blame] | 2183 | new_cr = old_cr & ~UART011_CR_CTSEN; |
| 2184 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 2185 | pl011_write(new_cr, uap, REG_CR); |
Andre Przywara | 71eec48 | 2015-05-21 17:26:21 +0100 | [diff] [blame] | 2186 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2187 | |
Russell King | d358788 | 2006-03-20 20:00:09 +0000 | [diff] [blame] | 2188 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2189 | |
| 2190 | /* |
| 2191 | * Finally, wait for transmitter to become empty |
| 2192 | * and restore the TCR |
| 2193 | */ |
Timur Tabi | 2f2fd08 | 2016-01-15 14:32:20 -0600 | [diff] [blame] | 2194 | while (pl011_read(uap, REG_FR) & UART01x_FR_BUSY) |
| 2195 | cpu_relax(); |
Andre Przywara | 71eec48 | 2015-05-21 17:26:21 +0100 | [diff] [blame] | 2196 | if (!uap->vendor->always_enabled) |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 2197 | pl011_write(old_cr, uap, REG_CR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2198 | |
Rabin Vincent | ef605fd | 2012-01-17 11:52:28 +0100 | [diff] [blame] | 2199 | if (locked) |
| 2200 | spin_unlock(&uap->port.lock); |
| 2201 | local_irq_restore(flags); |
| 2202 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2203 | clk_disable(uap->clk); |
| 2204 | } |
| 2205 | |
| 2206 | static void __init |
| 2207 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, |
| 2208 | int *parity, int *bits) |
| 2209 | { |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 2210 | if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2211 | unsigned int lcr_h, ibrd, fbrd; |
| 2212 | |
Russell King | e4df9a8 | 2015-11-16 17:40:41 +0000 | [diff] [blame] | 2213 | lcr_h = pl011_read(uap, REG_LCRH_TX); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2214 | |
| 2215 | *parity = 'n'; |
| 2216 | if (lcr_h & UART01x_LCRH_PEN) { |
| 2217 | if (lcr_h & UART01x_LCRH_EPS) |
| 2218 | *parity = 'e'; |
| 2219 | else |
| 2220 | *parity = 'o'; |
| 2221 | } |
| 2222 | |
| 2223 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) |
| 2224 | *bits = 7; |
| 2225 | else |
| 2226 | *bits = 8; |
| 2227 | |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 2228 | ibrd = pl011_read(uap, REG_IBRD); |
| 2229 | fbrd = pl011_read(uap, REG_FBRD); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2230 | |
| 2231 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); |
Linus Walleij | ac3e3fb | 2010-06-02 20:40:22 +0100 | [diff] [blame] | 2232 | |
Russell King | c19f12b | 2010-12-22 17:48:26 +0000 | [diff] [blame] | 2233 | if (uap->vendor->oversampling) { |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 2234 | if (pl011_read(uap, REG_CR) |
Linus Walleij | ac3e3fb | 2010-06-02 20:40:22 +0100 | [diff] [blame] | 2235 | & ST_UART011_CR_OVSFACT) |
| 2236 | *baud *= 2; |
| 2237 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2238 | } |
| 2239 | } |
| 2240 | |
| 2241 | static int __init pl011_console_setup(struct console *co, char *options) |
| 2242 | { |
| 2243 | struct uart_amba_port *uap; |
| 2244 | int baud = 38400; |
| 2245 | int bits = 8; |
| 2246 | int parity = 'n'; |
| 2247 | int flow = 'n'; |
Russell King | 4b4851c | 2011-09-22 11:35:30 +0100 | [diff] [blame] | 2248 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2249 | |
| 2250 | /* |
| 2251 | * Check whether an invalid uart number has been specified, and |
| 2252 | * if so, search for the first available port that does have |
| 2253 | * console support. |
| 2254 | */ |
| 2255 | if (co->index >= UART_NR) |
| 2256 | co->index = 0; |
| 2257 | uap = amba_ports[co->index]; |
Russell King | d28122a | 2007-01-22 18:59:42 +0000 | [diff] [blame] | 2258 | if (!uap) |
| 2259 | return -ENODEV; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2260 | |
Linus Walleij | 78d80c5 | 2012-05-23 21:18:46 +0200 | [diff] [blame] | 2261 | /* Allow pins to be muxed in and configured */ |
Linus Walleij | 2b996fc | 2013-06-05 15:36:42 +0200 | [diff] [blame] | 2262 | pinctrl_pm_select_default_state(uap->port.dev); |
Linus Walleij | 78d80c5 | 2012-05-23 21:18:46 +0200 | [diff] [blame] | 2263 | |
Russell King | 4b4851c | 2011-09-22 11:35:30 +0100 | [diff] [blame] | 2264 | ret = clk_prepare(uap->clk); |
| 2265 | if (ret) |
| 2266 | return ret; |
| 2267 | |
Jingoo Han | 574de55 | 2013-07-30 17:06:57 +0900 | [diff] [blame] | 2268 | if (dev_get_platdata(uap->port.dev)) { |
Shreshtha Kumar Sahu | c16d51a | 2011-06-13 10:11:33 +0200 | [diff] [blame] | 2269 | struct amba_pl011_data *plat; |
| 2270 | |
Jingoo Han | 574de55 | 2013-07-30 17:06:57 +0900 | [diff] [blame] | 2271 | plat = dev_get_platdata(uap->port.dev); |
Shreshtha Kumar Sahu | c16d51a | 2011-06-13 10:11:33 +0200 | [diff] [blame] | 2272 | if (plat->init) |
| 2273 | plat->init(); |
| 2274 | } |
| 2275 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2276 | uap->port.uartclk = clk_get_rate(uap->clk); |
| 2277 | |
Andre Przywara | cefc2d1 | 2015-05-21 17:26:22 +0100 | [diff] [blame] | 2278 | if (uap->vendor->fixed_options) { |
| 2279 | baud = uap->fixed_baud; |
| 2280 | } else { |
| 2281 | if (options) |
| 2282 | uart_parse_options(options, |
| 2283 | &baud, &parity, &bits, &flow); |
| 2284 | else |
| 2285 | pl011_console_get_options(uap, &baud, &parity, &bits); |
| 2286 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2287 | |
| 2288 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); |
| 2289 | } |
| 2290 | |
Vincent Sanders | 2d93486 | 2005-09-14 22:36:03 +0100 | [diff] [blame] | 2291 | static struct uart_driver amba_reg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2292 | static struct console amba_console = { |
| 2293 | .name = "ttyAMA", |
| 2294 | .write = pl011_console_write, |
| 2295 | .device = uart_console_device, |
| 2296 | .setup = pl011_console_setup, |
| 2297 | .flags = CON_PRINTBUFFER, |
| 2298 | .index = -1, |
| 2299 | .data = &amba_reg, |
| 2300 | }; |
| 2301 | |
| 2302 | #define AMBA_CONSOLE (&amba_console) |
Rob Herring | 0d3c673 | 2014-04-18 17:19:57 -0500 | [diff] [blame] | 2303 | |
| 2304 | static void pl011_putc(struct uart_port *port, int c) |
| 2305 | { |
Russell King | cdf091c | 2016-01-04 15:37:41 -0600 | [diff] [blame] | 2306 | while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) |
Timur Tabi | 2f2fd08 | 2016-01-15 14:32:20 -0600 | [diff] [blame] | 2307 | cpu_relax(); |
Timur Tabi | 3b78fae | 2016-01-04 15:37:42 -0600 | [diff] [blame] | 2308 | if (port->iotype == UPIO_MEM32) |
| 2309 | writel(c, port->membase + UART01x_DR); |
| 2310 | else |
| 2311 | writeb(c, port->membase + UART01x_DR); |
Russell King | cdf091c | 2016-01-04 15:37:41 -0600 | [diff] [blame] | 2312 | while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) |
Timur Tabi | 2f2fd08 | 2016-01-15 14:32:20 -0600 | [diff] [blame] | 2313 | cpu_relax(); |
Rob Herring | 0d3c673 | 2014-04-18 17:19:57 -0500 | [diff] [blame] | 2314 | } |
| 2315 | |
| 2316 | static void pl011_early_write(struct console *con, const char *s, unsigned n) |
| 2317 | { |
| 2318 | struct earlycon_device *dev = con->data; |
| 2319 | |
| 2320 | uart_console_write(&dev->port, s, n, pl011_putc); |
| 2321 | } |
| 2322 | |
| 2323 | static int __init pl011_early_console_setup(struct earlycon_device *device, |
| 2324 | const char *opt) |
| 2325 | { |
| 2326 | if (!device->port.membase) |
| 2327 | return -ENODEV; |
| 2328 | |
| 2329 | device->con->write = pl011_early_write; |
| 2330 | return 0; |
| 2331 | } |
Rob Herring | 45e0f0f | 2014-03-27 08:08:03 -0500 | [diff] [blame] | 2332 | OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); |
Rob Herring | 0d3c673 | 2014-04-18 17:19:57 -0500 | [diff] [blame] | 2333 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2334 | #else |
| 2335 | #define AMBA_CONSOLE NULL |
| 2336 | #endif |
| 2337 | |
| 2338 | static struct uart_driver amba_reg = { |
| 2339 | .owner = THIS_MODULE, |
| 2340 | .driver_name = "ttyAMA", |
| 2341 | .dev_name = "ttyAMA", |
| 2342 | .major = SERIAL_AMBA_MAJOR, |
| 2343 | .minor = SERIAL_AMBA_MINOR, |
| 2344 | .nr = UART_NR, |
| 2345 | .cons = AMBA_CONSOLE, |
| 2346 | }; |
| 2347 | |
Matthew Leach | 32614aa | 2012-08-28 16:41:28 +0100 | [diff] [blame] | 2348 | static int pl011_probe_dt_alias(int index, struct device *dev) |
| 2349 | { |
| 2350 | struct device_node *np; |
| 2351 | static bool seen_dev_with_alias = false; |
| 2352 | static bool seen_dev_without_alias = false; |
| 2353 | int ret = index; |
| 2354 | |
| 2355 | if (!IS_ENABLED(CONFIG_OF)) |
| 2356 | return ret; |
| 2357 | |
| 2358 | np = dev->of_node; |
| 2359 | if (!np) |
| 2360 | return ret; |
| 2361 | |
| 2362 | ret = of_alias_get_id(np, "serial"); |
Arnd Bergmann | 287980e | 2016-05-27 23:23:25 +0200 | [diff] [blame] | 2363 | if (ret < 0) { |
Matthew Leach | 32614aa | 2012-08-28 16:41:28 +0100 | [diff] [blame] | 2364 | seen_dev_without_alias = true; |
| 2365 | ret = index; |
| 2366 | } else { |
| 2367 | seen_dev_with_alias = true; |
| 2368 | if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { |
| 2369 | dev_warn(dev, "requested serial port %d not available.\n", ret); |
| 2370 | ret = index; |
| 2371 | } |
| 2372 | } |
| 2373 | |
| 2374 | if (seen_dev_with_alias && seen_dev_without_alias) |
| 2375 | dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); |
| 2376 | |
| 2377 | return ret; |
| 2378 | } |
| 2379 | |
Andre Przywara | 49bb3c8 | 2015-05-21 17:26:14 +0100 | [diff] [blame] | 2380 | /* unregisters the driver also if no more ports are left */ |
| 2381 | static void pl011_unregister_port(struct uart_amba_port *uap) |
| 2382 | { |
| 2383 | int i; |
| 2384 | bool busy = false; |
| 2385 | |
| 2386 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { |
| 2387 | if (amba_ports[i] == uap) |
| 2388 | amba_ports[i] = NULL; |
| 2389 | else if (amba_ports[i]) |
| 2390 | busy = true; |
| 2391 | } |
| 2392 | pl011_dma_remove(uap); |
| 2393 | if (!busy) |
| 2394 | uart_unregister_driver(&amba_reg); |
| 2395 | } |
| 2396 | |
Andre Przywara | 3873e2d | 2015-05-21 17:26:18 +0100 | [diff] [blame] | 2397 | static int pl011_find_free_port(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2398 | { |
Andre Przywara | 3873e2d | 2015-05-21 17:26:18 +0100 | [diff] [blame] | 2399 | int i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2400 | |
| 2401 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) |
| 2402 | if (amba_ports[i] == NULL) |
Andre Przywara | 3873e2d | 2015-05-21 17:26:18 +0100 | [diff] [blame] | 2403 | return i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2404 | |
Andre Przywara | 3873e2d | 2015-05-21 17:26:18 +0100 | [diff] [blame] | 2405 | return -EBUSY; |
| 2406 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2407 | |
Andre Przywara | 3873e2d | 2015-05-21 17:26:18 +0100 | [diff] [blame] | 2408 | static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, |
| 2409 | struct resource *mmiobase, int index) |
| 2410 | { |
| 2411 | void __iomem *base; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2412 | |
Andre Przywara | 3873e2d | 2015-05-21 17:26:18 +0100 | [diff] [blame] | 2413 | base = devm_ioremap_resource(dev, mmiobase); |
Krzysztof Kozlowski | 97a60ea | 2015-07-09 22:21:41 +0900 | [diff] [blame] | 2414 | if (IS_ERR(base)) |
| 2415 | return PTR_ERR(base); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2416 | |
Andre Przywara | 3873e2d | 2015-05-21 17:26:18 +0100 | [diff] [blame] | 2417 | index = pl011_probe_dt_alias(index, dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2418 | |
Shreshtha Kumar Sahu | d8d8ffa | 2012-01-18 15:53:59 +0530 | [diff] [blame] | 2419 | uap->old_cr = 0; |
Andre Przywara | 3873e2d | 2015-05-21 17:26:18 +0100 | [diff] [blame] | 2420 | uap->port.dev = dev; |
| 2421 | uap->port.mapbase = mmiobase->start; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2422 | uap->port.membase = base; |
Russell King | ffca2b1 | 2010-12-22 17:13:05 +0000 | [diff] [blame] | 2423 | uap->port.fifosize = uap->fifosize; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2424 | uap->port.flags = UPF_BOOT_AUTOCONF; |
Andre Przywara | 3873e2d | 2015-05-21 17:26:18 +0100 | [diff] [blame] | 2425 | uap->port.line = index; |
| 2426 | |
| 2427 | amba_ports[index] = uap; |
| 2428 | |
| 2429 | return 0; |
| 2430 | } |
| 2431 | |
| 2432 | static int pl011_register_port(struct uart_amba_port *uap) |
| 2433 | { |
| 2434 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2435 | |
Linus Walleij | c3d8b76 | 2012-03-21 20:15:18 +0100 | [diff] [blame] | 2436 | /* Ensure interrupts from this UART are masked and cleared */ |
Russell King | 9f25bc5 | 2015-11-03 14:51:13 +0000 | [diff] [blame] | 2437 | pl011_write(0, uap, REG_IMSC); |
| 2438 | pl011_write(0xffff, uap, REG_ICR); |
Linus Walleij | c3d8b76 | 2012-03-21 20:15:18 +0100 | [diff] [blame] | 2439 | |
Tushar Behera | ef2889f | 2014-01-20 14:32:35 +0530 | [diff] [blame] | 2440 | if (!amba_reg.state) { |
| 2441 | ret = uart_register_driver(&amba_reg); |
| 2442 | if (ret < 0) { |
Andre Przywara | 3873e2d | 2015-05-21 17:26:18 +0100 | [diff] [blame] | 2443 | dev_err(uap->port.dev, |
Jorge Ramirez-Ortiz | 1c9be31 | 2015-03-06 13:05:40 -0500 | [diff] [blame] | 2444 | "Failed to register AMBA-PL011 driver\n"); |
Tushar Behera | ef2889f | 2014-01-20 14:32:35 +0530 | [diff] [blame] | 2445 | return ret; |
| 2446 | } |
| 2447 | } |
| 2448 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2449 | ret = uart_add_one_port(&amba_reg, &uap->port); |
Andre Przywara | 49bb3c8 | 2015-05-21 17:26:14 +0100 | [diff] [blame] | 2450 | if (ret) |
| 2451 | pl011_unregister_port(uap); |
Tushar Behera | 7f6d942 | 2014-06-26 15:35:35 +0530 | [diff] [blame] | 2452 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2453 | return ret; |
| 2454 | } |
| 2455 | |
Andre Przywara | 3873e2d | 2015-05-21 17:26:18 +0100 | [diff] [blame] | 2456 | static int pl011_probe(struct amba_device *dev, const struct amba_id *id) |
| 2457 | { |
| 2458 | struct uart_amba_port *uap; |
| 2459 | struct vendor_data *vendor = id->data; |
| 2460 | int portnr, ret; |
| 2461 | |
| 2462 | portnr = pl011_find_free_port(); |
| 2463 | if (portnr < 0) |
| 2464 | return portnr; |
| 2465 | |
| 2466 | uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), |
| 2467 | GFP_KERNEL); |
| 2468 | if (!uap) |
| 2469 | return -ENOMEM; |
| 2470 | |
| 2471 | uap->clk = devm_clk_get(&dev->dev, NULL); |
| 2472 | if (IS_ERR(uap->clk)) |
| 2473 | return PTR_ERR(uap->clk); |
| 2474 | |
Russell King | 439403b | 2015-11-16 17:40:31 +0000 | [diff] [blame] | 2475 | uap->reg_offset = vendor->reg_offset; |
Andre Przywara | 3873e2d | 2015-05-21 17:26:18 +0100 | [diff] [blame] | 2476 | uap->vendor = vendor; |
Andre Przywara | 3873e2d | 2015-05-21 17:26:18 +0100 | [diff] [blame] | 2477 | uap->fifosize = vendor->get_fifosize(dev); |
Timur Tabi | 3b78fae | 2016-01-04 15:37:42 -0600 | [diff] [blame] | 2478 | uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; |
Andre Przywara | 3873e2d | 2015-05-21 17:26:18 +0100 | [diff] [blame] | 2479 | uap->port.irq = dev->irq[0]; |
| 2480 | uap->port.ops = &amba_pl011_pops; |
| 2481 | |
| 2482 | snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); |
| 2483 | |
| 2484 | ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); |
| 2485 | if (ret) |
| 2486 | return ret; |
| 2487 | |
| 2488 | amba_set_drvdata(dev, uap); |
| 2489 | |
| 2490 | return pl011_register_port(uap); |
| 2491 | } |
| 2492 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2493 | static int pl011_remove(struct amba_device *dev) |
| 2494 | { |
| 2495 | struct uart_amba_port *uap = amba_get_drvdata(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2496 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2497 | uart_remove_one_port(&amba_reg, &uap->port); |
Andre Przywara | 49bb3c8 | 2015-05-21 17:26:14 +0100 | [diff] [blame] | 2498 | pl011_unregister_port(uap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2499 | return 0; |
| 2500 | } |
| 2501 | |
Ulf Hansson | d0ce850 | 2013-12-03 11:04:28 +0100 | [diff] [blame] | 2502 | #ifdef CONFIG_PM_SLEEP |
| 2503 | static int pl011_suspend(struct device *dev) |
Leo Chen | b736b89 | 2009-07-28 23:43:33 +0100 | [diff] [blame] | 2504 | { |
Ulf Hansson | d0ce850 | 2013-12-03 11:04:28 +0100 | [diff] [blame] | 2505 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
Leo Chen | b736b89 | 2009-07-28 23:43:33 +0100 | [diff] [blame] | 2506 | |
| 2507 | if (!uap) |
| 2508 | return -EINVAL; |
| 2509 | |
| 2510 | return uart_suspend_port(&amba_reg, &uap->port); |
| 2511 | } |
| 2512 | |
Ulf Hansson | d0ce850 | 2013-12-03 11:04:28 +0100 | [diff] [blame] | 2513 | static int pl011_resume(struct device *dev) |
Leo Chen | b736b89 | 2009-07-28 23:43:33 +0100 | [diff] [blame] | 2514 | { |
Ulf Hansson | d0ce850 | 2013-12-03 11:04:28 +0100 | [diff] [blame] | 2515 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
Leo Chen | b736b89 | 2009-07-28 23:43:33 +0100 | [diff] [blame] | 2516 | |
| 2517 | if (!uap) |
| 2518 | return -EINVAL; |
| 2519 | |
| 2520 | return uart_resume_port(&amba_reg, &uap->port); |
| 2521 | } |
| 2522 | #endif |
| 2523 | |
Ulf Hansson | d0ce850 | 2013-12-03 11:04:28 +0100 | [diff] [blame] | 2524 | static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); |
| 2525 | |
Andre Przywara | 0dd1e24 | 2015-05-21 17:26:23 +0100 | [diff] [blame] | 2526 | static int sbsa_uart_probe(struct platform_device *pdev) |
| 2527 | { |
| 2528 | struct uart_amba_port *uap; |
| 2529 | struct resource *r; |
| 2530 | int portnr, ret; |
| 2531 | int baudrate; |
| 2532 | |
| 2533 | /* |
| 2534 | * Check the mandatory baud rate parameter in the DT node early |
| 2535 | * so that we can easily exit with the error. |
| 2536 | */ |
| 2537 | if (pdev->dev.of_node) { |
| 2538 | struct device_node *np = pdev->dev.of_node; |
| 2539 | |
| 2540 | ret = of_property_read_u32(np, "current-speed", &baudrate); |
| 2541 | if (ret) |
| 2542 | return ret; |
| 2543 | } else { |
| 2544 | baudrate = 115200; |
| 2545 | } |
| 2546 | |
| 2547 | portnr = pl011_find_free_port(); |
| 2548 | if (portnr < 0) |
| 2549 | return portnr; |
| 2550 | |
| 2551 | uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), |
| 2552 | GFP_KERNEL); |
| 2553 | if (!uap) |
| 2554 | return -ENOMEM; |
| 2555 | |
Russell King | 439403b | 2015-11-16 17:40:31 +0000 | [diff] [blame] | 2556 | uap->reg_offset = vendor_sbsa.reg_offset; |
Andre Przywara | 0dd1e24 | 2015-05-21 17:26:23 +0100 | [diff] [blame] | 2557 | uap->vendor = &vendor_sbsa; |
| 2558 | uap->fifosize = 32; |
Timur Tabi | 3b78fae | 2016-01-04 15:37:42 -0600 | [diff] [blame] | 2559 | uap->port.iotype = vendor_sbsa.access_32b ? UPIO_MEM32 : UPIO_MEM; |
Andre Przywara | 0dd1e24 | 2015-05-21 17:26:23 +0100 | [diff] [blame] | 2560 | uap->port.irq = platform_get_irq(pdev, 0); |
| 2561 | uap->port.ops = &sbsa_uart_pops; |
| 2562 | uap->fixed_baud = baudrate; |
| 2563 | |
| 2564 | snprintf(uap->type, sizeof(uap->type), "SBSA"); |
| 2565 | |
| 2566 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 2567 | |
| 2568 | ret = pl011_setup_port(&pdev->dev, uap, r, portnr); |
| 2569 | if (ret) |
| 2570 | return ret; |
| 2571 | |
| 2572 | platform_set_drvdata(pdev, uap); |
| 2573 | |
| 2574 | return pl011_register_port(uap); |
| 2575 | } |
| 2576 | |
| 2577 | static int sbsa_uart_remove(struct platform_device *pdev) |
| 2578 | { |
| 2579 | struct uart_amba_port *uap = platform_get_drvdata(pdev); |
| 2580 | |
| 2581 | uart_remove_one_port(&amba_reg, &uap->port); |
| 2582 | pl011_unregister_port(uap); |
| 2583 | return 0; |
| 2584 | } |
| 2585 | |
| 2586 | static const struct of_device_id sbsa_uart_of_match[] = { |
| 2587 | { .compatible = "arm,sbsa-uart", }, |
| 2588 | {}, |
| 2589 | }; |
| 2590 | MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); |
| 2591 | |
Graeme Gregory | 3db9ab0 | 2015-05-21 17:26:24 +0100 | [diff] [blame] | 2592 | static const struct acpi_device_id sbsa_uart_acpi_match[] = { |
| 2593 | { "ARMH0011", 0 }, |
| 2594 | {}, |
| 2595 | }; |
| 2596 | MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); |
| 2597 | |
Andre Przywara | 0dd1e24 | 2015-05-21 17:26:23 +0100 | [diff] [blame] | 2598 | static struct platform_driver arm_sbsa_uart_platform_driver = { |
| 2599 | .probe = sbsa_uart_probe, |
| 2600 | .remove = sbsa_uart_remove, |
| 2601 | .driver = { |
| 2602 | .name = "sbsa-uart", |
| 2603 | .of_match_table = of_match_ptr(sbsa_uart_of_match), |
Graeme Gregory | 3db9ab0 | 2015-05-21 17:26:24 +0100 | [diff] [blame] | 2604 | .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match), |
Andre Przywara | 0dd1e24 | 2015-05-21 17:26:23 +0100 | [diff] [blame] | 2605 | }, |
| 2606 | }; |
| 2607 | |
Russell King | 2c39c9e | 2010-07-27 08:50:16 +0100 | [diff] [blame] | 2608 | static struct amba_id pl011_ids[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2609 | { |
| 2610 | .id = 0x00041011, |
| 2611 | .mask = 0x000fffff, |
Alessandro Rubini | 5926a29 | 2009-06-04 17:43:04 +0100 | [diff] [blame] | 2612 | .data = &vendor_arm, |
| 2613 | }, |
| 2614 | { |
| 2615 | .id = 0x00380802, |
| 2616 | .mask = 0x00ffffff, |
| 2617 | .data = &vendor_st, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2618 | }, |
| 2619 | { 0, 0 }, |
| 2620 | }; |
| 2621 | |
Dave Martin | 60f7a33 | 2011-10-05 15:15:22 +0100 | [diff] [blame] | 2622 | MODULE_DEVICE_TABLE(amba, pl011_ids); |
| 2623 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2624 | static struct amba_driver pl011_driver = { |
| 2625 | .drv = { |
| 2626 | .name = "uart-pl011", |
Ulf Hansson | d0ce850 | 2013-12-03 11:04:28 +0100 | [diff] [blame] | 2627 | .pm = &pl011_dev_pm_ops, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2628 | }, |
| 2629 | .id_table = pl011_ids, |
| 2630 | .probe = pl011_probe, |
| 2631 | .remove = pl011_remove, |
| 2632 | }; |
| 2633 | |
| 2634 | static int __init pl011_init(void) |
| 2635 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2636 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); |
| 2637 | |
Andre Przywara | 0dd1e24 | 2015-05-21 17:26:23 +0100 | [diff] [blame] | 2638 | if (platform_driver_register(&arm_sbsa_uart_platform_driver)) |
| 2639 | pr_warn("could not register SBSA UART platform driver\n"); |
Greg Kroah-Hartman | 062a68a | 2015-09-04 09:11:24 -0700 | [diff] [blame] | 2640 | return amba_driver_register(&pl011_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2641 | } |
| 2642 | |
| 2643 | static void __exit pl011_exit(void) |
| 2644 | { |
Andre Przywara | 0dd1e24 | 2015-05-21 17:26:23 +0100 | [diff] [blame] | 2645 | platform_driver_unregister(&arm_sbsa_uart_platform_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2646 | amba_driver_unregister(&pl011_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2647 | } |
| 2648 | |
Alessandro Rubini | 4dd9e74 | 2009-05-05 05:54:13 +0100 | [diff] [blame] | 2649 | /* |
| 2650 | * While this can be a module, if builtin it's most likely the console |
| 2651 | * So let's leave module_exit but move module_init to an earlier place |
| 2652 | */ |
| 2653 | arch_initcall(pl011_init); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2654 | module_exit(pl011_exit); |
| 2655 | |
| 2656 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); |
| 2657 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); |
| 2658 | MODULE_LICENSE("GPL"); |