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gerrit-public.fairphone.software / kernel / msm-4.9 / 41844e36206be90cd4d962ea49b0abc3612a99d0 / . / sound / soc / intel / skylake / skl.h
blob: 5d4fbb094c48da9fe238b8c27f09f3c41141d0ed [file] [log] [blame]
Jeeja KPa40e6932015-07-09 15:20:08 +0530[diff] [blame]1/*
2 * skl.h - HD Audio skylake defintions.
3 *
4 * Copyright (C) 2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
18 *
19 */
20
21#ifndef __SOUND_SOC_SKL_H
22#define __SOUND_SOC_SKL_H
23
24#include <sound/hda_register.h>
25#include <sound/hdaudio_ext.h>
Jeeja KP473eb872015-07-21 23:53:55 +0530[diff] [blame]26#include "skl-nhlt.h"
Jeeja KPa40e6932015-07-09 15:20:08 +0530[diff] [blame]27
28#define SKL_SUSPEND_DELAY 2000
29
30/* Vendor Specific Registers */
31#define AZX_REG_VS_EM1 0x1000
32#define AZX_REG_VS_INRC 0x1004
33#define AZX_REG_VS_OUTRC 0x1008
34#define AZX_REG_VS_FIFOTRK 0x100C
35#define AZX_REG_VS_FIFOTRK2 0x1010
36#define AZX_REG_VS_EM2 0x1030
37#define AZX_REG_VS_EM3L 0x1038
38#define AZX_REG_VS_EM3U 0x103C
39#define AZX_REG_VS_EM4L 0x1040
40#define AZX_REG_VS_EM4U 0x1044
41#define AZX_REG_VS_LTRC 0x1048
42#define AZX_REG_VS_D0I3C 0x104A
43#define AZX_REG_VS_PCE 0x104B
44#define AZX_REG_VS_L2MAGC 0x1050
45#define AZX_REG_VS_L2LAHPT 0x1054
46#define AZX_REG_VS_SDXDPIB_XBASE 0x1084
47#define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20
48#define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094
49#define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20
50
Dharageswari R51a01b82016-06-03 18:29:37 +0530[diff] [blame]51#define AZX_PCIREG_PGCTL 0x44
52#define AZX_PGCTL_LSRMD_MASK (1 << 4)
Jayachandran B0c8ba9d2015-12-18 15:12:03 +0530[diff] [blame]53#define AZX_PCIREG_CGCTL 0x48
54#define AZX_CGCTL_MISCBDCGE_MASK (1 << 6)
55
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100[diff] [blame]56struct skl_dsp_resource {
57 u32 max_mcps;
58 u32 max_mem;
59 u32 mcps;
60 u32 mem;
61};
62
Jeeja KPa40e6932015-07-09 15:20:08 +0530[diff] [blame]63struct skl {
64 struct hdac_ext_bus ebus;
65 struct pci_dev *pci;
66
67 unsigned int init_failed:1; /* delayed init failed */
68 struct platform_device *dmic_dev;
Vinod Koulcc18c5f2015-11-05 21:34:13 +0530[diff] [blame]69 struct platform_device *i2s_dev;
Dharageswari Rfe3f4442016-06-03 18:29:39 +0530[diff] [blame]70 struct snd_soc_platform *platform;
Jeeja KP473eb872015-07-21 23:53:55 +0530[diff] [blame]71
Jeeja KPc286b3f2016-05-05 11:19:19 +0530[diff] [blame]72 struct nhlt_acpi_table *nhlt; /* nhlt ptr */
Jeeja KPd255b092015-07-21 23:53:56 +0530[diff] [blame]73 struct skl_sst *skl_sst; /* sst skl ctx */
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100[diff] [blame]74
75 struct skl_dsp_resource resource;
76 struct list_head ppl_list;
Vinod Koulaecf6fd2015-11-05 21:34:15 +0530[diff] [blame]77
78 const char *fw_name;
Vinod Koul4b235c42016-02-19 11:42:34 +0530[diff] [blame]79 char tplg_name[64];
80 unsigned short pci_id;
Vinod Kould8018362016-01-05 17:16:04 +0530[diff] [blame]81 const struct firmware *tplg;
Jeeja KP4557c302015-12-03 23:30:00 +0530[diff] [blame]82
83 int supend_active;
Jeeja KPa40e6932015-07-09 15:20:08 +0530[diff] [blame]84};
85
86#define skl_to_ebus(s) (&(s)->ebus)
87#define ebus_to_skl(sbus) \
88 container_of(sbus, struct skl, sbus)
89
90/* to pass dai dma data */
91struct skl_dma_params {
92 u32 format;
93 u8 stream_tag;
94};
95
Yong Zhif65cf7d62016-05-26 21:30:15 -0700[diff] [blame]96/* to pass dmic data */
97struct skl_machine_pdata {
98 u32 dmic_num;
99};
100
Jeeja KPbc23ca32016-03-11 10:12:53 +0530[diff] [blame]101struct skl_dsp_ops {
102 int id;
103 struct skl_dsp_loader_ops (*loader_ops)(void);
104 int (*init)(struct device *dev, void __iomem *mmio_base,
105 int irq, const char *fw_name,
106 struct skl_dsp_loader_ops loader_ops,
107 struct skl_sst **skl_sst);
Vinod Koul78cdbbd2016-07-26 18:06:42 +0530[diff] [blame]108 int (*init_fw)(struct device *dev, struct skl_sst *ctx);
Jeeja KPbc23ca32016-03-11 10:12:53 +0530[diff] [blame]109 void (*cleanup)(struct device *dev, struct skl_sst *ctx);
110};
111
Jeeja KPa40e6932015-07-09 15:20:08 +0530[diff] [blame]112int skl_platform_unregister(struct device *dev);
113int skl_platform_register(struct device *dev);
114
Jeeja KPc286b3f2016-05-05 11:19:19 +0530[diff] [blame]115struct nhlt_acpi_table *skl_nhlt_init(struct device *dev);
116void skl_nhlt_free(struct nhlt_acpi_table *addr);
Jeeja KP473eb872015-07-21 23:53:55 +0530[diff] [blame]117struct nhlt_specific_cfg *skl_get_ep_blob(struct skl *skl, u32 instance,
118 u8 link_type, u8 s_fmt, u8 no_ch, u32 s_rate, u8 dirn);
Jeeja KPd255b092015-07-21 23:53:56 +0530[diff] [blame]119
Yong Zhif65cf7d62016-05-26 21:30:15 -0700[diff] [blame]120int skl_get_dmic_geo(struct skl *skl);
Vinod Koul4b235c42016-02-19 11:42:34 +0530[diff] [blame]121int skl_nhlt_update_topology_bin(struct skl *skl);
Jeeja KPd255b092015-07-21 23:53:56 +0530[diff] [blame]122int skl_init_dsp(struct skl *skl);
Jeeja KPbc23ca32016-03-11 10:12:53 +0530[diff] [blame]123int skl_free_dsp(struct skl *skl);
Jeeja KPd255b092015-07-21 23:53:56 +0530[diff] [blame]124int skl_suspend_dsp(struct skl *skl);
125int skl_resume_dsp(struct skl *skl);
Dharageswari Rfe3f4442016-06-03 18:29:39 +0530[diff] [blame]126void skl_cleanup_resources(struct skl *skl);
Vinod Koul73a67582016-07-26 18:06:41 +0530[diff] [blame]127const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id);
Jeeja KPa40e6932015-07-09 15:20:08 +0530[diff] [blame]128#endif /* __SOUND_SOC_SKL_H */