Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Keith Packard <keithp@keithp.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 30 | #include <linux/export.h> |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 31 | #include <linux/notifier.h> |
| 32 | #include <linux/reboot.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 33 | #include <drm/drmP.h> |
Matt Roper | c6f95f2 | 2015-01-22 16:50:32 -0800 | [diff] [blame] | 34 | #include <drm/drm_atomic_helper.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 35 | #include <drm/drm_crtc.h> |
| 36 | #include <drm/drm_crtc_helper.h> |
| 37 | #include <drm/drm_edid.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 38 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 39 | #include <drm/i915_drm.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 40 | #include "i915_drv.h" |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 41 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 42 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
| 43 | |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 44 | /* Compliance test status bits */ |
| 45 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 |
| 46 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| 47 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| 48 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| 49 | |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 50 | struct dp_link_dpll { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 51 | int clock; |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 52 | struct dpll dpll; |
| 53 | }; |
| 54 | |
| 55 | static const struct dp_link_dpll gen4_dpll[] = { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 56 | { 162000, |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 57 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 58 | { 270000, |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 59 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
| 60 | }; |
| 61 | |
| 62 | static const struct dp_link_dpll pch_dpll[] = { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 63 | { 162000, |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 64 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 65 | { 270000, |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 66 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
| 67 | }; |
| 68 | |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 69 | static const struct dp_link_dpll vlv_dpll[] = { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 70 | { 162000, |
Chon Ming Lee | 58f6e63 | 2013-09-25 15:47:51 +0800 | [diff] [blame] | 71 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 72 | { 270000, |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 73 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
| 74 | }; |
| 75 | |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 76 | /* |
| 77 | * CHV supports eDP 1.4 that have more link rates. |
| 78 | * Below only provides the fixed rate but exclude variable rate. |
| 79 | */ |
| 80 | static const struct dp_link_dpll chv_dpll[] = { |
| 81 | /* |
| 82 | * CHV requires to program fractional division for m2. |
| 83 | * m2 is stored in fixed point format using formula below |
| 84 | * (m2_int << 22) | m2_fraction |
| 85 | */ |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 86 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 87 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 88 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 89 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 90 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 91 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
| 92 | }; |
Sonika Jindal | 637a9c6 | 2015-05-07 09:52:08 +0530 | [diff] [blame] | 93 | |
Sonika Jindal | 64987fc | 2015-05-26 17:50:13 +0530 | [diff] [blame] | 94 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
| 95 | 324000, 432000, 540000 }; |
Sonika Jindal | 637a9c6 | 2015-05-07 09:52:08 +0530 | [diff] [blame] | 96 | static const int skl_rates[] = { 162000, 216000, 270000, |
Ville Syrjälä | f4896f1 | 2015-03-12 17:10:27 +0200 | [diff] [blame] | 97 | 324000, 432000, 540000 }; |
| 98 | static const int default_rates[] = { 162000, 270000, 540000 }; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 99 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 100 | /** |
| 101 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
| 102 | * @intel_dp: DP struct |
| 103 | * |
| 104 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
| 105 | * will return true, and false otherwise. |
| 106 | */ |
| 107 | static bool is_edp(struct intel_dp *intel_dp) |
| 108 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 109 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 110 | |
| 111 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 112 | } |
| 113 | |
Imre Deak | 68b4d82 | 2013-05-08 13:14:06 +0300 | [diff] [blame] | 114 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 115 | { |
Imre Deak | 68b4d82 | 2013-05-08 13:14:06 +0300 | [diff] [blame] | 116 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 117 | |
| 118 | return intel_dig_port->base.base.dev; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 119 | } |
| 120 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 121 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
| 122 | { |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 123 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 124 | } |
| 125 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 126 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
Ville Syrjälä | 1e0560e | 2014-08-19 13:24:25 +0300 | [diff] [blame] | 127 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 128 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 129 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 130 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
| 131 | enum pipe pipe); |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 132 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 133 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 134 | static unsigned int intel_dp_unused_lane_mask(int lane_count) |
| 135 | { |
| 136 | return ~((1 << lane_count) - 1) & 0xf; |
| 137 | } |
| 138 | |
Ville Syrjälä | ed4e9c1 | 2015-03-12 17:10:36 +0200 | [diff] [blame] | 139 | static int |
| 140 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 141 | { |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 142 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 143 | |
| 144 | switch (max_link_bw) { |
| 145 | case DP_LINK_BW_1_62: |
| 146 | case DP_LINK_BW_2_7: |
Ville Syrjälä | 1db10e2 | 2015-03-12 17:10:32 +0200 | [diff] [blame] | 147 | case DP_LINK_BW_5_4: |
Imre Deak | d4eead5 | 2013-07-09 17:05:26 +0300 | [diff] [blame] | 148 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 149 | default: |
Imre Deak | d4eead5 | 2013-07-09 17:05:26 +0300 | [diff] [blame] | 150 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
| 151 | max_link_bw); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 152 | max_link_bw = DP_LINK_BW_1_62; |
| 153 | break; |
| 154 | } |
| 155 | return max_link_bw; |
| 156 | } |
| 157 | |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 158 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
| 159 | { |
| 160 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 161 | u8 source_max, sink_max; |
| 162 | |
Ville Syrjälä | ccb1a83 | 2015-12-08 19:59:38 +0200 | [diff] [blame] | 163 | source_max = intel_dig_port->max_lanes; |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 164 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
| 165 | |
| 166 | return min(source_max, sink_max); |
| 167 | } |
| 168 | |
Adam Jackson | cd9dde4 | 2011-10-14 12:43:49 -0400 | [diff] [blame] | 169 | /* |
| 170 | * The units on the numbers in the next two are... bizarre. Examples will |
| 171 | * make it clearer; this one parallels an example in the eDP spec. |
| 172 | * |
| 173 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
| 174 | * |
| 175 | * 270000 * 1 * 8 / 10 == 216000 |
| 176 | * |
| 177 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
| 178 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
| 179 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
| 180 | * 119000. At 18bpp that's 2142000 kilobits per second. |
| 181 | * |
| 182 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
| 183 | * get the result in decakilobits instead of kilobits. |
| 184 | */ |
| 185 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 186 | static int |
Keith Packard | c898261 | 2012-01-25 08:16:25 -0800 | [diff] [blame] | 187 | intel_dp_link_required(int pixel_clock, int bpp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 188 | { |
Adam Jackson | cd9dde4 | 2011-10-14 12:43:49 -0400 | [diff] [blame] | 189 | return (pixel_clock * bpp + 9) / 10; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 190 | } |
| 191 | |
| 192 | static int |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 193 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
| 194 | { |
| 195 | return (max_link_clock * max_lanes * 8) / 10; |
| 196 | } |
| 197 | |
Damien Lespiau | c19de8e | 2013-11-28 15:29:18 +0000 | [diff] [blame] | 198 | static enum drm_mode_status |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 199 | intel_dp_mode_valid(struct drm_connector *connector, |
| 200 | struct drm_display_mode *mode) |
| 201 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 202 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 203 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 204 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 205 | int target_clock = mode->clock; |
| 206 | int max_rate, mode_rate, max_lanes, max_link_clock; |
Mika Kahola | 799487f | 2016-02-02 15:16:38 +0200 | [diff] [blame] | 207 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 208 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 209 | if (is_edp(intel_dp) && fixed_mode) { |
| 210 | if (mode->hdisplay > fixed_mode->hdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 211 | return MODE_PANEL; |
| 212 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 213 | if (mode->vdisplay > fixed_mode->vdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 214 | return MODE_PANEL; |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 215 | |
| 216 | target_clock = fixed_mode->clock; |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 217 | } |
| 218 | |
Ville Syrjälä | 50fec21 | 2015-03-12 17:10:34 +0200 | [diff] [blame] | 219 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 220 | max_lanes = intel_dp_max_lane_count(intel_dp); |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 221 | |
| 222 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
| 223 | mode_rate = intel_dp_link_required(target_clock, 18); |
| 224 | |
Mika Kahola | 799487f | 2016-02-02 15:16:38 +0200 | [diff] [blame] | 225 | if (mode_rate > max_rate || target_clock > max_dotclk) |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 226 | return MODE_CLOCK_HIGH; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 227 | |
| 228 | if (mode->clock < 10000) |
| 229 | return MODE_CLOCK_LOW; |
| 230 | |
Daniel Vetter | 0af78a2 | 2012-05-23 11:30:55 +0200 | [diff] [blame] | 231 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
| 232 | return MODE_H_ILLEGAL; |
| 233 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 234 | return MODE_OK; |
| 235 | } |
| 236 | |
Rodrigo Vivi | a4f1289 | 2014-11-14 08:52:27 -0800 | [diff] [blame] | 237 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 238 | { |
| 239 | int i; |
| 240 | uint32_t v = 0; |
| 241 | |
| 242 | if (src_bytes > 4) |
| 243 | src_bytes = 4; |
| 244 | for (i = 0; i < src_bytes; i++) |
| 245 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
| 246 | return v; |
| 247 | } |
| 248 | |
Damien Lespiau | c2af70e | 2015-02-10 19:32:23 +0000 | [diff] [blame] | 249 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 250 | { |
| 251 | int i; |
| 252 | if (dst_bytes > 4) |
| 253 | dst_bytes = 4; |
| 254 | for (i = 0; i < dst_bytes; i++) |
| 255 | dst[i] = src >> ((3-i) * 8); |
| 256 | } |
| 257 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 258 | static void |
| 259 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 260 | struct intel_dp *intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 261 | static void |
| 262 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 263 | struct intel_dp *intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 264 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 265 | static void pps_lock(struct intel_dp *intel_dp) |
| 266 | { |
| 267 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 268 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 269 | struct drm_device *dev = encoder->base.dev; |
| 270 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 271 | enum intel_display_power_domain power_domain; |
| 272 | |
| 273 | /* |
| 274 | * See vlv_power_sequencer_reset() why we need |
| 275 | * a power domain reference here. |
| 276 | */ |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 277 | power_domain = intel_display_port_aux_power_domain(encoder); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 278 | intel_display_power_get(dev_priv, power_domain); |
| 279 | |
| 280 | mutex_lock(&dev_priv->pps_mutex); |
| 281 | } |
| 282 | |
| 283 | static void pps_unlock(struct intel_dp *intel_dp) |
| 284 | { |
| 285 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 286 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 287 | struct drm_device *dev = encoder->base.dev; |
| 288 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 289 | enum intel_display_power_domain power_domain; |
| 290 | |
| 291 | mutex_unlock(&dev_priv->pps_mutex); |
| 292 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 293 | power_domain = intel_display_port_aux_power_domain(encoder); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 294 | intel_display_power_put(dev_priv, power_domain); |
| 295 | } |
| 296 | |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 297 | static void |
| 298 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) |
| 299 | { |
| 300 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 301 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 302 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 303 | enum pipe pipe = intel_dp->pps_pipe; |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 304 | bool pll_enabled, release_cl_override = false; |
| 305 | enum dpio_phy phy = DPIO_PHY(pipe); |
| 306 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 307 | uint32_t DP; |
| 308 | |
| 309 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, |
| 310 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", |
| 311 | pipe_name(pipe), port_name(intel_dig_port->port))) |
| 312 | return; |
| 313 | |
| 314 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", |
| 315 | pipe_name(pipe), port_name(intel_dig_port->port)); |
| 316 | |
| 317 | /* Preserve the BIOS-computed detected bit. This is |
| 318 | * supposed to be read-only. |
| 319 | */ |
| 320 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
| 321 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
| 322 | DP |= DP_PORT_WIDTH(1); |
| 323 | DP |= DP_LINK_TRAIN_PAT_1; |
| 324 | |
| 325 | if (IS_CHERRYVIEW(dev)) |
| 326 | DP |= DP_PIPE_SELECT_CHV(pipe); |
| 327 | else if (pipe == PIPE_B) |
| 328 | DP |= DP_PIPEB_SELECT; |
| 329 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 330 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
| 331 | |
| 332 | /* |
| 333 | * The DPLL for the pipe must be enabled for this to work. |
| 334 | * So enable temporarily it if it's not already enabled. |
| 335 | */ |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 336 | if (!pll_enabled) { |
| 337 | release_cl_override = IS_CHERRYVIEW(dev) && |
| 338 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
| 339 | |
Tvrtko Ursulin | 3f36b93 | 2016-01-19 15:25:17 +0000 | [diff] [blame] | 340 | if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? |
| 341 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
| 342 | DRM_ERROR("Failed to force on pll for pipe %c!\n", |
| 343 | pipe_name(pipe)); |
| 344 | return; |
| 345 | } |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 346 | } |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 347 | |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 348 | /* |
| 349 | * Similar magic as in intel_dp_enable_port(). |
| 350 | * We _must_ do this port enable + disable trick |
| 351 | * to make this power seqeuencer lock onto the port. |
| 352 | * Otherwise even VDD force bit won't work. |
| 353 | */ |
| 354 | I915_WRITE(intel_dp->output_reg, DP); |
| 355 | POSTING_READ(intel_dp->output_reg); |
| 356 | |
| 357 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); |
| 358 | POSTING_READ(intel_dp->output_reg); |
| 359 | |
| 360 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
| 361 | POSTING_READ(intel_dp->output_reg); |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 362 | |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 363 | if (!pll_enabled) { |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 364 | vlv_force_pll_off(dev, pipe); |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 365 | |
| 366 | if (release_cl_override) |
| 367 | chv_phy_powergate_ch(dev_priv, phy, ch, false); |
| 368 | } |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 369 | } |
| 370 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 371 | static enum pipe |
| 372 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
| 373 | { |
| 374 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 375 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 376 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 377 | struct intel_encoder *encoder; |
| 378 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 379 | enum pipe pipe; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 380 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 381 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 382 | |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 383 | /* We should never land here with regular DP ports */ |
| 384 | WARN_ON(!is_edp(intel_dp)); |
| 385 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 386 | if (intel_dp->pps_pipe != INVALID_PIPE) |
| 387 | return intel_dp->pps_pipe; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 388 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 389 | /* |
| 390 | * We don't have power sequencer currently. |
| 391 | * Pick one that's not used by other ports. |
| 392 | */ |
Jani Nikula | 19c8054 | 2015-12-16 12:48:16 +0200 | [diff] [blame] | 393 | for_each_intel_encoder(dev, encoder) { |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 394 | struct intel_dp *tmp; |
| 395 | |
| 396 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 397 | continue; |
| 398 | |
| 399 | tmp = enc_to_intel_dp(&encoder->base); |
| 400 | |
| 401 | if (tmp->pps_pipe != INVALID_PIPE) |
| 402 | pipes &= ~(1 << tmp->pps_pipe); |
| 403 | } |
| 404 | |
| 405 | /* |
| 406 | * Didn't find one. This should not happen since there |
| 407 | * are two power sequencers and up to two eDP ports. |
| 408 | */ |
| 409 | if (WARN_ON(pipes == 0)) |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 410 | pipe = PIPE_A; |
| 411 | else |
| 412 | pipe = ffs(pipes) - 1; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 413 | |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 414 | vlv_steal_power_sequencer(dev, pipe); |
| 415 | intel_dp->pps_pipe = pipe; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 416 | |
| 417 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", |
| 418 | pipe_name(intel_dp->pps_pipe), |
| 419 | port_name(intel_dig_port->port)); |
| 420 | |
| 421 | /* init power sequencer on this pipe and port */ |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 422 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 423 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 424 | |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 425 | /* |
| 426 | * Even vdd force doesn't work until we've made |
| 427 | * the power sequencer lock in on the port. |
| 428 | */ |
| 429 | vlv_power_sequencer_kick(intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 430 | |
| 431 | return intel_dp->pps_pipe; |
| 432 | } |
| 433 | |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 434 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
| 435 | enum pipe pipe); |
| 436 | |
| 437 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, |
| 438 | enum pipe pipe) |
| 439 | { |
| 440 | return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; |
| 441 | } |
| 442 | |
| 443 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, |
| 444 | enum pipe pipe) |
| 445 | { |
| 446 | return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
| 447 | } |
| 448 | |
| 449 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, |
| 450 | enum pipe pipe) |
| 451 | { |
| 452 | return true; |
| 453 | } |
| 454 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 455 | static enum pipe |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 456 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
| 457 | enum port port, |
| 458 | vlv_pipe_check pipe_check) |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 459 | { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 460 | enum pipe pipe; |
| 461 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 462 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
| 463 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
| 464 | PANEL_PORT_SELECT_MASK; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 465 | |
| 466 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) |
| 467 | continue; |
| 468 | |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 469 | if (!pipe_check(dev_priv, pipe)) |
| 470 | continue; |
| 471 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 472 | return pipe; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 473 | } |
| 474 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 475 | return INVALID_PIPE; |
| 476 | } |
| 477 | |
| 478 | static void |
| 479 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) |
| 480 | { |
| 481 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 482 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 483 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 484 | enum port port = intel_dig_port->port; |
| 485 | |
| 486 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 487 | |
| 488 | /* try to find a pipe with this port selected */ |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 489 | /* first pick one where the panel is on */ |
| 490 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 491 | vlv_pipe_has_pp_on); |
| 492 | /* didn't find one? pick one where vdd is on */ |
| 493 | if (intel_dp->pps_pipe == INVALID_PIPE) |
| 494 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 495 | vlv_pipe_has_vdd_on); |
| 496 | /* didn't find one? pick one with just the correct port */ |
| 497 | if (intel_dp->pps_pipe == INVALID_PIPE) |
| 498 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 499 | vlv_pipe_any); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 500 | |
| 501 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ |
| 502 | if (intel_dp->pps_pipe == INVALID_PIPE) { |
| 503 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", |
| 504 | port_name(port)); |
| 505 | return; |
| 506 | } |
| 507 | |
| 508 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
| 509 | port_name(port), pipe_name(intel_dp->pps_pipe)); |
| 510 | |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 511 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 512 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 513 | } |
| 514 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 515 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
| 516 | { |
| 517 | struct drm_device *dev = dev_priv->dev; |
| 518 | struct intel_encoder *encoder; |
| 519 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 520 | if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))) |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 521 | return; |
| 522 | |
| 523 | /* |
| 524 | * We can't grab pps_mutex here due to deadlock with power_domain |
| 525 | * mutex when power_domain functions are called while holding pps_mutex. |
| 526 | * That also means that in order to use pps_pipe the code needs to |
| 527 | * hold both a power domain reference and pps_mutex, and the power domain |
| 528 | * reference get/put must be done while _not_ holding pps_mutex. |
| 529 | * pps_{lock,unlock}() do these steps in the correct order, so one |
| 530 | * should use them always. |
| 531 | */ |
| 532 | |
Jani Nikula | 19c8054 | 2015-12-16 12:48:16 +0200 | [diff] [blame] | 533 | for_each_intel_encoder(dev, encoder) { |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 534 | struct intel_dp *intel_dp; |
| 535 | |
| 536 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 537 | continue; |
| 538 | |
| 539 | intel_dp = enc_to_intel_dp(&encoder->base); |
| 540 | intel_dp->pps_pipe = INVALID_PIPE; |
| 541 | } |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 542 | } |
| 543 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 544 | static i915_reg_t |
| 545 | _pp_ctrl_reg(struct intel_dp *intel_dp) |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 546 | { |
| 547 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 548 | |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 549 | if (IS_BROXTON(dev)) |
| 550 | return BXT_PP_CONTROL(0); |
| 551 | else if (HAS_PCH_SPLIT(dev)) |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 552 | return PCH_PP_CONTROL; |
| 553 | else |
| 554 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
| 555 | } |
| 556 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 557 | static i915_reg_t |
| 558 | _pp_stat_reg(struct intel_dp *intel_dp) |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 559 | { |
| 560 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 561 | |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 562 | if (IS_BROXTON(dev)) |
| 563 | return BXT_PP_STATUS(0); |
| 564 | else if (HAS_PCH_SPLIT(dev)) |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 565 | return PCH_PP_STATUS; |
| 566 | else |
| 567 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
| 568 | } |
| 569 | |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 570 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
| 571 | This function only applicable when panel PM state is not to be tracked */ |
| 572 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, |
| 573 | void *unused) |
| 574 | { |
| 575 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), |
| 576 | edp_notifier); |
| 577 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 578 | struct drm_i915_private *dev_priv = dev->dev_private; |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 579 | |
| 580 | if (!is_edp(intel_dp) || code != SYS_RESTART) |
| 581 | return 0; |
| 582 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 583 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 584 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 585 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 586 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 587 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 588 | u32 pp_div; |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 589 | |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 590 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
| 591 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
| 592 | pp_div = I915_READ(pp_div_reg); |
| 593 | pp_div &= PP_REFERENCE_DIVIDER_MASK; |
| 594 | |
| 595 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ |
| 596 | I915_WRITE(pp_div_reg, pp_div | 0x1F); |
| 597 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
| 598 | msleep(intel_dp->panel_power_cycle_delay); |
| 599 | } |
| 600 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 601 | pps_unlock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 602 | |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 603 | return 0; |
| 604 | } |
| 605 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 606 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 607 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 608 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 609 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 610 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 611 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 612 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 613 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
Ville Syrjälä | 9a42356 | 2014-10-16 21:29:48 +0300 | [diff] [blame] | 614 | intel_dp->pps_pipe == INVALID_PIPE) |
| 615 | return false; |
| 616 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 617 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 618 | } |
| 619 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 620 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 621 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 622 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 623 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 624 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 625 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 626 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 627 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
Ville Syrjälä | 9a42356 | 2014-10-16 21:29:48 +0300 | [diff] [blame] | 628 | intel_dp->pps_pipe == INVALID_PIPE) |
| 629 | return false; |
| 630 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 631 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 632 | } |
| 633 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 634 | static void |
| 635 | intel_dp_check_edp(struct intel_dp *intel_dp) |
| 636 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 637 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 638 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 639 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 640 | if (!is_edp(intel_dp)) |
| 641 | return; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 642 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 643 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 644 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
| 645 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 646 | I915_READ(_pp_stat_reg(intel_dp)), |
| 647 | I915_READ(_pp_ctrl_reg(intel_dp))); |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 648 | } |
| 649 | } |
| 650 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 651 | static uint32_t |
| 652 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
| 653 | { |
| 654 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 655 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 656 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 657 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 658 | uint32_t status; |
| 659 | bool done; |
| 660 | |
Daniel Vetter | ef04f00 | 2012-12-01 21:03:59 +0100 | [diff] [blame] | 661 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 662 | if (has_aux_irq) |
Paulo Zanoni | b18ac46 | 2013-02-18 19:00:24 -0300 | [diff] [blame] | 663 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
Imre Deak | 3598706 | 2013-05-21 20:03:20 +0300 | [diff] [blame] | 664 | msecs_to_jiffies_timeout(10)); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 665 | else |
| 666 | done = wait_for_atomic(C, 10) == 0; |
| 667 | if (!done) |
| 668 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
| 669 | has_aux_irq); |
| 670 | #undef C |
| 671 | |
| 672 | return status; |
| 673 | } |
| 674 | |
Ville Syrjälä | 6ffb1be | 2016-03-02 17:22:14 +0200 | [diff] [blame] | 675 | static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 676 | { |
| 677 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 678 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 679 | |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 680 | if (index) |
| 681 | return 0; |
| 682 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 683 | /* |
| 684 | * The clock divider is based off the hrawclk, and would like to run at |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 685 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 686 | */ |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 687 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 688 | } |
| 689 | |
| 690 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 691 | { |
| 692 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 693 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 694 | |
| 695 | if (index) |
| 696 | return 0; |
| 697 | |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 698 | /* |
| 699 | * The clock divider is based off the cdclk or PCH rawclk, and would |
| 700 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and |
| 701 | * divide by 2000 and use that |
| 702 | */ |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 703 | if (intel_dig_port->port == PORT_A) |
Ville Syrjälä | fce18c4 | 2015-11-30 16:23:46 +0200 | [diff] [blame] | 704 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 705 | else |
| 706 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 707 | } |
| 708 | |
| 709 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 710 | { |
| 711 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 712 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 713 | |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 714 | if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 715 | /* Workaround for non-ULT HSW */ |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 716 | switch (index) { |
| 717 | case 0: return 63; |
| 718 | case 1: return 72; |
| 719 | default: return 0; |
| 720 | } |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 721 | } |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 722 | |
| 723 | return ilk_get_aux_clock_divider(intel_dp, index); |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 724 | } |
| 725 | |
Damien Lespiau | b6b5e38 | 2014-01-20 16:00:59 +0000 | [diff] [blame] | 726 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 727 | { |
| 728 | /* |
| 729 | * SKL doesn't need us to program the AUX clock divider (Hardware will |
| 730 | * derive the clock from CDCLK automatically). We still implement the |
| 731 | * get_aux_clock_divider vfunc to plug-in into the existing code. |
| 732 | */ |
| 733 | return index ? 0 : 1; |
| 734 | } |
| 735 | |
Ville Syrjälä | 6ffb1be | 2016-03-02 17:22:14 +0200 | [diff] [blame] | 736 | static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
| 737 | bool has_aux_irq, |
| 738 | int send_bytes, |
| 739 | uint32_t aux_clock_divider) |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 740 | { |
| 741 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 742 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 743 | uint32_t precharge, timeout; |
| 744 | |
| 745 | if (IS_GEN6(dev)) |
| 746 | precharge = 3; |
| 747 | else |
| 748 | precharge = 5; |
| 749 | |
Ville Syrjälä | f3c6a3a | 2015-11-11 20:34:10 +0200 | [diff] [blame] | 750 | if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A) |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 751 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
| 752 | else |
| 753 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
| 754 | |
| 755 | return DP_AUX_CH_CTL_SEND_BUSY | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 756 | DP_AUX_CH_CTL_DONE | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 757 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 758 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 759 | timeout | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 760 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 761 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 762 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 763 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 764 | } |
| 765 | |
Damien Lespiau | b9ca5fa | 2014-01-20 16:01:00 +0000 | [diff] [blame] | 766 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
| 767 | bool has_aux_irq, |
| 768 | int send_bytes, |
| 769 | uint32_t unused) |
| 770 | { |
| 771 | return DP_AUX_CH_CTL_SEND_BUSY | |
| 772 | DP_AUX_CH_CTL_DONE | |
| 773 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
| 774 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 775 | DP_AUX_CH_CTL_TIME_OUT_1600us | |
| 776 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
| 777 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 778 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
| 779 | } |
| 780 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 781 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 782 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
Daniel Vetter | bd9f74a | 2014-10-02 09:45:35 +0200 | [diff] [blame] | 783 | const uint8_t *send, int send_bytes, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 784 | uint8_t *recv, int recv_size) |
| 785 | { |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 786 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 787 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 788 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 789 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 790 | uint32_t aux_clock_divider; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 791 | int i, ret, recv_bytes; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 792 | uint32_t status; |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 793 | int try, clock = 0; |
Daniel Vetter | 4e6b788 | 2014-02-07 16:33:20 +0100 | [diff] [blame] | 794 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
Jani Nikula | 884f19e | 2014-03-14 16:51:14 +0200 | [diff] [blame] | 795 | bool vdd; |
| 796 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 797 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 798 | |
Ville Syrjälä | 72c3500 | 2014-08-18 22:16:00 +0300 | [diff] [blame] | 799 | /* |
| 800 | * We will be called with VDD already enabled for dpcd/edid/oui reads. |
| 801 | * In such cases we want to leave VDD enabled and it's up to upper layers |
| 802 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off |
| 803 | * ourselves. |
| 804 | */ |
Ville Syrjälä | 1e0560e | 2014-08-19 13:24:25 +0300 | [diff] [blame] | 805 | vdd = edp_panel_vdd_on(intel_dp); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 806 | |
| 807 | /* dp aux is extremely sensitive to irq latency, hence request the |
| 808 | * lowest possible wakeup latency and so prevent the cpu from going into |
| 809 | * deep sleep states. |
| 810 | */ |
| 811 | pm_qos_update_request(&dev_priv->pm_qos, 0); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 812 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 813 | intel_dp_check_edp(intel_dp); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 814 | |
Jesse Barnes | 11bee43 | 2011-08-01 15:02:20 -0700 | [diff] [blame] | 815 | /* Try to wait for any previous AUX channel activity */ |
| 816 | for (try = 0; try < 3; try++) { |
Daniel Vetter | ef04f00 | 2012-12-01 21:03:59 +0100 | [diff] [blame] | 817 | status = I915_READ_NOTRACE(ch_ctl); |
Jesse Barnes | 11bee43 | 2011-08-01 15:02:20 -0700 | [diff] [blame] | 818 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 819 | break; |
| 820 | msleep(1); |
| 821 | } |
| 822 | |
| 823 | if (try == 3) { |
Mika Kuoppala | 02196c7 | 2015-08-06 16:48:58 +0300 | [diff] [blame] | 824 | static u32 last_status = -1; |
| 825 | const u32 status = I915_READ(ch_ctl); |
| 826 | |
| 827 | if (status != last_status) { |
| 828 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
| 829 | status); |
| 830 | last_status = status; |
| 831 | } |
| 832 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 833 | ret = -EBUSY; |
| 834 | goto out; |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 835 | } |
| 836 | |
Paulo Zanoni | 46a5ae9 | 2013-09-17 11:14:10 -0300 | [diff] [blame] | 837 | /* Only 5 data registers! */ |
| 838 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
| 839 | ret = -E2BIG; |
| 840 | goto out; |
| 841 | } |
| 842 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 843 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
Damien Lespiau | 153b110 | 2014-01-21 13:37:15 +0000 | [diff] [blame] | 844 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
| 845 | has_aux_irq, |
| 846 | send_bytes, |
| 847 | aux_clock_divider); |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 848 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 849 | /* Must try at least 3 times according to DP spec */ |
| 850 | for (try = 0; try < 5; try++) { |
| 851 | /* Load the send data into the aux channel data registers */ |
| 852 | for (i = 0; i < send_bytes; i += 4) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 853 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
Rodrigo Vivi | a4f1289 | 2014-11-14 08:52:27 -0800 | [diff] [blame] | 854 | intel_dp_pack_aux(send + i, |
| 855 | send_bytes - i)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 856 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 857 | /* Send the command and wait for it to complete */ |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 858 | I915_WRITE(ch_ctl, send_ctl); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 859 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 860 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 861 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 862 | /* Clear done status and any errors */ |
| 863 | I915_WRITE(ch_ctl, |
| 864 | status | |
| 865 | DP_AUX_CH_CTL_DONE | |
| 866 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 867 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
Adam Jackson | d7e96fe | 2011-07-26 15:39:46 -0400 | [diff] [blame] | 868 | |
Todd Previte | 74ebf29 | 2015-04-15 08:38:41 -0700 | [diff] [blame] | 869 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 870 | continue; |
Todd Previte | 74ebf29 | 2015-04-15 08:38:41 -0700 | [diff] [blame] | 871 | |
| 872 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
| 873 | * 400us delay required for errors and timeouts |
| 874 | * Timeout errors from the HW already meet this |
| 875 | * requirement so skip to next iteration |
| 876 | */ |
| 877 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
| 878 | usleep_range(400, 500); |
| 879 | continue; |
| 880 | } |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 881 | if (status & DP_AUX_CH_CTL_DONE) |
Jim Bride | e058c94 | 2015-05-27 10:21:48 -0700 | [diff] [blame] | 882 | goto done; |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 883 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 884 | } |
| 885 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 886 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 887 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 888 | ret = -EBUSY; |
| 889 | goto out; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 890 | } |
| 891 | |
Jim Bride | e058c94 | 2015-05-27 10:21:48 -0700 | [diff] [blame] | 892 | done: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 893 | /* Check for timeout or receive error. |
| 894 | * Timeouts occur when the sink is not connected |
| 895 | */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 896 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 897 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 898 | ret = -EIO; |
| 899 | goto out; |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 900 | } |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 901 | |
| 902 | /* Timeouts occur when the device isn't connected, so they're |
| 903 | * "normal" -- don't fill the kernel log with these */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 904 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 905 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 906 | ret = -ETIMEDOUT; |
| 907 | goto out; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 908 | } |
| 909 | |
| 910 | /* Unload any bytes sent back from the other side */ |
| 911 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
| 912 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
Rodrigo Vivi | 14e0188 | 2015-12-10 11:12:27 -0800 | [diff] [blame] | 913 | |
| 914 | /* |
| 915 | * By BSpec: "Message sizes of 0 or >20 are not allowed." |
| 916 | * We have no idea of what happened so we return -EBUSY so |
| 917 | * drm layer takes care for the necessary retries. |
| 918 | */ |
| 919 | if (recv_bytes == 0 || recv_bytes > 20) { |
| 920 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", |
| 921 | recv_bytes); |
| 922 | /* |
| 923 | * FIXME: This patch was created on top of a series that |
| 924 | * organize the retries at drm level. There EBUSY should |
| 925 | * also take care for 1ms wait before retrying. |
| 926 | * That aux retries re-org is still needed and after that is |
| 927 | * merged we remove this sleep from here. |
| 928 | */ |
| 929 | usleep_range(1000, 1500); |
| 930 | ret = -EBUSY; |
| 931 | goto out; |
| 932 | } |
| 933 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 934 | if (recv_bytes > recv_size) |
| 935 | recv_bytes = recv_size; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 936 | |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 937 | for (i = 0; i < recv_bytes; i += 4) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 938 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
Rodrigo Vivi | a4f1289 | 2014-11-14 08:52:27 -0800 | [diff] [blame] | 939 | recv + i, recv_bytes - i); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 940 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 941 | ret = recv_bytes; |
| 942 | out: |
| 943 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
| 944 | |
Jani Nikula | 884f19e | 2014-03-14 16:51:14 +0200 | [diff] [blame] | 945 | if (vdd) |
| 946 | edp_panel_vdd_off(intel_dp, false); |
| 947 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 948 | pps_unlock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 949 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 950 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 951 | } |
| 952 | |
Jani Nikula | a6c8aff0 | 2014-04-07 12:37:25 +0300 | [diff] [blame] | 953 | #define BARE_ADDRESS_SIZE 3 |
| 954 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 955 | static ssize_t |
| 956 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 957 | { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 958 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
| 959 | uint8_t txbuf[20], rxbuf[20]; |
| 960 | size_t txsize, rxsize; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 961 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 962 | |
Ville Syrjälä | d2d9cbb | 2015-03-19 11:44:06 +0200 | [diff] [blame] | 963 | txbuf[0] = (msg->request << 4) | |
| 964 | ((msg->address >> 16) & 0xf); |
| 965 | txbuf[1] = (msg->address >> 8) & 0xff; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 966 | txbuf[2] = msg->address & 0xff; |
| 967 | txbuf[3] = msg->size - 1; |
Paulo Zanoni | 46a5ae9 | 2013-09-17 11:14:10 -0300 | [diff] [blame] | 968 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 969 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
| 970 | case DP_AUX_NATIVE_WRITE: |
| 971 | case DP_AUX_I2C_WRITE: |
Ville Syrjälä | c1e74122 | 2015-08-27 17:23:27 +0300 | [diff] [blame] | 972 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
Jani Nikula | a6c8aff0 | 2014-04-07 12:37:25 +0300 | [diff] [blame] | 973 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
Jani Nikula | a1ddefd | 2015-03-17 17:18:54 +0200 | [diff] [blame] | 974 | rxsize = 2; /* 0 or 1 data bytes */ |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 975 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 976 | if (WARN_ON(txsize > 20)) |
| 977 | return -E2BIG; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 978 | |
Imre Deak | d81a67c | 2016-01-29 14:52:26 +0200 | [diff] [blame] | 979 | if (msg->buffer) |
| 980 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
| 981 | else |
| 982 | WARN_ON(msg->size); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 983 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 984 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
| 985 | if (ret > 0) { |
| 986 | msg->reply = rxbuf[0] >> 4; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 987 | |
Jani Nikula | a1ddefd | 2015-03-17 17:18:54 +0200 | [diff] [blame] | 988 | if (ret > 1) { |
| 989 | /* Number of bytes written in a short write. */ |
| 990 | ret = clamp_t(int, rxbuf[1], 0, msg->size); |
| 991 | } else { |
| 992 | /* Return payload size. */ |
| 993 | ret = msg->size; |
| 994 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 995 | } |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 996 | break; |
| 997 | |
| 998 | case DP_AUX_NATIVE_READ: |
| 999 | case DP_AUX_I2C_READ: |
Jani Nikula | a6c8aff0 | 2014-04-07 12:37:25 +0300 | [diff] [blame] | 1000 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1001 | rxsize = msg->size + 1; |
| 1002 | |
| 1003 | if (WARN_ON(rxsize > 20)) |
| 1004 | return -E2BIG; |
| 1005 | |
| 1006 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
| 1007 | if (ret > 0) { |
| 1008 | msg->reply = rxbuf[0] >> 4; |
| 1009 | /* |
| 1010 | * Assume happy day, and copy the data. The caller is |
| 1011 | * expected to check msg->reply before touching it. |
| 1012 | * |
| 1013 | * Return payload size. |
| 1014 | */ |
| 1015 | ret--; |
| 1016 | memcpy(msg->buffer, rxbuf + 1, ret); |
| 1017 | } |
| 1018 | break; |
| 1019 | |
| 1020 | default: |
| 1021 | ret = -EINVAL; |
| 1022 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1023 | } |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 1024 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1025 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1026 | } |
| 1027 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1028 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1029 | enum port port) |
Ville Syrjälä | da00bdc | 2015-11-11 20:34:13 +0200 | [diff] [blame] | 1030 | { |
| 1031 | switch (port) { |
| 1032 | case PORT_B: |
| 1033 | case PORT_C: |
| 1034 | case PORT_D: |
| 1035 | return DP_AUX_CH_CTL(port); |
| 1036 | default: |
| 1037 | MISSING_CASE(port); |
| 1038 | return DP_AUX_CH_CTL(PORT_B); |
| 1039 | } |
| 1040 | } |
| 1041 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1042 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1043 | enum port port, int index) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1044 | { |
| 1045 | switch (port) { |
| 1046 | case PORT_B: |
| 1047 | case PORT_C: |
| 1048 | case PORT_D: |
| 1049 | return DP_AUX_CH_DATA(port, index); |
| 1050 | default: |
| 1051 | MISSING_CASE(port); |
| 1052 | return DP_AUX_CH_DATA(PORT_B, index); |
| 1053 | } |
| 1054 | } |
| 1055 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1056 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1057 | enum port port) |
Ville Syrjälä | da00bdc | 2015-11-11 20:34:13 +0200 | [diff] [blame] | 1058 | { |
| 1059 | switch (port) { |
| 1060 | case PORT_A: |
| 1061 | return DP_AUX_CH_CTL(port); |
| 1062 | case PORT_B: |
| 1063 | case PORT_C: |
| 1064 | case PORT_D: |
| 1065 | return PCH_DP_AUX_CH_CTL(port); |
| 1066 | default: |
| 1067 | MISSING_CASE(port); |
| 1068 | return DP_AUX_CH_CTL(PORT_A); |
| 1069 | } |
| 1070 | } |
| 1071 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1072 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1073 | enum port port, int index) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1074 | { |
| 1075 | switch (port) { |
| 1076 | case PORT_A: |
| 1077 | return DP_AUX_CH_DATA(port, index); |
| 1078 | case PORT_B: |
| 1079 | case PORT_C: |
| 1080 | case PORT_D: |
| 1081 | return PCH_DP_AUX_CH_DATA(port, index); |
| 1082 | default: |
| 1083 | MISSING_CASE(port); |
| 1084 | return DP_AUX_CH_DATA(PORT_A, index); |
| 1085 | } |
| 1086 | } |
| 1087 | |
Ville Syrjälä | da00bdc | 2015-11-11 20:34:13 +0200 | [diff] [blame] | 1088 | /* |
| 1089 | * On SKL we don't have Aux for port E so we rely |
| 1090 | * on VBT to set a proper alternate aux channel. |
| 1091 | */ |
| 1092 | static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv) |
| 1093 | { |
| 1094 | const struct ddi_vbt_port_info *info = |
| 1095 | &dev_priv->vbt.ddi_port_info[PORT_E]; |
| 1096 | |
| 1097 | switch (info->alternate_aux_channel) { |
| 1098 | case DP_AUX_A: |
| 1099 | return PORT_A; |
| 1100 | case DP_AUX_B: |
| 1101 | return PORT_B; |
| 1102 | case DP_AUX_C: |
| 1103 | return PORT_C; |
| 1104 | case DP_AUX_D: |
| 1105 | return PORT_D; |
| 1106 | default: |
| 1107 | MISSING_CASE(info->alternate_aux_channel); |
| 1108 | return PORT_A; |
| 1109 | } |
| 1110 | } |
| 1111 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1112 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1113 | enum port port) |
Ville Syrjälä | da00bdc | 2015-11-11 20:34:13 +0200 | [diff] [blame] | 1114 | { |
| 1115 | if (port == PORT_E) |
| 1116 | port = skl_porte_aux_port(dev_priv); |
| 1117 | |
| 1118 | switch (port) { |
| 1119 | case PORT_A: |
| 1120 | case PORT_B: |
| 1121 | case PORT_C: |
| 1122 | case PORT_D: |
| 1123 | return DP_AUX_CH_CTL(port); |
| 1124 | default: |
| 1125 | MISSING_CASE(port); |
| 1126 | return DP_AUX_CH_CTL(PORT_A); |
| 1127 | } |
| 1128 | } |
| 1129 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1130 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1131 | enum port port, int index) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1132 | { |
| 1133 | if (port == PORT_E) |
| 1134 | port = skl_porte_aux_port(dev_priv); |
| 1135 | |
| 1136 | switch (port) { |
| 1137 | case PORT_A: |
| 1138 | case PORT_B: |
| 1139 | case PORT_C: |
| 1140 | case PORT_D: |
| 1141 | return DP_AUX_CH_DATA(port, index); |
| 1142 | default: |
| 1143 | MISSING_CASE(port); |
| 1144 | return DP_AUX_CH_DATA(PORT_A, index); |
| 1145 | } |
| 1146 | } |
| 1147 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1148 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1149 | enum port port) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1150 | { |
| 1151 | if (INTEL_INFO(dev_priv)->gen >= 9) |
| 1152 | return skl_aux_ctl_reg(dev_priv, port); |
| 1153 | else if (HAS_PCH_SPLIT(dev_priv)) |
| 1154 | return ilk_aux_ctl_reg(dev_priv, port); |
| 1155 | else |
| 1156 | return g4x_aux_ctl_reg(dev_priv, port); |
| 1157 | } |
| 1158 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1159 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1160 | enum port port, int index) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1161 | { |
| 1162 | if (INTEL_INFO(dev_priv)->gen >= 9) |
| 1163 | return skl_aux_data_reg(dev_priv, port, index); |
| 1164 | else if (HAS_PCH_SPLIT(dev_priv)) |
| 1165 | return ilk_aux_data_reg(dev_priv, port, index); |
| 1166 | else |
| 1167 | return g4x_aux_data_reg(dev_priv, port, index); |
| 1168 | } |
| 1169 | |
| 1170 | static void intel_aux_reg_init(struct intel_dp *intel_dp) |
| 1171 | { |
| 1172 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
| 1173 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 1174 | int i; |
| 1175 | |
| 1176 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); |
| 1177 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) |
| 1178 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); |
| 1179 | } |
| 1180 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1181 | static void |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1182 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
| 1183 | { |
| 1184 | drm_dp_aux_unregister(&intel_dp->aux); |
| 1185 | kfree(intel_dp->aux.name); |
| 1186 | } |
| 1187 | |
| 1188 | static int |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1189 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1190 | { |
Jani Nikula | 33ad662 | 2014-03-14 16:51:16 +0200 | [diff] [blame] | 1191 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1192 | enum port port = intel_dig_port->port; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 1193 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1194 | |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1195 | intel_aux_reg_init(intel_dp); |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 1196 | |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1197 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
| 1198 | if (!intel_dp->aux.name) |
| 1199 | return -ENOMEM; |
| 1200 | |
Rafael Antognolli | 4d32c0d | 2016-01-21 15:10:20 -0800 | [diff] [blame] | 1201 | intel_dp->aux.dev = connector->base.kdev; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1202 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 1203 | |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1204 | DRM_DEBUG_KMS("registering %s bus for %s\n", |
| 1205 | intel_dp->aux.name, |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 1206 | connector->base.kdev->kobj.name); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1207 | |
Dave Airlie | 4f71d0c | 2014-06-04 16:02:28 +1000 | [diff] [blame] | 1208 | ret = drm_dp_aux_register(&intel_dp->aux); |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 1209 | if (ret < 0) { |
Dave Airlie | 4f71d0c | 2014-06-04 16:02:28 +1000 | [diff] [blame] | 1210 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1211 | intel_dp->aux.name, ret); |
| 1212 | kfree(intel_dp->aux.name); |
| 1213 | return ret; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 1214 | } |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 1215 | |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1216 | return 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1217 | } |
| 1218 | |
Imre Deak | 80f65de | 2014-02-11 17:12:49 +0200 | [diff] [blame] | 1219 | static void |
| 1220 | intel_dp_connector_unregister(struct intel_connector *intel_connector) |
| 1221 | { |
| 1222 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); |
| 1223 | |
Rafael Antognolli | 4d32c0d | 2016-01-21 15:10:20 -0800 | [diff] [blame] | 1224 | intel_dp_aux_fini(intel_dp); |
Imre Deak | 80f65de | 2014-02-11 17:12:49 +0200 | [diff] [blame] | 1225 | intel_connector_unregister(intel_connector); |
| 1226 | } |
| 1227 | |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 1228 | static int |
Ville Syrjälä | 12f6a2e | 2015-03-12 17:10:30 +0200 | [diff] [blame] | 1229 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 1230 | { |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1231 | if (intel_dp->num_sink_rates) { |
| 1232 | *sink_rates = intel_dp->sink_rates; |
| 1233 | return intel_dp->num_sink_rates; |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 1234 | } |
Ville Syrjälä | 12f6a2e | 2015-03-12 17:10:30 +0200 | [diff] [blame] | 1235 | |
| 1236 | *sink_rates = default_rates; |
| 1237 | |
| 1238 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 1239 | } |
| 1240 | |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1241 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
Thulasimani,Sivakumar | ed63baa | 2015-08-18 15:30:37 +0530 | [diff] [blame] | 1242 | { |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1243 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1244 | struct drm_device *dev = dig_port->base.base.dev; |
| 1245 | |
Thulasimani,Sivakumar | ed63baa | 2015-08-18 15:30:37 +0530 | [diff] [blame] | 1246 | /* WaDisableHBR2:skl */ |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 1247 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0)) |
Thulasimani,Sivakumar | ed63baa | 2015-08-18 15:30:37 +0530 | [diff] [blame] | 1248 | return false; |
| 1249 | |
| 1250 | if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || |
| 1251 | (INTEL_INFO(dev)->gen >= 9)) |
| 1252 | return true; |
| 1253 | else |
| 1254 | return false; |
| 1255 | } |
| 1256 | |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1257 | static int |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1258 | intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1259 | { |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1260 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1261 | struct drm_device *dev = dig_port->base.base.dev; |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1262 | int size; |
| 1263 | |
Sonika Jindal | 64987fc | 2015-05-26 17:50:13 +0530 | [diff] [blame] | 1264 | if (IS_BROXTON(dev)) { |
| 1265 | *source_rates = bxt_rates; |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1266 | size = ARRAY_SIZE(bxt_rates); |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 1267 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
Sonika Jindal | 637a9c6 | 2015-05-07 09:52:08 +0530 | [diff] [blame] | 1268 | *source_rates = skl_rates; |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1269 | size = ARRAY_SIZE(skl_rates); |
| 1270 | } else { |
| 1271 | *source_rates = default_rates; |
| 1272 | size = ARRAY_SIZE(default_rates); |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1273 | } |
Ville Syrjälä | 636280b | 2015-03-12 17:10:29 +0200 | [diff] [blame] | 1274 | |
Thulasimani,Sivakumar | ed63baa | 2015-08-18 15:30:37 +0530 | [diff] [blame] | 1275 | /* This depends on the fact that 5.4 is last value in the array */ |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1276 | if (!intel_dp_source_supports_hbr2(intel_dp)) |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1277 | size--; |
Ville Syrjälä | 636280b | 2015-03-12 17:10:29 +0200 | [diff] [blame] | 1278 | |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1279 | return size; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1280 | } |
| 1281 | |
Daniel Vetter | 0e50338 | 2014-07-04 11:26:04 -0300 | [diff] [blame] | 1282 | static void |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1283 | intel_dp_set_clock(struct intel_encoder *encoder, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1284 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1285 | { |
| 1286 | struct drm_device *dev = encoder->base.dev; |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1287 | const struct dp_link_dpll *divisor = NULL; |
| 1288 | int i, count = 0; |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1289 | |
| 1290 | if (IS_G4X(dev)) { |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1291 | divisor = gen4_dpll; |
| 1292 | count = ARRAY_SIZE(gen4_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1293 | } else if (HAS_PCH_SPLIT(dev)) { |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1294 | divisor = pch_dpll; |
| 1295 | count = ARRAY_SIZE(pch_dpll); |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 1296 | } else if (IS_CHERRYVIEW(dev)) { |
| 1297 | divisor = chv_dpll; |
| 1298 | count = ARRAY_SIZE(chv_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1299 | } else if (IS_VALLEYVIEW(dev)) { |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 1300 | divisor = vlv_dpll; |
| 1301 | count = ARRAY_SIZE(vlv_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1302 | } |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1303 | |
| 1304 | if (divisor && count) { |
| 1305 | for (i = 0; i < count; i++) { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1306 | if (pipe_config->port_clock == divisor[i].clock) { |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1307 | pipe_config->dpll = divisor[i].dpll; |
| 1308 | pipe_config->clock_set = true; |
| 1309 | break; |
| 1310 | } |
| 1311 | } |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1312 | } |
| 1313 | } |
| 1314 | |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1315 | static int intersect_rates(const int *source_rates, int source_len, |
| 1316 | const int *sink_rates, int sink_len, |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1317 | int *common_rates) |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1318 | { |
| 1319 | int i = 0, j = 0, k = 0; |
| 1320 | |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1321 | while (i < source_len && j < sink_len) { |
| 1322 | if (source_rates[i] == sink_rates[j]) { |
Ville Syrjälä | e6bda3e | 2015-03-12 17:10:37 +0200 | [diff] [blame] | 1323 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
| 1324 | return k; |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1325 | common_rates[k] = source_rates[i]; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1326 | ++k; |
| 1327 | ++i; |
| 1328 | ++j; |
| 1329 | } else if (source_rates[i] < sink_rates[j]) { |
| 1330 | ++i; |
| 1331 | } else { |
| 1332 | ++j; |
| 1333 | } |
| 1334 | } |
| 1335 | return k; |
| 1336 | } |
| 1337 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1338 | static int intel_dp_common_rates(struct intel_dp *intel_dp, |
| 1339 | int *common_rates) |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1340 | { |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1341 | const int *source_rates, *sink_rates; |
| 1342 | int source_len, sink_len; |
| 1343 | |
| 1344 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1345 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1346 | |
| 1347 | return intersect_rates(source_rates, source_len, |
| 1348 | sink_rates, sink_len, |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1349 | common_rates); |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1350 | } |
| 1351 | |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1352 | static void snprintf_int_array(char *str, size_t len, |
| 1353 | const int *array, int nelem) |
| 1354 | { |
| 1355 | int i; |
| 1356 | |
| 1357 | str[0] = '\0'; |
| 1358 | |
| 1359 | for (i = 0; i < nelem; i++) { |
Jani Nikula | b2f505b | 2015-05-18 16:01:45 +0300 | [diff] [blame] | 1360 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1361 | if (r >= len) |
| 1362 | return; |
| 1363 | str += r; |
| 1364 | len -= r; |
| 1365 | } |
| 1366 | } |
| 1367 | |
| 1368 | static void intel_dp_print_rates(struct intel_dp *intel_dp) |
| 1369 | { |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1370 | const int *source_rates, *sink_rates; |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1371 | int source_len, sink_len, common_len; |
| 1372 | int common_rates[DP_MAX_SUPPORTED_RATES]; |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1373 | char str[128]; /* FIXME: too big for stack? */ |
| 1374 | |
| 1375 | if ((drm_debug & DRM_UT_KMS) == 0) |
| 1376 | return; |
| 1377 | |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1378 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1379 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
| 1380 | DRM_DEBUG_KMS("source rates: %s\n", str); |
| 1381 | |
| 1382 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
| 1383 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); |
| 1384 | DRM_DEBUG_KMS("sink rates: %s\n", str); |
| 1385 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1386 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
| 1387 | snprintf_int_array(str, sizeof(str), common_rates, common_len); |
| 1388 | DRM_DEBUG_KMS("common rates: %s\n", str); |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1389 | } |
| 1390 | |
Ville Syrjälä | f4896f1 | 2015-03-12 17:10:27 +0200 | [diff] [blame] | 1391 | static int rate_to_index(int find, const int *rates) |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1392 | { |
| 1393 | int i = 0; |
| 1394 | |
| 1395 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) |
| 1396 | if (find == rates[i]) |
| 1397 | break; |
| 1398 | |
| 1399 | return i; |
| 1400 | } |
| 1401 | |
Ville Syrjälä | 50fec21 | 2015-03-12 17:10:34 +0200 | [diff] [blame] | 1402 | int |
| 1403 | intel_dp_max_link_rate(struct intel_dp *intel_dp) |
| 1404 | { |
| 1405 | int rates[DP_MAX_SUPPORTED_RATES] = {}; |
| 1406 | int len; |
| 1407 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1408 | len = intel_dp_common_rates(intel_dp, rates); |
Ville Syrjälä | 50fec21 | 2015-03-12 17:10:34 +0200 | [diff] [blame] | 1409 | if (WARN_ON(len <= 0)) |
| 1410 | return 162000; |
| 1411 | |
| 1412 | return rates[rate_to_index(0, rates) - 1]; |
| 1413 | } |
| 1414 | |
Ville Syrjälä | ed4e9c1 | 2015-03-12 17:10:36 +0200 | [diff] [blame] | 1415 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
| 1416 | { |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1417 | return rate_to_index(rate, intel_dp->sink_rates); |
Ville Syrjälä | ed4e9c1 | 2015-03-12 17:10:36 +0200 | [diff] [blame] | 1418 | } |
| 1419 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 1420 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
| 1421 | uint8_t *link_bw, uint8_t *rate_select) |
Ville Syrjälä | 04a60f9 | 2015-07-06 15:10:06 +0300 | [diff] [blame] | 1422 | { |
| 1423 | if (intel_dp->num_sink_rates) { |
| 1424 | *link_bw = 0; |
| 1425 | *rate_select = |
| 1426 | intel_dp_rate_select(intel_dp, port_clock); |
| 1427 | } else { |
| 1428 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); |
| 1429 | *rate_select = 0; |
| 1430 | } |
| 1431 | } |
| 1432 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 1433 | bool |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1434 | intel_dp_compute_config(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 1435 | struct intel_crtc_state *pipe_config) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1436 | { |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1437 | struct drm_device *dev = encoder->base.dev; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1438 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 1439 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1440 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1441 | enum port port = dp_to_dig_port(intel_dp)->port; |
Ander Conselvan de Oliveira | 84556d5 | 2015-03-20 16:18:10 +0200 | [diff] [blame] | 1442 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 1443 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1444 | int lane_count, clock; |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1445 | int min_lane_count = 1; |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 1446 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 1447 | /* Conveniently, the link BW constants become indices with a shift...*/ |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1448 | int min_clock = 0; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1449 | int max_clock; |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 1450 | int bpp, mode_rate; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 1451 | int link_avail, link_clock; |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1452 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
| 1453 | int common_len; |
Ville Syrjälä | 04a60f9 | 2015-07-06 15:10:06 +0300 | [diff] [blame] | 1454 | uint8_t link_bw, rate_select; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1455 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1456 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1457 | |
| 1458 | /* No common link rates between source and sink */ |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1459 | WARN_ON(common_len <= 0); |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1460 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1461 | max_clock = common_len - 1; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1462 | |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1463 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1464 | pipe_config->has_pch_encoder = true; |
| 1465 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 1466 | pipe_config->has_dp_encoder = true; |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 1467 | pipe_config->has_drrs = false; |
Jani Nikula | 9fcb170 | 2015-05-05 16:32:12 +0300 | [diff] [blame] | 1468 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1469 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 1470 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
| 1471 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
| 1472 | adjusted_mode); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 1473 | |
| 1474 | if (INTEL_INFO(dev)->gen >= 9) { |
| 1475 | int ret; |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 1476 | ret = skl_update_scaler_crtc(pipe_config); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 1477 | if (ret) |
| 1478 | return ret; |
| 1479 | } |
| 1480 | |
Matt Roper | b5667627 | 2015-11-04 09:05:27 -0800 | [diff] [blame] | 1481 | if (HAS_GMCH_DISPLAY(dev)) |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 1482 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
| 1483 | intel_connector->panel.fitting_mode); |
| 1484 | else |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 1485 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
| 1486 | intel_connector->panel.fitting_mode); |
Zhao Yakui | 0d3a1be | 2010-07-19 09:43:13 +0100 | [diff] [blame] | 1487 | } |
| 1488 | |
Daniel Vetter | cb1793c | 2012-06-04 18:39:21 +0200 | [diff] [blame] | 1489 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
Daniel Vetter | 0af78a2 | 2012-05-23 11:30:55 +0200 | [diff] [blame] | 1490 | return false; |
| 1491 | |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 1492 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1493 | "max bw %d pixel clock %iKHz\n", |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1494 | max_lane_count, common_rates[max_clock], |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1495 | adjusted_mode->crtc_clock); |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 1496 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1497 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
| 1498 | * bpc in between. */ |
Daniel Vetter | 3e7ca98 | 2013-06-01 19:45:56 +0200 | [diff] [blame] | 1499 | bpp = pipe_config->pipe_bpp; |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1500 | if (is_edp(intel_dp)) { |
Thulasimani,Sivakumar | 22ce562 | 2015-07-31 11:05:27 +0530 | [diff] [blame] | 1501 | |
| 1502 | /* Get bpp from vbt only for panels that dont have bpp in edid */ |
| 1503 | if (intel_connector->base.display_info.bpc == 0 && |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 1504 | (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1505 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 1506 | dev_priv->vbt.edp.bpp); |
| 1507 | bpp = dev_priv->vbt.edp.bpp; |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1508 | } |
| 1509 | |
Jani Nikula | 344c5bb | 2014-09-09 11:25:13 +0300 | [diff] [blame] | 1510 | /* |
| 1511 | * Use the maximum clock and number of lanes the eDP panel |
| 1512 | * advertizes being capable of. The panels are generally |
| 1513 | * designed to support only a single clock and lane |
| 1514 | * configuration, and typically these values correspond to the |
| 1515 | * native resolution of the panel. |
| 1516 | */ |
| 1517 | min_lane_count = max_lane_count; |
| 1518 | min_clock = max_clock; |
Imre Deak | 7984211 | 2013-07-18 17:44:13 +0300 | [diff] [blame] | 1519 | } |
Daniel Vetter | 657445f | 2013-05-04 10:09:18 +0200 | [diff] [blame] | 1520 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1521 | for (; bpp >= 6*3; bpp -= 2*3) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1522 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
| 1523 | bpp); |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 1524 | |
Dave Airlie | c693099 | 2014-07-14 11:04:39 +1000 | [diff] [blame] | 1525 | for (clock = min_clock; clock <= max_clock; clock++) { |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1526 | for (lane_count = min_lane_count; |
| 1527 | lane_count <= max_lane_count; |
| 1528 | lane_count <<= 1) { |
| 1529 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1530 | link_clock = common_rates[clock]; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1531 | link_avail = intel_dp_max_data_rate(link_clock, |
| 1532 | lane_count); |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 1533 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1534 | if (mode_rate <= link_avail) { |
| 1535 | goto found; |
| 1536 | } |
| 1537 | } |
| 1538 | } |
| 1539 | } |
| 1540 | |
| 1541 | return false; |
| 1542 | |
| 1543 | found: |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 1544 | if (intel_dp->color_range_auto) { |
| 1545 | /* |
| 1546 | * See: |
| 1547 | * CEA-861-E - 5.1 Default Encoding Parameters |
| 1548 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
| 1549 | */ |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 1550 | pipe_config->limited_color_range = |
| 1551 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; |
| 1552 | } else { |
| 1553 | pipe_config->limited_color_range = |
| 1554 | intel_dp->limited_color_range; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 1555 | } |
| 1556 | |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 1557 | pipe_config->lane_count = lane_count; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1558 | |
Daniel Vetter | 657445f | 2013-05-04 10:09:18 +0200 | [diff] [blame] | 1559 | pipe_config->pipe_bpp = bpp; |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1560 | pipe_config->port_clock = common_rates[clock]; |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 1561 | |
Ville Syrjälä | 04a60f9 | 2015-07-06 15:10:06 +0300 | [diff] [blame] | 1562 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
| 1563 | &link_bw, &rate_select); |
| 1564 | |
| 1565 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", |
| 1566 | link_bw, rate_select, pipe_config->lane_count, |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 1567 | pipe_config->port_clock, bpp); |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1568 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
| 1569 | mode_rate, link_avail); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1570 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 1571 | intel_link_compute_m_n(bpp, lane_count, |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1572 | adjusted_mode->crtc_clock, |
| 1573 | pipe_config->port_clock, |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 1574 | &pipe_config->dp_m_n); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1575 | |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 1576 | if (intel_connector->panel.downclock_mode != NULL && |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 1577 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 1578 | pipe_config->has_drrs = true; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 1579 | intel_link_compute_m_n(bpp, lane_count, |
| 1580 | intel_connector->panel.downclock_mode->clock, |
| 1581 | pipe_config->port_clock, |
| 1582 | &pipe_config->dp_m2_n2); |
| 1583 | } |
| 1584 | |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 1585 | if (!HAS_DDI(dev)) |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1586 | intel_dp_set_clock(encoder, pipe_config); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1587 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1588 | return true; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1589 | } |
| 1590 | |
Ville Syrjälä | 901c2da | 2015-08-17 18:05:12 +0300 | [diff] [blame] | 1591 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
| 1592 | const struct intel_crtc_state *pipe_config) |
| 1593 | { |
| 1594 | intel_dp->link_rate = pipe_config->port_clock; |
| 1595 | intel_dp->lane_count = pipe_config->lane_count; |
| 1596 | } |
| 1597 | |
Daniel Vetter | 8ac33ed | 2014-04-24 23:54:54 +0200 | [diff] [blame] | 1598 | static void intel_dp_prepare(struct intel_encoder *encoder) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1599 | { |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1600 | struct drm_device *dev = encoder->base.dev; |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1601 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1602 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1603 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1604 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 1605 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1606 | |
Ville Syrjälä | 901c2da | 2015-08-17 18:05:12 +0300 | [diff] [blame] | 1607 | intel_dp_set_link_params(intel_dp, crtc->config); |
| 1608 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1609 | /* |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1610 | * There are four kinds of DP registers: |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1611 | * |
| 1612 | * IBX PCH |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1613 | * SNB CPU |
| 1614 | * IVB CPU |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1615 | * CPT PCH |
| 1616 | * |
| 1617 | * IBX PCH and CPU are the same for almost everything, |
| 1618 | * except that the CPU DP PLL is configured in this |
| 1619 | * register |
| 1620 | * |
| 1621 | * CPT PCH is quite different, having many bits moved |
| 1622 | * to the TRANS_DP_CTL register instead. That |
| 1623 | * configuration happens (oddly) in ironlake_pch_enable |
| 1624 | */ |
Adam Jackson | 9c9e792 | 2010-04-05 17:57:59 -0400 | [diff] [blame] | 1625 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1626 | /* Preserve the BIOS-computed detected bit. This is |
| 1627 | * supposed to be read-only. |
| 1628 | */ |
| 1629 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1630 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1631 | /* Handle DP bits in common between all three register formats */ |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1632 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 1633 | intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1634 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1635 | /* Split out the IBX/CPU vs CPT settings */ |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1636 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1637 | if (IS_GEN7(dev) && port == PORT_A) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1638 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1639 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 1640 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1641 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 1642 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
| 1643 | |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 1644 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1645 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 1646 | |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 1647 | intel_dp->DP |= crtc->pipe << 29; |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1648 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
Ville Syrjälä | e3ef447 | 2015-05-05 17:17:31 +0300 | [diff] [blame] | 1649 | u32 trans_dp; |
| 1650 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1651 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
Ville Syrjälä | e3ef447 | 2015-05-05 17:17:31 +0300 | [diff] [blame] | 1652 | |
| 1653 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
| 1654 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 1655 | trans_dp |= TRANS_DP_ENH_FRAMING; |
| 1656 | else |
| 1657 | trans_dp &= ~TRANS_DP_ENH_FRAMING; |
| 1658 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1659 | } else { |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 1660 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 1661 | !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range) |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 1662 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1663 | |
| 1664 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1665 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 1666 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1667 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 1668 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
| 1669 | |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 1670 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1671 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 1672 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1673 | if (IS_CHERRYVIEW(dev)) |
Chon Ming Lee | 44f37d1 | 2014-04-09 13:28:21 +0300 | [diff] [blame] | 1674 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1675 | else if (crtc->pipe == PIPE_B) |
| 1676 | intel_dp->DP |= DP_PIPEB_SELECT; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1677 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1678 | } |
| 1679 | |
Paulo Zanoni | ffd6749d | 2013-12-19 14:29:42 -0200 | [diff] [blame] | 1680 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
| 1681 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1682 | |
Paulo Zanoni | 1a5ef5b | 2013-12-19 14:29:43 -0200 | [diff] [blame] | 1683 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
| 1684 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1685 | |
Paulo Zanoni | ffd6749d | 2013-12-19 14:29:42 -0200 | [diff] [blame] | 1686 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
| 1687 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1688 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1689 | static void wait_panel_status(struct intel_dp *intel_dp, |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1690 | u32 mask, |
| 1691 | u32 value) |
| 1692 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1693 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1694 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1695 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1696 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1697 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1698 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1699 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1700 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1701 | |
| 1702 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1703 | mask, value, |
| 1704 | I915_READ(pp_stat_reg), |
| 1705 | I915_READ(pp_ctrl_reg)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1706 | |
Tvrtko Ursulin | 3f17762 | 2016-03-03 14:36:41 +0000 | [diff] [blame] | 1707 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, |
| 1708 | 5 * USEC_PER_SEC, 10 * USEC_PER_MSEC)) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1709 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1710 | I915_READ(pp_stat_reg), |
| 1711 | I915_READ(pp_ctrl_reg)); |
Chris Wilson | 54c136d | 2013-12-02 09:57:16 +0000 | [diff] [blame] | 1712 | |
| 1713 | DRM_DEBUG_KMS("Wait complete\n"); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1714 | } |
| 1715 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1716 | static void wait_panel_on(struct intel_dp *intel_dp) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1717 | { |
| 1718 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1719 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1720 | } |
| 1721 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1722 | static void wait_panel_off(struct intel_dp *intel_dp) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1723 | { |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1724 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1725 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1726 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1727 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1728 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1729 | { |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 1730 | ktime_t panel_power_on_time; |
| 1731 | s64 panel_power_off_duration; |
| 1732 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1733 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1734 | |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 1735 | /* take the difference of currrent time and panel power off time |
| 1736 | * and then make panel wait for t11_t12 if needed. */ |
| 1737 | panel_power_on_time = ktime_get_boottime(); |
| 1738 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); |
| 1739 | |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1740 | /* When we disable the VDD override bit last we have to do the manual |
| 1741 | * wait. */ |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 1742 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
| 1743 | wait_remaining_ms_from_jiffies(jiffies, |
| 1744 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1745 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1746 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1747 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1748 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1749 | static void wait_backlight_on(struct intel_dp *intel_dp) |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1750 | { |
| 1751 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
| 1752 | intel_dp->backlight_on_delay); |
| 1753 | } |
| 1754 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1755 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1756 | { |
| 1757 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
| 1758 | intel_dp->backlight_off_delay); |
| 1759 | } |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1760 | |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1761 | /* Read the current pp_control value, unlocking the register if it |
| 1762 | * is locked |
| 1763 | */ |
| 1764 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1765 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1766 | { |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1767 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1768 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1769 | u32 control; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1770 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1771 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1772 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1773 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 1774 | if (!IS_BROXTON(dev)) { |
| 1775 | control &= ~PANEL_UNLOCK_MASK; |
| 1776 | control |= PANEL_UNLOCK_REGS; |
| 1777 | } |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1778 | return control; |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1779 | } |
| 1780 | |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 1781 | /* |
| 1782 | * Must be paired with edp_panel_vdd_off(). |
| 1783 | * Must hold pps_mutex around the whole on/off sequence. |
| 1784 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
| 1785 | */ |
Ville Syrjälä | 1e0560e | 2014-08-19 13:24:25 +0300 | [diff] [blame] | 1786 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1787 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1788 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1789 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1790 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1791 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1792 | enum intel_display_power_domain power_domain; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1793 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1794 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1795 | bool need_to_disable = !intel_dp->want_panel_vdd; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1796 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1797 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1798 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1799 | if (!is_edp(intel_dp)) |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1800 | return false; |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1801 | |
Egbert Eich | 2c623c1 | 2014-11-25 12:54:57 +0100 | [diff] [blame] | 1802 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1803 | intel_dp->want_panel_vdd = true; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1804 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1805 | if (edp_have_panel_vdd(intel_dp)) |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1806 | return need_to_disable; |
Paulo Zanoni | b0665d5 | 2013-10-30 19:50:27 -0200 | [diff] [blame] | 1807 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 1808 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1809 | intel_display_power_get(dev_priv, power_domain); |
Paulo Zanoni | e9cb81a | 2013-11-21 13:47:23 -0200 | [diff] [blame] | 1810 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1811 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
| 1812 | port_name(intel_dig_port->port)); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1813 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1814 | if (!edp_have_panel_power(intel_dp)) |
| 1815 | wait_panel_power_cycle(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1816 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1817 | pp = ironlake_get_pp_control(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1818 | pp |= EDP_FORCE_VDD; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 1819 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1820 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1821 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1822 | |
| 1823 | I915_WRITE(pp_ctrl_reg, pp); |
| 1824 | POSTING_READ(pp_ctrl_reg); |
| 1825 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1826 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 1827 | /* |
| 1828 | * If the panel wasn't on, delay before accessing aux channel |
| 1829 | */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1830 | if (!edp_have_panel_power(intel_dp)) { |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1831 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
| 1832 | port_name(intel_dig_port->port)); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1833 | msleep(intel_dp->panel_power_up_delay); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1834 | } |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1835 | |
| 1836 | return need_to_disable; |
| 1837 | } |
| 1838 | |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 1839 | /* |
| 1840 | * Must be paired with intel_edp_panel_vdd_off() or |
| 1841 | * intel_edp_panel_off(). |
| 1842 | * Nested calls to these functions are not allowed since |
| 1843 | * we drop the lock. Caller must use some higher level |
| 1844 | * locking to prevent nested calls from other threads. |
| 1845 | */ |
Daniel Vetter | b80d6c7 | 2014-03-19 15:54:37 +0100 | [diff] [blame] | 1846 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1847 | { |
Ville Syrjälä | c695b6b | 2014-08-18 22:16:03 +0300 | [diff] [blame] | 1848 | bool vdd; |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1849 | |
Ville Syrjälä | c695b6b | 2014-08-18 22:16:03 +0300 | [diff] [blame] | 1850 | if (!is_edp(intel_dp)) |
| 1851 | return; |
| 1852 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1853 | pps_lock(intel_dp); |
Ville Syrjälä | c695b6b | 2014-08-18 22:16:03 +0300 | [diff] [blame] | 1854 | vdd = edp_panel_vdd_on(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1855 | pps_unlock(intel_dp); |
Ville Syrjälä | c695b6b | 2014-08-18 22:16:03 +0300 | [diff] [blame] | 1856 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1857 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1858 | port_name(dp_to_dig_port(intel_dp)->port)); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1859 | } |
| 1860 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1861 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1862 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1863 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1864 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1865 | struct intel_digital_port *intel_dig_port = |
| 1866 | dp_to_dig_port(intel_dp); |
| 1867 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 1868 | enum intel_display_power_domain power_domain; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1869 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1870 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1871 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1872 | lockdep_assert_held(&dev_priv->pps_mutex); |
Daniel Vetter | a0e99e6 | 2012-12-02 01:05:46 +0100 | [diff] [blame] | 1873 | |
Ville Syrjälä | 15e899a | 2014-08-18 22:16:02 +0300 | [diff] [blame] | 1874 | WARN_ON(intel_dp->want_panel_vdd); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1875 | |
Ville Syrjälä | 15e899a | 2014-08-18 22:16:02 +0300 | [diff] [blame] | 1876 | if (!edp_have_panel_vdd(intel_dp)) |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1877 | return; |
Paulo Zanoni | b0665d5 | 2013-10-30 19:50:27 -0200 | [diff] [blame] | 1878 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1879 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
| 1880 | port_name(intel_dig_port->port)); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1881 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1882 | pp = ironlake_get_pp_control(intel_dp); |
| 1883 | pp &= ~EDP_FORCE_VDD; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1884 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1885 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 1886 | pp_stat_reg = _pp_stat_reg(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1887 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1888 | I915_WRITE(pp_ctrl_reg, pp); |
| 1889 | POSTING_READ(pp_ctrl_reg); |
Paulo Zanoni | 90791a5 | 2013-12-06 17:32:42 -0200 | [diff] [blame] | 1890 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1891 | /* Make sure sequencer is idle before allowing subsequent activity */ |
| 1892 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1893 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
Paulo Zanoni | e9cb81a | 2013-11-21 13:47:23 -0200 | [diff] [blame] | 1894 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1895 | if ((pp & POWER_TARGET_ON) == 0) |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 1896 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
Paulo Zanoni | e9cb81a | 2013-11-21 13:47:23 -0200 | [diff] [blame] | 1897 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 1898 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1899 | intel_display_power_put(dev_priv, power_domain); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1900 | } |
| 1901 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1902 | static void edp_panel_vdd_work(struct work_struct *__work) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1903 | { |
| 1904 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
| 1905 | struct intel_dp, panel_vdd_work); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1906 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1907 | pps_lock(intel_dp); |
Ville Syrjälä | 15e899a | 2014-08-18 22:16:02 +0300 | [diff] [blame] | 1908 | if (!intel_dp->want_panel_vdd) |
| 1909 | edp_panel_vdd_off_sync(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1910 | pps_unlock(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1911 | } |
| 1912 | |
Imre Deak | aba8689 | 2014-07-30 15:57:31 +0300 | [diff] [blame] | 1913 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
| 1914 | { |
| 1915 | unsigned long delay; |
| 1916 | |
| 1917 | /* |
| 1918 | * Queue the timer to fire a long time from now (relative to the power |
| 1919 | * down delay) to keep the panel power up across a sequence of |
| 1920 | * operations. |
| 1921 | */ |
| 1922 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
| 1923 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
| 1924 | } |
| 1925 | |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 1926 | /* |
| 1927 | * Must be paired with edp_panel_vdd_on(). |
| 1928 | * Must hold pps_mutex around the whole on/off sequence. |
| 1929 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
| 1930 | */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1931 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1932 | { |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1933 | struct drm_i915_private *dev_priv = |
| 1934 | intel_dp_to_dev(intel_dp)->dev_private; |
| 1935 | |
| 1936 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1937 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1938 | if (!is_edp(intel_dp)) |
| 1939 | return; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1940 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1941 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1942 | port_name(dp_to_dig_port(intel_dp)->port)); |
Keith Packard | f2e8b18 | 2011-11-01 20:01:35 -0700 | [diff] [blame] | 1943 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1944 | intel_dp->want_panel_vdd = false; |
| 1945 | |
Imre Deak | aba8689 | 2014-07-30 15:57:31 +0300 | [diff] [blame] | 1946 | if (sync) |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1947 | edp_panel_vdd_off_sync(intel_dp); |
Imre Deak | aba8689 | 2014-07-30 15:57:31 +0300 | [diff] [blame] | 1948 | else |
| 1949 | edp_panel_vdd_schedule_off(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1950 | } |
| 1951 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 1952 | static void edp_panel_on(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1953 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1954 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1955 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1956 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1957 | i915_reg_t pp_ctrl_reg; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1958 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 1959 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1960 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1961 | if (!is_edp(intel_dp)) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1962 | return; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1963 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1964 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
| 1965 | port_name(dp_to_dig_port(intel_dp)->port)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1966 | |
Ville Syrjälä | e7a89ac | 2014-10-16 21:30:07 +0300 | [diff] [blame] | 1967 | if (WARN(edp_have_panel_power(intel_dp), |
| 1968 | "eDP port %c panel power already on\n", |
| 1969 | port_name(dp_to_dig_port(intel_dp)->port))) |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 1970 | return; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1971 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1972 | wait_panel_power_cycle(intel_dp); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1973 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1974 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1975 | pp = ironlake_get_pp_control(intel_dp); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1976 | if (IS_GEN5(dev)) { |
| 1977 | /* ILK workaround: disable reset around power sequence */ |
| 1978 | pp &= ~PANEL_POWER_RESET; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1979 | I915_WRITE(pp_ctrl_reg, pp); |
| 1980 | POSTING_READ(pp_ctrl_reg); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1981 | } |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1982 | |
Keith Packard | 1c0ae80 | 2011-09-19 13:59:29 -0700 | [diff] [blame] | 1983 | pp |= POWER_TARGET_ON; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1984 | if (!IS_GEN5(dev)) |
| 1985 | pp |= PANEL_POWER_RESET; |
| 1986 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1987 | I915_WRITE(pp_ctrl_reg, pp); |
| 1988 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1989 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1990 | wait_panel_on(intel_dp); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1991 | intel_dp->last_power_on = jiffies; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1992 | |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1993 | if (IS_GEN5(dev)) { |
| 1994 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1995 | I915_WRITE(pp_ctrl_reg, pp); |
| 1996 | POSTING_READ(pp_ctrl_reg); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1997 | } |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 1998 | } |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1999 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2000 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
| 2001 | { |
| 2002 | if (!is_edp(intel_dp)) |
| 2003 | return; |
| 2004 | |
| 2005 | pps_lock(intel_dp); |
| 2006 | edp_panel_on(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2007 | pps_unlock(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2008 | } |
| 2009 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2010 | |
| 2011 | static void edp_panel_off(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2012 | { |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 2013 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2014 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2015 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2016 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 2017 | enum intel_display_power_domain power_domain; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2018 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2019 | i915_reg_t pp_ctrl_reg; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2020 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2021 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2022 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 2023 | if (!is_edp(intel_dp)) |
| 2024 | return; |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 2025 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 2026 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
| 2027 | port_name(dp_to_dig_port(intel_dp)->port)); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 2028 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 2029 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
| 2030 | port_name(dp_to_dig_port(intel_dp)->port)); |
Jani Nikula | 24f3e09 | 2014-03-17 16:43:36 +0200 | [diff] [blame] | 2031 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2032 | pp = ironlake_get_pp_control(intel_dp); |
Daniel Vetter | 35a3855 | 2012-08-12 22:17:14 +0200 | [diff] [blame] | 2033 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
| 2034 | * panels get very unhappy and cease to work. */ |
Patrik Jakobsson | b306415 | 2014-03-04 00:42:44 +0100 | [diff] [blame] | 2035 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
| 2036 | EDP_BLC_ENABLE); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2037 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2038 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2039 | |
Paulo Zanoni | 849e39f | 2014-03-07 20:05:20 -0300 | [diff] [blame] | 2040 | intel_dp->want_panel_vdd = false; |
| 2041 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2042 | I915_WRITE(pp_ctrl_reg, pp); |
| 2043 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2044 | |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 2045 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2046 | wait_panel_off(intel_dp); |
Paulo Zanoni | 849e39f | 2014-03-07 20:05:20 -0300 | [diff] [blame] | 2047 | |
| 2048 | /* We got a reference when we enabled the VDD. */ |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 2049 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 2050 | intel_display_power_put(dev_priv, power_domain); |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2051 | } |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2052 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2053 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
| 2054 | { |
| 2055 | if (!is_edp(intel_dp)) |
| 2056 | return; |
| 2057 | |
| 2058 | pps_lock(intel_dp); |
| 2059 | edp_panel_off(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2060 | pps_unlock(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2061 | } |
| 2062 | |
Jani Nikula | 1250d10 | 2014-08-12 17:11:39 +0300 | [diff] [blame] | 2063 | /* Enable backlight in the panel power control. */ |
| 2064 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2065 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2066 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2067 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2068 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2069 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2070 | i915_reg_t pp_ctrl_reg; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2071 | |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 2072 | /* |
| 2073 | * If we enable the backlight right away following a panel power |
| 2074 | * on, we may see slight flicker as the panel syncs with the eDP |
| 2075 | * link. So delay a bit to make sure the image is solid before |
| 2076 | * allowing it to appear. |
| 2077 | */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2078 | wait_backlight_on(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2079 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2080 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2081 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2082 | pp = ironlake_get_pp_control(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2083 | pp |= EDP_BLC_ENABLE; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2084 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2085 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2086 | |
| 2087 | I915_WRITE(pp_ctrl_reg, pp); |
| 2088 | POSTING_READ(pp_ctrl_reg); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2089 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2090 | pps_unlock(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2091 | } |
| 2092 | |
Jani Nikula | 1250d10 | 2014-08-12 17:11:39 +0300 | [diff] [blame] | 2093 | /* Enable backlight PWM and backlight PP control. */ |
| 2094 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
| 2095 | { |
| 2096 | if (!is_edp(intel_dp)) |
| 2097 | return; |
| 2098 | |
| 2099 | DRM_DEBUG_KMS("\n"); |
| 2100 | |
| 2101 | intel_panel_enable_backlight(intel_dp->attached_connector); |
| 2102 | _intel_edp_backlight_on(intel_dp); |
| 2103 | } |
| 2104 | |
| 2105 | /* Disable backlight in the panel power control. */ |
| 2106 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2107 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2108 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2109 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2110 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2111 | i915_reg_t pp_ctrl_reg; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2112 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 2113 | if (!is_edp(intel_dp)) |
| 2114 | return; |
| 2115 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2116 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2117 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2118 | pp = ironlake_get_pp_control(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2119 | pp &= ~EDP_BLC_ENABLE; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2120 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2121 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2122 | |
| 2123 | I915_WRITE(pp_ctrl_reg, pp); |
| 2124 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | f7d2323 | 2014-03-31 11:13:56 -0700 | [diff] [blame] | 2125 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2126 | pps_unlock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2127 | |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 2128 | intel_dp->last_backlight_off = jiffies; |
Jesse Barnes | f7d2323 | 2014-03-31 11:13:56 -0700 | [diff] [blame] | 2129 | edp_wait_backlight_off(intel_dp); |
Jani Nikula | 1250d10 | 2014-08-12 17:11:39 +0300 | [diff] [blame] | 2130 | } |
Jesse Barnes | f7d2323 | 2014-03-31 11:13:56 -0700 | [diff] [blame] | 2131 | |
Jani Nikula | 1250d10 | 2014-08-12 17:11:39 +0300 | [diff] [blame] | 2132 | /* Disable backlight PP control and backlight PWM. */ |
| 2133 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
| 2134 | { |
| 2135 | if (!is_edp(intel_dp)) |
| 2136 | return; |
| 2137 | |
| 2138 | DRM_DEBUG_KMS("\n"); |
| 2139 | |
| 2140 | _intel_edp_backlight_off(intel_dp); |
Jesse Barnes | f7d2323 | 2014-03-31 11:13:56 -0700 | [diff] [blame] | 2141 | intel_panel_disable_backlight(intel_dp->attached_connector); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2142 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2143 | |
Jani Nikula | 73580fb7 | 2014-08-12 17:11:41 +0300 | [diff] [blame] | 2144 | /* |
| 2145 | * Hook for controlling the panel power control backlight through the bl_power |
| 2146 | * sysfs attribute. Take care to handle multiple calls. |
| 2147 | */ |
| 2148 | static void intel_edp_backlight_power(struct intel_connector *connector, |
| 2149 | bool enable) |
| 2150 | { |
| 2151 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2152 | bool is_enabled; |
| 2153 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2154 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2155 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2156 | pps_unlock(intel_dp); |
Jani Nikula | 73580fb7 | 2014-08-12 17:11:41 +0300 | [diff] [blame] | 2157 | |
| 2158 | if (is_enabled == enable) |
| 2159 | return; |
| 2160 | |
Jani Nikula | 23ba937 | 2014-08-27 14:08:43 +0300 | [diff] [blame] | 2161 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
| 2162 | enable ? "enable" : "disable"); |
Jani Nikula | 73580fb7 | 2014-08-12 17:11:41 +0300 | [diff] [blame] | 2163 | |
| 2164 | if (enable) |
| 2165 | _intel_edp_backlight_on(intel_dp); |
| 2166 | else |
| 2167 | _intel_edp_backlight_off(intel_dp); |
| 2168 | } |
| 2169 | |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2170 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
| 2171 | { |
| 2172 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 2173 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
| 2174 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; |
| 2175 | |
| 2176 | I915_STATE_WARN(cur_state != state, |
| 2177 | "DP port %c state assertion failure (expected %s, current %s)\n", |
| 2178 | port_name(dig_port->port), |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 2179 | onoff(state), onoff(cur_state)); |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2180 | } |
| 2181 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) |
| 2182 | |
| 2183 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) |
| 2184 | { |
| 2185 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; |
| 2186 | |
| 2187 | I915_STATE_WARN(cur_state != state, |
| 2188 | "eDP PLL state assertion failure (expected %s, current %s)\n", |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 2189 | onoff(state), onoff(cur_state)); |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2190 | } |
| 2191 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) |
| 2192 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) |
| 2193 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2194 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2195 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2196 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2197 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
| 2198 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2199 | |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2200 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 2201 | assert_dp_port_disabled(intel_dp); |
| 2202 | assert_edp_pll_disabled(dev_priv); |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2203 | |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2204 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
| 2205 | crtc->config->port_clock); |
| 2206 | |
| 2207 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; |
| 2208 | |
| 2209 | if (crtc->config->port_clock == 162000) |
| 2210 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
| 2211 | else |
| 2212 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
| 2213 | |
| 2214 | I915_WRITE(DP_A, intel_dp->DP); |
| 2215 | POSTING_READ(DP_A); |
| 2216 | udelay(500); |
| 2217 | |
Ville Syrjälä | 6b23f3e | 2016-04-01 21:53:19 +0300 | [diff] [blame] | 2218 | /* |
| 2219 | * [DevILK] Work around required when enabling DP PLL |
| 2220 | * while a pipe is enabled going to FDI: |
| 2221 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI |
| 2222 | * 2. Program DP PLL enable |
| 2223 | */ |
| 2224 | if (IS_GEN5(dev_priv)) |
| 2225 | intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe); |
| 2226 | |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 2227 | intel_dp->DP |= DP_PLL_ENABLE; |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2228 | |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 2229 | I915_WRITE(DP_A, intel_dp->DP); |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 2230 | POSTING_READ(DP_A); |
| 2231 | udelay(200); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2232 | } |
| 2233 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2234 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2235 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2236 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2237 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
| 2238 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2239 | |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2240 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 2241 | assert_dp_port_disabled(intel_dp); |
| 2242 | assert_edp_pll_enabled(dev_priv); |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2243 | |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2244 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
| 2245 | |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2246 | intel_dp->DP &= ~DP_PLL_ENABLE; |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 2247 | |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2248 | I915_WRITE(DP_A, intel_dp->DP); |
Chris Wilson | 1af5fa1 | 2010-09-08 21:07:28 +0100 | [diff] [blame] | 2249 | POSTING_READ(DP_A); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2250 | udelay(200); |
| 2251 | } |
| 2252 | |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2253 | /* If the sink supports it, try to set the power state appropriately */ |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2254 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2255 | { |
| 2256 | int ret, i; |
| 2257 | |
| 2258 | /* Should have a valid DPCD by this point */ |
| 2259 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
| 2260 | return; |
| 2261 | |
| 2262 | if (mode != DRM_MODE_DPMS_ON) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2263 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
| 2264 | DP_SET_POWER_D3); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2265 | } else { |
| 2266 | /* |
| 2267 | * When turning on, we need to retry for 1ms to give the sink |
| 2268 | * time to wake up. |
| 2269 | */ |
| 2270 | for (i = 0; i < 3; i++) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2271 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
| 2272 | DP_SET_POWER_D0); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2273 | if (ret == 1) |
| 2274 | break; |
| 2275 | msleep(1); |
| 2276 | } |
| 2277 | } |
Jani Nikula | f9cac72 | 2014-09-02 16:33:52 +0300 | [diff] [blame] | 2278 | |
| 2279 | if (ret != 1) |
| 2280 | DRM_DEBUG_KMS("failed to %s sink power state\n", |
| 2281 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2282 | } |
| 2283 | |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2284 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
| 2285 | enum pipe *pipe) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2286 | { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2287 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2288 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2289 | struct drm_device *dev = encoder->base.dev; |
| 2290 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 2291 | enum intel_display_power_domain power_domain; |
| 2292 | u32 tmp; |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2293 | bool ret; |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 2294 | |
| 2295 | power_domain = intel_display_port_power_domain(encoder); |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2296 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 2297 | return false; |
| 2298 | |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2299 | ret = false; |
| 2300 | |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 2301 | tmp = I915_READ(intel_dp->output_reg); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2302 | |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2303 | if (!(tmp & DP_PORT_EN)) |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2304 | goto out; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2305 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2306 | if (IS_GEN7(dev) && port == PORT_A) { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2307 | *pipe = PORT_TO_PIPE_CPT(tmp); |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2308 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
Ville Syrjälä | adc289d | 2015-05-05 17:17:30 +0300 | [diff] [blame] | 2309 | enum pipe p; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2310 | |
Ville Syrjälä | adc289d | 2015-05-05 17:17:30 +0300 | [diff] [blame] | 2311 | for_each_pipe(dev_priv, p) { |
| 2312 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); |
| 2313 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { |
| 2314 | *pipe = p; |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2315 | ret = true; |
| 2316 | |
| 2317 | goto out; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2318 | } |
| 2319 | } |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2320 | |
Daniel Vetter | 4a0833e | 2012-10-26 10:58:11 +0200 | [diff] [blame] | 2321 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2322 | i915_mmio_reg_offset(intel_dp->output_reg)); |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2323 | } else if (IS_CHERRYVIEW(dev)) { |
| 2324 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
| 2325 | } else { |
| 2326 | *pipe = PORT_TO_PIPE(tmp); |
Daniel Vetter | 4a0833e | 2012-10-26 10:58:11 +0200 | [diff] [blame] | 2327 | } |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2328 | |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2329 | ret = true; |
| 2330 | |
| 2331 | out: |
| 2332 | intel_display_power_put(dev_priv, power_domain); |
| 2333 | |
| 2334 | return ret; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2335 | } |
| 2336 | |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2337 | static void intel_dp_get_config(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 2338 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2339 | { |
| 2340 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2341 | u32 tmp, flags = 0; |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2342 | struct drm_device *dev = encoder->base.dev; |
| 2343 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2344 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 2345 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2346 | |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 2347 | tmp = I915_READ(intel_dp->output_reg); |
Jani Nikula | 9fcb170 | 2015-05-05 16:32:12 +0300 | [diff] [blame] | 2348 | |
| 2349 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 2350 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2351 | if (HAS_PCH_CPT(dev) && port != PORT_A) { |
Ville Syrjälä | b81e34c | 2015-07-06 15:10:03 +0300 | [diff] [blame] | 2352 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
| 2353 | |
| 2354 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2355 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 2356 | else |
| 2357 | flags |= DRM_MODE_FLAG_NHSYNC; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2358 | |
Ville Syrjälä | b81e34c | 2015-07-06 15:10:03 +0300 | [diff] [blame] | 2359 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2360 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 2361 | else |
| 2362 | flags |= DRM_MODE_FLAG_NVSYNC; |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2363 | } else { |
| 2364 | if (tmp & DP_SYNC_HS_HIGH) |
| 2365 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 2366 | else |
| 2367 | flags |= DRM_MODE_FLAG_NHSYNC; |
| 2368 | |
| 2369 | if (tmp & DP_SYNC_VS_HIGH) |
| 2370 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 2371 | else |
| 2372 | flags |= DRM_MODE_FLAG_NVSYNC; |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2373 | } |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2374 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 2375 | pipe_config->base.adjusted_mode.flags |= flags; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 2376 | |
Ville Syrjälä | 8c875fc | 2014-09-12 15:46:29 +0300 | [diff] [blame] | 2377 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2378 | !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235) |
Ville Syrjälä | 8c875fc | 2014-09-12 15:46:29 +0300 | [diff] [blame] | 2379 | pipe_config->limited_color_range = true; |
| 2380 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 2381 | pipe_config->has_dp_encoder = true; |
| 2382 | |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 2383 | pipe_config->lane_count = |
| 2384 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; |
| 2385 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 2386 | intel_dp_get_m_n(crtc, pipe_config); |
| 2387 | |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 2388 | if (port == PORT_A) { |
Ville Syrjälä | b377e0d | 2015-10-29 21:25:59 +0200 | [diff] [blame] | 2389 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 2390 | pipe_config->port_clock = 162000; |
| 2391 | else |
| 2392 | pipe_config->port_clock = 270000; |
| 2393 | } |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 2394 | |
Ville Syrjälä | e3b247d | 2016-02-17 21:41:09 +0200 | [diff] [blame] | 2395 | pipe_config->base.adjusted_mode.crtc_clock = |
| 2396 | intel_dotclock_calculate(pipe_config->port_clock, |
| 2397 | &pipe_config->dp_m_n); |
Daniel Vetter | 7f16e5c | 2013-11-04 16:28:47 +0100 | [diff] [blame] | 2398 | |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 2399 | if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
| 2400 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { |
Jani Nikula | c6cd2ee | 2013-10-21 10:52:07 +0300 | [diff] [blame] | 2401 | /* |
| 2402 | * This is a big fat ugly hack. |
| 2403 | * |
| 2404 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
| 2405 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
| 2406 | * unknown we fail to light up. Yet the same BIOS boots up with |
| 2407 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
| 2408 | * max, not what it tells us to use. |
| 2409 | * |
| 2410 | * Note: This will still be broken if the eDP panel is not lit |
| 2411 | * up by the BIOS, and thus we can't get the mode at module |
| 2412 | * load. |
| 2413 | */ |
| 2414 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 2415 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
| 2416 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; |
Jani Nikula | c6cd2ee | 2013-10-21 10:52:07 +0300 | [diff] [blame] | 2417 | } |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2418 | } |
| 2419 | |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 2420 | static void intel_disable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2421 | { |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 2422 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 2423 | struct drm_device *dev = encoder->base.dev; |
Jani Nikula | 495a5bb | 2014-10-27 16:26:55 +0200 | [diff] [blame] | 2424 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 2425 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2426 | if (crtc->config->has_audio) |
Jani Nikula | 495a5bb | 2014-10-27 16:26:55 +0200 | [diff] [blame] | 2427 | intel_audio_codec_disable(encoder); |
Daniel Vetter | 6cb4983 | 2012-05-20 17:14:50 +0200 | [diff] [blame] | 2428 | |
Rodrigo Vivi | b32c6f4 | 2014-11-20 03:44:37 -0800 | [diff] [blame] | 2429 | if (HAS_PSR(dev) && !HAS_DDI(dev)) |
| 2430 | intel_psr_disable(intel_dp); |
| 2431 | |
Daniel Vetter | 6cb4983 | 2012-05-20 17:14:50 +0200 | [diff] [blame] | 2432 | /* Make sure the panel is off before trying to change the mode. But also |
| 2433 | * ensure that we have vdd while we switch off the panel. */ |
Jani Nikula | 24f3e09 | 2014-03-17 16:43:36 +0200 | [diff] [blame] | 2434 | intel_edp_panel_vdd_on(intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2435 | intel_edp_backlight_off(intel_dp); |
Jani Nikula | fdbc3b1 | 2013-11-12 17:10:13 +0200 | [diff] [blame] | 2436 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2437 | intel_edp_panel_off(intel_dp); |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 2438 | |
Ville Syrjälä | 08aff3f | 2014-08-18 22:16:09 +0300 | [diff] [blame] | 2439 | /* disable the port before the pipe on g4x */ |
| 2440 | if (INTEL_INFO(dev)->gen < 5) |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 2441 | intel_dp_link_down(intel_dp); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2442 | } |
| 2443 | |
Ville Syrjälä | 08aff3f | 2014-08-18 22:16:09 +0300 | [diff] [blame] | 2444 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2445 | { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2446 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 2447 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2448 | |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 2449 | intel_dp_link_down(intel_dp); |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2450 | |
| 2451 | /* Only ilk+ has port A */ |
Ville Syrjälä | 08aff3f | 2014-08-18 22:16:09 +0300 | [diff] [blame] | 2452 | if (port == PORT_A) |
| 2453 | ironlake_edp_pll_off(intel_dp); |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 2454 | } |
| 2455 | |
| 2456 | static void vlv_post_disable_dp(struct intel_encoder *encoder) |
| 2457 | { |
| 2458 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2459 | |
| 2460 | intel_dp_link_down(intel_dp); |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2461 | } |
| 2462 | |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2463 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
| 2464 | { |
| 2465 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2466 | struct drm_device *dev = encoder->base.dev; |
| 2467 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2468 | |
| 2469 | intel_dp_link_down(intel_dp); |
| 2470 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2471 | mutex_lock(&dev_priv->sb_lock); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2472 | |
Ville Syrjälä | a8f327f | 2015-07-09 20:14:11 +0300 | [diff] [blame] | 2473 | /* Assert data lane reset */ |
| 2474 | chv_data_lane_soft_reset(encoder, true); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2475 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2476 | mutex_unlock(&dev_priv->sb_lock); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2477 | } |
| 2478 | |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2479 | static void |
| 2480 | _intel_dp_set_link_train(struct intel_dp *intel_dp, |
| 2481 | uint32_t *DP, |
| 2482 | uint8_t dp_train_pat) |
| 2483 | { |
| 2484 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2485 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 2486 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2487 | enum port port = intel_dig_port->port; |
| 2488 | |
| 2489 | if (HAS_DDI(dev)) { |
| 2490 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
| 2491 | |
| 2492 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
| 2493 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2494 | else |
| 2495 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2496 | |
| 2497 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 2498 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2499 | case DP_TRAINING_PATTERN_DISABLE: |
| 2500 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
| 2501 | |
| 2502 | break; |
| 2503 | case DP_TRAINING_PATTERN_1: |
| 2504 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 2505 | break; |
| 2506 | case DP_TRAINING_PATTERN_2: |
| 2507 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
| 2508 | break; |
| 2509 | case DP_TRAINING_PATTERN_3: |
| 2510 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
| 2511 | break; |
| 2512 | } |
| 2513 | I915_WRITE(DP_TP_CTL(port), temp); |
| 2514 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2515 | } else if ((IS_GEN7(dev) && port == PORT_A) || |
| 2516 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2517 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
| 2518 | |
| 2519 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2520 | case DP_TRAINING_PATTERN_DISABLE: |
| 2521 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
| 2522 | break; |
| 2523 | case DP_TRAINING_PATTERN_1: |
| 2524 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
| 2525 | break; |
| 2526 | case DP_TRAINING_PATTERN_2: |
| 2527 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
| 2528 | break; |
| 2529 | case DP_TRAINING_PATTERN_3: |
| 2530 | DRM_ERROR("DP training pattern 3 not supported\n"); |
| 2531 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
| 2532 | break; |
| 2533 | } |
| 2534 | |
| 2535 | } else { |
| 2536 | if (IS_CHERRYVIEW(dev)) |
| 2537 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
| 2538 | else |
| 2539 | *DP &= ~DP_LINK_TRAIN_MASK; |
| 2540 | |
| 2541 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2542 | case DP_TRAINING_PATTERN_DISABLE: |
| 2543 | *DP |= DP_LINK_TRAIN_OFF; |
| 2544 | break; |
| 2545 | case DP_TRAINING_PATTERN_1: |
| 2546 | *DP |= DP_LINK_TRAIN_PAT_1; |
| 2547 | break; |
| 2548 | case DP_TRAINING_PATTERN_2: |
| 2549 | *DP |= DP_LINK_TRAIN_PAT_2; |
| 2550 | break; |
| 2551 | case DP_TRAINING_PATTERN_3: |
| 2552 | if (IS_CHERRYVIEW(dev)) { |
| 2553 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
| 2554 | } else { |
| 2555 | DRM_ERROR("DP training pattern 3 not supported\n"); |
| 2556 | *DP |= DP_LINK_TRAIN_PAT_2; |
| 2557 | } |
| 2558 | break; |
| 2559 | } |
| 2560 | } |
| 2561 | } |
| 2562 | |
| 2563 | static void intel_dp_enable_port(struct intel_dp *intel_dp) |
| 2564 | { |
| 2565 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 2566 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2567 | struct intel_crtc *crtc = |
| 2568 | to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc); |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2569 | |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2570 | /* enable with pattern 1 (as per spec) */ |
| 2571 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
| 2572 | DP_TRAINING_PATTERN_1); |
| 2573 | |
| 2574 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 2575 | POSTING_READ(intel_dp->output_reg); |
Ville Syrjälä | 7b713f5 | 2014-10-16 21:27:35 +0300 | [diff] [blame] | 2576 | |
| 2577 | /* |
| 2578 | * Magic for VLV/CHV. We _must_ first set up the register |
| 2579 | * without actually enabling the port, and then do another |
| 2580 | * write to enable the port. Otherwise link training will |
| 2581 | * fail when the power sequencer is freshly used for this port. |
| 2582 | */ |
| 2583 | intel_dp->DP |= DP_PORT_EN; |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2584 | if (crtc->config->has_audio) |
| 2585 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
Ville Syrjälä | 7b713f5 | 2014-10-16 21:27:35 +0300 | [diff] [blame] | 2586 | |
| 2587 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 2588 | POSTING_READ(intel_dp->output_reg); |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2589 | } |
| 2590 | |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 2591 | static void intel_enable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2592 | { |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 2593 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2594 | struct drm_device *dev = encoder->base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2595 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | c1dec79 | 2014-10-27 16:26:56 +0200 | [diff] [blame] | 2596 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2597 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
Ville Syrjälä | d6fbdd1 | 2015-10-29 21:25:58 +0200 | [diff] [blame] | 2598 | enum pipe pipe = crtc->pipe; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2599 | |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 2600 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
| 2601 | return; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2602 | |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2603 | pps_lock(intel_dp); |
| 2604 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2605 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2606 | vlv_init_panel_power_sequencer(intel_dp); |
| 2607 | |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2608 | intel_dp_enable_port(intel_dp); |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2609 | |
| 2610 | edp_panel_vdd_on(intel_dp); |
| 2611 | edp_panel_on(intel_dp); |
| 2612 | edp_panel_vdd_off(intel_dp, true); |
| 2613 | |
| 2614 | pps_unlock(intel_dp); |
| 2615 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2616 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2617 | unsigned int lane_mask = 0x0; |
| 2618 | |
| 2619 | if (IS_CHERRYVIEW(dev)) |
| 2620 | lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count); |
| 2621 | |
Ville Syrjälä | 9b6de0a | 2015-04-10 18:21:31 +0300 | [diff] [blame] | 2622 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
| 2623 | lane_mask); |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2624 | } |
Ville Syrjälä | 61234fa | 2014-10-16 21:27:34 +0300 | [diff] [blame] | 2625 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2626 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
| 2627 | intel_dp_start_link_train(intel_dp); |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2628 | intel_dp_stop_link_train(intel_dp); |
Jani Nikula | c1dec79 | 2014-10-27 16:26:56 +0200 | [diff] [blame] | 2629 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2630 | if (crtc->config->has_audio) { |
Jani Nikula | c1dec79 | 2014-10-27 16:26:56 +0200 | [diff] [blame] | 2631 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
Ville Syrjälä | d6fbdd1 | 2015-10-29 21:25:58 +0200 | [diff] [blame] | 2632 | pipe_name(pipe)); |
Jani Nikula | c1dec79 | 2014-10-27 16:26:56 +0200 | [diff] [blame] | 2633 | intel_audio_codec_enable(encoder); |
| 2634 | } |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2635 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2636 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 2637 | static void g4x_enable_dp(struct intel_encoder *encoder) |
| 2638 | { |
Jani Nikula | 828f5c6 | 2013-09-05 16:44:45 +0300 | [diff] [blame] | 2639 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2640 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 2641 | intel_enable_dp(encoder); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2642 | intel_edp_backlight_on(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2643 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2644 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2645 | static void vlv_enable_dp(struct intel_encoder *encoder) |
| 2646 | { |
Jani Nikula | 828f5c6 | 2013-09-05 16:44:45 +0300 | [diff] [blame] | 2647 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2648 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2649 | intel_edp_backlight_on(intel_dp); |
Rodrigo Vivi | b32c6f4 | 2014-11-20 03:44:37 -0800 | [diff] [blame] | 2650 | intel_psr_enable(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2651 | } |
| 2652 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 2653 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2654 | { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2655 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Ville Syrjälä | d6fbdd1 | 2015-10-29 21:25:58 +0200 | [diff] [blame] | 2656 | enum port port = dp_to_dig_port(intel_dp)->port; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2657 | |
Daniel Vetter | 8ac33ed | 2014-04-24 23:54:54 +0200 | [diff] [blame] | 2658 | intel_dp_prepare(encoder); |
| 2659 | |
Daniel Vetter | d41f1ef | 2014-04-24 23:54:53 +0200 | [diff] [blame] | 2660 | /* Only ilk+ has port A */ |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2661 | if (port == PORT_A) |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2662 | ironlake_edp_pll_on(intel_dp); |
| 2663 | } |
| 2664 | |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2665 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
| 2666 | { |
| 2667 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2668 | struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; |
| 2669 | enum pipe pipe = intel_dp->pps_pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2670 | i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2671 | |
| 2672 | edp_panel_vdd_off_sync(intel_dp); |
| 2673 | |
| 2674 | /* |
| 2675 | * VLV seems to get confused when multiple power seqeuencers |
| 2676 | * have the same port selected (even if only one has power/vdd |
| 2677 | * enabled). The failure manifests as vlv_wait_port_ready() failing |
| 2678 | * CHV on the other hand doesn't seem to mind having the same port |
| 2679 | * selected in multiple power seqeuencers, but let's clear the |
| 2680 | * port select always when logically disconnecting a power sequencer |
| 2681 | * from a port. |
| 2682 | */ |
| 2683 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", |
| 2684 | pipe_name(pipe), port_name(intel_dig_port->port)); |
| 2685 | I915_WRITE(pp_on_reg, 0); |
| 2686 | POSTING_READ(pp_on_reg); |
| 2687 | |
| 2688 | intel_dp->pps_pipe = INVALID_PIPE; |
| 2689 | } |
| 2690 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2691 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
| 2692 | enum pipe pipe) |
| 2693 | { |
| 2694 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2695 | struct intel_encoder *encoder; |
| 2696 | |
| 2697 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2698 | |
Ville Syrjälä | ac3c12e | 2014-10-16 21:29:56 +0300 | [diff] [blame] | 2699 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
| 2700 | return; |
| 2701 | |
Jani Nikula | 19c8054 | 2015-12-16 12:48:16 +0200 | [diff] [blame] | 2702 | for_each_intel_encoder(dev, encoder) { |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2703 | struct intel_dp *intel_dp; |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2704 | enum port port; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2705 | |
| 2706 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 2707 | continue; |
| 2708 | |
| 2709 | intel_dp = enc_to_intel_dp(&encoder->base); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2710 | port = dp_to_dig_port(intel_dp)->port; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2711 | |
| 2712 | if (intel_dp->pps_pipe != pipe) |
| 2713 | continue; |
| 2714 | |
| 2715 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2716 | pipe_name(pipe), port_name(port)); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2717 | |
Maarten Lankhorst | e02f9a0 | 2015-08-05 12:37:08 +0200 | [diff] [blame] | 2718 | WARN(encoder->base.crtc, |
Ville Syrjälä | 034e43c | 2014-10-16 21:27:28 +0300 | [diff] [blame] | 2719 | "stealing pipe %c power sequencer from active eDP port %c\n", |
| 2720 | pipe_name(pipe), port_name(port)); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2721 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2722 | /* make sure vdd is off before we steal it */ |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2723 | vlv_detach_power_sequencer(intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2724 | } |
| 2725 | } |
| 2726 | |
| 2727 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) |
| 2728 | { |
| 2729 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2730 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 2731 | struct drm_device *dev = encoder->base.dev; |
| 2732 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2733 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2734 | |
| 2735 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2736 | |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2737 | if (!is_edp(intel_dp)) |
| 2738 | return; |
| 2739 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2740 | if (intel_dp->pps_pipe == crtc->pipe) |
| 2741 | return; |
| 2742 | |
| 2743 | /* |
| 2744 | * If another power sequencer was being used on this |
| 2745 | * port previously make sure to turn off vdd there while |
| 2746 | * we still have control of it. |
| 2747 | */ |
| 2748 | if (intel_dp->pps_pipe != INVALID_PIPE) |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2749 | vlv_detach_power_sequencer(intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2750 | |
| 2751 | /* |
| 2752 | * We may be stealing the power |
| 2753 | * sequencer from another port. |
| 2754 | */ |
| 2755 | vlv_steal_power_sequencer(dev, crtc->pipe); |
| 2756 | |
| 2757 | /* now it's all ours */ |
| 2758 | intel_dp->pps_pipe = crtc->pipe; |
| 2759 | |
| 2760 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", |
| 2761 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); |
| 2762 | |
| 2763 | /* init power sequencer on this pipe and port */ |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 2764 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 2765 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2766 | } |
| 2767 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2768 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
| 2769 | { |
| 2770 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2771 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
Jesse Barnes | b263401 | 2013-03-28 09:55:40 -0700 | [diff] [blame] | 2772 | struct drm_device *dev = encoder->base.dev; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2773 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2774 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 2775 | enum dpio_channel port = vlv_dport_to_channel(dport); |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2776 | int pipe = intel_crtc->pipe; |
| 2777 | u32 val; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2778 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2779 | mutex_lock(&dev_priv->sb_lock); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2780 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2781 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2782 | val = 0; |
| 2783 | if (pipe) |
| 2784 | val |= (1<<21); |
| 2785 | else |
| 2786 | val &= ~(1<<21); |
| 2787 | val |= 0x001000c4; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2788 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
| 2789 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
| 2790 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2791 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2792 | mutex_unlock(&dev_priv->sb_lock); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2793 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2794 | intel_enable_dp(encoder); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2795 | } |
| 2796 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 2797 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2798 | { |
| 2799 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
| 2800 | struct drm_device *dev = encoder->base.dev; |
| 2801 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 2802 | struct intel_crtc *intel_crtc = |
| 2803 | to_intel_crtc(encoder->base.crtc); |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 2804 | enum dpio_channel port = vlv_dport_to_channel(dport); |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 2805 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2806 | |
Daniel Vetter | 8ac33ed | 2014-04-24 23:54:54 +0200 | [diff] [blame] | 2807 | intel_dp_prepare(encoder); |
| 2808 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2809 | /* Program Tx lane resets to default */ |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2810 | mutex_lock(&dev_priv->sb_lock); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2811 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2812 | DPIO_PCS_TX_LANE2_RESET | |
| 2813 | DPIO_PCS_TX_LANE1_RESET); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2814 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2815 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
| 2816 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
| 2817 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | |
| 2818 | DPIO_PCS_CLK_SOFT_RESET); |
| 2819 | |
| 2820 | /* Fix up inter-pair skew failure */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2821 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
| 2822 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
| 2823 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2824 | mutex_unlock(&dev_priv->sb_lock); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2825 | } |
| 2826 | |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2827 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
| 2828 | { |
| 2829 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2830 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 2831 | struct drm_device *dev = encoder->base.dev; |
| 2832 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2833 | struct intel_crtc *intel_crtc = |
| 2834 | to_intel_crtc(encoder->base.crtc); |
| 2835 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
| 2836 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | 2e523e9 | 2015-04-10 18:21:27 +0300 | [diff] [blame] | 2837 | int data, i, stagger; |
Ville Syrjälä | 949c1d4 | 2014-04-09 13:28:58 +0300 | [diff] [blame] | 2838 | u32 val; |
| 2839 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2840 | mutex_lock(&dev_priv->sb_lock); |
Ville Syrjälä | 949c1d4 | 2014-04-09 13:28:58 +0300 | [diff] [blame] | 2841 | |
Ville Syrjälä | 570e2a7 | 2014-08-18 14:42:46 +0300 | [diff] [blame] | 2842 | /* allow hardware to manage TX FIFO reset source */ |
| 2843 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
| 2844 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
| 2845 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
| 2846 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2847 | if (intel_crtc->config->lane_count > 2) { |
| 2848 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
| 2849 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
| 2850 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
| 2851 | } |
Ville Syrjälä | 570e2a7 | 2014-08-18 14:42:46 +0300 | [diff] [blame] | 2852 | |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2853 | /* Program Tx lane latency optimal setting*/ |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2854 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2855 | /* Set the upar bit */ |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2856 | if (intel_crtc->config->lane_count == 1) |
| 2857 | data = 0x0; |
| 2858 | else |
| 2859 | data = (i == 1) ? 0x0 : 0x1; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2860 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
| 2861 | data << DPIO_UPAR_SHIFT); |
| 2862 | } |
| 2863 | |
| 2864 | /* Data lane stagger programming */ |
Ville Syrjälä | 2e523e9 | 2015-04-10 18:21:27 +0300 | [diff] [blame] | 2865 | if (intel_crtc->config->port_clock > 270000) |
| 2866 | stagger = 0x18; |
| 2867 | else if (intel_crtc->config->port_clock > 135000) |
| 2868 | stagger = 0xd; |
| 2869 | else if (intel_crtc->config->port_clock > 67500) |
| 2870 | stagger = 0x7; |
| 2871 | else if (intel_crtc->config->port_clock > 33750) |
| 2872 | stagger = 0x4; |
| 2873 | else |
| 2874 | stagger = 0x2; |
| 2875 | |
| 2876 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
| 2877 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
| 2878 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
| 2879 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2880 | if (intel_crtc->config->lane_count > 2) { |
| 2881 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
| 2882 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
| 2883 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
| 2884 | } |
Ville Syrjälä | 2e523e9 | 2015-04-10 18:21:27 +0300 | [diff] [blame] | 2885 | |
| 2886 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), |
| 2887 | DPIO_LANESTAGGER_STRAP(stagger) | |
| 2888 | DPIO_LANESTAGGER_STRAP_OVRD | |
| 2889 | DPIO_TX1_STAGGER_MASK(0x1f) | |
| 2890 | DPIO_TX1_STAGGER_MULT(6) | |
| 2891 | DPIO_TX2_STAGGER_MULT(0)); |
| 2892 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2893 | if (intel_crtc->config->lane_count > 2) { |
| 2894 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), |
| 2895 | DPIO_LANESTAGGER_STRAP(stagger) | |
| 2896 | DPIO_LANESTAGGER_STRAP_OVRD | |
| 2897 | DPIO_TX1_STAGGER_MASK(0x1f) | |
| 2898 | DPIO_TX1_STAGGER_MULT(7) | |
| 2899 | DPIO_TX2_STAGGER_MULT(5)); |
| 2900 | } |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2901 | |
Ville Syrjälä | a8f327f | 2015-07-09 20:14:11 +0300 | [diff] [blame] | 2902 | /* Deassert data lane reset */ |
| 2903 | chv_data_lane_soft_reset(encoder, false); |
| 2904 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2905 | mutex_unlock(&dev_priv->sb_lock); |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2906 | |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2907 | intel_enable_dp(encoder); |
Ville Syrjälä | b0b3384 | 2015-07-08 23:45:55 +0300 | [diff] [blame] | 2908 | |
| 2909 | /* Second common lane will stay alive on its own now */ |
| 2910 | if (dport->release_cl2_override) { |
| 2911 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); |
| 2912 | dport->release_cl2_override = false; |
| 2913 | } |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2914 | } |
| 2915 | |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 2916 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
| 2917 | { |
| 2918 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
| 2919 | struct drm_device *dev = encoder->base.dev; |
| 2920 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2921 | struct intel_crtc *intel_crtc = |
| 2922 | to_intel_crtc(encoder->base.crtc); |
| 2923 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
| 2924 | enum pipe pipe = intel_crtc->pipe; |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2925 | unsigned int lane_mask = |
| 2926 | intel_dp_unused_lane_mask(intel_crtc->config->lane_count); |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 2927 | u32 val; |
| 2928 | |
Ville Syrjälä | 625695f | 2014-06-28 02:04:02 +0300 | [diff] [blame] | 2929 | intel_dp_prepare(encoder); |
| 2930 | |
Ville Syrjälä | b0b3384 | 2015-07-08 23:45:55 +0300 | [diff] [blame] | 2931 | /* |
| 2932 | * Must trick the second common lane into life. |
| 2933 | * Otherwise we can't even access the PLL. |
| 2934 | */ |
| 2935 | if (ch == DPIO_CH0 && pipe == PIPE_B) |
| 2936 | dport->release_cl2_override = |
| 2937 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); |
| 2938 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2939 | chv_phy_powergate_lanes(encoder, true, lane_mask); |
| 2940 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2941 | mutex_lock(&dev_priv->sb_lock); |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 2942 | |
Ville Syrjälä | a8f327f | 2015-07-09 20:14:11 +0300 | [diff] [blame] | 2943 | /* Assert data lane reset */ |
| 2944 | chv_data_lane_soft_reset(encoder, true); |
| 2945 | |
Ville Syrjälä | b9e5ac3 | 2014-05-27 16:30:18 +0300 | [diff] [blame] | 2946 | /* program left/right clock distribution */ |
| 2947 | if (pipe != PIPE_B) { |
| 2948 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
| 2949 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
| 2950 | if (ch == DPIO_CH0) |
| 2951 | val |= CHV_BUFLEFTENA1_FORCE; |
| 2952 | if (ch == DPIO_CH1) |
| 2953 | val |= CHV_BUFRIGHTENA1_FORCE; |
| 2954 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
| 2955 | } else { |
| 2956 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
| 2957 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
| 2958 | if (ch == DPIO_CH0) |
| 2959 | val |= CHV_BUFLEFTENA2_FORCE; |
| 2960 | if (ch == DPIO_CH1) |
| 2961 | val |= CHV_BUFRIGHTENA2_FORCE; |
| 2962 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
| 2963 | } |
| 2964 | |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 2965 | /* program clock channel usage */ |
| 2966 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); |
| 2967 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
| 2968 | if (pipe != PIPE_B) |
| 2969 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
| 2970 | else |
| 2971 | val |= CHV_PCS_USEDCLKCHANNEL; |
| 2972 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); |
| 2973 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2974 | if (intel_crtc->config->lane_count > 2) { |
| 2975 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
| 2976 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
| 2977 | if (pipe != PIPE_B) |
| 2978 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
| 2979 | else |
| 2980 | val |= CHV_PCS_USEDCLKCHANNEL; |
| 2981 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); |
| 2982 | } |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 2983 | |
| 2984 | /* |
| 2985 | * This a a bit weird since generally CL |
| 2986 | * matches the pipe, but here we need to |
| 2987 | * pick the CL based on the port. |
| 2988 | */ |
| 2989 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); |
| 2990 | if (pipe != PIPE_B) |
| 2991 | val &= ~CHV_CMN_USEDCLKCHANNEL; |
| 2992 | else |
| 2993 | val |= CHV_CMN_USEDCLKCHANNEL; |
| 2994 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); |
| 2995 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2996 | mutex_unlock(&dev_priv->sb_lock); |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 2997 | } |
| 2998 | |
Ville Syrjälä | d6db995 | 2015-07-08 23:45:49 +0300 | [diff] [blame] | 2999 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder) |
| 3000 | { |
| 3001 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 3002 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
| 3003 | u32 val; |
| 3004 | |
| 3005 | mutex_lock(&dev_priv->sb_lock); |
| 3006 | |
| 3007 | /* disable left/right clock distribution */ |
| 3008 | if (pipe != PIPE_B) { |
| 3009 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
| 3010 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
| 3011 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
| 3012 | } else { |
| 3013 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
| 3014 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
| 3015 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
| 3016 | } |
| 3017 | |
| 3018 | mutex_unlock(&dev_priv->sb_lock); |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3019 | |
Ville Syrjälä | b0b3384 | 2015-07-08 23:45:55 +0300 | [diff] [blame] | 3020 | /* |
| 3021 | * Leave the power down bit cleared for at least one |
| 3022 | * lane so that chv_powergate_phy_ch() will power |
| 3023 | * on something when the channel is otherwise unused. |
| 3024 | * When the port is off and the override is removed |
| 3025 | * the lanes power down anyway, so otherwise it doesn't |
| 3026 | * really matter what the state of power down bits is |
| 3027 | * after this. |
| 3028 | */ |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3029 | chv_phy_powergate_lanes(encoder, false, 0x0); |
Ville Syrjälä | d6db995 | 2015-07-08 23:45:49 +0300 | [diff] [blame] | 3030 | } |
| 3031 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3032 | /* |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 3033 | * Native read with retry for link status and receiver capability reads for |
| 3034 | * cases where the sink may still be asleep. |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3035 | * |
| 3036 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also |
| 3037 | * supposed to retry 3 times per the spec. |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 3038 | */ |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3039 | static ssize_t |
| 3040 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, |
| 3041 | void *buffer, size_t size) |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 3042 | { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3043 | ssize_t ret; |
| 3044 | int i; |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 3045 | |
Ville Syrjälä | f6a1906 | 2014-10-16 20:46:09 +0300 | [diff] [blame] | 3046 | /* |
| 3047 | * Sometime we just get the same incorrect byte repeated |
| 3048 | * over the entire buffer. Doing just one throw away read |
| 3049 | * initially seems to "solve" it. |
| 3050 | */ |
| 3051 | drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1); |
| 3052 | |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 3053 | for (i = 0; i < 3; i++) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3054 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
| 3055 | if (ret == size) |
| 3056 | return ret; |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 3057 | msleep(1); |
| 3058 | } |
| 3059 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3060 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3061 | } |
| 3062 | |
| 3063 | /* |
| 3064 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
| 3065 | * link status information |
| 3066 | */ |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3067 | bool |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 3068 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3069 | { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3070 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 3071 | DP_LANE0_1_STATUS, |
| 3072 | link_status, |
| 3073 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3074 | } |
| 3075 | |
Paulo Zanoni | 1100244 | 2014-06-13 18:45:41 -0300 | [diff] [blame] | 3076 | /* These are source-specific values. */ |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3077 | uint8_t |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3078 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3079 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 3080 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Sonika Jindal | 7ad14a2 | 2015-02-25 10:29:12 +0530 | [diff] [blame] | 3081 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3082 | enum port port = dp_to_dig_port(intel_dp)->port; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3083 | |
Vandana Kannan | 9314726 | 2014-11-18 15:45:29 +0530 | [diff] [blame] | 3084 | if (IS_BROXTON(dev)) |
| 3085 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
| 3086 | else if (INTEL_INFO(dev)->gen >= 9) { |
Jani Nikula | 06411f0 | 2016-03-24 17:50:21 +0200 | [diff] [blame] | 3087 | if (dev_priv->vbt.edp.low_vswing && port == PORT_A) |
Sonika Jindal | 7ad14a2 | 2015-02-25 10:29:12 +0530 | [diff] [blame] | 3088 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
Damien Lespiau | 5a9d1f1 | 2013-12-03 13:56:26 +0000 | [diff] [blame] | 3089 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 3090 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3091 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3092 | else if (IS_GEN7(dev) && port == PORT_A) |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3093 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3094 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3095 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3096 | else |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3097 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3098 | } |
| 3099 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3100 | uint8_t |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3101 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
| 3102 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 3103 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3104 | enum port port = dp_to_dig_port(intel_dp)->port; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3105 | |
Damien Lespiau | 5a9d1f1 | 2013-12-03 13:56:26 +0000 | [diff] [blame] | 3106 | if (INTEL_INFO(dev)->gen >= 9) { |
| 3107 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3108 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3109 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 3110 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3111 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3112 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3113 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
Sonika Jindal | 7ad14a2 | 2015-02-25 10:29:12 +0530 | [diff] [blame] | 3114 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 3115 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Damien Lespiau | 5a9d1f1 | 2013-12-03 13:56:26 +0000 | [diff] [blame] | 3116 | default: |
| 3117 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
| 3118 | } |
| 3119 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 3120 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3121 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3122 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 3123 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3124 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3125 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3126 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 3127 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 3128 | default: |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3129 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 3130 | } |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 3131 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3132 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3133 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3134 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 3135 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3136 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3137 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3138 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 3139 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3140 | default: |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3141 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3142 | } |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3143 | } else if (IS_GEN7(dev) && port == PORT_A) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3144 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3145 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3146 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3147 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3148 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3149 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3150 | default: |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3151 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3152 | } |
| 3153 | } else { |
| 3154 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3155 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3156 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3157 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3158 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3159 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3160 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 3161 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3162 | default: |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3163 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3164 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3165 | } |
| 3166 | } |
| 3167 | |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3168 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3169 | { |
| 3170 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 3171 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3172 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 3173 | struct intel_crtc *intel_crtc = |
| 3174 | to_intel_crtc(dport->base.base.crtc); |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3175 | unsigned long demph_reg_value, preemph_reg_value, |
| 3176 | uniqtranscale_reg_value; |
| 3177 | uint8_t train_set = intel_dp->train_set[0]; |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 3178 | enum dpio_channel port = vlv_dport_to_channel(dport); |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 3179 | int pipe = intel_crtc->pipe; |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3180 | |
| 3181 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3182 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3183 | preemph_reg_value = 0x0004000; |
| 3184 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3185 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3186 | demph_reg_value = 0x2B405555; |
| 3187 | uniqtranscale_reg_value = 0x552AB83A; |
| 3188 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3189 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3190 | demph_reg_value = 0x2B404040; |
| 3191 | uniqtranscale_reg_value = 0x5548B83A; |
| 3192 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3193 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3194 | demph_reg_value = 0x2B245555; |
| 3195 | uniqtranscale_reg_value = 0x5560B83A; |
| 3196 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3197 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3198 | demph_reg_value = 0x2B405555; |
| 3199 | uniqtranscale_reg_value = 0x5598DA3A; |
| 3200 | break; |
| 3201 | default: |
| 3202 | return 0; |
| 3203 | } |
| 3204 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3205 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3206 | preemph_reg_value = 0x0002000; |
| 3207 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3208 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3209 | demph_reg_value = 0x2B404040; |
| 3210 | uniqtranscale_reg_value = 0x5552B83A; |
| 3211 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3212 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3213 | demph_reg_value = 0x2B404848; |
| 3214 | uniqtranscale_reg_value = 0x5580B83A; |
| 3215 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3216 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3217 | demph_reg_value = 0x2B404040; |
| 3218 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3219 | break; |
| 3220 | default: |
| 3221 | return 0; |
| 3222 | } |
| 3223 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3224 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3225 | preemph_reg_value = 0x0000000; |
| 3226 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3227 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3228 | demph_reg_value = 0x2B305555; |
| 3229 | uniqtranscale_reg_value = 0x5570B83A; |
| 3230 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3231 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3232 | demph_reg_value = 0x2B2B4040; |
| 3233 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3234 | break; |
| 3235 | default: |
| 3236 | return 0; |
| 3237 | } |
| 3238 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3239 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3240 | preemph_reg_value = 0x0006000; |
| 3241 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3242 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3243 | demph_reg_value = 0x1B405555; |
| 3244 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3245 | break; |
| 3246 | default: |
| 3247 | return 0; |
| 3248 | } |
| 3249 | break; |
| 3250 | default: |
| 3251 | return 0; |
| 3252 | } |
| 3253 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 3254 | mutex_lock(&dev_priv->sb_lock); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 3255 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
| 3256 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); |
| 3257 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3258 | uniqtranscale_reg_value); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 3259 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
| 3260 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
| 3261 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); |
| 3262 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 3263 | mutex_unlock(&dev_priv->sb_lock); |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3264 | |
| 3265 | return 0; |
| 3266 | } |
| 3267 | |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3268 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3269 | { |
Ander Conselvan de Oliveira | b7fa22d | 2016-04-27 15:44:17 +0300 | [diff] [blame] | 3270 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
| 3271 | u32 deemph_reg_value, margin_reg_value; |
| 3272 | bool uniq_trans_scale = false; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3273 | uint8_t train_set = intel_dp->train_set[0]; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3274 | |
| 3275 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3276 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3277 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3278 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3279 | deemph_reg_value = 128; |
| 3280 | margin_reg_value = 52; |
| 3281 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3282 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3283 | deemph_reg_value = 128; |
| 3284 | margin_reg_value = 77; |
| 3285 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3286 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3287 | deemph_reg_value = 128; |
| 3288 | margin_reg_value = 102; |
| 3289 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3290 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3291 | deemph_reg_value = 128; |
| 3292 | margin_reg_value = 154; |
Ander Conselvan de Oliveira | b7fa22d | 2016-04-27 15:44:17 +0300 | [diff] [blame] | 3293 | uniq_trans_scale = true; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3294 | break; |
| 3295 | default: |
| 3296 | return 0; |
| 3297 | } |
| 3298 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3299 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3300 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3301 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3302 | deemph_reg_value = 85; |
| 3303 | margin_reg_value = 78; |
| 3304 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3305 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3306 | deemph_reg_value = 85; |
| 3307 | margin_reg_value = 116; |
| 3308 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3309 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3310 | deemph_reg_value = 85; |
| 3311 | margin_reg_value = 154; |
| 3312 | break; |
| 3313 | default: |
| 3314 | return 0; |
| 3315 | } |
| 3316 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3317 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3318 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3319 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3320 | deemph_reg_value = 64; |
| 3321 | margin_reg_value = 104; |
| 3322 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3323 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3324 | deemph_reg_value = 64; |
| 3325 | margin_reg_value = 154; |
| 3326 | break; |
| 3327 | default: |
| 3328 | return 0; |
| 3329 | } |
| 3330 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3331 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3332 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3333 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3334 | deemph_reg_value = 43; |
| 3335 | margin_reg_value = 154; |
| 3336 | break; |
| 3337 | default: |
| 3338 | return 0; |
| 3339 | } |
| 3340 | break; |
| 3341 | default: |
| 3342 | return 0; |
| 3343 | } |
| 3344 | |
Ander Conselvan de Oliveira | b7fa22d | 2016-04-27 15:44:17 +0300 | [diff] [blame] | 3345 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
| 3346 | margin_reg_value, uniq_trans_scale); |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3347 | |
| 3348 | return 0; |
| 3349 | } |
| 3350 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3351 | static uint32_t |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3352 | gen4_signal_levels(uint8_t train_set) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3353 | { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 3354 | uint32_t signal_levels = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3355 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 3356 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3357 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3358 | default: |
| 3359 | signal_levels |= DP_VOLTAGE_0_4; |
| 3360 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3361 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3362 | signal_levels |= DP_VOLTAGE_0_6; |
| 3363 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3364 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3365 | signal_levels |= DP_VOLTAGE_0_8; |
| 3366 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3367 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3368 | signal_levels |= DP_VOLTAGE_1_2; |
| 3369 | break; |
| 3370 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 3371 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3372 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3373 | default: |
| 3374 | signal_levels |= DP_PRE_EMPHASIS_0; |
| 3375 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3376 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3377 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
| 3378 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3379 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3380 | signal_levels |= DP_PRE_EMPHASIS_6; |
| 3381 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3382 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3383 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
| 3384 | break; |
| 3385 | } |
| 3386 | return signal_levels; |
| 3387 | } |
| 3388 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3389 | /* Gen6's DP voltage swing and pre-emphasis control */ |
| 3390 | static uint32_t |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3391 | gen6_edp_signal_levels(uint8_t train_set) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3392 | { |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3393 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 3394 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 3395 | switch (signal_levels) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3396 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3397 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3398 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3399 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3400 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3401 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3402 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3403 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3404 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3405 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3406 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3407 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3408 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3409 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3410 | default: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3411 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 3412 | "0x%x\n", signal_levels); |
| 3413 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3414 | } |
| 3415 | } |
| 3416 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3417 | /* Gen7's DP voltage swing and pre-emphasis control */ |
| 3418 | static uint32_t |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3419 | gen7_edp_signal_levels(uint8_t train_set) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3420 | { |
| 3421 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 3422 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 3423 | switch (signal_levels) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3424 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3425 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3426 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3427 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3428 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3429 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
| 3430 | |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3431 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3432 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3433 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3434 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
| 3435 | |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3436 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3437 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3438 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3439 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
| 3440 | |
| 3441 | default: |
| 3442 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 3443 | "0x%x\n", signal_levels); |
| 3444 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
| 3445 | } |
| 3446 | } |
| 3447 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3448 | void |
Ander Conselvan de Oliveira | f4eb692 | 2015-10-23 13:01:44 +0300 | [diff] [blame] | 3449 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3450 | { |
| 3451 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3452 | enum port port = intel_dig_port->port; |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3453 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Ander Conselvan de Oliveira | b905a91 | 2015-10-23 13:01:47 +0300 | [diff] [blame] | 3454 | struct drm_i915_private *dev_priv = to_i915(dev); |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 3455 | uint32_t signal_levels, mask = 0; |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3456 | uint8_t train_set = intel_dp->train_set[0]; |
| 3457 | |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 3458 | if (HAS_DDI(dev)) { |
| 3459 | signal_levels = ddi_signal_levels(intel_dp); |
| 3460 | |
| 3461 | if (IS_BROXTON(dev)) |
| 3462 | signal_levels = 0; |
| 3463 | else |
| 3464 | mask = DDI_BUF_EMP_MASK; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3465 | } else if (IS_CHERRYVIEW(dev)) { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3466 | signal_levels = chv_signal_levels(intel_dp); |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3467 | } else if (IS_VALLEYVIEW(dev)) { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3468 | signal_levels = vlv_signal_levels(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3469 | } else if (IS_GEN7(dev) && port == PORT_A) { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3470 | signal_levels = gen7_edp_signal_levels(train_set); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3471 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3472 | } else if (IS_GEN6(dev) && port == PORT_A) { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3473 | signal_levels = gen6_edp_signal_levels(train_set); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3474 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
| 3475 | } else { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3476 | signal_levels = gen4_signal_levels(train_set); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3477 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
| 3478 | } |
| 3479 | |
Vandana Kannan | 96fb9f9 | 2014-11-18 15:45:27 +0530 | [diff] [blame] | 3480 | if (mask) |
| 3481 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
| 3482 | |
| 3483 | DRM_DEBUG_KMS("Using vswing level %d\n", |
| 3484 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); |
| 3485 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", |
| 3486 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
| 3487 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3488 | |
Ander Conselvan de Oliveira | f4eb692 | 2015-10-23 13:01:44 +0300 | [diff] [blame] | 3489 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
Ander Conselvan de Oliveira | b905a91 | 2015-10-23 13:01:47 +0300 | [diff] [blame] | 3490 | |
| 3491 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 3492 | POSTING_READ(intel_dp->output_reg); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3493 | } |
| 3494 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3495 | void |
Ander Conselvan de Oliveira | e9c176d | 2015-10-23 13:01:45 +0300 | [diff] [blame] | 3496 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
| 3497 | uint8_t dp_train_pat) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3498 | { |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 3499 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 3500 | struct drm_i915_private *dev_priv = |
| 3501 | to_i915(intel_dig_port->base.base.dev); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3502 | |
Ander Conselvan de Oliveira | f4eb692 | 2015-10-23 13:01:44 +0300 | [diff] [blame] | 3503 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 3504 | |
Ander Conselvan de Oliveira | f4eb692 | 2015-10-23 13:01:44 +0300 | [diff] [blame] | 3505 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3506 | POSTING_READ(intel_dp->output_reg); |
Ander Conselvan de Oliveira | e9c176d | 2015-10-23 13:01:45 +0300 | [diff] [blame] | 3507 | } |
| 3508 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3509 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 3510 | { |
| 3511 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3512 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 3513 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3514 | enum port port = intel_dig_port->port; |
| 3515 | uint32_t val; |
| 3516 | |
| 3517 | if (!HAS_DDI(dev)) |
| 3518 | return; |
| 3519 | |
| 3520 | val = I915_READ(DP_TP_CTL(port)); |
| 3521 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 3522 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
| 3523 | I915_WRITE(DP_TP_CTL(port), val); |
| 3524 | |
| 3525 | /* |
| 3526 | * On PORT_A we can have only eDP in SST mode. There the only reason |
| 3527 | * we need to set idle transmission mode is to work around a HW issue |
| 3528 | * where we enable the pipe while not in idle link-training mode. |
| 3529 | * In this case there is requirement to wait for a minimum number of |
| 3530 | * idle patterns to be sent. |
| 3531 | */ |
| 3532 | if (port == PORT_A) |
| 3533 | return; |
| 3534 | |
| 3535 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), |
| 3536 | 1)) |
| 3537 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
| 3538 | } |
| 3539 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3540 | static void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3541 | intel_dp_link_down(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3542 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3543 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3544 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3545 | enum port port = intel_dig_port->port; |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3546 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3547 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3548 | uint32_t DP = intel_dp->DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3549 | |
Daniel Vetter | bc76e320 | 2014-05-20 22:46:50 +0200 | [diff] [blame] | 3550 | if (WARN_ON(HAS_DDI(dev))) |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 3551 | return; |
| 3552 | |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 3553 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
Chris Wilson | 1b39d6f | 2010-12-06 11:20:45 +0000 | [diff] [blame] | 3554 | return; |
| 3555 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3556 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3557 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 3558 | if ((IS_GEN7(dev) && port == PORT_A) || |
| 3559 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3560 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3561 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3562 | } else { |
Ville Syrjälä | aad3d14 | 2014-06-28 02:04:25 +0300 | [diff] [blame] | 3563 | if (IS_CHERRYVIEW(dev)) |
| 3564 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
| 3565 | else |
| 3566 | DP &= ~DP_LINK_TRAIN_MASK; |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3567 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3568 | } |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3569 | I915_WRITE(intel_dp->output_reg, DP); |
Chris Wilson | fe255d0 | 2010-09-11 21:37:48 +0100 | [diff] [blame] | 3570 | POSTING_READ(intel_dp->output_reg); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3571 | |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3572 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
| 3573 | I915_WRITE(intel_dp->output_reg, DP); |
| 3574 | POSTING_READ(intel_dp->output_reg); |
| 3575 | |
| 3576 | /* |
| 3577 | * HW workaround for IBX, we need to move the port |
| 3578 | * to transcoder A after disabling it to allow the |
| 3579 | * matching HDMI port to be enabled on transcoder A. |
| 3580 | */ |
| 3581 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { |
Ville Syrjälä | 0c241d5 | 2015-10-30 19:23:22 +0200 | [diff] [blame] | 3582 | /* |
| 3583 | * We get CPU/PCH FIFO underruns on the other pipe when |
| 3584 | * doing the workaround. Sweep them under the rug. |
| 3585 | */ |
| 3586 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
| 3587 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
| 3588 | |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3589 | /* always enable with pattern 1 (as per spec) */ |
| 3590 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); |
| 3591 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; |
| 3592 | I915_WRITE(intel_dp->output_reg, DP); |
| 3593 | POSTING_READ(intel_dp->output_reg); |
| 3594 | |
| 3595 | DP &= ~DP_PORT_EN; |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 3596 | I915_WRITE(intel_dp->output_reg, DP); |
Daniel Vetter | 0ca0968 | 2014-11-24 16:54:11 +0100 | [diff] [blame] | 3597 | POSTING_READ(intel_dp->output_reg); |
Ville Syrjälä | 0c241d5 | 2015-10-30 19:23:22 +0200 | [diff] [blame] | 3598 | |
| 3599 | intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A); |
| 3600 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
| 3601 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 3602 | } |
| 3603 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 3604 | msleep(intel_dp->panel_power_down_delay); |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 3605 | |
| 3606 | intel_dp->DP = DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3607 | } |
| 3608 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3609 | static bool |
| 3610 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3611 | { |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 3612 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 3613 | struct drm_device *dev = dig_port->base.base.dev; |
| 3614 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3615 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3616 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
| 3617 | sizeof(intel_dp->dpcd)) < 0) |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3618 | return false; /* aux transfer failed */ |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3619 | |
Andy Shevchenko | a8e9815 | 2014-09-01 14:12:01 +0300 | [diff] [blame] | 3620 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
Damien Lespiau | 577c7a5 | 2012-12-13 16:09:02 +0000 | [diff] [blame] | 3621 | |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3622 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
| 3623 | return false; /* DPCD not present */ |
| 3624 | |
Shubhangi Shrivastava | 30d9aa4 | 2016-03-30 18:05:25 +0530 | [diff] [blame] | 3625 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, |
| 3626 | &intel_dp->sink_count, 1) < 0) |
| 3627 | return false; |
| 3628 | |
| 3629 | /* |
| 3630 | * Sink count can change between short pulse hpd hence |
| 3631 | * a member variable in intel_dp will track any changes |
| 3632 | * between short pulse interrupts. |
| 3633 | */ |
| 3634 | intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count); |
| 3635 | |
| 3636 | /* |
| 3637 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that |
| 3638 | * a dongle is present but no display. Unless we require to know |
| 3639 | * if a dongle is present or not, we don't need to update |
| 3640 | * downstream port information. So, an early return here saves |
| 3641 | * time from performing other operations which are not required. |
| 3642 | */ |
Shubhangi Shrivastava | 1034ce7 | 2016-04-12 12:23:54 +0530 | [diff] [blame] | 3643 | if (!is_edp(intel_dp) && !intel_dp->sink_count) |
Shubhangi Shrivastava | 30d9aa4 | 2016-03-30 18:05:25 +0530 | [diff] [blame] | 3644 | return false; |
| 3645 | |
Shobhit Kumar | 2293bb5 | 2013-07-11 18:44:56 -0300 | [diff] [blame] | 3646 | /* Check if the panel supports PSR */ |
| 3647 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
Jani Nikula | 5000393 | 2013-09-20 16:42:17 +0300 | [diff] [blame] | 3648 | if (is_edp(intel_dp)) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3649 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
| 3650 | intel_dp->psr_dpcd, |
| 3651 | sizeof(intel_dp->psr_dpcd)); |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 3652 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
| 3653 | dev_priv->psr.sink_support = true; |
Jani Nikula | 5000393 | 2013-09-20 16:42:17 +0300 | [diff] [blame] | 3654 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 3655 | } |
Sonika Jindal | 474d1ec | 2015-04-02 11:02:44 +0530 | [diff] [blame] | 3656 | |
| 3657 | if (INTEL_INFO(dev)->gen >= 9 && |
| 3658 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { |
| 3659 | uint8_t frame_sync_cap; |
| 3660 | |
| 3661 | dev_priv->psr.sink_support = true; |
| 3662 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 3663 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, |
| 3664 | &frame_sync_cap, 1); |
| 3665 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; |
| 3666 | /* PSR2 needs frame sync as well */ |
| 3667 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; |
| 3668 | DRM_DEBUG_KMS("PSR2 %s on sink", |
| 3669 | dev_priv->psr.psr2_support ? "supported" : "not supported"); |
| 3670 | } |
Yetunde Adebisi | 86ee27b | 2016-04-05 15:10:51 +0100 | [diff] [blame] | 3671 | |
| 3672 | /* Read the eDP Display control capabilities registers */ |
| 3673 | memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd)); |
| 3674 | if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && |
| 3675 | (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, |
| 3676 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == |
| 3677 | sizeof(intel_dp->edp_dpcd))) |
| 3678 | DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), |
| 3679 | intel_dp->edp_dpcd); |
Jani Nikula | 5000393 | 2013-09-20 16:42:17 +0300 | [diff] [blame] | 3680 | } |
| 3681 | |
Jani Nikula | bc5133d | 2015-09-03 11:16:07 +0300 | [diff] [blame] | 3682 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 3683 | yesno(intel_dp_source_supports_hbr2(intel_dp)), |
Jani Nikula | 742f491 | 2015-09-03 11:16:09 +0300 | [diff] [blame] | 3684 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 3685 | |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 3686 | /* Intermediate frequency support */ |
Yetunde Adebisi | 86ee27b | 2016-04-05 15:10:51 +0100 | [diff] [blame] | 3687 | if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */ |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 3688 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
Ville Syrjälä | ea2d8a4 | 2015-03-12 17:10:28 +0200 | [diff] [blame] | 3689 | int i; |
| 3690 | |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 3691 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 3692 | DP_SUPPORTED_LINK_RATES, |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 3693 | sink_rates, |
| 3694 | sizeof(sink_rates)); |
Ville Syrjälä | ea2d8a4 | 2015-03-12 17:10:28 +0200 | [diff] [blame] | 3695 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 3696 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
| 3697 | int val = le16_to_cpu(sink_rates[i]); |
Ville Syrjälä | ea2d8a4 | 2015-03-12 17:10:28 +0200 | [diff] [blame] | 3698 | |
| 3699 | if (val == 0) |
| 3700 | break; |
| 3701 | |
Sonika Jindal | af77b97 | 2015-05-07 13:59:28 +0530 | [diff] [blame] | 3702 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
| 3703 | intel_dp->sink_rates[i] = (val * 200) / 10; |
Ville Syrjälä | ea2d8a4 | 2015-03-12 17:10:28 +0200 | [diff] [blame] | 3704 | } |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 3705 | intel_dp->num_sink_rates = i; |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 3706 | } |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 3707 | |
| 3708 | intel_dp_print_rates(intel_dp); |
| 3709 | |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3710 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 3711 | DP_DWN_STRM_PORT_PRESENT)) |
| 3712 | return true; /* native DP sink */ |
| 3713 | |
| 3714 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
| 3715 | return true; /* no per-port downstream info */ |
| 3716 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3717 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
| 3718 | intel_dp->downstream_ports, |
| 3719 | DP_MAX_DOWNSTREAM_PORTS) < 0) |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3720 | return false; /* downstream port status fetch failed */ |
| 3721 | |
| 3722 | return true; |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3723 | } |
| 3724 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3725 | static void |
| 3726 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
| 3727 | { |
| 3728 | u8 buf[3]; |
| 3729 | |
| 3730 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
| 3731 | return; |
| 3732 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3733 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3734 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
| 3735 | buf[0], buf[1], buf[2]); |
| 3736 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3737 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3738 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
| 3739 | buf[0], buf[1], buf[2]); |
| 3740 | } |
| 3741 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3742 | static bool |
| 3743 | intel_dp_probe_mst(struct intel_dp *intel_dp) |
| 3744 | { |
| 3745 | u8 buf[1]; |
| 3746 | |
Nathan Schulte | 7cc9613 | 2016-03-15 10:14:05 -0500 | [diff] [blame] | 3747 | if (!i915.enable_dp_mst) |
| 3748 | return false; |
| 3749 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3750 | if (!intel_dp->can_mst) |
| 3751 | return false; |
| 3752 | |
| 3753 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
| 3754 | return false; |
| 3755 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3756 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
| 3757 | if (buf[0] & DP_MST_CAP) { |
| 3758 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
| 3759 | intel_dp->is_mst = true; |
| 3760 | } else { |
| 3761 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
| 3762 | intel_dp->is_mst = false; |
| 3763 | } |
| 3764 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3765 | |
| 3766 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
| 3767 | return intel_dp->is_mst; |
| 3768 | } |
| 3769 | |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3770 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3771 | { |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3772 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
Rodrigo Vivi | d72f9d9 | 2015-11-05 10:50:19 -0800 | [diff] [blame] | 3773 | struct drm_device *dev = dig_port->base.base.dev; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3774 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 3775 | u8 buf; |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3776 | int ret = 0; |
Rodrigo Vivi | c629784 | 2015-11-05 10:50:20 -0800 | [diff] [blame] | 3777 | int count = 0; |
| 3778 | int attempts = 10; |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3779 | |
| 3780 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3781 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3782 | ret = -EIO; |
| 3783 | goto out; |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3784 | } |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3785 | |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3786 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3787 | buf & ~DP_TEST_SINK_START) < 0) { |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3788 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3789 | ret = -EIO; |
| 3790 | goto out; |
| 3791 | } |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3792 | |
Rodrigo Vivi | c629784 | 2015-11-05 10:50:20 -0800 | [diff] [blame] | 3793 | do { |
| 3794 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 3795 | |
| 3796 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
| 3797 | DP_TEST_SINK_MISC, &buf) < 0) { |
| 3798 | ret = -EIO; |
| 3799 | goto out; |
| 3800 | } |
| 3801 | count = buf & DP_TEST_COUNT_MASK; |
| 3802 | } while (--attempts && count); |
| 3803 | |
| 3804 | if (attempts == 0) { |
Rodrigo Vivi | dc5a903 | 2016-01-29 14:44:59 -0800 | [diff] [blame] | 3805 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
Rodrigo Vivi | c629784 | 2015-11-05 10:50:20 -0800 | [diff] [blame] | 3806 | ret = -ETIMEDOUT; |
| 3807 | } |
| 3808 | |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3809 | out: |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3810 | hsw_enable_ips(intel_crtc); |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3811 | return ret; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3812 | } |
| 3813 | |
| 3814 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) |
| 3815 | { |
| 3816 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
Rodrigo Vivi | d72f9d9 | 2015-11-05 10:50:19 -0800 | [diff] [blame] | 3817 | struct drm_device *dev = dig_port->base.base.dev; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3818 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 3819 | u8 buf; |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3820 | int ret; |
| 3821 | |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3822 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
| 3823 | return -EIO; |
| 3824 | |
| 3825 | if (!(buf & DP_TEST_CRC_SUPPORTED)) |
| 3826 | return -ENOTTY; |
| 3827 | |
| 3828 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
| 3829 | return -EIO; |
| 3830 | |
Rodrigo Vivi | 6d8175d | 2015-11-05 10:50:22 -0800 | [diff] [blame] | 3831 | if (buf & DP_TEST_SINK_START) { |
| 3832 | ret = intel_dp_sink_crc_stop(intel_dp); |
| 3833 | if (ret) |
| 3834 | return ret; |
| 3835 | } |
| 3836 | |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3837 | hsw_disable_ips(intel_crtc); |
| 3838 | |
| 3839 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
| 3840 | buf | DP_TEST_SINK_START) < 0) { |
| 3841 | hsw_enable_ips(intel_crtc); |
| 3842 | return -EIO; |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3843 | } |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3844 | |
Rodrigo Vivi | d72f9d9 | 2015-11-05 10:50:19 -0800 | [diff] [blame] | 3845 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3846 | return 0; |
| 3847 | } |
| 3848 | |
| 3849 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
| 3850 | { |
| 3851 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 3852 | struct drm_device *dev = dig_port->base.base.dev; |
| 3853 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 3854 | u8 buf; |
Rodrigo Vivi | 621d4c7 | 2015-07-23 16:35:49 -0700 | [diff] [blame] | 3855 | int count, ret; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3856 | int attempts = 6; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3857 | |
| 3858 | ret = intel_dp_sink_crc_start(intel_dp); |
| 3859 | if (ret) |
| 3860 | return ret; |
| 3861 | |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 3862 | do { |
Rodrigo Vivi | 621d4c7 | 2015-07-23 16:35:49 -0700 | [diff] [blame] | 3863 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 3864 | |
Rodrigo Vivi | 1dda5f9 | 2014-10-01 07:32:37 -0700 | [diff] [blame] | 3865 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3866 | DP_TEST_SINK_MISC, &buf) < 0) { |
| 3867 | ret = -EIO; |
Rodrigo Vivi | afe0d67 | 2015-07-23 16:35:45 -0700 | [diff] [blame] | 3868 | goto stop; |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3869 | } |
Rodrigo Vivi | 621d4c7 | 2015-07-23 16:35:49 -0700 | [diff] [blame] | 3870 | count = buf & DP_TEST_COUNT_MASK; |
Rodrigo Vivi | aabc95d | 2015-07-23 16:35:50 -0700 | [diff] [blame] | 3871 | |
Rodrigo Vivi | 7e38eef | 2015-11-05 10:50:21 -0800 | [diff] [blame] | 3872 | } while (--attempts && count == 0); |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 3873 | |
| 3874 | if (attempts == 0) { |
Rodrigo Vivi | 7e38eef | 2015-11-05 10:50:21 -0800 | [diff] [blame] | 3875 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
| 3876 | ret = -ETIMEDOUT; |
| 3877 | goto stop; |
| 3878 | } |
| 3879 | |
| 3880 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { |
| 3881 | ret = -EIO; |
| 3882 | goto stop; |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 3883 | } |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3884 | |
Rodrigo Vivi | afe0d67 | 2015-07-23 16:35:45 -0700 | [diff] [blame] | 3885 | stop: |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3886 | intel_dp_sink_crc_stop(intel_dp); |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3887 | return ret; |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3888 | } |
| 3889 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3890 | static bool |
| 3891 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 3892 | { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3893 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 3894 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 3895 | sink_irq_vector, 1) == 1; |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3896 | } |
| 3897 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3898 | static bool |
| 3899 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 3900 | { |
| 3901 | int ret; |
| 3902 | |
| 3903 | ret = intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 3904 | DP_SINK_COUNT_ESI, |
| 3905 | sink_irq_vector, 14); |
| 3906 | if (ret != 14) |
| 3907 | return false; |
| 3908 | |
| 3909 | return true; |
| 3910 | } |
| 3911 | |
Todd Previte | c5d5ab7 | 2015-04-15 08:38:38 -0700 | [diff] [blame] | 3912 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3913 | { |
Todd Previte | c5d5ab7 | 2015-04-15 08:38:38 -0700 | [diff] [blame] | 3914 | uint8_t test_result = DP_TEST_ACK; |
| 3915 | return test_result; |
| 3916 | } |
| 3917 | |
| 3918 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) |
| 3919 | { |
| 3920 | uint8_t test_result = DP_TEST_NAK; |
| 3921 | return test_result; |
| 3922 | } |
| 3923 | |
| 3924 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) |
| 3925 | { |
| 3926 | uint8_t test_result = DP_TEST_NAK; |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 3927 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 3928 | struct drm_connector *connector = &intel_connector->base; |
| 3929 | |
| 3930 | if (intel_connector->detect_edid == NULL || |
Daniel Vetter | ac6f2e2 | 2015-05-08 16:15:41 +0200 | [diff] [blame] | 3931 | connector->edid_corrupt || |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 3932 | intel_dp->aux.i2c_defer_count > 6) { |
| 3933 | /* Check EDID read for NACKs, DEFERs and corruption |
| 3934 | * (DP CTS 1.2 Core r1.1) |
| 3935 | * 4.2.2.4 : Failed EDID read, I2C_NAK |
| 3936 | * 4.2.2.5 : Failed EDID read, I2C_DEFER |
| 3937 | * 4.2.2.6 : EDID corruption detected |
| 3938 | * Use failsafe mode for all cases |
| 3939 | */ |
| 3940 | if (intel_dp->aux.i2c_nack_count > 0 || |
| 3941 | intel_dp->aux.i2c_defer_count > 0) |
| 3942 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", |
| 3943 | intel_dp->aux.i2c_nack_count, |
| 3944 | intel_dp->aux.i2c_defer_count); |
| 3945 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; |
| 3946 | } else { |
Thulasimani,Sivakumar | f79b468e | 2015-08-07 15:14:30 +0530 | [diff] [blame] | 3947 | struct edid *block = intel_connector->detect_edid; |
| 3948 | |
| 3949 | /* We have to write the checksum |
| 3950 | * of the last block read |
| 3951 | */ |
| 3952 | block += intel_connector->detect_edid->extensions; |
| 3953 | |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 3954 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
| 3955 | DP_TEST_EDID_CHECKSUM, |
Thulasimani,Sivakumar | f79b468e | 2015-08-07 15:14:30 +0530 | [diff] [blame] | 3956 | &block->checksum, |
Dan Carpenter | 5a1cc65 | 2015-05-12 21:07:37 +0300 | [diff] [blame] | 3957 | 1)) |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 3958 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
| 3959 | |
| 3960 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; |
| 3961 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; |
| 3962 | } |
| 3963 | |
| 3964 | /* Set test active flag here so userspace doesn't interrupt things */ |
| 3965 | intel_dp->compliance_test_active = 1; |
| 3966 | |
Todd Previte | c5d5ab7 | 2015-04-15 08:38:38 -0700 | [diff] [blame] | 3967 | return test_result; |
| 3968 | } |
| 3969 | |
| 3970 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) |
| 3971 | { |
| 3972 | uint8_t test_result = DP_TEST_NAK; |
| 3973 | return test_result; |
| 3974 | } |
| 3975 | |
| 3976 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) |
| 3977 | { |
| 3978 | uint8_t response = DP_TEST_NAK; |
| 3979 | uint8_t rxdata = 0; |
| 3980 | int status = 0; |
| 3981 | |
Todd Previte | c5d5ab7 | 2015-04-15 08:38:38 -0700 | [diff] [blame] | 3982 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
| 3983 | if (status <= 0) { |
| 3984 | DRM_DEBUG_KMS("Could not read test request from sink\n"); |
| 3985 | goto update_status; |
| 3986 | } |
| 3987 | |
| 3988 | switch (rxdata) { |
| 3989 | case DP_TEST_LINK_TRAINING: |
| 3990 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); |
| 3991 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; |
| 3992 | response = intel_dp_autotest_link_training(intel_dp); |
| 3993 | break; |
| 3994 | case DP_TEST_LINK_VIDEO_PATTERN: |
| 3995 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); |
| 3996 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; |
| 3997 | response = intel_dp_autotest_video_pattern(intel_dp); |
| 3998 | break; |
| 3999 | case DP_TEST_LINK_EDID_READ: |
| 4000 | DRM_DEBUG_KMS("EDID test requested\n"); |
| 4001 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; |
| 4002 | response = intel_dp_autotest_edid(intel_dp); |
| 4003 | break; |
| 4004 | case DP_TEST_LINK_PHY_TEST_PATTERN: |
| 4005 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); |
| 4006 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; |
| 4007 | response = intel_dp_autotest_phy_pattern(intel_dp); |
| 4008 | break; |
| 4009 | default: |
| 4010 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); |
| 4011 | break; |
| 4012 | } |
| 4013 | |
| 4014 | update_status: |
| 4015 | status = drm_dp_dpcd_write(&intel_dp->aux, |
| 4016 | DP_TEST_RESPONSE, |
| 4017 | &response, 1); |
| 4018 | if (status <= 0) |
| 4019 | DRM_DEBUG_KMS("Could not write test response to sink\n"); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4020 | } |
| 4021 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4022 | static int |
| 4023 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
| 4024 | { |
| 4025 | bool bret; |
| 4026 | |
| 4027 | if (intel_dp->is_mst) { |
| 4028 | u8 esi[16] = { 0 }; |
| 4029 | int ret = 0; |
| 4030 | int retry; |
| 4031 | bool handled; |
| 4032 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
| 4033 | go_again: |
| 4034 | if (bret == true) { |
| 4035 | |
| 4036 | /* check link status - esi[10] = 0x200c */ |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 4037 | if (intel_dp->active_mst_links && |
Ville Syrjälä | 901c2da | 2015-08-17 18:05:12 +0300 | [diff] [blame] | 4038 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4039 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
| 4040 | intel_dp_start_link_train(intel_dp); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4041 | intel_dp_stop_link_train(intel_dp); |
| 4042 | } |
| 4043 | |
Andy Shevchenko | 6f34cc3 | 2015-01-15 13:45:09 +0200 | [diff] [blame] | 4044 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4045 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
| 4046 | |
| 4047 | if (handled) { |
| 4048 | for (retry = 0; retry < 3; retry++) { |
| 4049 | int wret; |
| 4050 | wret = drm_dp_dpcd_write(&intel_dp->aux, |
| 4051 | DP_SINK_COUNT_ESI+1, |
| 4052 | &esi[1], 3); |
| 4053 | if (wret == 3) { |
| 4054 | break; |
| 4055 | } |
| 4056 | } |
| 4057 | |
| 4058 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
| 4059 | if (bret == true) { |
Andy Shevchenko | 6f34cc3 | 2015-01-15 13:45:09 +0200 | [diff] [blame] | 4060 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4061 | goto go_again; |
| 4062 | } |
| 4063 | } else |
| 4064 | ret = 0; |
| 4065 | |
| 4066 | return ret; |
| 4067 | } else { |
| 4068 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4069 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); |
| 4070 | intel_dp->is_mst = false; |
| 4071 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
| 4072 | /* send a hotplug event */ |
| 4073 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); |
| 4074 | } |
| 4075 | } |
| 4076 | return -EINVAL; |
| 4077 | } |
| 4078 | |
Shubhangi Shrivastava | 5c9114d | 2016-03-30 18:05:24 +0530 | [diff] [blame] | 4079 | static void |
| 4080 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
| 4081 | { |
| 4082 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
| 4083 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 4084 | u8 link_status[DP_LINK_STATUS_SIZE]; |
| 4085 | |
| 4086 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
| 4087 | |
| 4088 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
| 4089 | DRM_ERROR("Failed to get link status\n"); |
| 4090 | return; |
| 4091 | } |
| 4092 | |
| 4093 | if (!intel_encoder->base.crtc) |
| 4094 | return; |
| 4095 | |
| 4096 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) |
| 4097 | return; |
| 4098 | |
| 4099 | /* if link training is requested we should perform it always */ |
| 4100 | if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || |
| 4101 | (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { |
| 4102 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
| 4103 | intel_encoder->base.name); |
| 4104 | intel_dp_start_link_train(intel_dp); |
| 4105 | intel_dp_stop_link_train(intel_dp); |
| 4106 | } |
| 4107 | } |
| 4108 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4109 | /* |
| 4110 | * According to DP spec |
| 4111 | * 5.1.2: |
| 4112 | * 1. Read DPCD |
| 4113 | * 2. Configure link according to Receiver Capabilities |
| 4114 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
| 4115 | * 4. Check link status on receipt of hot-plug interrupt |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 4116 | * |
| 4117 | * intel_dp_short_pulse - handles short pulse interrupts |
| 4118 | * when full detection is not required. |
| 4119 | * Returns %true if short pulse is handled and full detection |
| 4120 | * is NOT required and %false otherwise. |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4121 | */ |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 4122 | static bool |
Shubhangi Shrivastava | 5c9114d | 2016-03-30 18:05:24 +0530 | [diff] [blame] | 4123 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4124 | { |
Dave Airlie | 5b215bc | 2014-08-05 10:40:20 +1000 | [diff] [blame] | 4125 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4126 | u8 sink_irq_vector; |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 4127 | u8 old_sink_count = intel_dp->sink_count; |
| 4128 | bool ret; |
Dave Airlie | 5b215bc | 2014-08-05 10:40:20 +1000 | [diff] [blame] | 4129 | |
Shubhangi Shrivastava | 4df6960 | 2015-10-28 15:30:36 +0530 | [diff] [blame] | 4130 | /* |
| 4131 | * Clearing compliance test variables to allow capturing |
| 4132 | * of values for next automated test request. |
| 4133 | */ |
| 4134 | intel_dp->compliance_test_active = 0; |
| 4135 | intel_dp->compliance_test_type = 0; |
| 4136 | intel_dp->compliance_test_data = 0; |
| 4137 | |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 4138 | /* |
| 4139 | * Now read the DPCD to see if it's actually running |
| 4140 | * If the current value of sink count doesn't match with |
| 4141 | * the value that was stored earlier or dpcd read failed |
| 4142 | * we need to do full detection |
| 4143 | */ |
| 4144 | ret = intel_dp_get_dpcd(intel_dp); |
| 4145 | |
| 4146 | if ((old_sink_count != intel_dp->sink_count) || !ret) { |
| 4147 | /* No need to proceed if we are going to do full detect */ |
| 4148 | return false; |
Jesse Barnes | 59cd09e | 2011-07-07 11:10:59 -0700 | [diff] [blame] | 4149 | } |
| 4150 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4151 | /* Try to read the source of the interrupt */ |
| 4152 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 4153 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
| 4154 | /* Clear interrupt source */ |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 4155 | drm_dp_dpcd_writeb(&intel_dp->aux, |
| 4156 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 4157 | sink_irq_vector); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4158 | |
| 4159 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
Todd Previte | 09b1eb1 | 2015-04-20 15:27:34 -0700 | [diff] [blame] | 4160 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4161 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
| 4162 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
| 4163 | } |
| 4164 | |
Shubhangi Shrivastava | 5c9114d | 2016-03-30 18:05:24 +0530 | [diff] [blame] | 4165 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
| 4166 | intel_dp_check_link_status(intel_dp); |
| 4167 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 4168 | |
| 4169 | return true; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4170 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4171 | |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4172 | /* XXX this is probably wrong for multiple downstream ports */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4173 | static enum drm_connector_status |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 4174 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 4175 | { |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4176 | uint8_t *dpcd = intel_dp->dpcd; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4177 | uint8_t type; |
| 4178 | |
| 4179 | if (!intel_dp_get_dpcd(intel_dp)) |
| 4180 | return connector_status_disconnected; |
| 4181 | |
Shubhangi Shrivastava | 1034ce7 | 2016-04-12 12:23:54 +0530 | [diff] [blame] | 4182 | if (is_edp(intel_dp)) |
| 4183 | return connector_status_connected; |
| 4184 | |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4185 | /* if there's no downstream port, we're done */ |
| 4186 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 4187 | return connector_status_connected; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4188 | |
| 4189 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
Jani Nikula | c9ff160 | 2013-09-27 14:48:42 +0300 | [diff] [blame] | 4190 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 4191 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 4192 | |
Shubhangi Shrivastava | 30d9aa4 | 2016-03-30 18:05:25 +0530 | [diff] [blame] | 4193 | return intel_dp->sink_count ? |
| 4194 | connector_status_connected : connector_status_disconnected; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4195 | } |
| 4196 | |
| 4197 | /* If no HPD, poke DDC gently */ |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 4198 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4199 | return connector_status_connected; |
| 4200 | |
| 4201 | /* Well we tried, say unknown for unreliable port types */ |
Jani Nikula | c9ff160 | 2013-09-27 14:48:42 +0300 | [diff] [blame] | 4202 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
| 4203 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
| 4204 | if (type == DP_DS_PORT_TYPE_VGA || |
| 4205 | type == DP_DS_PORT_TYPE_NON_EDID) |
| 4206 | return connector_status_unknown; |
| 4207 | } else { |
| 4208 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 4209 | DP_DWN_STRM_PORT_TYPE_MASK; |
| 4210 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
| 4211 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
| 4212 | return connector_status_unknown; |
| 4213 | } |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4214 | |
| 4215 | /* Anything else is out of spec, warn and ignore */ |
| 4216 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 4217 | return connector_status_disconnected; |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 4218 | } |
| 4219 | |
| 4220 | static enum drm_connector_status |
Chris Wilson | d410b56 | 2014-09-02 20:03:59 +0100 | [diff] [blame] | 4221 | edp_detect(struct intel_dp *intel_dp) |
| 4222 | { |
| 4223 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 4224 | enum drm_connector_status status; |
| 4225 | |
| 4226 | status = intel_panel_detect(dev); |
| 4227 | if (status == connector_status_unknown) |
| 4228 | status = connector_status_connected; |
| 4229 | |
| 4230 | return status; |
| 4231 | } |
| 4232 | |
Jani Nikula | b93433c | 2015-08-20 10:47:36 +0300 | [diff] [blame] | 4233 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4234 | struct intel_digital_port *port) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4235 | { |
Jani Nikula | b93433c | 2015-08-20 10:47:36 +0300 | [diff] [blame] | 4236 | u32 bit; |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 4237 | |
Jani Nikula | 0df53b7 | 2015-08-20 10:47:40 +0300 | [diff] [blame] | 4238 | switch (port->port) { |
| 4239 | case PORT_A: |
| 4240 | return true; |
| 4241 | case PORT_B: |
| 4242 | bit = SDE_PORTB_HOTPLUG; |
| 4243 | break; |
| 4244 | case PORT_C: |
| 4245 | bit = SDE_PORTC_HOTPLUG; |
| 4246 | break; |
| 4247 | case PORT_D: |
| 4248 | bit = SDE_PORTD_HOTPLUG; |
| 4249 | break; |
| 4250 | default: |
| 4251 | MISSING_CASE(port->port); |
| 4252 | return false; |
| 4253 | } |
| 4254 | |
| 4255 | return I915_READ(SDEISR) & bit; |
| 4256 | } |
| 4257 | |
| 4258 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4259 | struct intel_digital_port *port) |
| 4260 | { |
| 4261 | u32 bit; |
| 4262 | |
| 4263 | switch (port->port) { |
| 4264 | case PORT_A: |
| 4265 | return true; |
| 4266 | case PORT_B: |
| 4267 | bit = SDE_PORTB_HOTPLUG_CPT; |
| 4268 | break; |
| 4269 | case PORT_C: |
| 4270 | bit = SDE_PORTC_HOTPLUG_CPT; |
| 4271 | break; |
| 4272 | case PORT_D: |
| 4273 | bit = SDE_PORTD_HOTPLUG_CPT; |
| 4274 | break; |
Jani Nikula | a78695d | 2015-09-18 15:54:50 +0300 | [diff] [blame] | 4275 | case PORT_E: |
| 4276 | bit = SDE_PORTE_HOTPLUG_SPT; |
| 4277 | break; |
Jani Nikula | 0df53b7 | 2015-08-20 10:47:40 +0300 | [diff] [blame] | 4278 | default: |
| 4279 | MISSING_CASE(port->port); |
| 4280 | return false; |
Jani Nikula | b93433c | 2015-08-20 10:47:36 +0300 | [diff] [blame] | 4281 | } |
Damien Lespiau | 1b46963 | 2012-12-13 16:09:01 +0000 | [diff] [blame] | 4282 | |
Jani Nikula | b93433c | 2015-08-20 10:47:36 +0300 | [diff] [blame] | 4283 | return I915_READ(SDEISR) & bit; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4284 | } |
| 4285 | |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4286 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
Jani Nikula | 1d24598 | 2015-08-20 10:47:37 +0300 | [diff] [blame] | 4287 | struct intel_digital_port *port) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4288 | { |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4289 | u32 bit; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4290 | |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4291 | switch (port->port) { |
| 4292 | case PORT_B: |
| 4293 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
| 4294 | break; |
| 4295 | case PORT_C: |
| 4296 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
| 4297 | break; |
| 4298 | case PORT_D: |
| 4299 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
| 4300 | break; |
| 4301 | default: |
| 4302 | MISSING_CASE(port->port); |
| 4303 | return false; |
| 4304 | } |
| 4305 | |
| 4306 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
| 4307 | } |
| 4308 | |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 4309 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4310 | struct intel_digital_port *port) |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4311 | { |
| 4312 | u32 bit; |
| 4313 | |
| 4314 | switch (port->port) { |
| 4315 | case PORT_B: |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 4316 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4317 | break; |
| 4318 | case PORT_C: |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 4319 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4320 | break; |
| 4321 | case PORT_D: |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 4322 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4323 | break; |
| 4324 | default: |
| 4325 | MISSING_CASE(port->port); |
| 4326 | return false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4327 | } |
| 4328 | |
Jani Nikula | 1d24598 | 2015-08-20 10:47:37 +0300 | [diff] [blame] | 4329 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
Dave Airlie | 2a592be | 2014-09-01 16:58:12 +1000 | [diff] [blame] | 4330 | } |
| 4331 | |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4332 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
Sonika Jindal | e2ec35a | 2015-09-11 16:58:32 +0530 | [diff] [blame] | 4333 | struct intel_digital_port *intel_dig_port) |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4334 | { |
Sonika Jindal | e2ec35a | 2015-09-11 16:58:32 +0530 | [diff] [blame] | 4335 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 4336 | enum port port; |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4337 | u32 bit; |
| 4338 | |
Sonika Jindal | e2ec35a | 2015-09-11 16:58:32 +0530 | [diff] [blame] | 4339 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
| 4340 | switch (port) { |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4341 | case PORT_A: |
| 4342 | bit = BXT_DE_PORT_HP_DDIA; |
| 4343 | break; |
| 4344 | case PORT_B: |
| 4345 | bit = BXT_DE_PORT_HP_DDIB; |
| 4346 | break; |
| 4347 | case PORT_C: |
| 4348 | bit = BXT_DE_PORT_HP_DDIC; |
| 4349 | break; |
| 4350 | default: |
Sonika Jindal | e2ec35a | 2015-09-11 16:58:32 +0530 | [diff] [blame] | 4351 | MISSING_CASE(port); |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4352 | return false; |
| 4353 | } |
| 4354 | |
| 4355 | return I915_READ(GEN8_DE_PORT_ISR) & bit; |
| 4356 | } |
| 4357 | |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4358 | /* |
| 4359 | * intel_digital_port_connected - is the specified port connected? |
| 4360 | * @dev_priv: i915 private structure |
| 4361 | * @port: the port to test |
| 4362 | * |
| 4363 | * Return %true if @port is connected, %false otherwise. |
| 4364 | */ |
Sonika Jindal | 237ed86 | 2015-09-15 09:44:20 +0530 | [diff] [blame] | 4365 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4366 | struct intel_digital_port *port) |
| 4367 | { |
Jani Nikula | 0df53b7 | 2015-08-20 10:47:40 +0300 | [diff] [blame] | 4368 | if (HAS_PCH_IBX(dev_priv)) |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4369 | return ibx_digital_port_connected(dev_priv, port); |
Ville Syrjälä | 22824fa | 2016-02-11 16:44:28 +0200 | [diff] [blame] | 4370 | else if (HAS_PCH_SPLIT(dev_priv)) |
Jani Nikula | 0df53b7 | 2015-08-20 10:47:40 +0300 | [diff] [blame] | 4371 | return cpt_digital_port_connected(dev_priv, port); |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4372 | else if (IS_BROXTON(dev_priv)) |
| 4373 | return bxt_digital_port_connected(dev_priv, port); |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 4374 | else if (IS_GM45(dev_priv)) |
| 4375 | return gm45_digital_port_connected(dev_priv, port); |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4376 | else |
| 4377 | return g4x_digital_port_connected(dev_priv, port); |
| 4378 | } |
| 4379 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4380 | static struct edid * |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4381 | intel_dp_get_edid(struct intel_dp *intel_dp) |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4382 | { |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4383 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4384 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 4385 | /* use cached edid if we have one */ |
| 4386 | if (intel_connector->edid) { |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 4387 | /* invalid edid */ |
| 4388 | if (IS_ERR(intel_connector->edid)) |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 4389 | return NULL; |
| 4390 | |
Jani Nikula | 55e9ede | 2013-10-01 10:38:54 +0300 | [diff] [blame] | 4391 | return drm_edid_duplicate(intel_connector->edid); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4392 | } else |
| 4393 | return drm_get_edid(&intel_connector->base, |
| 4394 | &intel_dp->aux.ddc); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4395 | } |
| 4396 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4397 | static void |
| 4398 | intel_dp_set_edid(struct intel_dp *intel_dp) |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4399 | { |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4400 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 4401 | struct edid *edid; |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4402 | |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4403 | intel_dp_unset_edid(intel_dp); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4404 | edid = intel_dp_get_edid(intel_dp); |
| 4405 | intel_connector->detect_edid = edid; |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 4406 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4407 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) |
| 4408 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; |
| 4409 | else |
| 4410 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
| 4411 | } |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 4412 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4413 | static void |
| 4414 | intel_dp_unset_edid(struct intel_dp *intel_dp) |
| 4415 | { |
| 4416 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 4417 | |
| 4418 | kfree(intel_connector->detect_edid); |
| 4419 | intel_connector->detect_edid = NULL; |
| 4420 | |
| 4421 | intel_dp->has_audio = false; |
| 4422 | } |
| 4423 | |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4424 | static void |
| 4425 | intel_dp_long_pulse(struct intel_connector *intel_connector) |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4426 | { |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4427 | struct drm_connector *connector = &intel_connector->base; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4428 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Paulo Zanoni | d63885d | 2012-10-26 19:05:49 -0200 | [diff] [blame] | 4429 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4430 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 4431 | struct drm_device *dev = connector->dev; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4432 | enum drm_connector_status status; |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 4433 | enum intel_display_power_domain power_domain; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4434 | bool ret; |
Todd Previte | 09b1eb1 | 2015-04-20 15:27:34 -0700 | [diff] [blame] | 4435 | u8 sink_irq_vector; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4436 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4437 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
| 4438 | intel_display_power_get(to_i915(dev), power_domain); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4439 | |
Chris Wilson | d410b56 | 2014-09-02 20:03:59 +0100 | [diff] [blame] | 4440 | /* Can't disconnect eDP, but you can close the lid... */ |
| 4441 | if (is_edp(intel_dp)) |
| 4442 | status = edp_detect(intel_dp); |
Ander Conselvan de Oliveira | c555a81 | 2015-11-18 17:19:30 +0200 | [diff] [blame] | 4443 | else if (intel_digital_port_connected(to_i915(dev), |
| 4444 | dp_to_dig_port(intel_dp))) |
| 4445 | status = intel_dp_detect_dpcd(intel_dp); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4446 | else |
Ander Conselvan de Oliveira | c555a81 | 2015-11-18 17:19:30 +0200 | [diff] [blame] | 4447 | status = connector_status_disconnected; |
| 4448 | |
Shubhangi Shrivastava | 4df6960 | 2015-10-28 15:30:36 +0530 | [diff] [blame] | 4449 | if (status != connector_status_connected) { |
| 4450 | intel_dp->compliance_test_active = 0; |
| 4451 | intel_dp->compliance_test_type = 0; |
| 4452 | intel_dp->compliance_test_data = 0; |
| 4453 | |
jim.bride@linux.intel.com | 0e505a0 | 2016-04-11 10:11:24 -0700 | [diff] [blame] | 4454 | if (intel_dp->is_mst) { |
| 4455 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", |
| 4456 | intel_dp->is_mst, |
| 4457 | intel_dp->mst_mgr.mst_state); |
| 4458 | intel_dp->is_mst = false; |
| 4459 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, |
| 4460 | intel_dp->is_mst); |
| 4461 | } |
| 4462 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4463 | goto out; |
Shubhangi Shrivastava | 4df6960 | 2015-10-28 15:30:36 +0530 | [diff] [blame] | 4464 | } |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4465 | |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4466 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 4467 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 4468 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 4469 | intel_dp_probe_oui(intel_dp); |
| 4470 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4471 | ret = intel_dp_probe_mst(intel_dp); |
| 4472 | if (ret) { |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4473 | /* |
| 4474 | * If we are in MST mode then this connector |
| 4475 | * won't appear connected or have anything |
| 4476 | * with EDID on it |
| 4477 | */ |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4478 | status = connector_status_disconnected; |
| 4479 | goto out; |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4480 | } else if (connector->status == connector_status_connected) { |
| 4481 | /* |
| 4482 | * If display was connected already and is still connected |
| 4483 | * check links status, there has been known issues of |
| 4484 | * link loss triggerring long pulse!!!! |
| 4485 | */ |
| 4486 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
| 4487 | intel_dp_check_link_status(intel_dp); |
| 4488 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
| 4489 | goto out; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4490 | } |
| 4491 | |
Shubhangi Shrivastava | 4df6960 | 2015-10-28 15:30:36 +0530 | [diff] [blame] | 4492 | /* |
| 4493 | * Clearing NACK and defer counts to get their exact values |
| 4494 | * while reading EDID which are required by Compliance tests |
| 4495 | * 4.2.2.4 and 4.2.2.5 |
| 4496 | */ |
| 4497 | intel_dp->aux.i2c_nack_count = 0; |
| 4498 | intel_dp->aux.i2c_defer_count = 0; |
| 4499 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4500 | intel_dp_set_edid(intel_dp); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4501 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4502 | status = connector_status_connected; |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4503 | intel_dp->detect_done = true; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4504 | |
Todd Previte | 09b1eb1 | 2015-04-20 15:27:34 -0700 | [diff] [blame] | 4505 | /* Try to read the source of the interrupt */ |
| 4506 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 4507 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
| 4508 | /* Clear interrupt source */ |
| 4509 | drm_dp_dpcd_writeb(&intel_dp->aux, |
| 4510 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 4511 | sink_irq_vector); |
| 4512 | |
| 4513 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
| 4514 | intel_dp_handle_test_request(intel_dp); |
| 4515 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
| 4516 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
| 4517 | } |
| 4518 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4519 | out: |
jim.bride@linux.intel.com | 0e505a0 | 2016-04-11 10:11:24 -0700 | [diff] [blame] | 4520 | if ((status != connector_status_connected) && |
| 4521 | (intel_dp->is_mst == false)) |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4522 | intel_dp_unset_edid(intel_dp); |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4523 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4524 | intel_display_power_put(to_i915(dev), power_domain); |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4525 | return; |
| 4526 | } |
| 4527 | |
| 4528 | static enum drm_connector_status |
| 4529 | intel_dp_detect(struct drm_connector *connector, bool force) |
| 4530 | { |
| 4531 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 4532 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4533 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 4534 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4535 | |
| 4536 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 4537 | connector->base.id, connector->name); |
| 4538 | |
| 4539 | if (intel_dp->is_mst) { |
| 4540 | /* MST devices are disconnected from a monitor POV */ |
| 4541 | intel_dp_unset_edid(intel_dp); |
| 4542 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 4543 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 4544 | return connector_status_disconnected; |
| 4545 | } |
| 4546 | |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4547 | /* If full detect is not performed yet, do a full detect */ |
| 4548 | if (!intel_dp->detect_done) |
| 4549 | intel_dp_long_pulse(intel_dp->attached_connector); |
| 4550 | |
| 4551 | intel_dp->detect_done = false; |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4552 | |
| 4553 | if (intel_connector->detect_edid) |
| 4554 | return connector_status_connected; |
| 4555 | else |
| 4556 | return connector_status_disconnected; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4557 | } |
| 4558 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4559 | static void |
| 4560 | intel_dp_force(struct drm_connector *connector) |
| 4561 | { |
| 4562 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 4563 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4564 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4565 | enum intel_display_power_domain power_domain; |
| 4566 | |
| 4567 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 4568 | connector->base.id, connector->name); |
| 4569 | intel_dp_unset_edid(intel_dp); |
| 4570 | |
| 4571 | if (connector->status != connector_status_connected) |
| 4572 | return; |
| 4573 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4574 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
| 4575 | intel_display_power_get(dev_priv, power_domain); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4576 | |
| 4577 | intel_dp_set_edid(intel_dp); |
| 4578 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4579 | intel_display_power_put(dev_priv, power_domain); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4580 | |
| 4581 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 4582 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 4583 | } |
| 4584 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4585 | static int intel_dp_get_modes(struct drm_connector *connector) |
| 4586 | { |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 4587 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4588 | struct edid *edid; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4589 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4590 | edid = intel_connector->detect_edid; |
| 4591 | if (edid) { |
| 4592 | int ret = intel_connector_update_modes(connector, edid); |
| 4593 | if (ret) |
| 4594 | return ret; |
| 4595 | } |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4596 | |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 4597 | /* if eDP has no EDID, fall back to fixed mode */ |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4598 | if (is_edp(intel_attached_dp(connector)) && |
| 4599 | intel_connector->panel.fixed_mode) { |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 4600 | struct drm_display_mode *mode; |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4601 | |
| 4602 | mode = drm_mode_duplicate(connector->dev, |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 4603 | intel_connector->panel.fixed_mode); |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 4604 | if (mode) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4605 | drm_mode_probed_add(connector, mode); |
| 4606 | return 1; |
| 4607 | } |
| 4608 | } |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4609 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4610 | return 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4611 | } |
| 4612 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4613 | static bool |
| 4614 | intel_dp_detect_audio(struct drm_connector *connector) |
| 4615 | { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4616 | bool has_audio = false; |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4617 | struct edid *edid; |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4618 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4619 | edid = to_intel_connector(connector)->detect_edid; |
| 4620 | if (edid) |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4621 | has_audio = drm_detect_monitor_audio(edid); |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 4622 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4623 | return has_audio; |
| 4624 | } |
| 4625 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4626 | static int |
| 4627 | intel_dp_set_property(struct drm_connector *connector, |
| 4628 | struct drm_property *property, |
| 4629 | uint64_t val) |
| 4630 | { |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 4631 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4632 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 4633 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
| 4634 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4635 | int ret; |
| 4636 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 4637 | ret = drm_object_property_set_value(&connector->base, property, val); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4638 | if (ret) |
| 4639 | return ret; |
| 4640 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 4641 | if (property == dev_priv->force_audio_property) { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4642 | int i = val; |
| 4643 | bool has_audio; |
| 4644 | |
| 4645 | if (i == intel_dp->force_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4646 | return 0; |
| 4647 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4648 | intel_dp->force_audio = i; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4649 | |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 4650 | if (i == HDMI_AUDIO_AUTO) |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4651 | has_audio = intel_dp_detect_audio(connector); |
| 4652 | else |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 4653 | has_audio = (i == HDMI_AUDIO_ON); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4654 | |
| 4655 | if (has_audio == intel_dp->has_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4656 | return 0; |
| 4657 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4658 | intel_dp->has_audio = has_audio; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4659 | goto done; |
| 4660 | } |
| 4661 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 4662 | if (property == dev_priv->broadcast_rgb_property) { |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 4663 | bool old_auto = intel_dp->color_range_auto; |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 4664 | bool old_range = intel_dp->limited_color_range; |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 4665 | |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 4666 | switch (val) { |
| 4667 | case INTEL_BROADCAST_RGB_AUTO: |
| 4668 | intel_dp->color_range_auto = true; |
| 4669 | break; |
| 4670 | case INTEL_BROADCAST_RGB_FULL: |
| 4671 | intel_dp->color_range_auto = false; |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 4672 | intel_dp->limited_color_range = false; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 4673 | break; |
| 4674 | case INTEL_BROADCAST_RGB_LIMITED: |
| 4675 | intel_dp->color_range_auto = false; |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 4676 | intel_dp->limited_color_range = true; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 4677 | break; |
| 4678 | default: |
| 4679 | return -EINVAL; |
| 4680 | } |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 4681 | |
| 4682 | if (old_auto == intel_dp->color_range_auto && |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 4683 | old_range == intel_dp->limited_color_range) |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 4684 | return 0; |
| 4685 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 4686 | goto done; |
| 4687 | } |
| 4688 | |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4689 | if (is_edp(intel_dp) && |
| 4690 | property == connector->dev->mode_config.scaling_mode_property) { |
| 4691 | if (val == DRM_MODE_SCALE_NONE) { |
| 4692 | DRM_DEBUG_KMS("no scaling not supported\n"); |
| 4693 | return -EINVAL; |
| 4694 | } |
Ville Syrjälä | 234126c | 2016-04-12 22:14:38 +0300 | [diff] [blame] | 4695 | if (HAS_GMCH_DISPLAY(dev_priv) && |
| 4696 | val == DRM_MODE_SCALE_CENTER) { |
| 4697 | DRM_DEBUG_KMS("centering not supported\n"); |
| 4698 | return -EINVAL; |
| 4699 | } |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4700 | |
| 4701 | if (intel_connector->panel.fitting_mode == val) { |
| 4702 | /* the eDP scaling property is not changed */ |
| 4703 | return 0; |
| 4704 | } |
| 4705 | intel_connector->panel.fitting_mode = val; |
| 4706 | |
| 4707 | goto done; |
| 4708 | } |
| 4709 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4710 | return -EINVAL; |
| 4711 | |
| 4712 | done: |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 4713 | if (intel_encoder->base.crtc) |
| 4714 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4715 | |
| 4716 | return 0; |
| 4717 | } |
| 4718 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4719 | static void |
Paulo Zanoni | 73845ad | 2013-06-12 17:27:30 -0300 | [diff] [blame] | 4720 | intel_dp_connector_destroy(struct drm_connector *connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4721 | { |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 4722 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 4723 | |
Chris Wilson | 10e972d | 2014-09-04 21:43:45 +0100 | [diff] [blame] | 4724 | kfree(intel_connector->detect_edid); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4725 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 4726 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
| 4727 | kfree(intel_connector->edid); |
| 4728 | |
Paulo Zanoni | acd8db10 | 2013-06-12 17:27:23 -0300 | [diff] [blame] | 4729 | /* Can't call is_edp() since the encoder may have been destroyed |
| 4730 | * already. */ |
| 4731 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 4732 | intel_panel_fini(&intel_connector->panel); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 4733 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4734 | drm_connector_cleanup(connector); |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 4735 | kfree(connector); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4736 | } |
| 4737 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 4738 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 4739 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 4740 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
| 4741 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 4742 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4743 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 4744 | if (is_edp(intel_dp)) { |
| 4745 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 4746 | /* |
| 4747 | * vdd might still be enabled do to the delayed vdd off. |
| 4748 | * Make sure vdd is actually turned off here. |
| 4749 | */ |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 4750 | pps_lock(intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 4751 | edp_panel_vdd_off_sync(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 4752 | pps_unlock(intel_dp); |
| 4753 | |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 4754 | if (intel_dp->edp_notifier.notifier_call) { |
| 4755 | unregister_reboot_notifier(&intel_dp->edp_notifier); |
| 4756 | intel_dp->edp_notifier.notifier_call = NULL; |
| 4757 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 4758 | } |
Imre Deak | c8bd0e4 | 2014-12-12 17:57:38 +0200 | [diff] [blame] | 4759 | drm_encoder_cleanup(encoder); |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 4760 | kfree(intel_dig_port); |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 4761 | } |
| 4762 | |
Imre Deak | bf93ba6 | 2016-04-18 10:04:21 +0300 | [diff] [blame] | 4763 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 4764 | { |
| 4765 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
| 4766 | |
| 4767 | if (!is_edp(intel_dp)) |
| 4768 | return; |
| 4769 | |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 4770 | /* |
| 4771 | * vdd might still be enabled do to the delayed vdd off. |
| 4772 | * Make sure vdd is actually turned off here. |
| 4773 | */ |
Ville Syrjälä | afa4e53 | 2014-11-25 15:43:48 +0200 | [diff] [blame] | 4774 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 4775 | pps_lock(intel_dp); |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 4776 | edp_panel_vdd_off_sync(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 4777 | pps_unlock(intel_dp); |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 4778 | } |
| 4779 | |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4780 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
| 4781 | { |
| 4782 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4783 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 4784 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4785 | enum intel_display_power_domain power_domain; |
| 4786 | |
| 4787 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 4788 | |
| 4789 | if (!edp_have_panel_vdd(intel_dp)) |
| 4790 | return; |
| 4791 | |
| 4792 | /* |
| 4793 | * The VDD bit needs a power domain reference, so if the bit is |
| 4794 | * already enabled when we boot or resume, grab this reference and |
| 4795 | * schedule a vdd off, so we don't hold on to the reference |
| 4796 | * indefinitely. |
| 4797 | */ |
| 4798 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4799 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4800 | intel_display_power_get(dev_priv, power_domain); |
| 4801 | |
| 4802 | edp_panel_vdd_schedule_off(intel_dp); |
| 4803 | } |
| 4804 | |
Imre Deak | bf93ba6 | 2016-04-18 10:04:21 +0300 | [diff] [blame] | 4805 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
Imre Deak | 6d93c0c | 2014-07-31 14:03:36 +0300 | [diff] [blame] | 4806 | { |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4807 | struct intel_dp *intel_dp; |
| 4808 | |
| 4809 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) |
| 4810 | return; |
| 4811 | |
| 4812 | intel_dp = enc_to_intel_dp(encoder); |
| 4813 | |
| 4814 | pps_lock(intel_dp); |
| 4815 | |
| 4816 | /* |
| 4817 | * Read out the current power sequencer assignment, |
| 4818 | * in case the BIOS did something with it. |
| 4819 | */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 4820 | if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev)) |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4821 | vlv_initial_power_sequencer_setup(intel_dp); |
| 4822 | |
| 4823 | intel_edp_panel_vdd_sanitize(intel_dp); |
| 4824 | |
| 4825 | pps_unlock(intel_dp); |
Imre Deak | 6d93c0c | 2014-07-31 14:03:36 +0300 | [diff] [blame] | 4826 | } |
| 4827 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4828 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
Maarten Lankhorst | 4d688a2 | 2015-08-05 12:37:06 +0200 | [diff] [blame] | 4829 | .dpms = drm_atomic_helper_connector_dpms, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4830 | .detect = intel_dp_detect, |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4831 | .force = intel_dp_force, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4832 | .fill_modes = drm_helper_probe_single_connector_modes, |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4833 | .set_property = intel_dp_set_property, |
Matt Roper | 2545e4a | 2015-01-22 16:51:27 -0800 | [diff] [blame] | 4834 | .atomic_get_property = intel_connector_atomic_get_property, |
Paulo Zanoni | 73845ad | 2013-06-12 17:27:30 -0300 | [diff] [blame] | 4835 | .destroy = intel_dp_connector_destroy, |
Matt Roper | c6f95f2 | 2015-01-22 16:50:32 -0800 | [diff] [blame] | 4836 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
Ander Conselvan de Oliveira | 9896972 | 2015-03-20 16:18:06 +0200 | [diff] [blame] | 4837 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4838 | }; |
| 4839 | |
| 4840 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
| 4841 | .get_modes = intel_dp_get_modes, |
| 4842 | .mode_valid = intel_dp_mode_valid, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 4843 | .best_encoder = intel_best_encoder, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4844 | }; |
| 4845 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4846 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
Imre Deak | 6d93c0c | 2014-07-31 14:03:36 +0300 | [diff] [blame] | 4847 | .reset = intel_dp_encoder_reset, |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 4848 | .destroy = intel_dp_encoder_destroy, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4849 | }; |
| 4850 | |
Daniel Vetter | b2c5c18 | 2015-01-23 06:00:31 +0100 | [diff] [blame] | 4851 | enum irqreturn |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 4852 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
| 4853 | { |
| 4854 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4855 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4856 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 4857 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4858 | enum intel_display_power_domain power_domain; |
Daniel Vetter | b2c5c18 | 2015-01-23 06:00:31 +0100 | [diff] [blame] | 4859 | enum irqreturn ret = IRQ_NONE; |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4860 | |
Takashi Iwai | 2540058 | 2015-11-19 12:09:56 +0100 | [diff] [blame] | 4861 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
| 4862 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4863 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 4864 | |
Ville Syrjälä | 7a7f84c | 2014-10-16 20:46:10 +0300 | [diff] [blame] | 4865 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
| 4866 | /* |
| 4867 | * vdd off can generate a long pulse on eDP which |
| 4868 | * would require vdd on to handle it, and thus we |
| 4869 | * would end up in an endless cycle of |
| 4870 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." |
| 4871 | */ |
| 4872 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", |
| 4873 | port_name(intel_dig_port->port)); |
Ville Syrjälä | a8b3d52 | 2015-02-10 14:11:46 +0200 | [diff] [blame] | 4874 | return IRQ_HANDLED; |
Ville Syrjälä | 7a7f84c | 2014-10-16 20:46:10 +0300 | [diff] [blame] | 4875 | } |
| 4876 | |
Ville Syrjälä | 26fbb77 | 2014-08-11 18:37:37 +0300 | [diff] [blame] | 4877 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
| 4878 | port_name(intel_dig_port->port), |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4879 | long_hpd ? "long" : "short"); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 4880 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4881 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4882 | intel_display_power_get(dev_priv, power_domain); |
| 4883 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4884 | if (long_hpd) { |
Mika Kahola | 5fa836a | 2015-04-29 09:17:40 +0300 | [diff] [blame] | 4885 | /* indicate that we need to restart link training */ |
| 4886 | intel_dp->train_set_valid = false; |
Dave Airlie | 2a592be | 2014-09-01 16:58:12 +1000 | [diff] [blame] | 4887 | |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4888 | intel_dp_long_pulse(intel_dp->attached_connector); |
| 4889 | if (intel_dp->is_mst) |
| 4890 | ret = IRQ_HANDLED; |
| 4891 | goto put_power; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4892 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4893 | } else { |
| 4894 | if (intel_dp->is_mst) { |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4895 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { |
| 4896 | /* |
| 4897 | * If we were in MST mode, and device is not |
| 4898 | * there, get out of MST mode |
| 4899 | */ |
| 4900 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", |
| 4901 | intel_dp->is_mst, intel_dp->mst_mgr.mst_state); |
| 4902 | intel_dp->is_mst = false; |
| 4903 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, |
| 4904 | intel_dp->is_mst); |
| 4905 | goto put_power; |
| 4906 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4907 | } |
| 4908 | |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 4909 | if (!intel_dp->is_mst) { |
| 4910 | if (!intel_dp_short_pulse(intel_dp)) { |
| 4911 | intel_dp_long_pulse(intel_dp->attached_connector); |
| 4912 | goto put_power; |
| 4913 | } |
| 4914 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4915 | } |
Daniel Vetter | b2c5c18 | 2015-01-23 06:00:31 +0100 | [diff] [blame] | 4916 | |
| 4917 | ret = IRQ_HANDLED; |
| 4918 | |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4919 | put_power: |
| 4920 | intel_display_power_put(dev_priv, power_domain); |
| 4921 | |
| 4922 | return ret; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 4923 | } |
| 4924 | |
Rodrigo Vivi | 477ec32 | 2015-08-06 15:51:39 +0800 | [diff] [blame] | 4925 | /* check the VBT to see whether the eDP is on another port */ |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 4926 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 4927 | { |
| 4928 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 4929 | |
Ville Syrjälä | 53ce81a | 2015-09-11 21:04:38 +0300 | [diff] [blame] | 4930 | /* |
| 4931 | * eDP not supported on g4x. so bail out early just |
| 4932 | * for a bit extra safety in case the VBT is bonkers. |
| 4933 | */ |
| 4934 | if (INTEL_INFO(dev)->gen < 5) |
| 4935 | return false; |
| 4936 | |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 4937 | if (port == PORT_A) |
| 4938 | return true; |
| 4939 | |
Jani Nikula | 951d9ef | 2016-03-16 12:43:31 +0200 | [diff] [blame] | 4940 | return intel_bios_is_port_edp(dev_priv, port); |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 4941 | } |
| 4942 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4943 | void |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4944 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
| 4945 | { |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4946 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4947 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 4948 | intel_attach_force_audio_property(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 4949 | intel_attach_broadcast_rgb_property(connector); |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 4950 | intel_dp->color_range_auto = true; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4951 | |
| 4952 | if (is_edp(intel_dp)) { |
| 4953 | drm_mode_create_scaling_mode_property(connector->dev); |
Rob Clark | 6de6d84 | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 4954 | drm_object_attach_property( |
| 4955 | &connector->base, |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4956 | connector->dev->mode_config.scaling_mode_property, |
Yuly Novikov | 8e740cd | 2012-10-26 12:04:01 +0300 | [diff] [blame] | 4957 | DRM_MODE_SCALE_ASPECT); |
| 4958 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4959 | } |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4960 | } |
| 4961 | |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 4962 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
| 4963 | { |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 4964 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 4965 | intel_dp->last_power_on = jiffies; |
| 4966 | intel_dp->last_backlight_off = jiffies; |
| 4967 | } |
| 4968 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4969 | static void |
| 4970 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 4971 | struct intel_dp *intel_dp) |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4972 | { |
| 4973 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 4974 | struct edp_power_seq cur, vbt, spec, |
| 4975 | *final = &intel_dp->pps_delays; |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4976 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 4977 | i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 4978 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 4979 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 4980 | |
Ville Syrjälä | 81ddbc6 | 2014-10-16 21:27:31 +0300 | [diff] [blame] | 4981 | /* already initialized? */ |
| 4982 | if (final->t11_t12 != 0) |
| 4983 | return; |
| 4984 | |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4985 | if (IS_BROXTON(dev)) { |
| 4986 | /* |
| 4987 | * TODO: BXT has 2 sets of PPS registers. |
| 4988 | * Correct Register for Broxton need to be identified |
| 4989 | * using VBT. hardcoding for now |
| 4990 | */ |
| 4991 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
| 4992 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
| 4993 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
| 4994 | } else if (HAS_PCH_SPLIT(dev)) { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 4995 | pp_ctrl_reg = PCH_PP_CONTROL; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 4996 | pp_on_reg = PCH_PP_ON_DELAYS; |
| 4997 | pp_off_reg = PCH_PP_OFF_DELAYS; |
| 4998 | pp_div_reg = PCH_PP_DIVISOR; |
| 4999 | } else { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 5000 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
| 5001 | |
| 5002 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
| 5003 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
| 5004 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
| 5005 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5006 | } |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5007 | |
| 5008 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
| 5009 | * the very first thing. */ |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5010 | pp_ctl = ironlake_get_pp_control(intel_dp); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5011 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5012 | pp_on = I915_READ(pp_on_reg); |
| 5013 | pp_off = I915_READ(pp_off_reg); |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5014 | if (!IS_BROXTON(dev)) { |
| 5015 | I915_WRITE(pp_ctrl_reg, pp_ctl); |
| 5016 | pp_div = I915_READ(pp_div_reg); |
| 5017 | } |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5018 | |
| 5019 | /* Pull timing values out of registers */ |
| 5020 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
| 5021 | PANEL_POWER_UP_DELAY_SHIFT; |
| 5022 | |
| 5023 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
| 5024 | PANEL_LIGHT_ON_DELAY_SHIFT; |
| 5025 | |
| 5026 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
| 5027 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
| 5028 | |
| 5029 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
| 5030 | PANEL_POWER_DOWN_DELAY_SHIFT; |
| 5031 | |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5032 | if (IS_BROXTON(dev)) { |
| 5033 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
| 5034 | BXT_POWER_CYCLE_DELAY_SHIFT; |
| 5035 | if (tmp > 0) |
| 5036 | cur.t11_t12 = (tmp - 1) * 1000; |
| 5037 | else |
| 5038 | cur.t11_t12 = 0; |
| 5039 | } else { |
| 5040 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5041 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5042 | } |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5043 | |
| 5044 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 5045 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
| 5046 | |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 5047 | vbt = dev_priv->vbt.edp.pps; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5048 | |
| 5049 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
| 5050 | * our hw here, which are all in 100usec. */ |
| 5051 | spec.t1_t3 = 210 * 10; |
| 5052 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
| 5053 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
| 5054 | spec.t10 = 500 * 10; |
| 5055 | /* This one is special and actually in units of 100ms, but zero |
| 5056 | * based in the hw (so we need to add 100 ms). But the sw vbt |
| 5057 | * table multiplies it with 1000 to make it in units of 100usec, |
| 5058 | * too. */ |
| 5059 | spec.t11_t12 = (510 + 100) * 10; |
| 5060 | |
| 5061 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 5062 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
| 5063 | |
| 5064 | /* Use the max of the register settings and vbt. If both are |
| 5065 | * unset, fall back to the spec limits. */ |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5066 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5067 | spec.field : \ |
| 5068 | max(cur.field, vbt.field)) |
| 5069 | assign_final(t1_t3); |
| 5070 | assign_final(t8); |
| 5071 | assign_final(t9); |
| 5072 | assign_final(t10); |
| 5073 | assign_final(t11_t12); |
| 5074 | #undef assign_final |
| 5075 | |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5076 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5077 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
| 5078 | intel_dp->backlight_on_delay = get_delay(t8); |
| 5079 | intel_dp->backlight_off_delay = get_delay(t9); |
| 5080 | intel_dp->panel_power_down_delay = get_delay(t10); |
| 5081 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
| 5082 | #undef get_delay |
| 5083 | |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 5084 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
| 5085 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
| 5086 | intel_dp->panel_power_cycle_delay); |
| 5087 | |
| 5088 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
| 5089 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 5090 | } |
| 5091 | |
| 5092 | static void |
| 5093 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5094 | struct intel_dp *intel_dp) |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 5095 | { |
| 5096 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5097 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 5098 | int div = dev_priv->rawclk_freq / 1000; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5099 | i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg; |
Ville Syrjälä | ad933b5 | 2014-08-18 22:15:56 +0300 | [diff] [blame] | 5100 | enum port port = dp_to_dig_port(intel_dp)->port; |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5101 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5102 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 5103 | lockdep_assert_held(&dev_priv->pps_mutex); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5104 | |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5105 | if (IS_BROXTON(dev)) { |
| 5106 | /* |
| 5107 | * TODO: BXT has 2 sets of PPS registers. |
| 5108 | * Correct Register for Broxton need to be identified |
| 5109 | * using VBT. hardcoding for now |
| 5110 | */ |
| 5111 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
| 5112 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
| 5113 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
| 5114 | |
| 5115 | } else if (HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5116 | pp_on_reg = PCH_PP_ON_DELAYS; |
| 5117 | pp_off_reg = PCH_PP_OFF_DELAYS; |
| 5118 | pp_div_reg = PCH_PP_DIVISOR; |
| 5119 | } else { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 5120 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
| 5121 | |
| 5122 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
| 5123 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
| 5124 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5125 | } |
| 5126 | |
Paulo Zanoni | b2f19d1 | 2013-12-19 14:29:44 -0200 | [diff] [blame] | 5127 | /* |
| 5128 | * And finally store the new values in the power sequencer. The |
| 5129 | * backlight delays are set to 1 because we do manual waits on them. For |
| 5130 | * T8, even BSpec recommends doing it. For T9, if we don't do this, |
| 5131 | * we'll end up waiting for the backlight off delay twice: once when we |
| 5132 | * do the manual sleep, and once when we disable the panel and wait for |
| 5133 | * the PP_STATUS bit to become zero. |
| 5134 | */ |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 5135 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
Paulo Zanoni | b2f19d1 | 2013-12-19 14:29:44 -0200 | [diff] [blame] | 5136 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
| 5137 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 5138 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5139 | /* Compute the divisor for the pp clock, simply match the Bspec |
| 5140 | * formula. */ |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5141 | if (IS_BROXTON(dev)) { |
| 5142 | pp_div = I915_READ(pp_ctrl_reg); |
| 5143 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
| 5144 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) |
| 5145 | << BXT_POWER_CYCLE_DELAY_SHIFT); |
| 5146 | } else { |
| 5147 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
| 5148 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
| 5149 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
| 5150 | } |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5151 | |
| 5152 | /* Haswell doesn't have any port selection bits for the panel |
| 5153 | * power sequencer any more. */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5154 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | ad933b5 | 2014-08-18 22:15:56 +0300 | [diff] [blame] | 5155 | port_sel = PANEL_PORT_SELECT_VLV(port); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 5156 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
Ville Syrjälä | ad933b5 | 2014-08-18 22:15:56 +0300 | [diff] [blame] | 5157 | if (port == PORT_A) |
Jani Nikula | a24c144 | 2013-09-05 16:44:46 +0300 | [diff] [blame] | 5158 | port_sel = PANEL_PORT_SELECT_DPA; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5159 | else |
Jani Nikula | a24c144 | 2013-09-05 16:44:46 +0300 | [diff] [blame] | 5160 | port_sel = PANEL_PORT_SELECT_DPD; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5161 | } |
| 5162 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5163 | pp_on |= port_sel; |
| 5164 | |
| 5165 | I915_WRITE(pp_on_reg, pp_on); |
| 5166 | I915_WRITE(pp_off_reg, pp_off); |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5167 | if (IS_BROXTON(dev)) |
| 5168 | I915_WRITE(pp_ctrl_reg, pp_div); |
| 5169 | else |
| 5170 | I915_WRITE(pp_div_reg, pp_div); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5171 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5172 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5173 | I915_READ(pp_on_reg), |
| 5174 | I915_READ(pp_off_reg), |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5175 | IS_BROXTON(dev) ? |
| 5176 | (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) : |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5177 | I915_READ(pp_div_reg)); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 5178 | } |
| 5179 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5180 | /** |
| 5181 | * intel_dp_set_drrs_state - program registers for RR switch to take effect |
| 5182 | * @dev: DRM device |
| 5183 | * @refresh_rate: RR to be programmed |
| 5184 | * |
| 5185 | * This function gets called when refresh rate (RR) has to be changed from |
| 5186 | * one frequency to another. Switches can be between high and low RR |
| 5187 | * supported by the panel or to any other RR based on media playback (in |
| 5188 | * this case, RR value needs to be passed from user space). |
| 5189 | * |
| 5190 | * The caller of this function needs to take a lock on dev_priv->drrs. |
| 5191 | */ |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5192 | static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5193 | { |
| 5194 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5195 | struct intel_encoder *encoder; |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5196 | struct intel_digital_port *dig_port = NULL; |
| 5197 | struct intel_dp *intel_dp = dev_priv->drrs.dp; |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 5198 | struct intel_crtc_state *config = NULL; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5199 | struct intel_crtc *intel_crtc = NULL; |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5200 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5201 | |
| 5202 | if (refresh_rate <= 0) { |
| 5203 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); |
| 5204 | return; |
| 5205 | } |
| 5206 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5207 | if (intel_dp == NULL) { |
| 5208 | DRM_DEBUG_KMS("DRRS not supported.\n"); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5209 | return; |
| 5210 | } |
| 5211 | |
Daniel Vetter | 1fcc9d1 | 2014-07-11 10:30:10 -0700 | [diff] [blame] | 5212 | /* |
Rodrigo Vivi | e4d59f6 | 2014-11-20 02:22:08 -0800 | [diff] [blame] | 5213 | * FIXME: This needs proper synchronization with psr state for some |
| 5214 | * platforms that cannot have PSR and DRRS enabled at the same time. |
Daniel Vetter | 1fcc9d1 | 2014-07-11 10:30:10 -0700 | [diff] [blame] | 5215 | */ |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5216 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5217 | dig_port = dp_to_dig_port(intel_dp); |
| 5218 | encoder = &dig_port->base; |
Ander Conselvan de Oliveira | 723f9aa | 2015-03-20 16:18:18 +0200 | [diff] [blame] | 5219 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5220 | |
| 5221 | if (!intel_crtc) { |
| 5222 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); |
| 5223 | return; |
| 5224 | } |
| 5225 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5226 | config = intel_crtc->config; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5227 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5228 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5229 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
| 5230 | return; |
| 5231 | } |
| 5232 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5233 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
| 5234 | refresh_rate) |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5235 | index = DRRS_LOW_RR; |
| 5236 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5237 | if (index == dev_priv->drrs.refresh_rate_type) { |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5238 | DRM_DEBUG_KMS( |
| 5239 | "DRRS requested for previously set RR...ignoring\n"); |
| 5240 | return; |
| 5241 | } |
| 5242 | |
| 5243 | if (!intel_crtc->active) { |
| 5244 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
| 5245 | return; |
| 5246 | } |
| 5247 | |
Durgadoss R | 44395bf | 2015-02-13 15:33:02 +0530 | [diff] [blame] | 5248 | if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { |
Vandana Kannan | a4c30b1 | 2015-02-13 15:33:00 +0530 | [diff] [blame] | 5249 | switch (index) { |
| 5250 | case DRRS_HIGH_RR: |
| 5251 | intel_dp_set_m_n(intel_crtc, M1_N1); |
| 5252 | break; |
| 5253 | case DRRS_LOW_RR: |
| 5254 | intel_dp_set_m_n(intel_crtc, M2_N2); |
| 5255 | break; |
| 5256 | case DRRS_MAX_RR: |
| 5257 | default: |
| 5258 | DRM_ERROR("Unsupported refreshrate type\n"); |
| 5259 | } |
| 5260 | } else if (INTEL_INFO(dev)->gen > 6) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5261 | i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 5262 | u32 val; |
Vandana Kannan | a4c30b1 | 2015-02-13 15:33:00 +0530 | [diff] [blame] | 5263 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 5264 | val = I915_READ(reg); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5265 | if (index > DRRS_HIGH_RR) { |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5266 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Vandana Kannan | 6fa7aec | 2015-02-13 15:33:01 +0530 | [diff] [blame] | 5267 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
| 5268 | else |
| 5269 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5270 | } else { |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5271 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Vandana Kannan | 6fa7aec | 2015-02-13 15:33:01 +0530 | [diff] [blame] | 5272 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
| 5273 | else |
| 5274 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5275 | } |
| 5276 | I915_WRITE(reg, val); |
| 5277 | } |
| 5278 | |
Vandana Kannan | 4e9ac94 | 2015-01-22 15:14:45 +0530 | [diff] [blame] | 5279 | dev_priv->drrs.refresh_rate_type = index; |
| 5280 | |
| 5281 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); |
| 5282 | } |
| 5283 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5284 | /** |
| 5285 | * intel_edp_drrs_enable - init drrs struct if supported |
| 5286 | * @intel_dp: DP struct |
| 5287 | * |
| 5288 | * Initializes frontbuffer_bits and drrs.dp |
| 5289 | */ |
Vandana Kannan | c395578 | 2015-01-22 15:17:40 +0530 | [diff] [blame] | 5290 | void intel_edp_drrs_enable(struct intel_dp *intel_dp) |
| 5291 | { |
| 5292 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 5293 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5294 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 5295 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
| 5296 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5297 | |
| 5298 | if (!intel_crtc->config->has_drrs) { |
| 5299 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
| 5300 | return; |
| 5301 | } |
| 5302 | |
| 5303 | mutex_lock(&dev_priv->drrs.mutex); |
| 5304 | if (WARN_ON(dev_priv->drrs.dp)) { |
| 5305 | DRM_ERROR("DRRS already enabled\n"); |
| 5306 | goto unlock; |
| 5307 | } |
| 5308 | |
| 5309 | dev_priv->drrs.busy_frontbuffer_bits = 0; |
| 5310 | |
| 5311 | dev_priv->drrs.dp = intel_dp; |
| 5312 | |
| 5313 | unlock: |
| 5314 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5315 | } |
| 5316 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5317 | /** |
| 5318 | * intel_edp_drrs_disable - Disable DRRS |
| 5319 | * @intel_dp: DP struct |
| 5320 | * |
| 5321 | */ |
Vandana Kannan | c395578 | 2015-01-22 15:17:40 +0530 | [diff] [blame] | 5322 | void intel_edp_drrs_disable(struct intel_dp *intel_dp) |
| 5323 | { |
| 5324 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 5325 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5326 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 5327 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
| 5328 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5329 | |
| 5330 | if (!intel_crtc->config->has_drrs) |
| 5331 | return; |
| 5332 | |
| 5333 | mutex_lock(&dev_priv->drrs.mutex); |
| 5334 | if (!dev_priv->drrs.dp) { |
| 5335 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5336 | return; |
| 5337 | } |
| 5338 | |
| 5339 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
| 5340 | intel_dp_set_drrs_state(dev_priv->dev, |
| 5341 | intel_dp->attached_connector->panel. |
| 5342 | fixed_mode->vrefresh); |
| 5343 | |
| 5344 | dev_priv->drrs.dp = NULL; |
| 5345 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5346 | |
| 5347 | cancel_delayed_work_sync(&dev_priv->drrs.work); |
| 5348 | } |
| 5349 | |
Vandana Kannan | 4e9ac94 | 2015-01-22 15:14:45 +0530 | [diff] [blame] | 5350 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
| 5351 | { |
| 5352 | struct drm_i915_private *dev_priv = |
| 5353 | container_of(work, typeof(*dev_priv), drrs.work.work); |
| 5354 | struct intel_dp *intel_dp; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5355 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5356 | mutex_lock(&dev_priv->drrs.mutex); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5357 | |
Vandana Kannan | 4e9ac94 | 2015-01-22 15:14:45 +0530 | [diff] [blame] | 5358 | intel_dp = dev_priv->drrs.dp; |
| 5359 | |
| 5360 | if (!intel_dp) |
| 5361 | goto unlock; |
| 5362 | |
| 5363 | /* |
| 5364 | * The delayed work can race with an invalidate hence we need to |
| 5365 | * recheck. |
| 5366 | */ |
| 5367 | |
| 5368 | if (dev_priv->drrs.busy_frontbuffer_bits) |
| 5369 | goto unlock; |
| 5370 | |
| 5371 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) |
| 5372 | intel_dp_set_drrs_state(dev_priv->dev, |
| 5373 | intel_dp->attached_connector->panel. |
| 5374 | downclock_mode->vrefresh); |
| 5375 | |
| 5376 | unlock: |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5377 | mutex_unlock(&dev_priv->drrs.mutex); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5378 | } |
| 5379 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5380 | /** |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5381 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5382 | * @dev: DRM device |
| 5383 | * @frontbuffer_bits: frontbuffer plane tracking bits |
| 5384 | * |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5385 | * This function gets called everytime rendering on the given planes start. |
| 5386 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5387 | * |
| 5388 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
| 5389 | */ |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5390 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
| 5391 | unsigned frontbuffer_bits) |
| 5392 | { |
| 5393 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5394 | struct drm_crtc *crtc; |
| 5395 | enum pipe pipe; |
| 5396 | |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5397 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5398 | return; |
| 5399 | |
Daniel Vetter | 88f933a | 2015-04-09 16:44:16 +0200 | [diff] [blame] | 5400 | cancel_delayed_work(&dev_priv->drrs.work); |
Ramalingam C | 3954e73 | 2015-03-03 12:11:46 +0530 | [diff] [blame] | 5401 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5402 | mutex_lock(&dev_priv->drrs.mutex); |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5403 | if (!dev_priv->drrs.dp) { |
| 5404 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5405 | return; |
| 5406 | } |
| 5407 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5408 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
| 5409 | pipe = to_intel_crtc(crtc)->pipe; |
| 5410 | |
Daniel Vetter | c1d038c | 2015-06-18 10:30:25 +0200 | [diff] [blame] | 5411 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
| 5412 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; |
| 5413 | |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5414 | /* invalidate means busy screen hence upclock */ |
Daniel Vetter | c1d038c | 2015-06-18 10:30:25 +0200 | [diff] [blame] | 5415 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5416 | intel_dp_set_drrs_state(dev_priv->dev, |
| 5417 | dev_priv->drrs.dp->attached_connector->panel. |
| 5418 | fixed_mode->vrefresh); |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5419 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5420 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5421 | } |
| 5422 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5423 | /** |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5424 | * intel_edp_drrs_flush - Restart Idleness DRRS |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5425 | * @dev: DRM device |
| 5426 | * @frontbuffer_bits: frontbuffer plane tracking bits |
| 5427 | * |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5428 | * This function gets called every time rendering on the given planes has |
| 5429 | * completed or flip on a crtc is completed. So DRRS should be upclocked |
| 5430 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, |
| 5431 | * if no other planes are dirty. |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5432 | * |
| 5433 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
| 5434 | */ |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5435 | void intel_edp_drrs_flush(struct drm_device *dev, |
| 5436 | unsigned frontbuffer_bits) |
| 5437 | { |
| 5438 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5439 | struct drm_crtc *crtc; |
| 5440 | enum pipe pipe; |
| 5441 | |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5442 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5443 | return; |
| 5444 | |
Daniel Vetter | 88f933a | 2015-04-09 16:44:16 +0200 | [diff] [blame] | 5445 | cancel_delayed_work(&dev_priv->drrs.work); |
Ramalingam C | 3954e73 | 2015-03-03 12:11:46 +0530 | [diff] [blame] | 5446 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5447 | mutex_lock(&dev_priv->drrs.mutex); |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5448 | if (!dev_priv->drrs.dp) { |
| 5449 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5450 | return; |
| 5451 | } |
| 5452 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5453 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
| 5454 | pipe = to_intel_crtc(crtc)->pipe; |
Daniel Vetter | c1d038c | 2015-06-18 10:30:25 +0200 | [diff] [blame] | 5455 | |
| 5456 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5457 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
| 5458 | |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5459 | /* flush means busy screen hence upclock */ |
Daniel Vetter | c1d038c | 2015-06-18 10:30:25 +0200 | [diff] [blame] | 5460 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5461 | intel_dp_set_drrs_state(dev_priv->dev, |
| 5462 | dev_priv->drrs.dp->attached_connector->panel. |
| 5463 | fixed_mode->vrefresh); |
| 5464 | |
| 5465 | /* |
| 5466 | * flush also means no more activity hence schedule downclock, if all |
| 5467 | * other fbs are quiescent too |
| 5468 | */ |
| 5469 | if (!dev_priv->drrs.busy_frontbuffer_bits) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5470 | schedule_delayed_work(&dev_priv->drrs.work, |
| 5471 | msecs_to_jiffies(1000)); |
| 5472 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5473 | } |
| 5474 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5475 | /** |
| 5476 | * DOC: Display Refresh Rate Switching (DRRS) |
| 5477 | * |
| 5478 | * Display Refresh Rate Switching (DRRS) is a power conservation feature |
| 5479 | * which enables swtching between low and high refresh rates, |
| 5480 | * dynamically, based on the usage scenario. This feature is applicable |
| 5481 | * for internal panels. |
| 5482 | * |
| 5483 | * Indication that the panel supports DRRS is given by the panel EDID, which |
| 5484 | * would list multiple refresh rates for one resolution. |
| 5485 | * |
| 5486 | * DRRS is of 2 types - static and seamless. |
| 5487 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset |
| 5488 | * (may appear as a blink on screen) and is used in dock-undock scenario. |
| 5489 | * Seamless DRRS involves changing RR without any visual effect to the user |
| 5490 | * and can be used during normal system usage. This is done by programming |
| 5491 | * certain registers. |
| 5492 | * |
| 5493 | * Support for static/seamless DRRS may be indicated in the VBT based on |
| 5494 | * inputs from the panel spec. |
| 5495 | * |
| 5496 | * DRRS saves power by switching to low RR based on usage scenarios. |
| 5497 | * |
| 5498 | * eDP DRRS:- |
| 5499 | * The implementation is based on frontbuffer tracking implementation. |
| 5500 | * When there is a disturbance on the screen triggered by user activity or a |
| 5501 | * periodic system activity, DRRS is disabled (RR is changed to high RR). |
| 5502 | * When there is no movement on screen, after a timeout of 1 second, a switch |
| 5503 | * to low RR is made. |
| 5504 | * For integration with frontbuffer tracking code, |
| 5505 | * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called. |
| 5506 | * |
| 5507 | * DRRS can be further extended to support other internal panels and also |
| 5508 | * the scenario of video playback wherein RR is set based on the rate |
| 5509 | * requested by userspace. |
| 5510 | */ |
| 5511 | |
| 5512 | /** |
| 5513 | * intel_dp_drrs_init - Init basic DRRS work and mutex. |
| 5514 | * @intel_connector: eDP connector |
| 5515 | * @fixed_mode: preferred mode of panel |
| 5516 | * |
| 5517 | * This function is called only once at driver load to initialize basic |
| 5518 | * DRRS stuff. |
| 5519 | * |
| 5520 | * Returns: |
| 5521 | * Downclock mode if panel supports it, else return NULL. |
| 5522 | * DRRS support is determined by the presence of downclock mode (apart |
| 5523 | * from VBT setting). |
| 5524 | */ |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5525 | static struct drm_display_mode * |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5526 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
| 5527 | struct drm_display_mode *fixed_mode) |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5528 | { |
| 5529 | struct drm_connector *connector = &intel_connector->base; |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5530 | struct drm_device *dev = connector->dev; |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5531 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5532 | struct drm_display_mode *downclock_mode = NULL; |
| 5533 | |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5534 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
| 5535 | mutex_init(&dev_priv->drrs.mutex); |
| 5536 | |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5537 | if (INTEL_INFO(dev)->gen <= 6) { |
| 5538 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
| 5539 | return NULL; |
| 5540 | } |
| 5541 | |
| 5542 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
Damien Lespiau | 4079b8d | 2014-08-05 10:39:42 +0100 | [diff] [blame] | 5543 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5544 | return NULL; |
| 5545 | } |
| 5546 | |
| 5547 | downclock_mode = intel_find_panel_downclock |
| 5548 | (dev, fixed_mode, connector); |
| 5549 | |
| 5550 | if (!downclock_mode) { |
Ramalingam C | a1d2634 | 2015-02-23 17:38:33 +0530 | [diff] [blame] | 5551 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5552 | return NULL; |
| 5553 | } |
| 5554 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5555 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5556 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5557 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
Damien Lespiau | 4079b8d | 2014-08-05 10:39:42 +0100 | [diff] [blame] | 5558 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5559 | return downclock_mode; |
| 5560 | } |
| 5561 | |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5562 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5563 | struct intel_connector *intel_connector) |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5564 | { |
| 5565 | struct drm_connector *connector = &intel_connector->base; |
| 5566 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Paulo Zanoni | 6363521 | 2014-04-22 19:55:42 -0300 | [diff] [blame] | 5567 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 5568 | struct drm_device *dev = intel_encoder->base.dev; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5569 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5570 | struct drm_display_mode *fixed_mode = NULL; |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5571 | struct drm_display_mode *downclock_mode = NULL; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5572 | bool has_dpcd; |
| 5573 | struct drm_display_mode *scan; |
| 5574 | struct edid *edid; |
Ville Syrjälä | 6517d27 | 2014-11-07 11:16:02 +0200 | [diff] [blame] | 5575 | enum pipe pipe = INVALID_PIPE; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5576 | |
| 5577 | if (!is_edp(intel_dp)) |
| 5578 | return true; |
| 5579 | |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 5580 | pps_lock(intel_dp); |
| 5581 | intel_edp_panel_vdd_sanitize(intel_dp); |
| 5582 | pps_unlock(intel_dp); |
Paulo Zanoni | 6363521 | 2014-04-22 19:55:42 -0300 | [diff] [blame] | 5583 | |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5584 | /* Cache DPCD and EDID for edp. */ |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5585 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5586 | |
| 5587 | if (has_dpcd) { |
| 5588 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
| 5589 | dev_priv->no_aux_handshake = |
| 5590 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
| 5591 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
| 5592 | } else { |
| 5593 | /* if this fails, presume the device is a ghost */ |
| 5594 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5595 | return false; |
| 5596 | } |
| 5597 | |
| 5598 | /* We now know it's not a ghost, init power sequence regs. */ |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 5599 | pps_lock(intel_dp); |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5600 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 5601 | pps_unlock(intel_dp); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5602 | |
Daniel Vetter | 060c877 | 2014-03-21 23:22:35 +0100 | [diff] [blame] | 5603 | mutex_lock(&dev->mode_config.mutex); |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 5604 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5605 | if (edid) { |
| 5606 | if (drm_add_edid_modes(connector, edid)) { |
| 5607 | drm_mode_connector_update_edid_property(connector, |
| 5608 | edid); |
| 5609 | drm_edid_to_eld(connector, edid); |
| 5610 | } else { |
| 5611 | kfree(edid); |
| 5612 | edid = ERR_PTR(-EINVAL); |
| 5613 | } |
| 5614 | } else { |
| 5615 | edid = ERR_PTR(-ENOENT); |
| 5616 | } |
| 5617 | intel_connector->edid = edid; |
| 5618 | |
| 5619 | /* prefer fixed mode from EDID if available */ |
| 5620 | list_for_each_entry(scan, &connector->probed_modes, head) { |
| 5621 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
| 5622 | fixed_mode = drm_mode_duplicate(dev, scan); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5623 | downclock_mode = intel_dp_drrs_init( |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5624 | intel_connector, fixed_mode); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5625 | break; |
| 5626 | } |
| 5627 | } |
| 5628 | |
| 5629 | /* fallback to VBT if available for eDP */ |
| 5630 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
| 5631 | fixed_mode = drm_mode_duplicate(dev, |
| 5632 | dev_priv->vbt.lfp_lvds_vbt_mode); |
| 5633 | if (fixed_mode) |
| 5634 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
| 5635 | } |
Daniel Vetter | 060c877 | 2014-03-21 23:22:35 +0100 | [diff] [blame] | 5636 | mutex_unlock(&dev->mode_config.mutex); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5637 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5638 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 5639 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
| 5640 | register_reboot_notifier(&intel_dp->edp_notifier); |
Ville Syrjälä | 6517d27 | 2014-11-07 11:16:02 +0200 | [diff] [blame] | 5641 | |
| 5642 | /* |
| 5643 | * Figure out the current pipe for the initial backlight setup. |
| 5644 | * If the current pipe isn't valid, try the PPS pipe, and if that |
| 5645 | * fails just assume pipe A. |
| 5646 | */ |
| 5647 | if (IS_CHERRYVIEW(dev)) |
| 5648 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); |
| 5649 | else |
| 5650 | pipe = PORT_TO_PIPE(intel_dp->DP); |
| 5651 | |
| 5652 | if (pipe != PIPE_A && pipe != PIPE_B) |
| 5653 | pipe = intel_dp->pps_pipe; |
| 5654 | |
| 5655 | if (pipe != PIPE_A && pipe != PIPE_B) |
| 5656 | pipe = PIPE_A; |
| 5657 | |
| 5658 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", |
| 5659 | pipe_name(pipe)); |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 5660 | } |
| 5661 | |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5662 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
Jani Nikula | 5507fae | 2015-09-14 14:03:48 +0300 | [diff] [blame] | 5663 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
Ville Syrjälä | 6517d27 | 2014-11-07 11:16:02 +0200 | [diff] [blame] | 5664 | intel_panel_setup_backlight(connector, pipe); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5665 | |
| 5666 | return true; |
| 5667 | } |
| 5668 | |
Paulo Zanoni | 16c2553 | 2013-06-12 17:27:25 -0300 | [diff] [blame] | 5669 | bool |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5670 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| 5671 | struct intel_connector *intel_connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5672 | { |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5673 | struct drm_connector *connector = &intel_connector->base; |
| 5674 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 5675 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 5676 | struct drm_device *dev = intel_encoder->base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5677 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 5678 | enum port port = intel_dig_port->port; |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 5679 | int type, ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5680 | |
Ville Syrjälä | ccb1a83 | 2015-12-08 19:59:38 +0200 | [diff] [blame] | 5681 | if (WARN(intel_dig_port->max_lanes < 1, |
| 5682 | "Not enough lanes (%d) for DP on port %c\n", |
| 5683 | intel_dig_port->max_lanes, port_name(port))) |
| 5684 | return false; |
| 5685 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 5686 | intel_dp->pps_pipe = INVALID_PIPE; |
| 5687 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 5688 | /* intel_dp vfuncs */ |
Damien Lespiau | b6b5e38 | 2014-01-20 16:00:59 +0000 | [diff] [blame] | 5689 | if (INTEL_INFO(dev)->gen >= 9) |
| 5690 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 5691 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 5692 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
| 5693 | else if (HAS_PCH_SPLIT(dev)) |
| 5694 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
| 5695 | else |
Ville Syrjälä | 6ffb1be | 2016-03-02 17:22:14 +0200 | [diff] [blame] | 5696 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 5697 | |
Damien Lespiau | b9ca5fa | 2014-01-20 16:01:00 +0000 | [diff] [blame] | 5698 | if (INTEL_INFO(dev)->gen >= 9) |
| 5699 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
| 5700 | else |
Ville Syrjälä | 6ffb1be | 2016-03-02 17:22:14 +0200 | [diff] [blame] | 5701 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; |
Damien Lespiau | 153b110 | 2014-01-21 13:37:15 +0000 | [diff] [blame] | 5702 | |
Ander Conselvan de Oliveira | ad64217 | 2015-10-23 13:01:49 +0300 | [diff] [blame] | 5703 | if (HAS_DDI(dev)) |
| 5704 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; |
| 5705 | |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 5706 | /* Preserve the current hw state. */ |
| 5707 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 5708 | intel_dp->attached_connector = intel_connector; |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 5709 | |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 5710 | if (intel_dp_is_edp(dev, port)) |
Gajanan Bhat | 19c0392 | 2012-09-27 19:13:07 +0530 | [diff] [blame] | 5711 | type = DRM_MODE_CONNECTOR_eDP; |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 5712 | else |
| 5713 | type = DRM_MODE_CONNECTOR_DisplayPort; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 5714 | |
Imre Deak | f7d2490 | 2013-05-08 13:14:05 +0300 | [diff] [blame] | 5715 | /* |
| 5716 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
| 5717 | * for DP the encoder type can be set by the caller to |
| 5718 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
| 5719 | */ |
| 5720 | if (type == DRM_MODE_CONNECTOR_eDP) |
| 5721 | intel_encoder->type = INTEL_OUTPUT_EDP; |
| 5722 | |
Ville Syrjälä | c17ed5b | 2014-10-16 21:27:27 +0300 | [diff] [blame] | 5723 | /* eDP only on port B and/or C on vlv/chv */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5724 | if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
| 5725 | is_edp(intel_dp) && port != PORT_B && port != PORT_C)) |
Ville Syrjälä | c17ed5b | 2014-10-16 21:27:27 +0300 | [diff] [blame] | 5726 | return false; |
| 5727 | |
Imre Deak | e7281ea | 2013-05-08 13:14:08 +0300 | [diff] [blame] | 5728 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
| 5729 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
| 5730 | port_name(port)); |
| 5731 | |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 5732 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5733 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
| 5734 | |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5735 | connector->interlace_allowed = true; |
| 5736 | connector->doublescan_allowed = 0; |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 5737 | |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 5738 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 5739 | edp_panel_vdd_work); |
Zhenyu Wang | 6251ec0 | 2010-01-12 05:38:32 +0800 | [diff] [blame] | 5740 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 5741 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
Thomas Wood | 34ea3d3 | 2014-05-29 16:57:41 +0100 | [diff] [blame] | 5742 | drm_connector_register(connector); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5743 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 5744 | if (HAS_DDI(dev)) |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 5745 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
| 5746 | else |
| 5747 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
Imre Deak | 80f65de | 2014-02-11 17:12:49 +0200 | [diff] [blame] | 5748 | intel_connector->unregister = intel_dp_connector_unregister; |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 5749 | |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 5750 | /* Set up the hotplug pin. */ |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5751 | switch (port) { |
| 5752 | case PORT_A: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 5753 | intel_encoder->hpd_pin = HPD_PORT_A; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5754 | break; |
| 5755 | case PORT_B: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 5756 | intel_encoder->hpd_pin = HPD_PORT_B; |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 5757 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
Sonika Jindal | cf1d588 | 2015-08-10 10:35:36 +0530 | [diff] [blame] | 5758 | intel_encoder->hpd_pin = HPD_PORT_A; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5759 | break; |
| 5760 | case PORT_C: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 5761 | intel_encoder->hpd_pin = HPD_PORT_C; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5762 | break; |
| 5763 | case PORT_D: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 5764 | intel_encoder->hpd_pin = HPD_PORT_D; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5765 | break; |
Xiong Zhang | 26951ca | 2015-08-17 15:55:50 +0800 | [diff] [blame] | 5766 | case PORT_E: |
| 5767 | intel_encoder->hpd_pin = HPD_PORT_E; |
| 5768 | break; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5769 | default: |
Damien Lespiau | ad1c0b1 | 2013-03-07 15:30:28 +0000 | [diff] [blame] | 5770 | BUG(); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 5771 | } |
| 5772 | |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 5773 | if (is_edp(intel_dp)) { |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 5774 | pps_lock(intel_dp); |
Ville Syrjälä | 1e74a32 | 2014-10-28 16:15:51 +0200 | [diff] [blame] | 5775 | intel_dp_init_panel_power_timestamps(intel_dp); |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5776 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 5777 | vlv_initial_power_sequencer_setup(intel_dp); |
Ville Syrjälä | 1e74a32 | 2014-10-28 16:15:51 +0200 | [diff] [blame] | 5778 | else |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5779 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 5780 | pps_unlock(intel_dp); |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 5781 | } |
Paulo Zanoni | 0095e6d | 2013-12-19 14:29:39 -0200 | [diff] [blame] | 5782 | |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 5783 | ret = intel_dp_aux_init(intel_dp, intel_connector); |
| 5784 | if (ret) |
| 5785 | goto fail; |
Dave Airlie | c1f0526 | 2012-08-30 11:06:18 +1000 | [diff] [blame] | 5786 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5787 | /* init MST on ports that can support it */ |
Jani Nikula | 0c9b371 | 2015-05-18 17:10:01 +0300 | [diff] [blame] | 5788 | if (HAS_DP_MST(dev) && |
| 5789 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
| 5790 | intel_dp_mst_encoder_init(intel_dig_port, |
| 5791 | intel_connector->base.base.id); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5792 | |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5793 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 5794 | intel_dp_aux_fini(intel_dp); |
| 5795 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
| 5796 | goto fail; |
Paulo Zanoni | b2f246a | 2013-06-12 17:27:26 -0300 | [diff] [blame] | 5797 | } |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 5798 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 5799 | intel_dp_add_properties(intel_dp, connector); |
| 5800 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5801 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
| 5802 | * 0xd. Failure to do so will result in spurious interrupts being |
| 5803 | * generated on the port when a cable is not attached. |
| 5804 | */ |
| 5805 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
| 5806 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
| 5807 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
| 5808 | } |
Paulo Zanoni | 16c2553 | 2013-06-12 17:27:25 -0300 | [diff] [blame] | 5809 | |
Jani Nikula | aa7471d | 2015-04-01 11:15:21 +0300 | [diff] [blame] | 5810 | i915_debugfs_connector_add(connector); |
| 5811 | |
Paulo Zanoni | 16c2553 | 2013-06-12 17:27:25 -0300 | [diff] [blame] | 5812 | return true; |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 5813 | |
| 5814 | fail: |
| 5815 | if (is_edp(intel_dp)) { |
| 5816 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
| 5817 | /* |
| 5818 | * vdd might still be enabled do to the delayed vdd off. |
| 5819 | * Make sure vdd is actually turned off here. |
| 5820 | */ |
| 5821 | pps_lock(intel_dp); |
| 5822 | edp_panel_vdd_off_sync(intel_dp); |
| 5823 | pps_unlock(intel_dp); |
| 5824 | } |
| 5825 | drm_connector_unregister(connector); |
| 5826 | drm_connector_cleanup(connector); |
| 5827 | |
| 5828 | return false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5829 | } |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5830 | |
| 5831 | void |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5832 | intel_dp_init(struct drm_device *dev, |
| 5833 | i915_reg_t output_reg, enum port port) |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5834 | { |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 5835 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5836 | struct intel_digital_port *intel_dig_port; |
| 5837 | struct intel_encoder *intel_encoder; |
| 5838 | struct drm_encoder *encoder; |
| 5839 | struct intel_connector *intel_connector; |
| 5840 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 5841 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5842 | if (!intel_dig_port) |
| 5843 | return; |
| 5844 | |
Ander Conselvan de Oliveira | 08d9bc9 | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 5845 | intel_connector = intel_connector_alloc(); |
Sudip Mukherjee | 11aee0f | 2015-10-08 19:27:59 +0530 | [diff] [blame] | 5846 | if (!intel_connector) |
| 5847 | goto err_connector_alloc; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5848 | |
| 5849 | intel_encoder = &intel_dig_port->base; |
| 5850 | encoder = &intel_encoder->base; |
| 5851 | |
Sudip Mukherjee | 893da0c | 2015-10-08 19:28:00 +0530 | [diff] [blame] | 5852 | if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
Dave Airlie | ade1ba7 | 2015-12-23 14:22:09 +1000 | [diff] [blame] | 5853 | DRM_MODE_ENCODER_TMDS, NULL)) |
Sudip Mukherjee | 893da0c | 2015-10-08 19:28:00 +0530 | [diff] [blame] | 5854 | goto err_encoder_init; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5855 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 5856 | intel_encoder->compute_config = intel_dp_compute_config; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 5857 | intel_encoder->disable = intel_disable_dp; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 5858 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 5859 | intel_encoder->get_config = intel_dp_get_config; |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 5860 | intel_encoder->suspend = intel_dp_encoder_suspend; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 5861 | if (IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 5862 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 5863 | intel_encoder->pre_enable = chv_pre_enable_dp; |
| 5864 | intel_encoder->enable = vlv_enable_dp; |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 5865 | intel_encoder->post_disable = chv_post_disable_dp; |
Ville Syrjälä | d6db995 | 2015-07-08 23:45:49 +0300 | [diff] [blame] | 5866 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 5867 | } else if (IS_VALLEYVIEW(dev)) { |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 5868 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 5869 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
| 5870 | intel_encoder->enable = vlv_enable_dp; |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 5871 | intel_encoder->post_disable = vlv_post_disable_dp; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 5872 | } else { |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 5873 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
| 5874 | intel_encoder->enable = g4x_enable_dp; |
Ville Syrjälä | 08aff3f | 2014-08-18 22:16:09 +0300 | [diff] [blame] | 5875 | if (INTEL_INFO(dev)->gen >= 5) |
| 5876 | intel_encoder->post_disable = ilk_post_disable_dp; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 5877 | } |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5878 | |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 5879 | intel_dig_port->port = port; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5880 | intel_dig_port->dp.output_reg = output_reg; |
Ville Syrjälä | ccb1a83 | 2015-12-08 19:59:38 +0200 | [diff] [blame] | 5881 | intel_dig_port->max_lanes = 4; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5882 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 5883 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
Ville Syrjälä | 882ec38 | 2014-04-28 14:07:43 +0300 | [diff] [blame] | 5884 | if (IS_CHERRYVIEW(dev)) { |
| 5885 | if (port == PORT_D) |
| 5886 | intel_encoder->crtc_mask = 1 << 2; |
| 5887 | else |
| 5888 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
| 5889 | } else { |
| 5890 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
| 5891 | } |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 5892 | intel_encoder->cloneable = 0; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5893 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 5894 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
Jani Nikula | 5fcece8 | 2015-05-27 15:03:42 +0300 | [diff] [blame] | 5895 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 5896 | |
Sudip Mukherjee | 11aee0f | 2015-10-08 19:27:59 +0530 | [diff] [blame] | 5897 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
| 5898 | goto err_init_connector; |
| 5899 | |
| 5900 | return; |
| 5901 | |
| 5902 | err_init_connector: |
| 5903 | drm_encoder_cleanup(encoder); |
Sudip Mukherjee | 893da0c | 2015-10-08 19:28:00 +0530 | [diff] [blame] | 5904 | err_encoder_init: |
Sudip Mukherjee | 11aee0f | 2015-10-08 19:27:59 +0530 | [diff] [blame] | 5905 | kfree(intel_connector); |
| 5906 | err_connector_alloc: |
| 5907 | kfree(intel_dig_port); |
| 5908 | |
| 5909 | return; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5910 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5911 | |
| 5912 | void intel_dp_mst_suspend(struct drm_device *dev) |
| 5913 | { |
| 5914 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5915 | int i; |
| 5916 | |
| 5917 | /* disable MST */ |
| 5918 | for (i = 0; i < I915_MAX_PORTS; i++) { |
Jani Nikula | 5fcece8 | 2015-05-27 15:03:42 +0300 | [diff] [blame] | 5919 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5920 | if (!intel_dig_port) |
| 5921 | continue; |
| 5922 | |
| 5923 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
| 5924 | if (!intel_dig_port->dp.can_mst) |
| 5925 | continue; |
| 5926 | if (intel_dig_port->dp.is_mst) |
| 5927 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); |
| 5928 | } |
| 5929 | } |
| 5930 | } |
| 5931 | |
| 5932 | void intel_dp_mst_resume(struct drm_device *dev) |
| 5933 | { |
| 5934 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5935 | int i; |
| 5936 | |
| 5937 | for (i = 0; i < I915_MAX_PORTS; i++) { |
Jani Nikula | 5fcece8 | 2015-05-27 15:03:42 +0300 | [diff] [blame] | 5938 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5939 | if (!intel_dig_port) |
| 5940 | continue; |
| 5941 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
| 5942 | int ret; |
| 5943 | |
| 5944 | if (!intel_dig_port->dp.can_mst) |
| 5945 | continue; |
| 5946 | |
| 5947 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
| 5948 | if (ret != 0) { |
| 5949 | intel_dp_check_mst_status(&intel_dig_port->dp); |
| 5950 | } |
| 5951 | } |
| 5952 | } |
| 5953 | } |