Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | #include <linux/hdmi.h> |
| 24 | #include <drm/drmP.h> |
| 25 | #include "radeon.h" |
Slava Grigorev | 1a626b6 | 2014-12-01 13:49:39 -0500 | [diff] [blame] | 26 | #include "radeon_audio.h" |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 27 | #include "sid.h" |
| 28 | |
Slava Grigorev | 2afa326 | 2015-03-02 12:05:29 -0500 | [diff] [blame] | 29 | #define DCE8_DCCG_AUDIO_DTO1_PHASE 0x05b8 |
| 30 | #define DCE8_DCCG_AUDIO_DTO1_MODULE 0x05bc |
| 31 | |
Slava Grigorev | 1a626b6 | 2014-12-01 13:49:39 -0500 | [diff] [blame] | 32 | u32 dce6_endpoint_rreg(struct radeon_device *rdev, |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 33 | u32 block_offset, u32 reg) |
| 34 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 35 | unsigned long flags; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 36 | u32 r; |
| 37 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 38 | spin_lock_irqsave(&rdev->end_idx_lock, flags); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 39 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); |
| 40 | r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 41 | spin_unlock_irqrestore(&rdev->end_idx_lock, flags); |
| 42 | |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 43 | return r; |
| 44 | } |
| 45 | |
Slava Grigorev | 1a626b6 | 2014-12-01 13:49:39 -0500 | [diff] [blame] | 46 | void dce6_endpoint_wreg(struct radeon_device *rdev, |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 47 | u32 block_offset, u32 reg, u32 v) |
| 48 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 49 | unsigned long flags; |
| 50 | |
| 51 | spin_lock_irqsave(&rdev->end_idx_lock, flags); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 52 | if (ASIC_IS_DCE8(rdev)) |
| 53 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); |
| 54 | else |
| 55 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, |
| 56 | AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg)); |
| 57 | WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 58 | spin_unlock_irqrestore(&rdev->end_idx_lock, flags); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 59 | } |
| 60 | |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 61 | static void dce6_afmt_get_connected_pins(struct radeon_device *rdev) |
| 62 | { |
| 63 | int i; |
| 64 | u32 offset, tmp; |
| 65 | |
| 66 | for (i = 0; i < rdev->audio.num_pins; i++) { |
| 67 | offset = rdev->audio.pin[i].offset; |
| 68 | tmp = RREG32_ENDPOINT(offset, |
| 69 | AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); |
| 70 | if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1) |
| 71 | rdev->audio.pin[i].connected = false; |
| 72 | else |
| 73 | rdev->audio.pin[i].connected = true; |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev) |
| 78 | { |
Alex Deucher | d046520 | 2015-07-23 10:53:51 -0400 | [diff] [blame] | 79 | struct drm_encoder *encoder; |
| 80 | struct radeon_encoder *radeon_encoder; |
| 81 | struct radeon_encoder_atom_dig *dig; |
| 82 | struct r600_audio_pin *pin = NULL; |
| 83 | int i, pin_count; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 84 | |
| 85 | dce6_afmt_get_connected_pins(rdev); |
| 86 | |
| 87 | for (i = 0; i < rdev->audio.num_pins; i++) { |
Alex Deucher | d046520 | 2015-07-23 10:53:51 -0400 | [diff] [blame] | 88 | if (rdev->audio.pin[i].connected) { |
| 89 | pin = &rdev->audio.pin[i]; |
| 90 | pin_count = 0; |
| 91 | |
| 92 | list_for_each_entry(encoder, &rdev->ddev->mode_config.encoder_list, head) { |
| 93 | if (radeon_encoder_is_digital(encoder)) { |
| 94 | radeon_encoder = to_radeon_encoder(encoder); |
| 95 | dig = radeon_encoder->enc_priv; |
| 96 | if (dig->pin == pin) |
| 97 | pin_count++; |
| 98 | } |
| 99 | } |
| 100 | |
| 101 | if (pin_count == 0) |
| 102 | return pin; |
| 103 | } |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 104 | } |
Alex Deucher | d046520 | 2015-07-23 10:53:51 -0400 | [diff] [blame] | 105 | if (!pin) |
| 106 | DRM_ERROR("No connected audio pins found!\n"); |
| 107 | return pin; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | void dce6_afmt_select_pin(struct drm_encoder *encoder) |
| 111 | { |
| 112 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 113 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 114 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 115 | |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 116 | if (!dig || !dig->afmt || !dig->pin) |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 117 | return; |
| 118 | |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 119 | WREG32(AFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, |
| 120 | AFMT_AUDIO_SRC_SELECT(dig->pin->id)); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 121 | } |
| 122 | |
Alex Deucher | b188025 | 2013-10-10 18:03:06 -0400 | [diff] [blame] | 123 | void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 124 | struct drm_connector *connector, |
| 125 | struct drm_display_mode *mode) |
Alex Deucher | b188025 | 2013-10-10 18:03:06 -0400 | [diff] [blame] | 126 | { |
| 127 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 128 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 129 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 130 | u32 tmp = 0; |
Alex Deucher | b188025 | 2013-10-10 18:03:06 -0400 | [diff] [blame] | 131 | |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 132 | if (!dig || !dig->afmt || !dig->pin) |
Alex Deucher | b188025 | 2013-10-10 18:03:06 -0400 | [diff] [blame] | 133 | return; |
| 134 | |
Alex Deucher | b188025 | 2013-10-10 18:03:06 -0400 | [diff] [blame] | 135 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 136 | if (connector->latency_present[1]) |
| 137 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | |
| 138 | AUDIO_LIPSYNC(connector->audio_latency[1]); |
| 139 | else |
Stefan Brüns | c748990 | 2014-07-13 01:47:14 +0200 | [diff] [blame] | 140 | tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); |
Alex Deucher | b188025 | 2013-10-10 18:03:06 -0400 | [diff] [blame] | 141 | } else { |
| 142 | if (connector->latency_present[0]) |
| 143 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | |
| 144 | AUDIO_LIPSYNC(connector->audio_latency[0]); |
| 145 | else |
Stefan Brüns | c748990 | 2014-07-13 01:47:14 +0200 | [diff] [blame] | 146 | tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); |
Alex Deucher | b188025 | 2013-10-10 18:03:06 -0400 | [diff] [blame] | 147 | } |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 148 | WREG32_ENDPOINT(dig->pin->offset, |
| 149 | AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); |
Alex Deucher | b188025 | 2013-10-10 18:03:06 -0400 | [diff] [blame] | 150 | } |
| 151 | |
Slava Grigorev | 00a9d4b | 2014-12-01 18:02:57 -0500 | [diff] [blame] | 152 | void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 153 | u8 *sadb, int sad_count) |
Rafał Miłecki | 6159b65 | 2013-08-15 11:16:30 +0200 | [diff] [blame] | 154 | { |
| 155 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 156 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 157 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 158 | u32 tmp; |
Rafał Miłecki | 6159b65 | 2013-08-15 11:16:30 +0200 | [diff] [blame] | 159 | |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 160 | if (!dig || !dig->afmt || !dig->pin) |
Rafał Miłecki | 6159b65 | 2013-08-15 11:16:30 +0200 | [diff] [blame] | 161 | return; |
| 162 | |
Rafał Miłecki | 6159b65 | 2013-08-15 11:16:30 +0200 | [diff] [blame] | 163 | /* program the speaker allocation */ |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 164 | tmp = RREG32_ENDPOINT(dig->pin->offset, |
| 165 | AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); |
Rafał Miłecki | 6159b65 | 2013-08-15 11:16:30 +0200 | [diff] [blame] | 166 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
| 167 | /* set HDMI mode */ |
| 168 | tmp |= HDMI_CONNECTION; |
| 169 | if (sad_count) |
| 170 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
| 171 | else |
| 172 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 173 | WREG32_ENDPOINT(dig->pin->offset, |
| 174 | AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); |
Slava Grigorev | 00a9d4b | 2014-12-01 18:02:57 -0500 | [diff] [blame] | 175 | } |
Rafał Miłecki | 6159b65 | 2013-08-15 11:16:30 +0200 | [diff] [blame] | 176 | |
Slava Grigorev | 00a9d4b | 2014-12-01 18:02:57 -0500 | [diff] [blame] | 177 | void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 178 | u8 *sadb, int sad_count) |
Slava Grigorev | 00a9d4b | 2014-12-01 18:02:57 -0500 | [diff] [blame] | 179 | { |
| 180 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 181 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 182 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 183 | u32 tmp; |
Slava Grigorev | 00a9d4b | 2014-12-01 18:02:57 -0500 | [diff] [blame] | 184 | |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 185 | if (!dig || !dig->afmt || !dig->pin) |
Slava Grigorev | 00a9d4b | 2014-12-01 18:02:57 -0500 | [diff] [blame] | 186 | return; |
| 187 | |
Slava Grigorev | 00a9d4b | 2014-12-01 18:02:57 -0500 | [diff] [blame] | 188 | /* program the speaker allocation */ |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 189 | tmp = RREG32_ENDPOINT(dig->pin->offset, |
| 190 | AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); |
Slava Grigorev | 00a9d4b | 2014-12-01 18:02:57 -0500 | [diff] [blame] | 191 | tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK); |
| 192 | /* set DP mode */ |
| 193 | tmp |= DP_CONNECTION; |
| 194 | if (sad_count) |
| 195 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
| 196 | else |
| 197 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 198 | WREG32_ENDPOINT(dig->pin->offset, |
| 199 | AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); |
Rafał Miłecki | 6159b65 | 2013-08-15 11:16:30 +0200 | [diff] [blame] | 200 | } |
| 201 | |
Alex Deucher | 070a2e6 | 2015-01-22 10:41:55 -0500 | [diff] [blame] | 202 | void dce6_afmt_write_sad_regs(struct drm_encoder *encoder, |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 203 | struct cea_sad *sads, int sad_count) |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 204 | { |
Alex Deucher | 070a2e6 | 2015-01-22 10:41:55 -0500 | [diff] [blame] | 205 | int i; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 206 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 207 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Alex Deucher | 070a2e6 | 2015-01-22 10:41:55 -0500 | [diff] [blame] | 208 | struct radeon_device *rdev = encoder->dev->dev_private; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 209 | static const u16 eld_reg_to_type[][2] = { |
| 210 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, |
| 211 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, |
| 212 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
| 213 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, |
| 214 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
| 215 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
| 216 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, |
| 217 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
| 218 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
| 219 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
| 220 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
| 221 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
| 222 | }; |
| 223 | |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 224 | if (!dig || !dig->afmt || !dig->pin) |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 225 | return; |
| 226 | |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 227 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
| 228 | u32 value = 0; |
Anssi Hannula | 0f57bca | 2013-10-29 01:19:16 +0200 | [diff] [blame] | 229 | u8 stereo_freqs = 0; |
| 230 | int max_channels = -1; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 231 | int j; |
| 232 | |
| 233 | for (j = 0; j < sad_count; j++) { |
| 234 | struct cea_sad *sad = &sads[j]; |
| 235 | |
| 236 | if (sad->format == eld_reg_to_type[i][1]) { |
Anssi Hannula | 0f57bca | 2013-10-29 01:19:16 +0200 | [diff] [blame] | 237 | if (sad->channels > max_channels) { |
| 238 | value = MAX_CHANNELS(sad->channels) | |
| 239 | DESCRIPTOR_BYTE_2(sad->byte2) | |
| 240 | SUPPORTED_FREQUENCIES(sad->freq); |
| 241 | max_channels = sad->channels; |
| 242 | } |
| 243 | |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 244 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
Anssi Hannula | 0f57bca | 2013-10-29 01:19:16 +0200 | [diff] [blame] | 245 | stereo_freqs |= sad->freq; |
| 246 | else |
| 247 | break; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 248 | } |
| 249 | } |
Anssi Hannula | 0f57bca | 2013-10-29 01:19:16 +0200 | [diff] [blame] | 250 | |
| 251 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); |
| 252 | |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 253 | WREG32_ENDPOINT(dig->pin->offset, eld_reg_to_type[i][0], value); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 254 | } |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 255 | } |
| 256 | |
Alex Deucher | 832eafa | 2014-02-18 11:07:55 -0500 | [diff] [blame] | 257 | void dce6_audio_enable(struct radeon_device *rdev, |
| 258 | struct r600_audio_pin *pin, |
Alex Deucher | d3d8c14 | 2014-09-18 17:26:39 -0400 | [diff] [blame] | 259 | u8 enable_mask) |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 260 | { |
Alex Deucher | 832eafa | 2014-02-18 11:07:55 -0500 | [diff] [blame] | 261 | if (!pin) |
| 262 | return; |
| 263 | |
Alex Deucher | f68fdbe | 2014-09-18 16:19:04 -0400 | [diff] [blame] | 264 | WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
Alex Deucher | d3d8c14 | 2014-09-18 17:26:39 -0400 | [diff] [blame] | 265 | enable_mask ? AUDIO_ENABLED : 0); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 266 | } |
Slava Grigorev | a85d682 | 2014-12-05 13:38:31 -0500 | [diff] [blame] | 267 | |
| 268 | void dce6_hdmi_audio_set_dto(struct radeon_device *rdev, |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 269 | struct radeon_crtc *crtc, unsigned int clock) |
Slava Grigorev | a85d682 | 2014-12-05 13:38:31 -0500 | [diff] [blame] | 270 | { |
Slava Grigorev | b983a8f | 2015-03-02 11:31:07 -0500 | [diff] [blame] | 271 | /* Two dtos; generally use dto0 for HDMI */ |
Slava Grigorev | a85d682 | 2014-12-05 13:38:31 -0500 | [diff] [blame] | 272 | u32 value = 0; |
| 273 | |
Slava Grigorev | b983a8f | 2015-03-02 11:31:07 -0500 | [diff] [blame] | 274 | if (crtc) |
Slava Grigorev | a85d682 | 2014-12-05 13:38:31 -0500 | [diff] [blame] | 275 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
| 276 | |
| 277 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); |
| 278 | |
Slava Grigorev | b983a8f | 2015-03-02 11:31:07 -0500 | [diff] [blame] | 279 | /* Express [24MHz / target pixel clock] as an exact rational |
| 280 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
| 281 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
| 282 | */ |
| 283 | WREG32(DCCG_AUDIO_DTO0_PHASE, 24000); |
| 284 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock); |
Slava Grigorev | a85d682 | 2014-12-05 13:38:31 -0500 | [diff] [blame] | 285 | } |
| 286 | |
| 287 | void dce6_dp_audio_set_dto(struct radeon_device *rdev, |
Alex Deucher | d0ea397 | 2015-07-23 10:01:09 -0400 | [diff] [blame] | 288 | struct radeon_crtc *crtc, unsigned int clock) |
Slava Grigorev | a85d682 | 2014-12-05 13:38:31 -0500 | [diff] [blame] | 289 | { |
Slava Grigorev | b983a8f | 2015-03-02 11:31:07 -0500 | [diff] [blame] | 290 | /* Two dtos; generally use dto1 for DP */ |
Slava Grigorev | a85d682 | 2014-12-05 13:38:31 -0500 | [diff] [blame] | 291 | u32 value = 0; |
| 292 | value |= DCCG_AUDIO_DTO_SEL; |
| 293 | |
Slava Grigorev | b983a8f | 2015-03-02 11:31:07 -0500 | [diff] [blame] | 294 | if (crtc) |
Slava Grigorev | a85d682 | 2014-12-05 13:38:31 -0500 | [diff] [blame] | 295 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
| 296 | |
| 297 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); |
| 298 | |
Slava Grigorev | b983a8f | 2015-03-02 11:31:07 -0500 | [diff] [blame] | 299 | /* Express [24MHz / target pixel clock] as an exact rational |
| 300 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
| 301 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
| 302 | */ |
Slava Grigorev | 2afa326 | 2015-03-02 12:05:29 -0500 | [diff] [blame] | 303 | if (ASIC_IS_DCE8(rdev)) { |
Slava Grigorev | ac4a935 | 2015-12-17 11:09:58 -0500 | [diff] [blame] | 304 | unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) & |
| 305 | DENTIST_DPREFCLK_WDIVIDER_MASK) >> |
| 306 | DENTIST_DPREFCLK_WDIVIDER_SHIFT; |
Slava Grigorev | a64c9da | 2016-01-26 16:56:25 -0500 | [diff] [blame] | 307 | div = radeon_audio_decode_dfs_div(div); |
Slava Grigorev | ac4a935 | 2015-12-17 11:09:58 -0500 | [diff] [blame] | 308 | |
| 309 | if (div) |
Slava Grigorev | a64c9da | 2016-01-26 16:56:25 -0500 | [diff] [blame] | 310 | clock = clock * 100 / div; |
Slava Grigorev | ac4a935 | 2015-12-17 11:09:58 -0500 | [diff] [blame] | 311 | |
Slava Grigorev | 2afa326 | 2015-03-02 12:05:29 -0500 | [diff] [blame] | 312 | WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000); |
| 313 | WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock); |
| 314 | } else { |
| 315 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); |
| 316 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock); |
| 317 | } |
Slava Grigorev | a85d682 | 2014-12-05 13:38:31 -0500 | [diff] [blame] | 318 | } |