Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Christian König. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Christian König |
| 25 | */ |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 26 | #include <linux/hdmi.h> |
Pierre Ossman | a209825 | 2013-11-06 20:09:08 +0100 | [diff] [blame] | 27 | #include <linux/gcd.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
| 29 | #include <drm/radeon_drm.h> |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 30 | #include "radeon.h" |
Daniel Vetter | 3574dda | 2011-02-18 17:59:19 +0100 | [diff] [blame] | 31 | #include "radeon_asic.h" |
Slava Grigorev | 3cdde02 | 2014-12-02 15:22:43 -0500 | [diff] [blame] | 32 | #include "radeon_audio.h" |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 33 | #include "r600d.h" |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 34 | #include "atom.h" |
| 35 | |
| 36 | /* |
| 37 | * HDMI color format |
| 38 | */ |
| 39 | enum r600_hdmi_color_format { |
| 40 | RGB = 0, |
| 41 | YCC_422 = 1, |
| 42 | YCC_444 = 2 |
| 43 | }; |
| 44 | |
| 45 | /* |
| 46 | * IEC60958 status bits |
| 47 | */ |
| 48 | enum r600_hdmi_iec_status_bits { |
| 49 | AUDIO_STATUS_DIG_ENABLE = 0x01, |
Rafał Miłecki | 3fe373d | 2010-03-06 13:03:38 +0000 | [diff] [blame] | 50 | AUDIO_STATUS_V = 0x02, |
| 51 | AUDIO_STATUS_VCFG = 0x04, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 52 | AUDIO_STATUS_EMPHASIS = 0x08, |
| 53 | AUDIO_STATUS_COPYRIGHT = 0x10, |
| 54 | AUDIO_STATUS_NONAUDIO = 0x20, |
| 55 | AUDIO_STATUS_PROFESSIONAL = 0x40, |
Rafał Miłecki | 3fe373d | 2010-03-06 13:03:38 +0000 | [diff] [blame] | 56 | AUDIO_STATUS_LEVEL = 0x80 |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 57 | }; |
| 58 | |
Alex Deucher | 7215667 | 2014-09-18 16:36:08 -0400 | [diff] [blame] | 59 | static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev) |
| 60 | { |
| 61 | struct r600_audio_pin status; |
| 62 | uint32_t value; |
| 63 | |
| 64 | value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL); |
| 65 | |
| 66 | /* number of channels */ |
| 67 | status.channels = (value & 0x7) + 1; |
| 68 | |
| 69 | /* bits per sample */ |
| 70 | switch ((value & 0xF0) >> 4) { |
| 71 | case 0x0: |
| 72 | status.bits_per_sample = 8; |
| 73 | break; |
| 74 | case 0x1: |
| 75 | status.bits_per_sample = 16; |
| 76 | break; |
| 77 | case 0x2: |
| 78 | status.bits_per_sample = 20; |
| 79 | break; |
| 80 | case 0x3: |
| 81 | status.bits_per_sample = 24; |
| 82 | break; |
| 83 | case 0x4: |
| 84 | status.bits_per_sample = 32; |
| 85 | break; |
| 86 | default: |
| 87 | dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n", |
| 88 | (int)value); |
| 89 | status.bits_per_sample = 16; |
| 90 | } |
| 91 | |
| 92 | /* current sampling rate in HZ */ |
| 93 | if (value & 0x4000) |
| 94 | status.rate = 44100; |
| 95 | else |
| 96 | status.rate = 48000; |
| 97 | status.rate *= ((value >> 11) & 0x7) + 1; |
| 98 | status.rate /= ((value >> 8) & 0x7) + 1; |
| 99 | |
| 100 | value = RREG32(R600_AUDIO_STATUS_BITS); |
| 101 | |
| 102 | /* iec 60958 status bits */ |
| 103 | status.status_bits = value & 0xff; |
| 104 | |
| 105 | /* iec 60958 category code */ |
| 106 | status.category_code = (value >> 8) & 0xff; |
| 107 | |
| 108 | return status; |
| 109 | } |
| 110 | |
| 111 | /* |
| 112 | * update all hdmi interfaces with current audio parameters |
| 113 | */ |
| 114 | void r600_audio_update_hdmi(struct work_struct *work) |
| 115 | { |
| 116 | struct radeon_device *rdev = container_of(work, struct radeon_device, |
| 117 | audio_work); |
| 118 | struct drm_device *dev = rdev->ddev; |
| 119 | struct r600_audio_pin audio_status = r600_audio_status(rdev); |
| 120 | struct drm_encoder *encoder; |
| 121 | bool changed = false; |
| 122 | |
| 123 | if (rdev->audio.pin[0].channels != audio_status.channels || |
| 124 | rdev->audio.pin[0].rate != audio_status.rate || |
| 125 | rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample || |
| 126 | rdev->audio.pin[0].status_bits != audio_status.status_bits || |
| 127 | rdev->audio.pin[0].category_code != audio_status.category_code) { |
| 128 | rdev->audio.pin[0] = audio_status; |
| 129 | changed = true; |
| 130 | } |
| 131 | |
| 132 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 133 | if (!radeon_encoder_is_digital(encoder)) |
| 134 | continue; |
| 135 | if (changed || r600_hdmi_buffer_status_changed(encoder)) |
| 136 | r600_hdmi_update_audio_settings(encoder); |
| 137 | } |
| 138 | } |
| 139 | |
| 140 | /* enable the audio stream */ |
| 141 | void r600_audio_enable(struct radeon_device *rdev, |
| 142 | struct r600_audio_pin *pin, |
Alex Deucher | d3d8c14 | 2014-09-18 17:26:39 -0400 | [diff] [blame] | 143 | u8 enable_mask) |
Alex Deucher | 7215667 | 2014-09-18 16:36:08 -0400 | [diff] [blame] | 144 | { |
Alex Deucher | d3d8c14 | 2014-09-18 17:26:39 -0400 | [diff] [blame] | 145 | u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); |
Alex Deucher | 7215667 | 2014-09-18 16:36:08 -0400 | [diff] [blame] | 146 | |
| 147 | if (!pin) |
| 148 | return; |
| 149 | |
Alex Deucher | d3d8c14 | 2014-09-18 17:26:39 -0400 | [diff] [blame] | 150 | if (enable_mask) { |
| 151 | tmp |= AUDIO_ENABLED; |
| 152 | if (enable_mask & 1) |
| 153 | tmp |= PIN0_AUDIO_ENABLED; |
| 154 | if (enable_mask & 2) |
| 155 | tmp |= PIN1_AUDIO_ENABLED; |
| 156 | if (enable_mask & 4) |
| 157 | tmp |= PIN2_AUDIO_ENABLED; |
| 158 | if (enable_mask & 8) |
| 159 | tmp |= PIN3_AUDIO_ENABLED; |
Alex Deucher | 7215667 | 2014-09-18 16:36:08 -0400 | [diff] [blame] | 160 | } else { |
Alex Deucher | d3d8c14 | 2014-09-18 17:26:39 -0400 | [diff] [blame] | 161 | tmp &= ~(AUDIO_ENABLED | |
| 162 | PIN0_AUDIO_ENABLED | |
| 163 | PIN1_AUDIO_ENABLED | |
| 164 | PIN2_AUDIO_ENABLED | |
| 165 | PIN3_AUDIO_ENABLED); |
Alex Deucher | 7215667 | 2014-09-18 16:36:08 -0400 | [diff] [blame] | 166 | } |
Alex Deucher | d3d8c14 | 2014-09-18 17:26:39 -0400 | [diff] [blame] | 167 | |
| 168 | WREG32(AZ_HOT_PLUG_CONTROL, tmp); |
Alex Deucher | 7215667 | 2014-09-18 16:36:08 -0400 | [diff] [blame] | 169 | } |
| 170 | |
Alex Deucher | 7215667 | 2014-09-18 16:36:08 -0400 | [diff] [blame] | 171 | struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev) |
| 172 | { |
| 173 | /* only one pin on 6xx-NI */ |
| 174 | return &rdev->audio.pin[0]; |
| 175 | } |
| 176 | |
Slava Grigorev | 64424d6e | 2014-12-06 20:19:16 -0500 | [diff] [blame] | 177 | void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset, |
| 178 | const struct radeon_hdmi_acr *acr) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 179 | { |
| 180 | struct drm_device *dev = encoder->dev; |
| 181 | struct radeon_device *rdev = dev->dev_private; |
Slava Grigorev | 64424d6e | 2014-12-06 20:19:16 -0500 | [diff] [blame] | 182 | |
| 183 | /* DCE 3.0 uses register that's normally for CRC_CONTROL */ |
| 184 | uint32_t acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL : |
| 185 | HDMI0_ACR_PACKET_CONTROL; |
| 186 | WREG32_P(acr_ctl + offset, |
| 187 | HDMI0_ACR_SOURCE | /* select SW CTS value */ |
| 188 | HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */ |
| 189 | ~(HDMI0_ACR_SOURCE | |
| 190 | HDMI0_ACR_AUTO_SEND)); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 191 | |
Rafał Miłecki | 6870633 | 2014-05-16 11:10:30 +0200 | [diff] [blame] | 192 | WREG32_P(HDMI0_ACR_32_0 + offset, |
Slava Grigorev | 64424d6e | 2014-12-06 20:19:16 -0500 | [diff] [blame] | 193 | HDMI0_ACR_CTS_32(acr->cts_32khz), |
| 194 | ~HDMI0_ACR_CTS_32_MASK); |
Rafał Miłecki | 6870633 | 2014-05-16 11:10:30 +0200 | [diff] [blame] | 195 | WREG32_P(HDMI0_ACR_32_1 + offset, |
Slava Grigorev | 64424d6e | 2014-12-06 20:19:16 -0500 | [diff] [blame] | 196 | HDMI0_ACR_N_32(acr->n_32khz), |
| 197 | ~HDMI0_ACR_N_32_MASK); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 198 | |
Rafał Miłecki | 6870633 | 2014-05-16 11:10:30 +0200 | [diff] [blame] | 199 | WREG32_P(HDMI0_ACR_44_0 + offset, |
Slava Grigorev | 64424d6e | 2014-12-06 20:19:16 -0500 | [diff] [blame] | 200 | HDMI0_ACR_CTS_44(acr->cts_44_1khz), |
| 201 | ~HDMI0_ACR_CTS_44_MASK); |
Rafał Miłecki | 6870633 | 2014-05-16 11:10:30 +0200 | [diff] [blame] | 202 | WREG32_P(HDMI0_ACR_44_1 + offset, |
Slava Grigorev | 64424d6e | 2014-12-06 20:19:16 -0500 | [diff] [blame] | 203 | HDMI0_ACR_N_44(acr->n_44_1khz), |
| 204 | ~HDMI0_ACR_N_44_MASK); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 205 | |
Rafał Miłecki | 6870633 | 2014-05-16 11:10:30 +0200 | [diff] [blame] | 206 | WREG32_P(HDMI0_ACR_48_0 + offset, |
Slava Grigorev | 64424d6e | 2014-12-06 20:19:16 -0500 | [diff] [blame] | 207 | HDMI0_ACR_CTS_48(acr->cts_48khz), |
| 208 | ~HDMI0_ACR_CTS_48_MASK); |
Rafał Miłecki | 6870633 | 2014-05-16 11:10:30 +0200 | [diff] [blame] | 209 | WREG32_P(HDMI0_ACR_48_1 + offset, |
Slava Grigorev | 64424d6e | 2014-12-06 20:19:16 -0500 | [diff] [blame] | 210 | HDMI0_ACR_N_48(acr->n_48khz), |
| 211 | ~HDMI0_ACR_N_48_MASK); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 212 | } |
| 213 | |
| 214 | /* |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 215 | * build a HDMI Video Info Frame |
| 216 | */ |
Slava Grigorev | baa7d8e | 2014-12-08 18:28:33 -0500 | [diff] [blame] | 217 | void r600_set_avi_packet(struct radeon_device *rdev, u32 offset, |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 218 | unsigned char *buffer, size_t size) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 219 | { |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 220 | uint8_t *frame = buffer + 3; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 221 | |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 222 | WREG32(HDMI0_AVI_INFO0 + offset, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 223 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 224 | WREG32(HDMI0_AVI_INFO1 + offset, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 225 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 226 | WREG32(HDMI0_AVI_INFO2 + offset, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 227 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 228 | WREG32(HDMI0_AVI_INFO3 + offset, |
Slava Grigorev | 96ea7af | 2014-12-05 17:59:56 -0500 | [diff] [blame] | 229 | frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24)); |
Slava Grigorev | baa7d8e | 2014-12-08 18:28:33 -0500 | [diff] [blame] | 230 | |
Slava Grigorev | baa7d8e | 2014-12-08 18:28:33 -0500 | [diff] [blame] | 231 | WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset, |
Alex Deucher | 304f07e | 2015-03-31 10:33:05 -0400 | [diff] [blame] | 232 | HDMI0_AVI_INFO_LINE(2)); /* anything other than 0 */ |
| 233 | |
| 234 | WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, |
| 235 | HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ |
| 236 | HDMI0_AVI_INFO_CONT); /* send AVI info frames every frame/field */ |
| 237 | |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 238 | } |
| 239 | |
| 240 | /* |
| 241 | * build a Audio Info Frame |
| 242 | */ |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 243 | static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder, |
| 244 | const void *buffer, size_t size) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 245 | { |
| 246 | struct drm_device *dev = encoder->dev; |
| 247 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 248 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 249 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 250 | uint32_t offset = dig->afmt->offset; |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 251 | const u8 *frame = buffer + 3; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 252 | |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 253 | WREG32(HDMI0_AUDIO_INFO0 + offset, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 254 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 255 | WREG32(HDMI0_AUDIO_INFO1 + offset, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 256 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); |
| 257 | } |
| 258 | |
| 259 | /* |
| 260 | * test if audio buffer is filled enough to start playing |
| 261 | */ |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 262 | static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 263 | { |
| 264 | struct drm_device *dev = encoder->dev; |
| 265 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 266 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 267 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 268 | uint32_t offset = dig->afmt->offset; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 269 | |
Rafał Miłecki | c6543a6 | 2012-04-28 23:35:24 +0200 | [diff] [blame] | 270 | return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 271 | } |
| 272 | |
| 273 | /* |
| 274 | * have buffer status changed since last call? |
| 275 | */ |
| 276 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) |
| 277 | { |
| 278 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 279 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 280 | int status, result; |
| 281 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 282 | if (!dig->afmt || !dig->afmt->enabled) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 283 | return 0; |
| 284 | |
| 285 | status = r600_hdmi_is_audio_buffer_filled(encoder); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 286 | result = dig->afmt->last_buffer_filled_status != status; |
| 287 | dig->afmt->last_buffer_filled_status = status; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 288 | |
| 289 | return result; |
| 290 | } |
| 291 | |
| 292 | /* |
| 293 | * write the audio workaround status to the hardware |
| 294 | */ |
Rafał Miłecki | 8f33a15 | 2014-05-16 11:36:24 +0200 | [diff] [blame] | 295 | void r600_hdmi_audio_workaround(struct drm_encoder *encoder) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 296 | { |
| 297 | struct drm_device *dev = encoder->dev; |
| 298 | struct radeon_device *rdev = dev->dev_private; |
| 299 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 300 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 301 | uint32_t offset = dig->afmt->offset; |
| 302 | bool hdmi_audio_workaround = false; /* FIXME */ |
| 303 | u32 value; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 304 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 305 | if (!hdmi_audio_workaround || |
| 306 | r600_hdmi_is_audio_buffer_filled(encoder)) |
| 307 | value = 0; /* disable workaround */ |
| 308 | else |
| 309 | value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ |
| 310 | WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, |
| 311 | value, ~HDMI0_AUDIO_TEST_EN); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 312 | } |
| 313 | |
Slava Grigorev | a85d682 | 2014-12-05 13:38:31 -0500 | [diff] [blame] | 314 | void r600_hdmi_audio_set_dto(struct radeon_device *rdev, |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 315 | struct radeon_crtc *crtc, unsigned int clock) |
Alex Deucher | b1f6f47 | 2013-04-18 10:50:55 -0400 | [diff] [blame] | 316 | { |
Slava Grigorev | a85d682 | 2014-12-05 13:38:31 -0500 | [diff] [blame] | 317 | struct radeon_encoder *radeon_encoder; |
| 318 | struct radeon_encoder_atom_dig *dig; |
Alex Deucher | b1f6f47 | 2013-04-18 10:50:55 -0400 | [diff] [blame] | 319 | |
Slava Grigorev | a85d682 | 2014-12-05 13:38:31 -0500 | [diff] [blame] | 320 | if (!crtc) |
Alex Deucher | b1f6f47 | 2013-04-18 10:50:55 -0400 | [diff] [blame] | 321 | return; |
| 322 | |
Slava Grigorev | a85d682 | 2014-12-05 13:38:31 -0500 | [diff] [blame] | 323 | radeon_encoder = to_radeon_encoder(crtc->encoder); |
| 324 | dig = radeon_encoder->enc_priv; |
Alex Deucher | 1518dd8 | 2013-07-30 17:31:07 -0400 | [diff] [blame] | 325 | |
Slava Grigorev | a85d682 | 2014-12-05 13:38:31 -0500 | [diff] [blame] | 326 | if (!dig) |
| 327 | return; |
| 328 | |
| 329 | if (dig->dig_encoder == 0) { |
| 330 | WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100); |
| 331 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); |
| 332 | WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ |
Alex Deucher | 55d4e02 | 2013-11-25 13:20:59 -0500 | [diff] [blame] | 333 | } else { |
Slava Grigorev | a85d682 | 2014-12-05 13:38:31 -0500 | [diff] [blame] | 334 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100); |
| 335 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100); |
| 336 | WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ |
Alex Deucher | 1586505 | 2013-04-22 09:42:07 -0400 | [diff] [blame] | 337 | } |
Alex Deucher | b1f6f47 | 2013-04-18 10:50:55 -0400 | [diff] [blame] | 338 | } |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 339 | |
Alex Deucher | 930a978 | 2015-01-20 19:20:52 -0500 | [diff] [blame] | 340 | void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset) |
| 341 | { |
| 342 | struct drm_device *dev = encoder->dev; |
| 343 | struct radeon_device *rdev = dev->dev_private; |
| 344 | |
| 345 | WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset, |
| 346 | HDMI0_NULL_SEND | /* send null packets when required */ |
| 347 | HDMI0_GC_SEND | /* send general control packets */ |
| 348 | HDMI0_GC_CONT); /* send general control packets every frame */ |
| 349 | } |
| 350 | |
Slava Grigorev | 1852c9a | 2014-12-09 16:44:18 -0500 | [diff] [blame] | 351 | void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset) |
| 352 | { |
| 353 | struct drm_device *dev = encoder->dev; |
| 354 | struct radeon_device *rdev = dev->dev_private; |
| 355 | |
| 356 | WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, |
| 357 | HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ |
| 358 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ |
| 359 | HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ |
| 360 | HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */ |
| 361 | ~(HDMI0_AUDIO_SAMPLE_SEND | |
| 362 | HDMI0_AUDIO_DELAY_EN_MASK | |
| 363 | HDMI0_AUDIO_PACKETS_PER_LINE_MASK | |
| 364 | HDMI0_60958_CS_UPDATE)); |
| 365 | |
| 366 | WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, |
| 367 | HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
| 368 | HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ |
| 369 | |
| 370 | WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset, |
| 371 | HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */ |
| 372 | ~HDMI0_AUDIO_INFO_LINE_MASK); |
| 373 | |
| 374 | WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset, |
| 375 | ~(HDMI0_GENERIC0_SEND | |
| 376 | HDMI0_GENERIC0_CONT | |
| 377 | HDMI0_GENERIC0_UPDATE | |
| 378 | HDMI0_GENERIC1_SEND | |
| 379 | HDMI0_GENERIC1_CONT | |
| 380 | HDMI0_GENERIC0_LINE_MASK | |
| 381 | HDMI0_GENERIC1_LINE_MASK)); |
| 382 | |
| 383 | WREG32_P(HDMI0_60958_0 + offset, |
| 384 | HDMI0_60958_CS_CHANNEL_NUMBER_L(1), |
| 385 | ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK | |
| 386 | HDMI0_60958_CS_CLOCK_ACCURACY_MASK)); |
| 387 | |
| 388 | WREG32_P(HDMI0_60958_1 + offset, |
| 389 | HDMI0_60958_CS_CHANNEL_NUMBER_R(2), |
| 390 | ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK); |
| 391 | } |
| 392 | |
Slava Grigorev | 3be2e7d | 2014-12-09 17:17:35 -0500 | [diff] [blame] | 393 | void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute) |
| 394 | { |
| 395 | struct drm_device *dev = encoder->dev; |
| 396 | struct radeon_device *rdev = dev->dev_private; |
| 397 | |
| 398 | if (mute) |
| 399 | WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE); |
| 400 | else |
| 401 | WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE); |
| 402 | } |
| 403 | |
Rafał Miłecki | 8e4d9f8 | 2014-05-16 11:10:31 +0200 | [diff] [blame] | 404 | /** |
| 405 | * r600_hdmi_update_audio_settings - Update audio infoframe |
| 406 | * |
| 407 | * @encoder: drm encoder |
| 408 | * |
| 409 | * Gets info about current audio stream and updates audio infoframe. |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 410 | */ |
Christian König | 58bd086 | 2010-04-05 22:14:55 +0200 | [diff] [blame] | 411 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 412 | { |
| 413 | struct drm_device *dev = encoder->dev; |
| 414 | struct radeon_device *rdev = dev->dev_private; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 415 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 416 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 417 | struct r600_audio_pin audio = r600_audio_status(rdev); |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 418 | uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; |
| 419 | struct hdmi_audio_infoframe frame; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 420 | uint32_t offset; |
Rafał Miłecki | 8e4d9f8 | 2014-05-16 11:10:31 +0200 | [diff] [blame] | 421 | uint32_t value; |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 422 | ssize_t err; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 423 | |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 424 | if (!dig->afmt || !dig->afmt->enabled) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 425 | return; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 426 | offset = dig->afmt->offset; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 427 | |
| 428 | DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", |
| 429 | r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 430 | audio.channels, audio.rate, audio.bits_per_sample); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 431 | DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 432 | (int)audio.status_bits, (int)audio.category_code); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 433 | |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 434 | err = hdmi_audio_infoframe_init(&frame); |
| 435 | if (err < 0) { |
| 436 | DRM_ERROR("failed to setup audio infoframe\n"); |
| 437 | return; |
| 438 | } |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 439 | |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 440 | frame.channels = audio.channels; |
| 441 | |
| 442 | err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); |
| 443 | if (err < 0) { |
| 444 | DRM_ERROR("failed to pack audio infoframe\n"); |
| 445 | return; |
| 446 | } |
| 447 | |
Rafał Miłecki | 8e4d9f8 | 2014-05-16 11:10:31 +0200 | [diff] [blame] | 448 | value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset); |
| 449 | if (value & HDMI0_AUDIO_TEST_EN) |
| 450 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, |
| 451 | value & ~HDMI0_AUDIO_TEST_EN); |
| 452 | |
| 453 | WREG32_OR(HDMI0_CONTROL + offset, |
| 454 | HDMI0_ERROR_ACK); |
| 455 | |
| 456 | WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset, |
| 457 | ~HDMI0_AUDIO_INFO_SOURCE); |
| 458 | |
Thierry Reding | e3b2e03 | 2013-01-14 13:36:30 +0100 | [diff] [blame] | 459 | r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer)); |
Rafał Miłecki | 8e4d9f8 | 2014-05-16 11:10:31 +0200 | [diff] [blame] | 460 | |
| 461 | WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, |
| 462 | HDMI0_AUDIO_INFO_CONT | |
| 463 | HDMI0_AUDIO_INFO_UPDATE); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 464 | } |
| 465 | |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 466 | /* |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 467 | * enable the HDMI engine |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 468 | */ |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 469 | void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 470 | { |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 471 | struct drm_device *dev = encoder->dev; |
| 472 | struct radeon_device *rdev = dev->dev_private; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 473 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 474 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 475 | u32 hdmi = HDMI0_ERROR_ACK; |
Alex Deucher | 16823d1 | 2010-04-16 11:35:30 -0400 | [diff] [blame] | 476 | |
Alex Deucher | c2b4cac | 2013-07-08 18:16:56 -0400 | [diff] [blame] | 477 | if (!dig || !dig->afmt) |
| 478 | return; |
| 479 | |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 480 | /* Older chipsets require setting HDMI and routing manually */ |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 481 | if (!ASIC_IS_DCE3(rdev)) { |
| 482 | if (enable) |
| 483 | hdmi |= HDMI0_ENABLE; |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 484 | switch (radeon_encoder->encoder_id) { |
| 485 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 486 | if (enable) { |
| 487 | WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); |
| 488 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); |
| 489 | } else { |
| 490 | WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); |
| 491 | } |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 492 | break; |
| 493 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 494 | if (enable) { |
| 495 | WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); |
| 496 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); |
| 497 | } else { |
| 498 | WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); |
| 499 | } |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 500 | break; |
| 501 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 502 | if (enable) { |
| 503 | WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); |
| 504 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); |
| 505 | } else { |
| 506 | WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); |
| 507 | } |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 508 | break; |
| 509 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 510 | if (enable) |
| 511 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 512 | break; |
| 513 | default: |
Rafał Miłecki | 64fb4fb | 2012-04-30 15:44:53 +0200 | [diff] [blame] | 514 | dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", |
| 515 | radeon_encoder->encoder_id); |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 516 | break; |
| 517 | } |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 518 | WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi); |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 519 | } |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 520 | |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 521 | if (rdev->irq.installed) { |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 522 | /* if irq is available use it */ |
Alex Deucher | 9054ae1 | 2013-04-18 09:42:13 -0400 | [diff] [blame] | 523 | /* XXX: shouldn't need this on any asics. Double check DCE2/3 */ |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 524 | if (enable) |
Alex Deucher | 9054ae1 | 2013-04-18 09:42:13 -0400 | [diff] [blame] | 525 | radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 526 | else |
| 527 | radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 528 | } |
Christian König | 58bd086 | 2010-04-05 22:14:55 +0200 | [diff] [blame] | 529 | |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 530 | dig->afmt->enabled = enable; |
Rafał Miłecki | cfcbd6d | 2012-05-14 16:52:30 +0200 | [diff] [blame] | 531 | |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 532 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
| 533 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 534 | } |
| 535 | |