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gerrit-public.fairphone.software / kernel / msm-4.9 / 41cae2d01385af4199666db57274c0df3283b065 / . / drivers / net / wireless / rtlwifi / rtl8192c / phy_common.c
blob: a70228278398ab2c893391e963a7f520327d1026 [file] [log] [blame]
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]30#include "../wifi.h"
31#include "../rtl8192ce/reg.h"
32#include "../rtl8192ce/def.h"
33#include "dm_common.h"
34#include "phy_common.h"
35
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]36/* Define macro to shorten lines */
37#define MCS_TXPWR mcs_txpwrlevel_origoffset
38
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]39u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
40{
41 struct rtl_priv *rtlpriv = rtl_priv(hw);
42 u32 returnvalue, originalvalue, bitshift;
43
44 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
45 "bitmask(%#x)\n", regaddr,
46 bitmask));
47 originalvalue = rtl_read_dword(rtlpriv, regaddr);
48 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
49 returnvalue = (originalvalue & bitmask) >> bitshift;
50
51 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("BBR MASK=0x%x "
52 "Addr[0x%x]=0x%x\n", bitmask,
53 regaddr, originalvalue));
54
55 return returnvalue;
56
57}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]58EXPORT_SYMBOL(rtl92c_phy_query_bb_reg);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]59
60void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
61 u32 regaddr, u32 bitmask, u32 data)
62{
63 struct rtl_priv *rtlpriv = rtl_priv(hw);
64 u32 originalvalue, bitshift;
65
66 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
67 " data(%#x)\n", regaddr, bitmask,
68 data));
69
70 if (bitmask != MASKDWORD) {
71 originalvalue = rtl_read_dword(rtlpriv, regaddr);
72 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
73 data = ((originalvalue & (~bitmask)) | (data << bitshift));
74 }
75
76 rtl_write_dword(rtlpriv, regaddr, data);
77
78 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
79 " data(%#x)\n", regaddr, bitmask,
80 data));
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]81}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]82EXPORT_SYMBOL(rtl92c_phy_set_bb_reg);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]83
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]84u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]85 enum radio_path rfpath, u32 offset)
86{
87 RT_ASSERT(false, ("deprecated!\n"));
88 return 0;
89}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]90EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_read);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]91
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]92void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]93 enum radio_path rfpath, u32 offset,
94 u32 data)
95{
96 RT_ASSERT(false, ("deprecated!\n"));
97}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]98EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_write);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]99
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]100u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]101 enum radio_path rfpath, u32 offset)
102{
103 struct rtl_priv *rtlpriv = rtl_priv(hw);
104 struct rtl_phy *rtlphy = &(rtlpriv->phy);
105 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
106 u32 newoffset;
107 u32 tmplong, tmplong2;
108 u8 rfpi_enable = 0;
109 u32 retvalue;
110
111 offset &= 0x3f;
112 newoffset = offset;
113 if (RT_CANNOT_IO(hw)) {
114 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("return all one\n"));
115 return 0xFFFFFFFF;
116 }
117 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
118 if (rfpath == RF90_PATH_A)
119 tmplong2 = tmplong;
120 else
121 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
122 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
123 (newoffset << 23) | BLSSIREADEDGE;
124 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
125 tmplong & (~BLSSIREADEDGE));
126 mdelay(1);
127 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
128 mdelay(1);
129 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
130 tmplong | BLSSIREADEDGE);
131 mdelay(1);
132 if (rfpath == RF90_PATH_A)
133 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
134 BIT(8));
135 else if (rfpath == RF90_PATH_B)
136 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
137 BIT(8));
138 if (rfpi_enable)
139 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
140 BLSSIREADBACKDATA);
141 else
142 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
143 BLSSIREADBACKDATA);
144 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFR-%d Addr[0x%x]=0x%x\n",
145 rfpath, pphyreg->rflssi_readback,
146 retvalue));
147 return retvalue;
148}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]149EXPORT_SYMBOL(_rtl92c_phy_rf_serial_read);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]150
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]151void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]152 enum radio_path rfpath, u32 offset,
153 u32 data)
154{
155 u32 data_and_addr;
156 u32 newoffset;
157 struct rtl_priv *rtlpriv = rtl_priv(hw);
158 struct rtl_phy *rtlphy = &(rtlpriv->phy);
159 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
160
161 if (RT_CANNOT_IO(hw)) {
162 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("stop\n"));
163 return;
164 }
165 offset &= 0x3f;
166 newoffset = offset;
167 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
168 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
169 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFW-%d Addr[0x%x]=0x%x\n",
170 rfpath, pphyreg->rf3wire_offset,
171 data_and_addr));
172}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]173EXPORT_SYMBOL(_rtl92c_phy_rf_serial_write);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]174
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]175u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask)
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]176{
177 u32 i;
178
179 for (i = 0; i <= 31; i++) {
180 if (((bitmask >> i) & 0x1) == 1)
181 break;
182 }
183 return i;
184}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]185EXPORT_SYMBOL(_rtl92c_phy_calculate_bit_shift);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]186
187static void _rtl92c_phy_bb_config_1t(struct ieee80211_hw *hw)
188{
189 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
190 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
191 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
192 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
193 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
194 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
195 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
196 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
197 rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
198 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
199}
200bool rtl92c_phy_rf_config(struct ieee80211_hw *hw)
201{
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]202 struct rtl_priv *rtlpriv = rtl_priv(hw);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]203
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]204 return rtlpriv->cfg->ops->phy_rf6052_config(hw);
205}
206EXPORT_SYMBOL(rtl92c_phy_rf_config);
207
208bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]209{
210 struct rtl_priv *rtlpriv = rtl_priv(hw);
211 struct rtl_phy *rtlphy = &(rtlpriv->phy);
212 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
213 bool rtstatus;
214
215 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("==>\n"));
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]216 rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]217 BASEBAND_CONFIG_PHY_REG);
218 if (rtstatus != true) {
219 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Write BB Reg Fail!!"));
220 return false;
221 }
222 if (rtlphy->rf_type == RF_1T2R) {
223 _rtl92c_phy_bb_config_1t(hw);
224 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Config to 1T!!\n"));
225 }
226 if (rtlefuse->autoload_failflag == false) {
227 rtlphy->pwrgroup_cnt = 0;
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]228 rtstatus = rtlpriv->cfg->ops->config_bb_with_pgheaderfile(hw,
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]229 BASEBAND_CONFIG_PHY_REG);
230 }
231 if (rtstatus != true) {
232 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("BB_PG Reg Fail!!"));
233 return false;
234 }
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]235 rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]236 BASEBAND_CONFIG_AGC_TAB);
237 if (rtstatus != true) {
238 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("AGC Table Fail\n"));
239 return false;
240 }
241 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
242 RFPGA0_XA_HSSIPARAMETER2,
243 0x200));
244 return true;
245}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]246EXPORT_SYMBOL(_rtl92c_phy_bb8192c_config_parafile);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]247
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]248void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]249 u32 regaddr, u32 bitmask,
250 u32 data)
251{
252 struct rtl_priv *rtlpriv = rtl_priv(hw);
253 struct rtl_phy *rtlphy = &(rtlpriv->phy);
254
255 if (regaddr == RTXAGC_A_RATE18_06) {
256 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][0] = data;
257 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
258 ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
259 rtlphy->pwrgroup_cnt,
260 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][0]));
261 }
262 if (regaddr == RTXAGC_A_RATE54_24) {
263 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][1] = data;
264 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
265 ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
266 rtlphy->pwrgroup_cnt,
267 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][1]));
268 }
269 if (regaddr == RTXAGC_A_CCK1_MCS32) {
270 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][6] = data;
271 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
272 ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
273 rtlphy->pwrgroup_cnt,
274 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][6]));
275 }
276 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
277 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][7] = data;
278 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
279 ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
280 rtlphy->pwrgroup_cnt,
281 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][7]));
282 }
283 if (regaddr == RTXAGC_A_MCS03_MCS00) {
284 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][2] = data;
285 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
286 ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
287 rtlphy->pwrgroup_cnt,
288 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][2]));
289 }
290 if (regaddr == RTXAGC_A_MCS07_MCS04) {
291 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][3] = data;
292 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
293 ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
294 rtlphy->pwrgroup_cnt,
295 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][3]));
296 }
297 if (regaddr == RTXAGC_A_MCS11_MCS08) {
298 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][4] = data;
299 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
300 ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
301 rtlphy->pwrgroup_cnt,
302 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][4]));
303 }
304 if (regaddr == RTXAGC_A_MCS15_MCS12) {
305 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][5] = data;
306 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
307 ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
308 rtlphy->pwrgroup_cnt,
309 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][5]));
310 }
311 if (regaddr == RTXAGC_B_RATE18_06) {
312 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][8] = data;
313 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
314 ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
315 rtlphy->pwrgroup_cnt,
316 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][8]));
317 }
318 if (regaddr == RTXAGC_B_RATE54_24) {
319 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][9] = data;
320
321 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
322 ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
323 rtlphy->pwrgroup_cnt,
324 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][9]));
325 }
326
327 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
328 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][14] = data;
329
330 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
331 ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
332 rtlphy->pwrgroup_cnt,
333 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][14]));
334 }
335
336 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
337 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][15] = data;
338
339 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
340 ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
341 rtlphy->pwrgroup_cnt,
342 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][15]));
343 }
344
345 if (regaddr == RTXAGC_B_MCS03_MCS00) {
346 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][10] = data;
347
348 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
349 ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
350 rtlphy->pwrgroup_cnt,
351 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][10]));
352 }
353
354 if (regaddr == RTXAGC_B_MCS07_MCS04) {
355 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][11] = data;
356
357 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
358 ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
359 rtlphy->pwrgroup_cnt,
360 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][11]));
361 }
362
363 if (regaddr == RTXAGC_B_MCS11_MCS08) {
364 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][12] = data;
365
366 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
367 ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
368 rtlphy->pwrgroup_cnt,
369 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][12]));
370 }
371
372 if (regaddr == RTXAGC_B_MCS15_MCS12) {
373 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][13] = data;
374
375 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
376 ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
377 rtlphy->pwrgroup_cnt,
378 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][13]));
379
380 rtlphy->pwrgroup_cnt++;
381 }
382}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]383EXPORT_SYMBOL(_rtl92c_store_pwrIndex_diffrate_offset);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]384
385void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
386{
387 struct rtl_priv *rtlpriv = rtl_priv(hw);
388 struct rtl_phy *rtlphy = &(rtlpriv->phy);
389
390 rtlphy->default_initialgain[0] =
391 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
392 rtlphy->default_initialgain[1] =
393 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
394 rtlphy->default_initialgain[2] =
395 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
396 rtlphy->default_initialgain[3] =
397 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
398
399 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
400 ("Default initial gain (c50=0x%x, "
401 "c58=0x%x, c60=0x%x, c68=0x%x\n",
402 rtlphy->default_initialgain[0],
403 rtlphy->default_initialgain[1],
404 rtlphy->default_initialgain[2],
405 rtlphy->default_initialgain[3]));
406
407 rtlphy->framesync = (u8) rtl_get_bbreg(hw,
408 ROFDM0_RXDETECTOR3, MASKBYTE0);
409 rtlphy->framesync_c34 = rtl_get_bbreg(hw,
410 ROFDM0_RXDETECTOR2, MASKDWORD);
411
412 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
413 ("Default framesync (0x%x) = 0x%x\n",
414 ROFDM0_RXDETECTOR3, rtlphy->framesync));
415}
416
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]417void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]418{
419 struct rtl_priv *rtlpriv = rtl_priv(hw);
420 struct rtl_phy *rtlphy = &(rtlpriv->phy);
421
422 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
423 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
424 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
425 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
426
427 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
428 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
429 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
430 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
431
432 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
433 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
434
435 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
436 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
437
438 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
439 RFPGA0_XA_LSSIPARAMETER;
440 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
441 RFPGA0_XB_LSSIPARAMETER;
442
443 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
444 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
445 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
446 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
447
448 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
449 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
450 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
451 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
452
453 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
454 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
455
456 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
457 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
458
459 rtlphy->phyreg_def[RF90_PATH_A].rfswitch_control =
460 RFPGA0_XAB_SWITCHCONTROL;
461 rtlphy->phyreg_def[RF90_PATH_B].rfswitch_control =
462 RFPGA0_XAB_SWITCHCONTROL;
463 rtlphy->phyreg_def[RF90_PATH_C].rfswitch_control =
464 RFPGA0_XCD_SWITCHCONTROL;
465 rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control =
466 RFPGA0_XCD_SWITCHCONTROL;
467
468 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
469 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
470 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
471 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
472
473 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
474 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
475 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
476 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
477
478 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbalance =
479 ROFDM0_XARXIQIMBALANCE;
480 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbalance =
481 ROFDM0_XBRXIQIMBALANCE;
482 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbalance =
483 ROFDM0_XCRXIQIMBANLANCE;
484 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance =
485 ROFDM0_XDRXIQIMBALANCE;
486
487 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
488 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
489 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
490 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
491
492 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbalance =
493 ROFDM0_XATXIQIMBALANCE;
494 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbalance =
495 ROFDM0_XBTXIQIMBALANCE;
496 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbalance =
497 ROFDM0_XCTXIQIMBALANCE;
498 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance =
499 ROFDM0_XDTXIQIMBALANCE;
500
501 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
502 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
503 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
504 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
505
506 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback =
507 RFPGA0_XA_LSSIREADBACK;
508 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback =
509 RFPGA0_XB_LSSIREADBACK;
510 rtlphy->phyreg_def[RF90_PATH_C].rflssi_readback =
511 RFPGA0_XC_LSSIREADBACK;
512 rtlphy->phyreg_def[RF90_PATH_D].rflssi_readback =
513 RFPGA0_XD_LSSIREADBACK;
514
515 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi =
516 TRANSCEIVEA_HSPI_READBACK;
517 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi =
518 TRANSCEIVEB_HSPI_READBACK;
519
520}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]521EXPORT_SYMBOL(_rtl92c_phy_init_bb_rf_register_definition);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]522
523void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
524{
525 struct rtl_priv *rtlpriv = rtl_priv(hw);
526 struct rtl_phy *rtlphy = &(rtlpriv->phy);
527 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
528 u8 txpwr_level;
529 long txpwr_dbm;
530
531 txpwr_level = rtlphy->cur_cck_txpwridx;
532 txpwr_dbm = _rtl92c_phy_txpwr_idx_to_dbm(hw,
533 WIRELESS_MODE_B, txpwr_level);
534 txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
535 rtlefuse->legacy_ht_txpowerdiff;
536 if (_rtl92c_phy_txpwr_idx_to_dbm(hw,
537 WIRELESS_MODE_G,
538 txpwr_level) > txpwr_dbm)
539 txpwr_dbm =
540 _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
541 txpwr_level);
542 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
543 if (_rtl92c_phy_txpwr_idx_to_dbm(hw,
544 WIRELESS_MODE_N_24G,
545 txpwr_level) > txpwr_dbm)
546 txpwr_dbm =
547 _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
548 txpwr_level);
549 *powerlevel = txpwr_dbm;
550}
551
552static void _rtl92c_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
553 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
554{
555 struct rtl_priv *rtlpriv = rtl_priv(hw);
556 struct rtl_phy *rtlphy = &(rtlpriv->phy);
557 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
558 u8 index = (channel - 1);
559
560 cckpowerlevel[RF90_PATH_A] =
561 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
562 cckpowerlevel[RF90_PATH_B] =
563 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
564 if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
565 ofdmpowerlevel[RF90_PATH_A] =
566 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
567 ofdmpowerlevel[RF90_PATH_B] =
568 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
569 } else if (get_rf_type(rtlphy) == RF_2T2R) {
570 ofdmpowerlevel[RF90_PATH_A] =
571 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
572 ofdmpowerlevel[RF90_PATH_B] =
573 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
574 }
575}
576
577static void _rtl92c_ccxpower_index_check(struct ieee80211_hw *hw,
578 u8 channel, u8 *cckpowerlevel,
579 u8 *ofdmpowerlevel)
580{
581 struct rtl_priv *rtlpriv = rtl_priv(hw);
582 struct rtl_phy *rtlphy = &(rtlpriv->phy);
583
584 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
585 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
586}
587
588void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
589{
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]590 struct rtl_priv *rtlpriv = rtl_priv(hw);
591 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]592 u8 cckpowerlevel[2], ofdmpowerlevel[2];
593
594 if (rtlefuse->txpwr_fromeprom == false)
595 return;
596 _rtl92c_get_txpower_index(hw, channel,
597 &cckpowerlevel[0], &ofdmpowerlevel[0]);
598 _rtl92c_ccxpower_index_check(hw,
599 channel, &cckpowerlevel[0],
600 &ofdmpowerlevel[0]);
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]601 rtlpriv->cfg->ops->phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
602 rtlpriv->cfg->ops->phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0],
603 channel);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]604}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]605EXPORT_SYMBOL(rtl92c_phy_set_txpower_level);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]606
607bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
608{
609 struct rtl_priv *rtlpriv = rtl_priv(hw);
610 struct rtl_phy *rtlphy = &(rtlpriv->phy);
611 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
612 u8 idx;
613 u8 rf_path;
614
615 u8 ccktxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw,
616 WIRELESS_MODE_B,
617 power_indbm);
618 u8 ofdmtxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw,
619 WIRELESS_MODE_N_24G,
620 power_indbm);
621 if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
622 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
623 else
624 ofdmtxpwridx = 0;
625 RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
626 ("%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
627 power_indbm, ccktxpwridx, ofdmtxpwridx));
628 for (idx = 0; idx < 14; idx++) {
629 for (rf_path = 0; rf_path < 2; rf_path++) {
630 rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
631 rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
632 ofdmtxpwridx;
633 rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
634 ofdmtxpwridx;
635 }
636 }
637 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
638 return true;
639}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]640EXPORT_SYMBOL(rtl92c_phy_update_txpower_dbm);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]641
642void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw, u16 beaconinterval)
643{
644}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]645EXPORT_SYMBOL(rtl92c_phy_set_beacon_hw_reg);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]646
Johannes Berg41cae2d2011-02-24 20:39:05 +0100[diff] [blame^]647u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
648 enum wireless_mode wirelessmode,
649 long power_indbm)
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]650{
651 u8 txpwridx;
652 long offset;
653
654 switch (wirelessmode) {
655 case WIRELESS_MODE_B:
656 offset = -7;
657 break;
658 case WIRELESS_MODE_G:
659 case WIRELESS_MODE_N_24G:
660 offset = -8;
661 break;
662 default:
663 offset = -8;
664 break;
665 }
666
667 if ((power_indbm - offset) > 0)
668 txpwridx = (u8) ((power_indbm - offset) * 2);
669 else
670 txpwridx = 0;
671
672 if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
673 txpwridx = MAX_TXPWR_IDX_NMODE_92S;
674
675 return txpwridx;
676}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]677EXPORT_SYMBOL(_rtl92c_phy_dbm_to_txpwr_Idx);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]678
Johannes Berg41cae2d2011-02-24 20:39:05 +0100[diff] [blame^]679long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
680 enum wireless_mode wirelessmode,
681 u8 txpwridx)
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]682{
683 long offset;
684 long pwrout_dbm;
685
686 switch (wirelessmode) {
687 case WIRELESS_MODE_B:
688 offset = -7;
689 break;
690 case WIRELESS_MODE_G:
691 case WIRELESS_MODE_N_24G:
692 offset = -8;
693 break;
694 default:
695 offset = -8;
696 break;
697 }
698 pwrout_dbm = txpwridx / 2 + offset;
699 return pwrout_dbm;
700}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]701EXPORT_SYMBOL(_rtl92c_phy_txpwr_idx_to_dbm);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]702
703void rtl92c_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
704{
705 struct rtl_priv *rtlpriv = rtl_priv(hw);
706 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
707 enum io_type iotype;
708
709 if (!is_hal_stop(rtlhal)) {
710 switch (operation) {
711 case SCAN_OPT_BACKUP:
712 iotype = IO_CMD_PAUSE_DM_BY_SCAN;
713 rtlpriv->cfg->ops->set_hw_reg(hw,
714 HW_VAR_IO_CMD,
715 (u8 *)&iotype);
716
717 break;
718 case SCAN_OPT_RESTORE:
719 iotype = IO_CMD_RESUME_DM_BY_SCAN;
720 rtlpriv->cfg->ops->set_hw_reg(hw,
721 HW_VAR_IO_CMD,
722 (u8 *)&iotype);
723 break;
724 default:
725 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
726 ("Unknown Scan Backup operation.\n"));
727 break;
728 }
729 }
730}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]731EXPORT_SYMBOL(rtl92c_phy_scan_operation_backup);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]732
733void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
734 enum nl80211_channel_type ch_type)
735{
736 struct rtl_priv *rtlpriv = rtl_priv(hw);
737 struct rtl_phy *rtlphy = &(rtlpriv->phy);
738 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
739 u8 tmp_bw = rtlphy->current_chan_bw;
740
741 if (rtlphy->set_bwmode_inprogress)
742 return;
743 rtlphy->set_bwmode_inprogress = true;
744 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw)))
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]745 rtlpriv->cfg->ops->phy_set_bw_mode_callback(hw);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]746 else {
747 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
748 ("FALSE driver sleep or unload\n"));
749 rtlphy->set_bwmode_inprogress = false;
750 rtlphy->current_chan_bw = tmp_bw;
751 }
752}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]753EXPORT_SYMBOL(rtl92c_phy_set_bw_mode);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]754
755void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw)
756{
757 struct rtl_priv *rtlpriv = rtl_priv(hw);
758 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
759 struct rtl_phy *rtlphy = &(rtlpriv->phy);
760 u32 delay;
761
762 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
763 ("switch to channel%d\n", rtlphy->current_channel));
764 if (is_hal_stop(rtlhal))
765 return;
766 do {
767 if (!rtlphy->sw_chnl_inprogress)
768 break;
769 if (!_rtl92c_phy_sw_chnl_step_by_step
770 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
771 &rtlphy->sw_chnl_step, &delay)) {
772 if (delay > 0)
773 mdelay(delay);
774 else
775 continue;
776 } else
777 rtlphy->sw_chnl_inprogress = false;
778 break;
779 } while (true);
780 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
781}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]782EXPORT_SYMBOL(rtl92c_phy_sw_chnl_callback);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]783
784u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
785{
786 struct rtl_priv *rtlpriv = rtl_priv(hw);
787 struct rtl_phy *rtlphy = &(rtlpriv->phy);
788 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
789
790 if (rtlphy->sw_chnl_inprogress)
791 return 0;
792 if (rtlphy->set_bwmode_inprogress)
793 return 0;
794 RT_ASSERT((rtlphy->current_channel <= 14),
795 ("WIRELESS_MODE_G but channel>14"));
796 rtlphy->sw_chnl_inprogress = true;
797 rtlphy->sw_chnl_stage = 0;
798 rtlphy->sw_chnl_step = 0;
799 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
800 rtl92c_phy_sw_chnl_callback(hw);
801 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
802 ("sw_chnl_inprogress false schdule workitem\n"));
803 rtlphy->sw_chnl_inprogress = false;
804 } else {
805 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
806 ("sw_chnl_inprogress false driver sleep or"
807 " unload\n"));
808 rtlphy->sw_chnl_inprogress = false;
809 }
810 return 1;
811}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]812EXPORT_SYMBOL(rtl92c_phy_sw_chnl);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]813
814static bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
815 u8 channel, u8 *stage, u8 *step,
816 u32 *delay)
817{
818 struct rtl_priv *rtlpriv = rtl_priv(hw);
819 struct rtl_phy *rtlphy = &(rtlpriv->phy);
820 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
821 u32 precommoncmdcnt;
822 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
823 u32 postcommoncmdcnt;
824 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
825 u32 rfdependcmdcnt;
826 struct swchnlcmd *currentcmd = NULL;
827 u8 rfpath;
828 u8 num_total_rfpath = rtlphy->num_total_rfpath;
829
830 precommoncmdcnt = 0;
831 _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
832 MAX_PRECMD_CNT,
833 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
834 _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
835 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
836
837 postcommoncmdcnt = 0;
838
839 _rtl92c_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
840 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
841
842 rfdependcmdcnt = 0;
843
844 RT_ASSERT((channel >= 1 && channel <= 14),
845 ("illegal channel for Zebra: %d\n", channel));
846
847 _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
848 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
849 RF_CHNLBW, channel, 10);
850
851 _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
852 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
853 0);
854
855 do {
856 switch (*stage) {
857 case 0:
858 currentcmd = &precommoncmd[*step];
859 break;
860 case 1:
861 currentcmd = &rfdependcmd[*step];
862 break;
863 case 2:
864 currentcmd = &postcommoncmd[*step];
865 break;
866 }
867
868 if (currentcmd->cmdid == CMDID_END) {
869 if ((*stage) == 2) {
870 return true;
871 } else {
872 (*stage)++;
873 (*step) = 0;
874 continue;
875 }
876 }
877
878 switch (currentcmd->cmdid) {
879 case CMDID_SET_TXPOWEROWER_LEVEL:
880 rtl92c_phy_set_txpower_level(hw, channel);
881 break;
882 case CMDID_WRITEPORT_ULONG:
883 rtl_write_dword(rtlpriv, currentcmd->para1,
884 currentcmd->para2);
885 break;
886 case CMDID_WRITEPORT_USHORT:
887 rtl_write_word(rtlpriv, currentcmd->para1,
888 (u16) currentcmd->para2);
889 break;
890 case CMDID_WRITEPORT_UCHAR:
891 rtl_write_byte(rtlpriv, currentcmd->para1,
892 (u8) currentcmd->para2);
893 break;
894 case CMDID_RF_WRITEREG:
895 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
896 rtlphy->rfreg_chnlval[rfpath] =
897 ((rtlphy->rfreg_chnlval[rfpath] &
898 0xfffffc00) | currentcmd->para2);
899
900 rtl_set_rfreg(hw, (enum radio_path)rfpath,
901 currentcmd->para1,
902 RFREG_OFFSET_MASK,
903 rtlphy->rfreg_chnlval[rfpath]);
904 }
905 break;
906 default:
907 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
908 ("switch case not process\n"));
909 break;
910 }
911
912 break;
913 } while (true);
914
915 (*delay) = currentcmd->msdelay;
916 (*step)++;
917 return false;
918}
919
920static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
921 u32 cmdtableidx, u32 cmdtablesz,
922 enum swchnlcmd_id cmdid,
923 u32 para1, u32 para2, u32 msdelay)
924{
925 struct swchnlcmd *pcmd;
926
927 if (cmdtable == NULL) {
928 RT_ASSERT(false, ("cmdtable cannot be NULL.\n"));
929 return false;
930 }
931
932 if (cmdtableidx >= cmdtablesz)
933 return false;
934
935 pcmd = cmdtable + cmdtableidx;
936 pcmd->cmdid = cmdid;
937 pcmd->para1 = para1;
938 pcmd->para2 = para2;
939 pcmd->msdelay = msdelay;
940 return true;
941}
942
943bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, u32 rfpath)
944{
945 return true;
946}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]947EXPORT_SYMBOL(rtl8192_phy_check_is_legal_rfpath);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]948
949static u8 _rtl92c_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
950{
951 u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
952 u8 result = 0x00;
953
954 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
955 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
956 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
957 rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
958 config_pathb ? 0x28160202 : 0x28160502);
959
960 if (config_pathb) {
961 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
962 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
963 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
964 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
965 }
966
967 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
968 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
969 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
970
971 mdelay(IQK_DELAY_TIME);
972
973 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
974 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
975 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
976 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
977
978 if (!(reg_eac & BIT(28)) &&
979 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
980 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
981 result |= 0x01;
982 else
983 return result;
984
985 if (!(reg_eac & BIT(27)) &&
986 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
987 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
988 result |= 0x02;
989 return result;
990}
991
992static u8 _rtl92c_phy_path_b_iqk(struct ieee80211_hw *hw)
993{
994 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
995 u8 result = 0x00;
996
997 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
998 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
999 mdelay(IQK_DELAY_TIME);
1000 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1001 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1002 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1003 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1004 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1005 if (!(reg_eac & BIT(31)) &&
1006 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1007 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1008 result |= 0x01;
1009 else
1010 return result;
1011
1012 if (!(reg_eac & BIT(30)) &&
1013 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1014 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1015 result |= 0x02;
1016 return result;
1017}
1018
1019static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
1020 bool iqk_ok, long result[][8],
1021 u8 final_candidate, bool btxonly)
1022{
1023 u32 oldval_0, x, tx0_a, reg;
1024 long y, tx0_c;
1025
1026 if (final_candidate == 0xFF)
1027 return;
1028 else if (iqk_ok) {
1029 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1030 MASKDWORD) >> 22) & 0x3FF;
1031 x = result[final_candidate][0];
1032 if ((x & 0x00000200) != 0)
1033 x = x | 0xFFFFFC00;
1034 tx0_a = (x * oldval_0) >> 8;
1035 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
1036 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
1037 ((x * oldval_0 >> 7) & 0x1));
1038 y = result[final_candidate][1];
1039 if ((y & 0x00000200) != 0)
1040 y = y | 0xFFFFFC00;
1041 tx0_c = (y * oldval_0) >> 8;
1042 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1043 ((tx0_c & 0x3C0) >> 6));
1044 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
1045 (tx0_c & 0x3F));
1046 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1047 ((y * oldval_0 >> 7) & 0x1));
1048 if (btxonly)
1049 return;
1050 reg = result[final_candidate][2];
1051 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1052 reg = result[final_candidate][3] & 0x3F;
1053 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1054 reg = (result[final_candidate][3] >> 6) & 0xF;
1055 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1056 }
1057}
1058
1059static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
1060 bool iqk_ok, long result[][8],
1061 u8 final_candidate, bool btxonly)
1062{
1063 u32 oldval_1, x, tx1_a, reg;
1064 long y, tx1_c;
1065
1066 if (final_candidate == 0xFF)
1067 return;
1068 else if (iqk_ok) {
1069 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
1070 MASKDWORD) >> 22) & 0x3FF;
1071 x = result[final_candidate][4];
1072 if ((x & 0x00000200) != 0)
1073 x = x | 0xFFFFFC00;
1074 tx1_a = (x * oldval_1) >> 8;
1075 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
1076 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
1077 ((x * oldval_1 >> 7) & 0x1));
1078 y = result[final_candidate][5];
1079 if ((y & 0x00000200) != 0)
1080 y = y | 0xFFFFFC00;
1081 tx1_c = (y * oldval_1) >> 8;
1082 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
1083 ((tx1_c & 0x3C0) >> 6));
1084 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
1085 (tx1_c & 0x3F));
1086 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
1087 ((y * oldval_1 >> 7) & 0x1));
1088 if (btxonly)
1089 return;
1090 reg = result[final_candidate][6];
1091 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
1092 reg = result[final_candidate][7] & 0x3F;
1093 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
1094 reg = (result[final_candidate][7] >> 6) & 0xF;
1095 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
1096 }
1097}
1098
1099static void _rtl92c_phy_save_adda_registers(struct ieee80211_hw *hw,
1100 u32 *addareg, u32 *addabackup,
1101 u32 registernum)
1102{
1103 u32 i;
1104
1105 for (i = 0; i < registernum; i++)
1106 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1107}
1108
1109static void _rtl92c_phy_save_mac_registers(struct ieee80211_hw *hw,
1110 u32 *macreg, u32 *macbackup)
1111{
1112 struct rtl_priv *rtlpriv = rtl_priv(hw);
1113 u32 i;
1114
1115 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1116 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1117 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1118}
1119
1120static void _rtl92c_phy_reload_adda_registers(struct ieee80211_hw *hw,
1121 u32 *addareg, u32 *addabackup,
1122 u32 regiesternum)
1123{
1124 u32 i;
1125
1126 for (i = 0; i < regiesternum; i++)
1127 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1128}
1129
1130static void _rtl92c_phy_reload_mac_registers(struct ieee80211_hw *hw,
1131 u32 *macreg, u32 *macbackup)
1132{
1133 struct rtl_priv *rtlpriv = rtl_priv(hw);
1134 u32 i;
1135
1136 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1137 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1138 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1139}
1140
1141static void _rtl92c_phy_path_adda_on(struct ieee80211_hw *hw,
1142 u32 *addareg, bool is_patha_on, bool is2t)
1143{
1144 u32 pathOn;
1145 u32 i;
1146
1147 pathOn = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1148 if (false == is2t) {
1149 pathOn = 0x0bdb25a0;
1150 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1151 } else {
1152 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn);
1153 }
1154
1155 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1156 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn);
1157}
1158
1159static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1160 u32 *macreg, u32 *macbackup)
1161{
1162 struct rtl_priv *rtlpriv = rtl_priv(hw);
1163 u32 i;
1164
1165 rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1166
1167 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1168 rtl_write_byte(rtlpriv, macreg[i],
1169 (u8) (macbackup[i] & (~BIT(3))));
1170 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1171}
1172
1173static void _rtl92c_phy_path_a_standby(struct ieee80211_hw *hw)
1174{
1175 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1176 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1177 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1178}
1179
1180static void _rtl92c_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1181{
1182 u32 mode;
1183
1184 mode = pi_mode ? 0x01000100 : 0x01000000;
1185 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1186 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1187}
1188
1189static bool _rtl92c_phy_simularity_compare(struct ieee80211_hw *hw,
1190 long result[][8], u8 c1, u8 c2)
1191{
1192 u32 i, j, diff, simularity_bitmap, bound;
1193 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1194
1195 u8 final_candidate[2] = { 0xFF, 0xFF };
1196 bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1197
1198 if (is2t)
1199 bound = 8;
1200 else
1201 bound = 4;
1202
1203 simularity_bitmap = 0;
1204
1205 for (i = 0; i < bound; i++) {
1206 diff = (result[c1][i] > result[c2][i]) ?
1207 (result[c1][i] - result[c2][i]) :
1208 (result[c2][i] - result[c1][i]);
1209
1210 if (diff > MAX_TOLERANCE) {
1211 if ((i == 2 || i == 6) && !simularity_bitmap) {
1212 if (result[c1][i] + result[c1][i + 1] == 0)
1213 final_candidate[(i / 4)] = c2;
1214 else if (result[c2][i] + result[c2][i + 1] == 0)
1215 final_candidate[(i / 4)] = c1;
1216 else
1217 simularity_bitmap = simularity_bitmap |
1218 (1 << i);
1219 } else
1220 simularity_bitmap =
1221 simularity_bitmap | (1 << i);
1222 }
1223 }
1224
1225 if (simularity_bitmap == 0) {
1226 for (i = 0; i < (bound / 4); i++) {
1227 if (final_candidate[i] != 0xFF) {
1228 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1229 result[3][j] =
1230 result[final_candidate[i]][j];
1231 bresult = false;
1232 }
1233 }
1234 return bresult;
1235 } else if (!(simularity_bitmap & 0x0F)) {
1236 for (i = 0; i < 4; i++)
1237 result[3][i] = result[c1][i];
1238 return false;
1239 } else if (!(simularity_bitmap & 0xF0) && is2t) {
1240 for (i = 4; i < 8; i++)
1241 result[3][i] = result[c1][i];
1242 return false;
1243 } else {
1244 return false;
1245 }
1246
1247}
1248
1249static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1250 long result[][8], u8 t, bool is2t)
1251{
1252 struct rtl_priv *rtlpriv = rtl_priv(hw);
1253 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1254 u32 i;
1255 u8 patha_ok, pathb_ok;
1256 u32 adda_reg[IQK_ADDA_REG_NUM] = {
1257 0x85c, 0xe6c, 0xe70, 0xe74,
1258 0xe78, 0xe7c, 0xe80, 0xe84,
1259 0xe88, 0xe8c, 0xed0, 0xed4,
1260 0xed8, 0xedc, 0xee0, 0xeec
1261 };
1262
1263 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1264 0x522, 0x550, 0x551, 0x040
1265 };
1266
1267 const u32 retrycount = 2;
1268
1269 u32 bbvalue;
1270
1271 if (t == 0) {
1272 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD);
1273
1274 _rtl92c_phy_save_adda_registers(hw, adda_reg,
1275 rtlphy->adda_backup, 16);
1276 _rtl92c_phy_save_mac_registers(hw, iqk_mac_reg,
1277 rtlphy->iqk_mac_backup);
1278 }
1279 _rtl92c_phy_path_adda_on(hw, adda_reg, true, is2t);
1280 if (t == 0) {
1281 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1282 RFPGA0_XA_HSSIPARAMETER1,
1283 BIT(8));
1284 }
1285 if (!rtlphy->rfpi_enable)
1286 _rtl92c_phy_pi_mode_switch(hw, true);
1287 if (t == 0) {
1288 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1289 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1290 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1291 }
1292 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1293 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1294 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1295 if (is2t) {
1296 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1297 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1298 }
1299 _rtl92c_phy_mac_setting_calibration(hw, iqk_mac_reg,
1300 rtlphy->iqk_mac_backup);
1301 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1302 if (is2t)
1303 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1304 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1305 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1306 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1307 for (i = 0; i < retrycount; i++) {
1308 patha_ok = _rtl92c_phy_path_a_iqk(hw, is2t);
1309 if (patha_ok == 0x03) {
1310 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1311 0x3FF0000) >> 16;
1312 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1313 0x3FF0000) >> 16;
1314 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1315 0x3FF0000) >> 16;
1316 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1317 0x3FF0000) >> 16;
1318 break;
1319 } else if (i == (retrycount - 1) && patha_ok == 0x01)
1320 result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1321 MASKDWORD) & 0x3FF0000) >>
1322 16;
1323 result[t][1] =
1324 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1325
1326 }
1327
1328 if (is2t) {
1329 _rtl92c_phy_path_a_standby(hw);
1330 _rtl92c_phy_path_adda_on(hw, adda_reg, false, is2t);
1331 for (i = 0; i < retrycount; i++) {
1332 pathb_ok = _rtl92c_phy_path_b_iqk(hw);
1333 if (pathb_ok == 0x03) {
1334 result[t][4] = (rtl_get_bbreg(hw,
1335 0xeb4,
1336 MASKDWORD) &
1337 0x3FF0000) >> 16;
1338 result[t][5] =
1339 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1340 0x3FF0000) >> 16;
1341 result[t][6] =
1342 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1343 0x3FF0000) >> 16;
1344 result[t][7] =
1345 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1346 0x3FF0000) >> 16;
1347 break;
1348 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1349 result[t][4] = (rtl_get_bbreg(hw,
1350 0xeb4,
1351 MASKDWORD) &
1352 0x3FF0000) >> 16;
1353 }
1354 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1355 0x3FF0000) >> 16;
1356 }
1357 }
1358 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1359 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1360 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1361 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1362 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1363 if (is2t)
1364 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1365 if (t != 0) {
1366 if (!rtlphy->rfpi_enable)
1367 _rtl92c_phy_pi_mode_switch(hw, false);
1368 _rtl92c_phy_reload_adda_registers(hw, adda_reg,
1369 rtlphy->adda_backup, 16);
1370 _rtl92c_phy_reload_mac_registers(hw, iqk_mac_reg,
1371 rtlphy->iqk_mac_backup);
1372 }
1373}
1374
1375static void _rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw,
1376 char delta, bool is2t)
1377{
1378 /* This routine is deliberately dummied out for later fixes */
1379#if 0
1380 struct rtl_priv *rtlpriv = rtl_priv(hw);
1381 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1382 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1383
1384 u32 reg_d[PATH_NUM];
1385 u32 tmpreg, index, offset, path, i, pathbound = PATH_NUM, apkbound;
1386
1387 u32 bb_backup[APK_BB_REG_NUM];
1388 u32 bb_reg[APK_BB_REG_NUM] = {
1389 0x904, 0xc04, 0x800, 0xc08, 0x874
1390 };
1391 u32 bb_ap_mode[APK_BB_REG_NUM] = {
1392 0x00000020, 0x00a05430, 0x02040000,
1393 0x000800e4, 0x00204000
1394 };
1395 u32 bb_normal_ap_mode[APK_BB_REG_NUM] = {
1396 0x00000020, 0x00a05430, 0x02040000,
1397 0x000800e4, 0x22204000
1398 };
1399
1400 u32 afe_backup[APK_AFE_REG_NUM];
1401 u32 afe_reg[APK_AFE_REG_NUM] = {
1402 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78,
1403 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c,
1404 0xed0, 0xed4, 0xed8, 0xedc, 0xee0,
1405 0xeec
1406 };
1407
1408 u32 mac_backup[IQK_MAC_REG_NUM];
1409 u32 mac_reg[IQK_MAC_REG_NUM] = {
1410 0x522, 0x550, 0x551, 0x040
1411 };
1412
1413 u32 apk_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1414 {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
1415 {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
1416 };
1417
1418 u32 apk_normal_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1419 {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c},
1420 {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
1421 };
1422
1423 u32 apk_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1424 {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
1425 {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
1426 };
1427
1428 u32 apk_normal_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1429 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a},
1430 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
1431 };
1432
1433 u32 afe_on_off[PATH_NUM] = {
1434 0x04db25a4, 0x0b1b25a4
1435 };
1436
1437 u32 apk_offset[PATH_NUM] = { 0xb68, 0xb6c };
1438
1439 u32 apk_normal_offset[PATH_NUM] = { 0xb28, 0xb98 };
1440
1441 u32 apk_value[PATH_NUM] = { 0x92fc0000, 0x12fc0000 };
1442
1443 u32 apk_normal_value[PATH_NUM] = { 0x92680000, 0x12680000 };
1444
1445 const char apk_delta_mapping[APK_BB_REG_NUM][13] = {
1446 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1447 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1448 {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1449 {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1450 {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
1451 };
1452
1453 const u32 apk_normal_setting_value_1[13] = {
1454 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
1455 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
1456 0x12680000, 0x00880000, 0x00880000
1457 };
1458
1459 const u32 apk_normal_setting_value_2[16] = {
1460 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
1461 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
1462 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
1463 0x00050006
1464 };
1465
1466 const u32 apk_result[PATH_NUM][APK_BB_REG_NUM];
1467
1468 long bb_offset, delta_v, delta_offset;
1469
1470 if (!is2t)
1471 pathbound = 1;
1472
1473 for (index = 0; index < PATH_NUM; index++) {
1474 apk_offset[index] = apk_normal_offset[index];
1475 apk_value[index] = apk_normal_value[index];
1476 afe_on_off[index] = 0x6fdb25a4;
1477 }
1478
1479 for (index = 0; index < APK_BB_REG_NUM; index++) {
1480 for (path = 0; path < pathbound; path++) {
1481 apk_rf_init_value[path][index] =
1482 apk_normal_rf_init_value[path][index];
1483 apk_rf_value_0[path][index] =
1484 apk_normal_rf_value_0[path][index];
1485 }
1486 bb_ap_mode[index] = bb_normal_ap_mode[index];
1487
1488 apkbound = 6;
1489 }
1490
1491 for (index = 0; index < APK_BB_REG_NUM; index++) {
1492 if (index == 0)
1493 continue;
1494 bb_backup[index] = rtl_get_bbreg(hw, bb_reg[index], MASKDWORD);
1495 }
1496
1497 _rtl92c_phy_save_mac_registers(hw, mac_reg, mac_backup);
1498
1499 _rtl92c_phy_save_adda_registers(hw, afe_reg, afe_backup, 16);
1500
1501 for (path = 0; path < pathbound; path++) {
1502 if (path == RF90_PATH_A) {
1503 offset = 0xb00;
1504 for (index = 0; index < 11; index++) {
1505 rtl_set_bbreg(hw, offset, MASKDWORD,
1506 apk_normal_setting_value_1
1507 [index]);
1508
1509 offset += 0x04;
1510 }
1511
1512 rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
1513
1514 offset = 0xb68;
1515 for (; index < 13; index++) {
1516 rtl_set_bbreg(hw, offset, MASKDWORD,
1517 apk_normal_setting_value_1
1518 [index]);
1519
1520 offset += 0x04;
1521 }
1522
1523 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
1524
1525 offset = 0xb00;
1526 for (index = 0; index < 16; index++) {
1527 rtl_set_bbreg(hw, offset, MASKDWORD,
1528 apk_normal_setting_value_2
1529 [index]);
1530
1531 offset += 0x04;
1532 }
1533 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1534 } else if (path == RF90_PATH_B) {
1535 offset = 0xb70;
1536 for (index = 0; index < 10; index++) {
1537 rtl_set_bbreg(hw, offset, MASKDWORD,
1538 apk_normal_setting_value_1
1539 [index]);
1540
1541 offset += 0x04;
1542 }
1543 rtl_set_bbreg(hw, 0xb28, MASKDWORD, 0x12680000);
1544 rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
1545
1546 offset = 0xb68;
1547 index = 11;
1548 for (; index < 13; index++) {
1549 rtl_set_bbreg(hw, offset, MASKDWORD,
1550 apk_normal_setting_value_1
1551 [index]);
1552
1553 offset += 0x04;
1554 }
1555
1556 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
1557
1558 offset = 0xb60;
1559 for (index = 0; index < 16; index++) {
1560 rtl_set_bbreg(hw, offset, MASKDWORD,
1561 apk_normal_setting_value_2
1562 [index]);
1563
1564 offset += 0x04;
1565 }
1566 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1567 }
1568
1569 reg_d[path] = rtl_get_rfreg(hw, (enum radio_path)path,
1570 0xd, MASKDWORD);
1571
1572 for (index = 0; index < APK_AFE_REG_NUM; index++)
1573 rtl_set_bbreg(hw, afe_reg[index], MASKDWORD,
1574 afe_on_off[path]);
1575
1576 if (path == RF90_PATH_A) {
1577 for (index = 0; index < APK_BB_REG_NUM; index++) {
1578 if (index == 0)
1579 continue;
1580 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD,
1581 bb_ap_mode[index]);
1582 }
1583 }
1584
1585 _rtl92c_phy_mac_setting_calibration(hw, mac_reg, mac_backup);
1586
1587 if (path == 0) {
1588 rtl_set_rfreg(hw, RF90_PATH_B, 0x0, MASKDWORD, 0x10000);
1589 } else {
1590 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASKDWORD,
1591 0x10000);
1592 rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
1593 0x1000f);
1594 rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
1595 0x20103);
1596 }
1597
1598 delta_offset = ((delta + 14) / 2);
1599 if (delta_offset < 0)
1600 delta_offset = 0;
1601 else if (delta_offset > 12)
1602 delta_offset = 12;
1603
1604 for (index = 0; index < APK_BB_REG_NUM; index++) {
1605 if (index != 1)
1606 continue;
1607
1608 tmpreg = apk_rf_init_value[path][index];
1609
1610 if (!rtlefuse->apk_thermalmeterignore) {
1611 bb_offset = (tmpreg & 0xF0000) >> 16;
1612
1613 if (!(tmpreg & BIT(15)))
1614 bb_offset = -bb_offset;
1615
1616 delta_v =
1617 apk_delta_mapping[index][delta_offset];
1618
1619 bb_offset += delta_v;
1620
1621 if (bb_offset < 0) {
1622 tmpreg = tmpreg & (~BIT(15));
1623 bb_offset = -bb_offset;
1624 } else {
1625 tmpreg = tmpreg | BIT(15);
1626 }
1627
1628 tmpreg =
1629 (tmpreg & 0xFFF0FFFF) | (bb_offset << 16);
1630 }
1631
1632 rtl_set_rfreg(hw, (enum radio_path)path, 0xc,
1633 MASKDWORD, 0x8992e);
1634 rtl_set_rfreg(hw, (enum radio_path)path, 0x0,
1635 MASKDWORD, apk_rf_value_0[path][index]);
1636 rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
1637 MASKDWORD, tmpreg);
1638
1639 i = 0;
1640 do {
1641 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80000000);
1642 rtl_set_bbreg(hw, apk_offset[path],
1643 MASKDWORD, apk_value[0]);
1644 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1645 ("PHY_APCalibrate() offset 0x%x "
1646 "value 0x%x\n",
1647 apk_offset[path],
1648 rtl_get_bbreg(hw, apk_offset[path],
1649 MASKDWORD)));
1650
1651 mdelay(3);
1652
1653 rtl_set_bbreg(hw, apk_offset[path],
1654 MASKDWORD, apk_value[1]);
1655 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1656 ("PHY_APCalibrate() offset 0x%x "
1657 "value 0x%x\n",
1658 apk_offset[path],
1659 rtl_get_bbreg(hw, apk_offset[path],
1660 MASKDWORD)));
1661
1662 mdelay(20);
1663
1664 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1665
1666 if (path == RF90_PATH_A)
1667 tmpreg = rtl_get_bbreg(hw, 0xbd8,
1668 0x03E00000);
1669 else
1670 tmpreg = rtl_get_bbreg(hw, 0xbd8,
1671 0xF8000000);
1672
1673 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1674 ("PHY_APCalibrate() offset "
1675 "0xbd8[25:21] %x\n", tmpreg));
1676
1677 i++;
1678
1679 } while (tmpreg > apkbound && i < 4);
1680
1681 apk_result[path][index] = tmpreg;
1682 }
1683 }
1684
1685 _rtl92c_phy_reload_mac_registers(hw, mac_reg, mac_backup);
1686
1687 for (index = 0; index < APK_BB_REG_NUM; index++) {
1688 if (index == 0)
1689 continue;
1690 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD, bb_backup[index]);
1691 }
1692
1693 _rtl92c_phy_reload_adda_registers(hw, afe_reg, afe_backup, 16);
1694
1695 for (path = 0; path < pathbound; path++) {
1696 rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
1697 MASKDWORD, reg_d[path]);
1698
1699 if (path == RF90_PATH_B) {
1700 rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
1701 0x1000f);
1702 rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
1703 0x20101);
1704 }
1705
1706 if (apk_result[path][1] > 6)
1707 apk_result[path][1] = 6;
1708 }
1709
1710 for (path = 0; path < pathbound; path++) {
1711 rtl_set_rfreg(hw, (enum radio_path)path, 0x3, MASKDWORD,
1712 ((apk_result[path][1] << 15) |
1713 (apk_result[path][1] << 10) |
1714 (apk_result[path][1] << 5) |
1715 apk_result[path][1]));
1716
1717 if (path == RF90_PATH_A)
1718 rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
1719 ((apk_result[path][1] << 15) |
1720 (apk_result[path][1] << 10) |
1721 (0x00 << 5) | 0x05));
1722 else
1723 rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
1724 ((apk_result[path][1] << 15) |
1725 (apk_result[path][1] << 10) |
1726 (0x02 << 5) | 0x05));
1727
1728 rtl_set_rfreg(hw, (enum radio_path)path, 0xe, MASKDWORD,
1729 ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) |
1730 0x08));
1731
1732 }
1733
1734 rtlphy->apk_done = true;
1735#endif
1736}
1737
1738static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1739 bool bmain, bool is2t)
1740{
1741 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1742
1743 if (is_hal_stop(rtlhal)) {
1744 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1745 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1746 }
1747 if (is2t) {
1748 if (bmain)
1749 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1750 BIT(5) | BIT(6), 0x1);
1751 else
1752 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1753 BIT(5) | BIT(6), 0x2);
1754 } else {
1755 if (bmain)
1756 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
1757 else
1758 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1759
1760 }
1761}
1762
1763#undef IQK_ADDA_REG_NUM
1764#undef IQK_DELAY_TIME
1765
1766void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1767{
1768 struct rtl_priv *rtlpriv = rtl_priv(hw);
1769 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1770 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1771
1772 long result[4][8];
1773 u8 i, final_candidate;
1774 bool patha_ok, pathb_ok;
1775 long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
1776 reg_ecc, reg_tmp = 0;
1777 bool is12simular, is13simular, is23simular;
1778 bool start_conttx = false, singletone = false;
1779 u32 iqk_bb_reg[10] = {
1780 ROFDM0_XARXIQIMBALANCE,
1781 ROFDM0_XBRXIQIMBALANCE,
1782 ROFDM0_ECCATHRESHOLD,
1783 ROFDM0_AGCRSSITABLE,
1784 ROFDM0_XATXIQIMBALANCE,
1785 ROFDM0_XBTXIQIMBALANCE,
1786 ROFDM0_XCTXIQIMBALANCE,
1787 ROFDM0_XCTXAFE,
1788 ROFDM0_XDTXAFE,
1789 ROFDM0_RXIQEXTANTA
1790 };
1791
1792 if (recovery) {
1793 _rtl92c_phy_reload_adda_registers(hw,
1794 iqk_bb_reg,
1795 rtlphy->iqk_bb_backup, 10);
1796 return;
1797 }
1798 if (start_conttx || singletone)
1799 return;
1800 for (i = 0; i < 8; i++) {
1801 result[0][i] = 0;
1802 result[1][i] = 0;
1803 result[2][i] = 0;
1804 result[3][i] = 0;
1805 }
1806 final_candidate = 0xff;
1807 patha_ok = false;
1808 pathb_ok = false;
1809 is12simular = false;
1810 is23simular = false;
1811 is13simular = false;
1812 for (i = 0; i < 3; i++) {
1813 if (IS_92C_SERIAL(rtlhal->version))
1814 _rtl92c_phy_iq_calibrate(hw, result, i, true);
1815 else
1816 _rtl92c_phy_iq_calibrate(hw, result, i, false);
1817 if (i == 1) {
1818 is12simular = _rtl92c_phy_simularity_compare(hw,
1819 result, 0,
1820 1);
1821 if (is12simular) {
1822 final_candidate = 0;
1823 break;
1824 }
1825 }
1826 if (i == 2) {
1827 is13simular = _rtl92c_phy_simularity_compare(hw,
1828 result, 0,
1829 2);
1830 if (is13simular) {
1831 final_candidate = 0;
1832 break;
1833 }
1834 is23simular = _rtl92c_phy_simularity_compare(hw,
1835 result, 1,
1836 2);
1837 if (is23simular)
1838 final_candidate = 1;
1839 else {
1840 for (i = 0; i < 8; i++)
1841 reg_tmp += result[3][i];
1842
1843 if (reg_tmp != 0)
1844 final_candidate = 3;
1845 else
1846 final_candidate = 0xFF;
1847 }
1848 }
1849 }
1850 for (i = 0; i < 4; i++) {
1851 reg_e94 = result[i][0];
1852 reg_e9c = result[i][1];
1853 reg_ea4 = result[i][2];
1854 reg_eac = result[i][3];
1855 reg_eb4 = result[i][4];
1856 reg_ebc = result[i][5];
1857 reg_ec4 = result[i][6];
1858 reg_ecc = result[i][7];
1859 }
1860 if (final_candidate != 0xff) {
1861 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1862 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1863 reg_ea4 = result[final_candidate][2];
1864 reg_eac = result[final_candidate][3];
1865 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1866 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1867 reg_ec4 = result[final_candidate][6];
1868 reg_ecc = result[final_candidate][7];
1869 patha_ok = pathb_ok = true;
1870 } else {
1871 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1872 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1873 }
1874 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
1875 _rtl92c_phy_path_a_fill_iqk_matrix(hw, patha_ok, result,
1876 final_candidate,
1877 (reg_ea4 == 0));
1878 if (IS_92C_SERIAL(rtlhal->version)) {
1879 if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */
1880 _rtl92c_phy_path_b_fill_iqk_matrix(hw, pathb_ok,
1881 result,
1882 final_candidate,
1883 (reg_ec4 == 0));
1884 }
1885 _rtl92c_phy_save_adda_registers(hw, iqk_bb_reg,
1886 rtlphy->iqk_bb_backup, 10);
1887}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]1888EXPORT_SYMBOL(rtl92c_phy_iq_calibrate);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]1889
1890void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw)
1891{
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]1892 struct rtl_priv *rtlpriv = rtl_priv(hw);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]1893 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1894 bool start_conttx = false, singletone = false;
1895
1896 if (start_conttx || singletone)
1897 return;
1898 if (IS_92C_SERIAL(rtlhal->version))
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]1899 rtlpriv->cfg->ops->phy_lc_calibrate(hw, true);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]1900 else
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]1901 rtlpriv->cfg->ops->phy_lc_calibrate(hw, false);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]1902}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]1903EXPORT_SYMBOL(rtl92c_phy_lc_calibrate);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]1904
1905void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
1906{
1907 struct rtl_priv *rtlpriv = rtl_priv(hw);
1908 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1909 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1910
1911 if (rtlphy->apk_done)
1912 return;
1913 if (IS_92C_SERIAL(rtlhal->version))
1914 _rtl92c_phy_ap_calibrate(hw, delta, true);
1915 else
1916 _rtl92c_phy_ap_calibrate(hw, delta, false);
1917}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]1918EXPORT_SYMBOL(rtl92c_phy_ap_calibrate);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]1919
1920void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1921{
1922 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1923
1924 if (IS_92C_SERIAL(rtlhal->version))
1925 _rtl92c_phy_set_rfpath_switch(hw, bmain, true);
1926 else
1927 _rtl92c_phy_set_rfpath_switch(hw, bmain, false);
1928}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]1929EXPORT_SYMBOL(rtl92c_phy_set_rfpath_switch);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]1930
1931bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1932{
1933 struct rtl_priv *rtlpriv = rtl_priv(hw);
1934 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1935 bool postprocessing = false;
1936
1937 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1938 ("-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1939 iotype, rtlphy->set_io_inprogress));
1940 do {
1941 switch (iotype) {
1942 case IO_CMD_RESUME_DM_BY_SCAN:
1943 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1944 ("[IO CMD] Resume DM after scan.\n"));
1945 postprocessing = true;
1946 break;
1947 case IO_CMD_PAUSE_DM_BY_SCAN:
1948 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1949 ("[IO CMD] Pause DM before scan.\n"));
1950 postprocessing = true;
1951 break;
1952 default:
1953 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1954 ("switch case not process\n"));
1955 break;
1956 }
1957 } while (false);
1958 if (postprocessing && !rtlphy->set_io_inprogress) {
1959 rtlphy->set_io_inprogress = true;
1960 rtlphy->current_io_type = iotype;
1961 } else {
1962 return false;
1963 }
1964 rtl92c_phy_set_io(hw);
1965 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, ("<--IO Type(%#x)\n", iotype));
1966 return true;
1967}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]1968EXPORT_SYMBOL(rtl92c_phy_set_io_cmd);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]1969
1970void rtl92c_phy_set_io(struct ieee80211_hw *hw)
1971{
1972 struct rtl_priv *rtlpriv = rtl_priv(hw);
1973 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1974
1975 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1976 ("--->Cmd(%#x), set_io_inprogress(%d)\n",
1977 rtlphy->current_io_type, rtlphy->set_io_inprogress));
1978 switch (rtlphy->current_io_type) {
1979 case IO_CMD_RESUME_DM_BY_SCAN:
1980 dm_digtable.cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1981 rtl92c_dm_write_dig(hw);
1982 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1983 break;
1984 case IO_CMD_PAUSE_DM_BY_SCAN:
1985 rtlphy->initgain_backup.xaagccore1 = dm_digtable.cur_igvalue;
1986 dm_digtable.cur_igvalue = 0x17;
1987 rtl92c_dm_write_dig(hw);
1988 break;
1989 default:
1990 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1991 ("switch case not process\n"));
1992 break;
1993 }
1994 rtlphy->set_io_inprogress = false;
1995 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1996 ("<---(%#x)\n", rtlphy->current_io_type));
1997}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]1998EXPORT_SYMBOL(rtl92c_phy_set_io);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]1999
2000void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw)
2001{
2002 struct rtl_priv *rtlpriv = rtl_priv(hw);
2003
2004 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
2005 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2006 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2007 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2008 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2009 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2010}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]2011EXPORT_SYMBOL(rtl92ce_phy_set_rf_on);
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]2012
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]2013void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw)
Larry Finger4295cd22011-02-19 16:29:12 -0600[diff] [blame]2014{
2015 u32 u4b_tmp;
2016 u8 delay = 5;
2017 struct rtl_priv *rtlpriv = rtl_priv(hw);
2018
2019 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2020 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2021 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
2022 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
2023 while (u4b_tmp != 0 && delay > 0) {
2024 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
2025 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2026 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
2027 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
2028 delay--;
2029 }
2030 if (delay == 0) {
2031 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2032 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2033 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2034 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2035 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
2036 ("Switch RF timeout !!!.\n"));
2037 return;
2038 }
2039 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2040 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
2041}
Larry Finger1472d3a2011-02-23 10:24:58 -0600[diff] [blame]2042EXPORT_SYMBOL(_rtl92c_phy_set_rf_sleep);