blob: 15323d8bd9cfa4237c34069a76e3700dd6873c15 [file] [log] [blame]
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -07001/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/irq.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/platform_device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090033#include <linux/slab.h>
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -070034#include <linux/spi/spi.h>
35#include <linux/spi/spi_bitbang.h>
36#include <linux/types.h>
Shawn Guo22a85e42011-07-10 01:16:41 +080037#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_gpio.h>
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -070040
Arnd Bergmann82906b12012-08-24 15:14:29 +020041#include <linux/platform_data/spi-imx.h>
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -070042
43#define DRIVER_NAME "spi_imx"
44
45#define MXC_CSPIRXDATA 0x00
46#define MXC_CSPITXDATA 0x04
47#define MXC_CSPICTRL 0x08
48#define MXC_CSPIINT 0x0c
49#define MXC_RESET 0x1c
50
51/* generic defines to abstract from the different register layouts */
52#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
53#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
54
55struct spi_imx_config {
56 unsigned int speed_hz;
57 unsigned int bpw;
58 unsigned int mode;
Uwe Kleine-König3b2aa892010-09-10 09:42:29 +020059 u8 cs;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -070060};
61
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +020062enum spi_imx_devtype {
Shawn Guo04ee5852011-07-10 01:16:39 +080063 IMX1_CSPI,
64 IMX21_CSPI,
65 IMX27_CSPI,
66 IMX31_CSPI,
67 IMX35_CSPI, /* CSPI on all i.mx except above */
68 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +020069};
70
71struct spi_imx_data;
72
73struct spi_imx_devtype_data {
74 void (*intctrl)(struct spi_imx_data *, int);
75 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
76 void (*trigger)(struct spi_imx_data *);
77 int (*rx_available)(struct spi_imx_data *);
Uwe Kleine-König1723e662010-09-10 09:19:18 +020078 void (*reset)(struct spi_imx_data *);
Shawn Guo04ee5852011-07-10 01:16:39 +080079 enum spi_imx_devtype devtype;
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +020080};
81
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -070082struct spi_imx_data {
83 struct spi_bitbang bitbang;
84
85 struct completion xfer_done;
Uwe Kleine-Königcc4d22a2012-03-29 21:54:18 +020086 void __iomem *base;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -070087 int irq;
Sascha Haueraa29d842012-03-07 09:30:22 +010088 struct clk *clk_per;
89 struct clk *clk_ipg;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -070090 unsigned long spi_clk;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -070091
92 unsigned int count;
93 void (*tx)(struct spi_imx_data *);
94 void (*rx)(struct spi_imx_data *);
95 void *rx_buf;
96 const void *tx_buf;
97 unsigned int txfifo; /* number of words pushed in tx FIFO */
98
Uwe Kleine-König80023cb2012-05-21 21:49:35 +020099 const struct spi_imx_devtype_data *devtype_data;
Shawn Guoc2387cb2011-07-10 01:16:40 +0800100 int chipselect[0];
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700101};
102
Shawn Guo04ee5852011-07-10 01:16:39 +0800103static inline int is_imx27_cspi(struct spi_imx_data *d)
104{
105 return d->devtype_data->devtype == IMX27_CSPI;
106}
107
108static inline int is_imx35_cspi(struct spi_imx_data *d)
109{
110 return d->devtype_data->devtype == IMX35_CSPI;
111}
112
113static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
114{
115 return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
116}
117
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700118#define MXC_SPI_BUF_RX(type) \
119static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
120{ \
121 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
122 \
123 if (spi_imx->rx_buf) { \
124 *(type *)spi_imx->rx_buf = val; \
125 spi_imx->rx_buf += sizeof(type); \
126 } \
127}
128
129#define MXC_SPI_BUF_TX(type) \
130static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
131{ \
132 type val = 0; \
133 \
134 if (spi_imx->tx_buf) { \
135 val = *(type *)spi_imx->tx_buf; \
136 spi_imx->tx_buf += sizeof(type); \
137 } \
138 \
139 spi_imx->count -= sizeof(type); \
140 \
141 writel(val, spi_imx->base + MXC_CSPITXDATA); \
142}
143
144MXC_SPI_BUF_RX(u8)
145MXC_SPI_BUF_TX(u8)
146MXC_SPI_BUF_RX(u16)
147MXC_SPI_BUF_TX(u16)
148MXC_SPI_BUF_RX(u32)
149MXC_SPI_BUF_TX(u32)
150
151/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
152 * (which is currently not the case in this driver)
153 */
154static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
155 256, 384, 512, 768, 1024};
156
157/* MX21, MX27 */
158static unsigned int spi_imx_clkdiv_1(unsigned int fin,
Shawn Guo04ee5852011-07-10 01:16:39 +0800159 unsigned int fspi, unsigned int max)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700160{
Shawn Guo04ee5852011-07-10 01:16:39 +0800161 int i;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700162
163 for (i = 2; i < max; i++)
164 if (fspi * mxc_clkdivs[i] >= fin)
165 return i;
166
167 return max;
168}
169
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200170/* MX1, MX31, MX35, MX51 CSPI */
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700171static unsigned int spi_imx_clkdiv_2(unsigned int fin,
172 unsigned int fspi)
173{
174 int i, div = 4;
175
176 for (i = 0; i < 7; i++) {
177 if (fspi * div >= fin)
178 return i;
179 div <<= 1;
180 }
181
182 return 7;
183}
184
Shawn Guo66de7572011-07-10 01:16:37 +0800185#define MX51_ECSPI_CTRL 0x08
186#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
187#define MX51_ECSPI_CTRL_XCH (1 << 2)
188#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
189#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
190#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
191#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
192#define MX51_ECSPI_CTRL_BL_OFFSET 20
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200193
Shawn Guo66de7572011-07-10 01:16:37 +0800194#define MX51_ECSPI_CONFIG 0x0c
195#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
196#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
197#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
198#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
Knut Wohlrabc09b8902012-09-25 13:21:57 +0200199#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200200
Shawn Guo66de7572011-07-10 01:16:37 +0800201#define MX51_ECSPI_INT 0x10
202#define MX51_ECSPI_INT_TEEN (1 << 0)
203#define MX51_ECSPI_INT_RREN (1 << 3)
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200204
Shawn Guo66de7572011-07-10 01:16:37 +0800205#define MX51_ECSPI_STAT 0x18
206#define MX51_ECSPI_STAT_RR (1 << 3)
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200207
208/* MX51 eCSPI */
Shawn Guo66de7572011-07-10 01:16:37 +0800209static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi)
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200210{
211 /*
212 * there are two 4-bit dividers, the pre-divider divides by
213 * $pre, the post-divider by 2^$post
214 */
215 unsigned int pre, post;
216
217 if (unlikely(fspi > fin))
218 return 0;
219
220 post = fls(fin) - fls(fspi);
221 if (fin > fspi << post)
222 post++;
223
224 /* now we have: (fin <= fspi << post) with post being minimal */
225
226 post = max(4U, post) - 4;
227 if (unlikely(post > 0xf)) {
228 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
229 __func__, fspi, fin);
230 return 0xff;
231 }
232
233 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
234
235 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
236 __func__, fin, fspi, post, pre);
Shawn Guo66de7572011-07-10 01:16:37 +0800237 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
238 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200239}
240
Shawn Guo66de7572011-07-10 01:16:37 +0800241static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200242{
243 unsigned val = 0;
244
245 if (enable & MXC_INT_TE)
Shawn Guo66de7572011-07-10 01:16:37 +0800246 val |= MX51_ECSPI_INT_TEEN;
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200247
248 if (enable & MXC_INT_RR)
Shawn Guo66de7572011-07-10 01:16:37 +0800249 val |= MX51_ECSPI_INT_RREN;
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200250
Shawn Guo66de7572011-07-10 01:16:37 +0800251 writel(val, spi_imx->base + MX51_ECSPI_INT);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200252}
253
Shawn Guo66de7572011-07-10 01:16:37 +0800254static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200255{
256 u32 reg;
257
Shawn Guo66de7572011-07-10 01:16:37 +0800258 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
259 reg |= MX51_ECSPI_CTRL_XCH;
260 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200261}
262
Shawn Guo66de7572011-07-10 01:16:37 +0800263static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200264 struct spi_imx_config *config)
265{
Shawn Guo66de7572011-07-10 01:16:37 +0800266 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200267
Sascha Hauerf020c392011-02-08 21:08:59 +0100268 /*
269 * The hardware seems to have a race condition when changing modes. The
270 * current assumption is that the selection of the channel arrives
271 * earlier in the hardware than the mode bits when they are written at
272 * the same time.
273 * So set master mode for all channels as we do not support slave mode.
274 */
Shawn Guo66de7572011-07-10 01:16:37 +0800275 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200276
277 /* set clock speed */
Shawn Guo66de7572011-07-10 01:16:37 +0800278 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200279
280 /* set chip select to use */
Shawn Guo66de7572011-07-10 01:16:37 +0800281 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200282
Shawn Guo66de7572011-07-10 01:16:37 +0800283 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200284
Shawn Guo66de7572011-07-10 01:16:37 +0800285 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200286
287 if (config->mode & SPI_CPHA)
Shawn Guo66de7572011-07-10 01:16:37 +0800288 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200289
Knut Wohlrabc09b8902012-09-25 13:21:57 +0200290 if (config->mode & SPI_CPOL) {
Shawn Guo66de7572011-07-10 01:16:37 +0800291 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
Knut Wohlrabc09b8902012-09-25 13:21:57 +0200292 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
293 }
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200294 if (config->mode & SPI_CS_HIGH)
Shawn Guo66de7572011-07-10 01:16:37 +0800295 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200296
Shawn Guo66de7572011-07-10 01:16:37 +0800297 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
298 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200299
300 return 0;
301}
302
Shawn Guo66de7572011-07-10 01:16:37 +0800303static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200304{
Shawn Guo66de7572011-07-10 01:16:37 +0800305 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200306}
307
Shawn Guo66de7572011-07-10 01:16:37 +0800308static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200309{
310 /* drain receive buffer */
Shawn Guo66de7572011-07-10 01:16:37 +0800311 while (mx51_ecspi_rx_available(spi_imx))
Uwe Kleine-König0b599602010-09-09 21:02:48 +0200312 readl(spi_imx->base + MXC_CSPIRXDATA);
313}
314
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700315#define MX31_INTREG_TEEN (1 << 0)
316#define MX31_INTREG_RREN (1 << 3)
317
318#define MX31_CSPICTRL_ENABLE (1 << 0)
319#define MX31_CSPICTRL_MASTER (1 << 1)
320#define MX31_CSPICTRL_XCH (1 << 2)
321#define MX31_CSPICTRL_POL (1 << 4)
322#define MX31_CSPICTRL_PHA (1 << 5)
323#define MX31_CSPICTRL_SSCTL (1 << 6)
324#define MX31_CSPICTRL_SSPOL (1 << 7)
325#define MX31_CSPICTRL_BC_SHIFT 8
326#define MX35_CSPICTRL_BL_SHIFT 20
327#define MX31_CSPICTRL_CS_SHIFT 24
328#define MX35_CSPICTRL_CS_SHIFT 12
329#define MX31_CSPICTRL_DR_SHIFT 16
330
331#define MX31_CSPISTATUS 0x14
332#define MX31_STATUS_RR (1 << 3)
333
334/* These functions also work for the i.MX35, but be aware that
335 * the i.MX35 has a slightly different register layout for bits
336 * we do not use here.
337 */
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200338static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700339{
340 unsigned int val = 0;
341
342 if (enable & MXC_INT_TE)
343 val |= MX31_INTREG_TEEN;
344 if (enable & MXC_INT_RR)
345 val |= MX31_INTREG_RREN;
346
347 writel(val, spi_imx->base + MXC_CSPIINT);
348}
349
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200350static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700351{
352 unsigned int reg;
353
354 reg = readl(spi_imx->base + MXC_CSPICTRL);
355 reg |= MX31_CSPICTRL_XCH;
356 writel(reg, spi_imx->base + MXC_CSPICTRL);
357}
358
Shawn Guo2a64a902011-07-10 01:16:38 +0800359static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700360 struct spi_imx_config *config)
361{
362 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
Uwe Kleine-König3b2aa892010-09-10 09:42:29 +0200363 int cs = spi_imx->chipselect[config->cs];
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700364
365 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
366 MX31_CSPICTRL_DR_SHIFT;
367
Shawn Guo04ee5852011-07-10 01:16:39 +0800368 if (is_imx35_cspi(spi_imx)) {
Shawn Guo2a64a902011-07-10 01:16:38 +0800369 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
370 reg |= MX31_CSPICTRL_SSCTL;
371 } else {
372 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
373 }
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700374
375 if (config->mode & SPI_CPHA)
376 reg |= MX31_CSPICTRL_PHA;
377 if (config->mode & SPI_CPOL)
378 reg |= MX31_CSPICTRL_POL;
379 if (config->mode & SPI_CS_HIGH)
380 reg |= MX31_CSPICTRL_SSPOL;
Uwe Kleine-König3b2aa892010-09-10 09:42:29 +0200381 if (cs < 0)
Shawn Guo2a64a902011-07-10 01:16:38 +0800382 reg |= (cs + 32) <<
Shawn Guo04ee5852011-07-10 01:16:39 +0800383 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
384 MX31_CSPICTRL_CS_SHIFT);
Uwe Kleine-König1723e662010-09-10 09:19:18 +0200385
386 writel(reg, spi_imx->base + MXC_CSPICTRL);
387
388 return 0;
389}
390
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200391static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700392{
393 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
394}
395
Shawn Guo2a64a902011-07-10 01:16:38 +0800396static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
Uwe Kleine-König1723e662010-09-10 09:19:18 +0200397{
398 /* drain receive buffer */
Shawn Guo2a64a902011-07-10 01:16:38 +0800399 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
Uwe Kleine-König1723e662010-09-10 09:19:18 +0200400 readl(spi_imx->base + MXC_CSPIRXDATA);
401}
402
Shawn Guo3451fb12011-07-10 01:16:36 +0800403#define MX21_INTREG_RR (1 << 4)
404#define MX21_INTREG_TEEN (1 << 9)
405#define MX21_INTREG_RREN (1 << 13)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700406
Shawn Guo3451fb12011-07-10 01:16:36 +0800407#define MX21_CSPICTRL_POL (1 << 5)
408#define MX21_CSPICTRL_PHA (1 << 6)
409#define MX21_CSPICTRL_SSPOL (1 << 8)
410#define MX21_CSPICTRL_XCH (1 << 9)
411#define MX21_CSPICTRL_ENABLE (1 << 10)
412#define MX21_CSPICTRL_MASTER (1 << 11)
413#define MX21_CSPICTRL_DR_SHIFT 14
414#define MX21_CSPICTRL_CS_SHIFT 19
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700415
Shawn Guo3451fb12011-07-10 01:16:36 +0800416static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700417{
418 unsigned int val = 0;
419
420 if (enable & MXC_INT_TE)
Shawn Guo3451fb12011-07-10 01:16:36 +0800421 val |= MX21_INTREG_TEEN;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700422 if (enable & MXC_INT_RR)
Shawn Guo3451fb12011-07-10 01:16:36 +0800423 val |= MX21_INTREG_RREN;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700424
425 writel(val, spi_imx->base + MXC_CSPIINT);
426}
427
Shawn Guo3451fb12011-07-10 01:16:36 +0800428static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700429{
430 unsigned int reg;
431
432 reg = readl(spi_imx->base + MXC_CSPICTRL);
Shawn Guo3451fb12011-07-10 01:16:36 +0800433 reg |= MX21_CSPICTRL_XCH;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700434 writel(reg, spi_imx->base + MXC_CSPICTRL);
435}
436
Shawn Guo3451fb12011-07-10 01:16:36 +0800437static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700438 struct spi_imx_config *config)
439{
Shawn Guo3451fb12011-07-10 01:16:36 +0800440 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
Uwe Kleine-König3b2aa892010-09-10 09:42:29 +0200441 int cs = spi_imx->chipselect[config->cs];
Shawn Guo04ee5852011-07-10 01:16:39 +0800442 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700443
Shawn Guo04ee5852011-07-10 01:16:39 +0800444 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
Shawn Guo3451fb12011-07-10 01:16:36 +0800445 MX21_CSPICTRL_DR_SHIFT;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700446 reg |= config->bpw - 1;
447
448 if (config->mode & SPI_CPHA)
Shawn Guo3451fb12011-07-10 01:16:36 +0800449 reg |= MX21_CSPICTRL_PHA;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700450 if (config->mode & SPI_CPOL)
Shawn Guo3451fb12011-07-10 01:16:36 +0800451 reg |= MX21_CSPICTRL_POL;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700452 if (config->mode & SPI_CS_HIGH)
Shawn Guo3451fb12011-07-10 01:16:36 +0800453 reg |= MX21_CSPICTRL_SSPOL;
Uwe Kleine-König3b2aa892010-09-10 09:42:29 +0200454 if (cs < 0)
Shawn Guo3451fb12011-07-10 01:16:36 +0800455 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700456
457 writel(reg, spi_imx->base + MXC_CSPICTRL);
458
459 return 0;
460}
461
Shawn Guo3451fb12011-07-10 01:16:36 +0800462static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700463{
Shawn Guo3451fb12011-07-10 01:16:36 +0800464 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700465}
466
Shawn Guo3451fb12011-07-10 01:16:36 +0800467static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
Uwe Kleine-König1723e662010-09-10 09:19:18 +0200468{
469 writel(1, spi_imx->base + MXC_RESET);
470}
471
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700472#define MX1_INTREG_RR (1 << 3)
473#define MX1_INTREG_TEEN (1 << 8)
474#define MX1_INTREG_RREN (1 << 11)
475
476#define MX1_CSPICTRL_POL (1 << 4)
477#define MX1_CSPICTRL_PHA (1 << 5)
478#define MX1_CSPICTRL_XCH (1 << 8)
479#define MX1_CSPICTRL_ENABLE (1 << 9)
480#define MX1_CSPICTRL_MASTER (1 << 10)
481#define MX1_CSPICTRL_DR_SHIFT 13
482
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200483static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700484{
485 unsigned int val = 0;
486
487 if (enable & MXC_INT_TE)
488 val |= MX1_INTREG_TEEN;
489 if (enable & MXC_INT_RR)
490 val |= MX1_INTREG_RREN;
491
492 writel(val, spi_imx->base + MXC_CSPIINT);
493}
494
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200495static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700496{
497 unsigned int reg;
498
499 reg = readl(spi_imx->base + MXC_CSPICTRL);
500 reg |= MX1_CSPICTRL_XCH;
501 writel(reg, spi_imx->base + MXC_CSPICTRL);
502}
503
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200504static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700505 struct spi_imx_config *config)
506{
507 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
508
509 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
510 MX1_CSPICTRL_DR_SHIFT;
511 reg |= config->bpw - 1;
512
513 if (config->mode & SPI_CPHA)
514 reg |= MX1_CSPICTRL_PHA;
515 if (config->mode & SPI_CPOL)
516 reg |= MX1_CSPICTRL_POL;
517
518 writel(reg, spi_imx->base + MXC_CSPICTRL);
519
520 return 0;
521}
522
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200523static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700524{
525 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
526}
527
Uwe Kleine-König1723e662010-09-10 09:19:18 +0200528static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
529{
530 writel(1, spi_imx->base + MXC_RESET);
531}
532
Shawn Guo04ee5852011-07-10 01:16:39 +0800533static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
534 .intctrl = mx1_intctrl,
535 .config = mx1_config,
536 .trigger = mx1_trigger,
537 .rx_available = mx1_rx_available,
538 .reset = mx1_reset,
539 .devtype = IMX1_CSPI,
540};
541
542static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
543 .intctrl = mx21_intctrl,
544 .config = mx21_config,
545 .trigger = mx21_trigger,
546 .rx_available = mx21_rx_available,
547 .reset = mx21_reset,
548 .devtype = IMX21_CSPI,
549};
550
551static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
552 /* i.mx27 cspi shares the functions with i.mx21 one */
553 .intctrl = mx21_intctrl,
554 .config = mx21_config,
555 .trigger = mx21_trigger,
556 .rx_available = mx21_rx_available,
557 .reset = mx21_reset,
558 .devtype = IMX27_CSPI,
559};
560
561static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
562 .intctrl = mx31_intctrl,
563 .config = mx31_config,
564 .trigger = mx31_trigger,
565 .rx_available = mx31_rx_available,
566 .reset = mx31_reset,
567 .devtype = IMX31_CSPI,
568};
569
570static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
571 /* i.mx35 and later cspi shares the functions with i.mx31 one */
572 .intctrl = mx31_intctrl,
573 .config = mx31_config,
574 .trigger = mx31_trigger,
575 .rx_available = mx31_rx_available,
576 .reset = mx31_reset,
577 .devtype = IMX35_CSPI,
578};
579
580static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
581 .intctrl = mx51_ecspi_intctrl,
582 .config = mx51_ecspi_config,
583 .trigger = mx51_ecspi_trigger,
584 .rx_available = mx51_ecspi_rx_available,
585 .reset = mx51_ecspi_reset,
586 .devtype = IMX51_ECSPI,
587};
588
589static struct platform_device_id spi_imx_devtype[] = {
590 {
591 .name = "imx1-cspi",
592 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
593 }, {
594 .name = "imx21-cspi",
595 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
596 }, {
597 .name = "imx27-cspi",
598 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
599 }, {
600 .name = "imx31-cspi",
601 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
602 }, {
603 .name = "imx35-cspi",
604 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
605 }, {
606 .name = "imx51-ecspi",
607 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
608 }, {
609 /* sentinel */
610 }
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200611};
612
Shawn Guo22a85e42011-07-10 01:16:41 +0800613static const struct of_device_id spi_imx_dt_ids[] = {
614 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
615 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
616 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
617 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
618 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
619 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
620 { /* sentinel */ }
621};
Niels de Vos27743e02013-07-29 09:38:05 +0200622MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
Shawn Guo22a85e42011-07-10 01:16:41 +0800623
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700624static void spi_imx_chipselect(struct spi_device *spi, int is_active)
625{
626 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700627 int gpio = spi_imx->chipselect[spi->chip_select];
Uwe Kleine-Könige6a0a8b2009-10-01 15:44:33 -0700628 int active = is_active != BITBANG_CS_INACTIVE;
629 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700630
Hui Wang8b17e052012-07-13 10:51:29 +0800631 if (!gpio_is_valid(gpio))
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700632 return;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700633
Uwe Kleine-Könige6a0a8b2009-10-01 15:44:33 -0700634 gpio_set_value(gpio, dev_is_lowactive ^ active);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700635}
636
637static void spi_imx_push(struct spi_imx_data *spi_imx)
638{
Shawn Guo04ee5852011-07-10 01:16:39 +0800639 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700640 if (!spi_imx->count)
641 break;
642 spi_imx->tx(spi_imx);
643 spi_imx->txfifo++;
644 }
645
Shawn Guoedd501bb2011-07-10 01:16:35 +0800646 spi_imx->devtype_data->trigger(spi_imx);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700647}
648
649static irqreturn_t spi_imx_isr(int irq, void *dev_id)
650{
651 struct spi_imx_data *spi_imx = dev_id;
652
Shawn Guoedd501bb2011-07-10 01:16:35 +0800653 while (spi_imx->devtype_data->rx_available(spi_imx)) {
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700654 spi_imx->rx(spi_imx);
655 spi_imx->txfifo--;
656 }
657
658 if (spi_imx->count) {
659 spi_imx_push(spi_imx);
660 return IRQ_HANDLED;
661 }
662
663 if (spi_imx->txfifo) {
664 /* No data left to push, but still waiting for rx data,
665 * enable receive data available interrupt.
666 */
Shawn Guoedd501bb2011-07-10 01:16:35 +0800667 spi_imx->devtype_data->intctrl(
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200668 spi_imx, MXC_INT_RR);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700669 return IRQ_HANDLED;
670 }
671
Shawn Guoedd501bb2011-07-10 01:16:35 +0800672 spi_imx->devtype_data->intctrl(spi_imx, 0);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700673 complete(&spi_imx->xfer_done);
674
675 return IRQ_HANDLED;
676}
677
678static int spi_imx_setupxfer(struct spi_device *spi,
679 struct spi_transfer *t)
680{
681 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
682 struct spi_imx_config config;
683
684 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
685 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
686 config.mode = spi->mode;
Uwe Kleine-König3b2aa892010-09-10 09:42:29 +0200687 config.cs = spi->chip_select;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700688
Sascha Hauer462d26b2009-10-01 15:44:29 -0700689 if (!config.speed_hz)
690 config.speed_hz = spi->max_speed_hz;
691 if (!config.bpw)
692 config.bpw = spi->bits_per_word;
Sascha Hauer462d26b2009-10-01 15:44:29 -0700693
Uwe Kleine-Könige6a0a8b2009-10-01 15:44:33 -0700694 /* Initialize the functions for transfer */
695 if (config.bpw <= 8) {
696 spi_imx->rx = spi_imx_buf_rx_u8;
697 spi_imx->tx = spi_imx_buf_tx_u8;
698 } else if (config.bpw <= 16) {
699 spi_imx->rx = spi_imx_buf_rx_u16;
700 spi_imx->tx = spi_imx_buf_tx_u16;
Sachin Kamat60514262013-05-30 13:38:09 +0530701 } else {
Uwe Kleine-Könige6a0a8b2009-10-01 15:44:33 -0700702 spi_imx->rx = spi_imx_buf_rx_u32;
703 spi_imx->tx = spi_imx_buf_tx_u32;
Stephen Warren24778be2013-05-21 20:36:35 -0600704 }
Uwe Kleine-Könige6a0a8b2009-10-01 15:44:33 -0700705
Shawn Guoedd501bb2011-07-10 01:16:35 +0800706 spi_imx->devtype_data->config(spi_imx, &config);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700707
708 return 0;
709}
710
711static int spi_imx_transfer(struct spi_device *spi,
712 struct spi_transfer *transfer)
713{
714 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
715
716 spi_imx->tx_buf = transfer->tx_buf;
717 spi_imx->rx_buf = transfer->rx_buf;
718 spi_imx->count = transfer->len;
719 spi_imx->txfifo = 0;
720
721 init_completion(&spi_imx->xfer_done);
722
723 spi_imx_push(spi_imx);
724
Shawn Guoedd501bb2011-07-10 01:16:35 +0800725 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700726
727 wait_for_completion(&spi_imx->xfer_done);
728
729 return transfer->len;
730}
731
732static int spi_imx_setup(struct spi_device *spi)
733{
Sascha Hauer6c23e5d2009-10-01 15:44:29 -0700734 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
735 int gpio = spi_imx->chipselect[spi->chip_select];
736
Alberto Panizzof4d4ecf2010-01-20 13:49:45 -0700737 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700738 spi->mode, spi->bits_per_word, spi->max_speed_hz);
739
Hui Wang8b17e052012-07-13 10:51:29 +0800740 if (gpio_is_valid(gpio))
Sascha Hauer6c23e5d2009-10-01 15:44:29 -0700741 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
742
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700743 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
744
745 return 0;
746}
747
748static void spi_imx_cleanup(struct spi_device *spi)
749{
750}
751
Grant Likelyfd4a3192012-12-07 16:57:14 +0000752static int spi_imx_probe(struct platform_device *pdev)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700753{
Shawn Guo22a85e42011-07-10 01:16:41 +0800754 struct device_node *np = pdev->dev.of_node;
755 const struct of_device_id *of_id =
756 of_match_device(spi_imx_dt_ids, &pdev->dev);
757 struct spi_imx_master *mxc_platform_info =
758 dev_get_platdata(&pdev->dev);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700759 struct spi_master *master;
760 struct spi_imx_data *spi_imx;
761 struct resource *res;
Shawn Guoc2387cb2011-07-10 01:16:40 +0800762 int i, ret, num_cs;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700763
Shawn Guo22a85e42011-07-10 01:16:41 +0800764 if (!np && !mxc_platform_info) {
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700765 dev_err(&pdev->dev, "can't get the platform data\n");
766 return -EINVAL;
767 }
768
Shawn Guo22a85e42011-07-10 01:16:41 +0800769 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
Lothar Waßmann39ec0d32012-04-03 15:03:44 +0200770 if (ret < 0) {
771 if (mxc_platform_info)
772 num_cs = mxc_platform_info->num_chipselect;
773 else
774 return ret;
775 }
Shawn Guo22a85e42011-07-10 01:16:41 +0800776
Shawn Guoc2387cb2011-07-10 01:16:40 +0800777 master = spi_alloc_master(&pdev->dev,
778 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700779 if (!master)
780 return -ENOMEM;
781
782 platform_set_drvdata(pdev, master);
783
Stephen Warren24778be2013-05-21 20:36:35 -0600784 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700785 master->bus_num = pdev->id;
Shawn Guoc2387cb2011-07-10 01:16:40 +0800786 master->num_chipselect = num_cs;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700787
788 spi_imx = spi_master_get_devdata(master);
789 spi_imx->bitbang.master = spi_master_get(master);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700790
791 for (i = 0; i < master->num_chipselect; i++) {
Shawn Guo22a85e42011-07-10 01:16:41 +0800792 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
Hui Wang8b17e052012-07-13 10:51:29 +0800793 if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
Shawn Guo22a85e42011-07-10 01:16:41 +0800794 cs_gpio = mxc_platform_info->chipselect[i];
Fabio Estevam4cc122a2011-09-15 17:21:15 -0300795
796 spi_imx->chipselect[i] = cs_gpio;
Hui Wang8b17e052012-07-13 10:51:29 +0800797 if (!gpio_is_valid(cs_gpio))
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700798 continue;
Fabio Estevam4cc122a2011-09-15 17:21:15 -0300799
Fabio Estevam130b82c2013-07-11 01:26:48 -0300800 ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
801 DRIVER_NAME);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700802 if (ret) {
John Ognessbbd050a2009-11-24 16:53:07 +0000803 dev_err(&pdev->dev, "can't get cs gpios\n");
Fabio Estevam130b82c2013-07-11 01:26:48 -0300804 goto out_master_put;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700805 }
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700806 }
807
808 spi_imx->bitbang.chipselect = spi_imx_chipselect;
809 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
810 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
811 spi_imx->bitbang.master->setup = spi_imx_setup;
812 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
Sascha Hauer3910f2c2009-10-01 15:44:30 -0700813 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700814
815 init_completion(&spi_imx->xfer_done);
816
Shawn Guo22a85e42011-07-10 01:16:41 +0800817 spi_imx->devtype_data = of_id ? of_id->data :
Shawn Guo04ee5852011-07-10 01:16:39 +0800818 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200819
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700820 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Fabio Estevam130b82c2013-07-11 01:26:48 -0300821 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
822 if (IS_ERR(spi_imx->base)) {
823 ret = PTR_ERR(spi_imx->base);
824 goto out_master_put;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700825 }
826
827 spi_imx->irq = platform_get_irq(pdev, 0);
Richard Genoud73575932011-01-07 15:26:01 +0100828 if (spi_imx->irq < 0) {
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700829 ret = -EINVAL;
Fabio Estevam130b82c2013-07-11 01:26:48 -0300830 goto out_master_put;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700831 }
832
Fabio Estevam130b82c2013-07-11 01:26:48 -0300833 ret = devm_request_irq(&pdev->dev, spi_imx->irq, spi_imx_isr, 0,
834 DRIVER_NAME, spi_imx);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700835 if (ret) {
836 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
Fabio Estevam130b82c2013-07-11 01:26:48 -0300837 goto out_master_put;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700838 }
839
Sascha Haueraa29d842012-03-07 09:30:22 +0100840 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
841 if (IS_ERR(spi_imx->clk_ipg)) {
842 ret = PTR_ERR(spi_imx->clk_ipg);
Fabio Estevam130b82c2013-07-11 01:26:48 -0300843 goto out_master_put;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700844 }
845
Sascha Haueraa29d842012-03-07 09:30:22 +0100846 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
847 if (IS_ERR(spi_imx->clk_per)) {
848 ret = PTR_ERR(spi_imx->clk_per);
Fabio Estevam130b82c2013-07-11 01:26:48 -0300849 goto out_master_put;
Sascha Haueraa29d842012-03-07 09:30:22 +0100850 }
851
Fabio Estevam83174622013-07-11 01:26:49 -0300852 ret = clk_prepare_enable(spi_imx->clk_per);
853 if (ret)
854 goto out_master_put;
855
856 ret = clk_prepare_enable(spi_imx->clk_ipg);
857 if (ret)
858 goto out_put_per;
Sascha Haueraa29d842012-03-07 09:30:22 +0100859
860 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700861
Shawn Guoedd501bb2011-07-10 01:16:35 +0800862 spi_imx->devtype_data->reset(spi_imx);
Daniel Mackce1807b2009-11-19 19:01:42 +0000863
Shawn Guoedd501bb2011-07-10 01:16:35 +0800864 spi_imx->devtype_data->intctrl(spi_imx, 0);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700865
Shawn Guo22a85e42011-07-10 01:16:41 +0800866 master->dev.of_node = pdev->dev.of_node;
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700867 ret = spi_bitbang_start(&spi_imx->bitbang);
868 if (ret) {
869 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
870 goto out_clk_put;
871 }
872
873 dev_info(&pdev->dev, "probed\n");
874
875 return ret;
876
877out_clk_put:
Sascha Haueraa29d842012-03-07 09:30:22 +0100878 clk_disable_unprepare(spi_imx->clk_ipg);
Fabio Estevam83174622013-07-11 01:26:49 -0300879out_put_per:
880 clk_disable_unprepare(spi_imx->clk_per);
Fabio Estevam130b82c2013-07-11 01:26:48 -0300881out_master_put:
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700882 spi_master_put(master);
Fabio Estevam130b82c2013-07-11 01:26:48 -0300883
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700884 return ret;
885}
886
Grant Likelyfd4a3192012-12-07 16:57:14 +0000887static int spi_imx_remove(struct platform_device *pdev)
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700888{
889 struct spi_master *master = platform_get_drvdata(pdev);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700890 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700891
892 spi_bitbang_stop(&spi_imx->bitbang);
893
894 writel(0, spi_imx->base + MXC_CSPICTRL);
Sascha Haueraa29d842012-03-07 09:30:22 +0100895 clk_disable_unprepare(spi_imx->clk_ipg);
Fabio Estevam83174622013-07-11 01:26:49 -0300896 clk_disable_unprepare(spi_imx->clk_per);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700897 spi_master_put(master);
898
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700899 return 0;
900}
901
902static struct platform_driver spi_imx_driver = {
903 .driver = {
904 .name = DRIVER_NAME,
905 .owner = THIS_MODULE,
Shawn Guo22a85e42011-07-10 01:16:41 +0800906 .of_match_table = spi_imx_dt_ids,
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700907 },
Uwe Kleine-Königf4ba6312010-09-09 15:29:01 +0200908 .id_table = spi_imx_devtype,
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700909 .probe = spi_imx_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000910 .remove = spi_imx_remove,
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700911};
Grant Likely940ab882011-10-05 11:29:49 -0600912module_platform_driver(spi_imx_driver);
Uwe Kleine-König6cdeb002009-10-01 15:44:28 -0700913
914MODULE_DESCRIPTION("SPI Master Controller driver");
915MODULE_AUTHOR("Sascha Hauer, Pengutronix");
916MODULE_LICENSE("GPL");
Fabio Estevam3133fba32013-01-07 20:42:55 -0200917MODULE_ALIAS("platform:" DRIVER_NAME);