blob: 0ee53c25ba58b5d772633e4736f5c2bbbaf72ab4 [file] [log] [blame]
Steven A. Falco44dab882009-09-22 16:45:58 -07001/*
2 * SPI_PPC4XX SPI controller driver.
3 *
4 * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
5 * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
7 *
8 * Based in part on drivers/spi/spi_s3c24xx.c
9 *
10 * Copyright (c) 2006 Ben Dooks
11 * Copyright (c) 2006 Simtec Electronics
12 * Ben Dooks <ben@simtec.co.uk>
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published
16 * by the Free Software Foundation.
17 */
18
19/*
20 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
21 * generate an interrupt to the CPU. This can cause high CPU utilization.
22 * This driver allows platforms to reduce the interrupt load on the CPU
23 * during SPI transfers by setting max_speed_hz via the device tree.
24 */
25
26#include <linux/module.h>
27#include <linux/init.h>
28#include <linux/sched.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090029#include <linux/slab.h>
Steven A. Falco44dab882009-09-22 16:45:58 -070030#include <linux/errno.h>
31#include <linux/wait.h>
32#include <linux/of_platform.h>
Steven A. Falco44dab882009-09-22 16:45:58 -070033#include <linux/of_gpio.h>
34#include <linux/interrupt.h>
35#include <linux/delay.h>
36
37#include <linux/gpio.h>
38#include <linux/spi/spi.h>
39#include <linux/spi/spi_bitbang.h>
40
41#include <asm/io.h>
42#include <asm/dcr.h>
43#include <asm/dcr-regs.h>
44
45/* bits in mode register - bit 0 is MSb */
46
47/*
48 * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
49 * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
50 * Note: This is the inverse of CPHA.
51 */
52#define SPI_PPC4XX_MODE_SCP (0x80 >> 3)
53
54/* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
55#define SPI_PPC4XX_MODE_SPE (0x80 >> 4)
56
57/*
58 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
59 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
60 * Note: This is identical to SPI_LSB_FIRST.
61 */
62#define SPI_PPC4XX_MODE_RD (0x80 >> 5)
63
64/*
65 * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
66 * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
67 * Note: This is identical to CPOL.
68 */
69#define SPI_PPC4XX_MODE_CI (0x80 >> 6)
70
71/*
72 * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
73 * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
74 */
75#define SPI_PPC4XX_MODE_IL (0x80 >> 7)
76
77/* bits in control register */
78/* starts a transfer when set */
79#define SPI_PPC4XX_CR_STR (0x80 >> 7)
80
81/* bits in status register */
82/* port is busy with a transfer */
83#define SPI_PPC4XX_SR_BSY (0x80 >> 6)
84/* RxD ready */
85#define SPI_PPC4XX_SR_RBR (0x80 >> 7)
86
87/* clock settings (SCP and CI) for various SPI modes */
88#define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0)
89#define SPI_CLK_MODE1 (0 | 0)
90#define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
91#define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI)
92
93#define DRIVER_NAME "spi_ppc4xx_of"
94
95struct spi_ppc4xx_regs {
96 u8 mode;
97 u8 rxd;
98 u8 txd;
99 u8 cr;
100 u8 sr;
101 u8 dummy;
102 /*
103 * Clock divisor modulus register
Masanari Iida886db6ac2012-07-30 23:16:14 +0900104 * This uses the following formula:
Steven A. Falco44dab882009-09-22 16:45:58 -0700105 * SCPClkOut = OPBCLK/(4(CDM + 1))
106 * or
107 * CDM = (OPBCLK/4*SCPClkOut) - 1
108 * bit 0 is the MSb!
109 */
110 u8 cdm;
111};
112
113/* SPI Controller driver's private data. */
114struct ppc4xx_spi {
115 /* bitbang has to be first */
116 struct spi_bitbang bitbang;
117 struct completion done;
118
119 u64 mapbase;
120 u64 mapsize;
121 int irqnum;
122 /* need this to set the SPI clock */
123 unsigned int opb_freq;
124
125 /* for transfers */
126 int len;
127 int count;
128 /* data buffers */
129 const unsigned char *tx;
130 unsigned char *rx;
131
132 int *gpios;
133
134 struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
135 struct spi_master *master;
136 struct device *dev;
137};
138
139/* need this so we can set the clock in the chipselect routine */
140struct spi_ppc4xx_cs {
141 u8 mode;
142};
143
144static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
145{
146 struct ppc4xx_spi *hw;
147 u8 data;
148
149 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
150 t->tx_buf, t->rx_buf, t->len);
151
152 hw = spi_master_get_devdata(spi->master);
153
154 hw->tx = t->tx_buf;
155 hw->rx = t->rx_buf;
156 hw->len = t->len;
157 hw->count = 0;
158
159 /* send the first byte */
160 data = hw->tx ? hw->tx[0] : 0;
161 out_8(&hw->regs->txd, data);
162 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
163 wait_for_completion(&hw->done);
164
165 return hw->count;
166}
167
168static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
169{
170 struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
171 struct spi_ppc4xx_cs *cs = spi->controller_state;
172 int scr;
173 u8 cdm = 0;
174 u32 speed;
175 u8 bits_per_word;
176
177 /* Start with the generic configuration for this device. */
178 bits_per_word = spi->bits_per_word;
179 speed = spi->max_speed_hz;
180
181 /*
182 * Modify the configuration if the transfer overrides it. Do not allow
183 * the transfer to overwrite the generic configuration with zeros.
184 */
185 if (t) {
186 if (t->bits_per_word)
187 bits_per_word = t->bits_per_word;
188
189 if (t->speed_hz)
190 speed = min(t->speed_hz, spi->max_speed_hz);
191 }
192
Steven A. Falco44dab882009-09-22 16:45:58 -0700193 if (!speed || (speed > spi->max_speed_hz)) {
194 dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
195 return -EINVAL;
196 }
197
Masanari Iida886db6ac2012-07-30 23:16:14 +0900198 /* Write new configuration */
Steven A. Falco44dab882009-09-22 16:45:58 -0700199 out_8(&hw->regs->mode, cs->mode);
200
201 /* Set the clock */
202 /* opb_freq was already divided by 4 */
203 scr = (hw->opb_freq / speed) - 1;
204 if (scr > 0)
205 cdm = min(scr, 0xff);
206
207 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
208
209 if (in_8(&hw->regs->cdm) != cdm)
210 out_8(&hw->regs->cdm, cdm);
211
212 spin_lock(&hw->bitbang.lock);
213 if (!hw->bitbang.busy) {
214 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
215 /* Need to ndelay here? */
216 }
217 spin_unlock(&hw->bitbang.lock);
218
219 return 0;
220}
221
222static int spi_ppc4xx_setup(struct spi_device *spi)
223{
224 struct spi_ppc4xx_cs *cs = spi->controller_state;
225
Steven A. Falco44dab882009-09-22 16:45:58 -0700226 if (!spi->max_speed_hz) {
227 dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
228 return -EINVAL;
229 }
230
231 if (cs == NULL) {
232 cs = kzalloc(sizeof *cs, GFP_KERNEL);
233 if (!cs)
234 return -ENOMEM;
235 spi->controller_state = cs;
236 }
237
238 /*
239 * We set all bits of the SPI0_MODE register, so,
240 * no need to read-modify-write
241 */
242 cs->mode = SPI_PPC4XX_MODE_SPE;
243
244 switch (spi->mode & (SPI_CPHA | SPI_CPOL)) {
245 case SPI_MODE_0:
246 cs->mode |= SPI_CLK_MODE0;
247 break;
248 case SPI_MODE_1:
249 cs->mode |= SPI_CLK_MODE1;
250 break;
251 case SPI_MODE_2:
252 cs->mode |= SPI_CLK_MODE2;
253 break;
254 case SPI_MODE_3:
255 cs->mode |= SPI_CLK_MODE3;
256 break;
257 }
258
259 if (spi->mode & SPI_LSB_FIRST)
260 cs->mode |= SPI_PPC4XX_MODE_RD;
261
262 return 0;
263}
264
265static void spi_ppc4xx_chipsel(struct spi_device *spi, int value)
266{
267 struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
268 unsigned int cs = spi->chip_select;
269 unsigned int cspol;
270
271 /*
272 * If there are no chip selects at all, or if this is the special
273 * case of a non-existent (dummy) chip select, do nothing.
274 */
275
276 if (!hw->master->num_chipselect || hw->gpios[cs] == -EEXIST)
277 return;
278
279 cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
280 if (value == BITBANG_CS_INACTIVE)
281 cspol = !cspol;
282
283 gpio_set_value(hw->gpios[cs], cspol);
284}
285
286static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
287{
288 struct ppc4xx_spi *hw;
289 u8 status;
290 u8 data;
291 unsigned int count;
292
293 hw = (struct ppc4xx_spi *)dev_id;
294
295 status = in_8(&hw->regs->sr);
296 if (!status)
297 return IRQ_NONE;
298
299 /*
300 * BSY de-asserts one cycle after the transfer is complete. The
301 * interrupt is asserted after the transfer is complete. The exact
302 * relationship is not documented, hence this code.
303 */
304
305 if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
306 u8 lstatus;
307 int cnt = 0;
308
309 dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
310 do {
311 ndelay(10);
312 lstatus = in_8(&hw->regs->sr);
313 } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
314
315 if (cnt >= 100) {
316 dev_err(hw->dev, "busywait: too many loops!\n");
317 complete(&hw->done);
318 return IRQ_HANDLED;
319 } else {
320 /* status is always 1 (RBR) here */
321 status = in_8(&hw->regs->sr);
322 dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
323 }
324 }
325
326 count = hw->count;
327 hw->count++;
328
329 /* RBR triggered this interrupt. Therefore, data must be ready. */
330 data = in_8(&hw->regs->rxd);
331 if (hw->rx)
332 hw->rx[count] = data;
333
334 count++;
335
336 if (count < hw->len) {
337 data = hw->tx ? hw->tx[count] : 0;
338 out_8(&hw->regs->txd, data);
339 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
340 } else {
341 complete(&hw->done);
342 }
343
344 return IRQ_HANDLED;
345}
346
347static void spi_ppc4xx_cleanup(struct spi_device *spi)
348{
349 kfree(spi->controller_state);
350}
351
352static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
353{
354 /*
355 * On all 4xx PPC's the SPI bus is shared/multiplexed with
356 * the 2nd I2C bus. We need to enable the the SPI bus before
357 * using it.
358 */
359
360 /* need to clear bit 14 to enable SPC */
361 dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
362}
363
364static void free_gpios(struct ppc4xx_spi *hw)
365{
366 if (hw->master->num_chipselect) {
367 int i;
368 for (i = 0; i < hw->master->num_chipselect; i++)
369 if (gpio_is_valid(hw->gpios[i]))
370 gpio_free(hw->gpios[i]);
371
372 kfree(hw->gpios);
373 hw->gpios = NULL;
374 }
375}
376
377/*
Grant Likely2dc11582010-08-06 09:25:50 -0600378 * platform_device layer stuff...
Steven A. Falco44dab882009-09-22 16:45:58 -0700379 */
Grant Likely2deff8d2013-02-05 13:27:35 +0000380static int spi_ppc4xx_of_probe(struct platform_device *op)
Steven A. Falco44dab882009-09-22 16:45:58 -0700381{
382 struct ppc4xx_spi *hw;
383 struct spi_master *master;
384 struct spi_bitbang *bbp;
385 struct resource resource;
Grant Likelyb5355072010-05-25 23:24:02 -0600386 struct device_node *np = op->dev.of_node;
Steven A. Falco44dab882009-09-22 16:45:58 -0700387 struct device *dev = &op->dev;
388 struct device_node *opbnp;
389 int ret;
390 int num_gpios;
391 const unsigned int *clk;
392
393 master = spi_alloc_master(dev, sizeof *hw);
394 if (master == NULL)
395 return -ENOMEM;
Anatolij Gustschin12b15e82010-07-27 22:35:58 +0200396 master->dev.of_node = np;
Jingoo Han24b5a822013-05-23 19:20:40 +0900397 platform_set_drvdata(op, master);
Steven A. Falco44dab882009-09-22 16:45:58 -0700398 hw = spi_master_get_devdata(master);
399 hw->master = spi_master_get(master);
400 hw->dev = dev;
401
402 init_completion(&hw->done);
403
404 /*
405 * A count of zero implies a single SPI device without any chip-select.
406 * Note that of_gpio_count counts all gpios assigned to this spi master.
407 * This includes both "null" gpio's and real ones.
408 */
409 num_gpios = of_gpio_count(np);
Grant Likelye80beb22013-02-12 17:48:37 +0000410 if (num_gpios > 0) {
Steven A. Falco44dab882009-09-22 16:45:58 -0700411 int i;
412
413 hw->gpios = kzalloc(sizeof(int) * num_gpios, GFP_KERNEL);
414 if (!hw->gpios) {
415 ret = -ENOMEM;
416 goto free_master;
417 }
418
419 for (i = 0; i < num_gpios; i++) {
420 int gpio;
421 enum of_gpio_flags flags;
422
423 gpio = of_get_gpio_flags(np, i, &flags);
424 hw->gpios[i] = gpio;
425
426 if (gpio_is_valid(gpio)) {
427 /* Real CS - set the initial state. */
428 ret = gpio_request(gpio, np->name);
429 if (ret < 0) {
430 dev_err(dev, "can't request gpio "
431 "#%d: %d\n", i, ret);
432 goto free_gpios;
433 }
434
435 gpio_direction_output(gpio,
436 !!(flags & OF_GPIO_ACTIVE_LOW));
437 } else if (gpio == -EEXIST) {
438 ; /* No CS, but that's OK. */
439 } else {
440 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
441 ret = -EINVAL;
442 goto free_gpios;
443 }
444 }
445 }
446
447 /* Setup the state for the bitbang driver */
448 bbp = &hw->bitbang;
449 bbp->master = hw->master;
450 bbp->setup_transfer = spi_ppc4xx_setupxfer;
451 bbp->chipselect = spi_ppc4xx_chipsel;
452 bbp->txrx_bufs = spi_ppc4xx_txrx;
453 bbp->use_dma = 0;
454 bbp->master->setup = spi_ppc4xx_setup;
455 bbp->master->cleanup = spi_ppc4xx_cleanup;
Stephen Warren24778be2013-05-21 20:36:35 -0600456 bbp->master->bits_per_word_mask = SPI_BPW_MASK(8);
Steven A. Falco44dab882009-09-22 16:45:58 -0700457
Steven A. Falco44dab882009-09-22 16:45:58 -0700458 /* the spi->mode bits understood by this driver: */
459 bbp->master->mode_bits =
460 SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
461
462 /* this many pins in all GPIO controllers */
Grant Likelye80beb22013-02-12 17:48:37 +0000463 bbp->master->num_chipselect = num_gpios > 0 ? num_gpios : 0;
Steven A. Falco44dab882009-09-22 16:45:58 -0700464
465 /* Get the clock for the OPB */
466 opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
467 if (opbnp == NULL) {
468 dev_err(dev, "OPB: cannot find node\n");
469 ret = -ENODEV;
470 goto free_gpios;
471 }
472 /* Get the clock (Hz) for the OPB */
473 clk = of_get_property(opbnp, "clock-frequency", NULL);
474 if (clk == NULL) {
475 dev_err(dev, "OPB: no clock-frequency property set\n");
476 of_node_put(opbnp);
477 ret = -ENODEV;
478 goto free_gpios;
479 }
480 hw->opb_freq = *clk;
481 hw->opb_freq >>= 2;
482 of_node_put(opbnp);
483
484 ret = of_address_to_resource(np, 0, &resource);
485 if (ret) {
486 dev_err(dev, "error while parsing device node resource\n");
487 goto free_gpios;
488 }
489 hw->mapbase = resource.start;
Joe Perches8e2943c2011-06-10 18:11:25 -0700490 hw->mapsize = resource_size(&resource);
Steven A. Falco44dab882009-09-22 16:45:58 -0700491
492 /* Sanity check */
493 if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
494 dev_err(dev, "too small to map registers\n");
495 ret = -EINVAL;
496 goto free_gpios;
497 }
498
499 /* Request IRQ */
500 hw->irqnum = irq_of_parse_and_map(np, 0);
501 ret = request_irq(hw->irqnum, spi_ppc4xx_int,
Yong Zhang38ada212011-10-22 17:56:55 +0800502 0, "spi_ppc4xx_of", (void *)hw);
Steven A. Falco44dab882009-09-22 16:45:58 -0700503 if (ret) {
504 dev_err(dev, "unable to allocate interrupt\n");
505 goto free_gpios;
506 }
507
508 if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
509 dev_err(dev, "resource unavailable\n");
510 ret = -EBUSY;
511 goto request_mem_error;
512 }
513
514 hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
515
516 if (!hw->regs) {
517 dev_err(dev, "unable to memory map registers\n");
518 ret = -ENXIO;
519 goto map_io_error;
520 }
521
522 spi_ppc4xx_enable(hw);
523
524 /* Finally register our spi controller */
525 dev->dma_mask = 0;
526 ret = spi_bitbang_start(bbp);
527 if (ret) {
528 dev_err(dev, "failed to register SPI master\n");
529 goto unmap_regs;
530 }
531
532 dev_info(dev, "driver initialized\n");
Steven A. Falco44dab882009-09-22 16:45:58 -0700533
534 return 0;
535
536unmap_regs:
537 iounmap(hw->regs);
538map_io_error:
539 release_mem_region(hw->mapbase, hw->mapsize);
540request_mem_error:
541 free_irq(hw->irqnum, hw);
542free_gpios:
543 free_gpios(hw);
544free_master:
Steven A. Falco44dab882009-09-22 16:45:58 -0700545 spi_master_put(master);
546
547 dev_err(dev, "initialization failed\n");
548 return ret;
549}
550
Grant Likely2deff8d2013-02-05 13:27:35 +0000551static int spi_ppc4xx_of_remove(struct platform_device *op)
Steven A. Falco44dab882009-09-22 16:45:58 -0700552{
Jingoo Han24b5a822013-05-23 19:20:40 +0900553 struct spi_master *master = platform_get_drvdata(op);
Steven A. Falco44dab882009-09-22 16:45:58 -0700554 struct ppc4xx_spi *hw = spi_master_get_devdata(master);
555
556 spi_bitbang_stop(&hw->bitbang);
Steven A. Falco44dab882009-09-22 16:45:58 -0700557 release_mem_region(hw->mapbase, hw->mapsize);
558 free_irq(hw->irqnum, hw);
559 iounmap(hw->regs);
560 free_gpios(hw);
561 return 0;
562}
563
Márton Németh631e61b2010-01-20 13:49:44 -0700564static const struct of_device_id spi_ppc4xx_of_match[] = {
Steven A. Falco44dab882009-09-22 16:45:58 -0700565 { .compatible = "ibm,ppc4xx-spi", },
566 {},
567};
568
569MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
570
Grant Likely18d306d2011-02-22 21:02:43 -0700571static struct platform_driver spi_ppc4xx_of_driver = {
Steven A. Falco44dab882009-09-22 16:45:58 -0700572 .probe = spi_ppc4xx_of_probe,
Grant Likely2deff8d2013-02-05 13:27:35 +0000573 .remove = spi_ppc4xx_of_remove,
Steven A. Falco44dab882009-09-22 16:45:58 -0700574 .driver = {
575 .name = DRIVER_NAME,
576 .owner = THIS_MODULE,
Grant Likely40182942010-04-13 16:13:02 -0700577 .of_match_table = spi_ppc4xx_of_match,
Steven A. Falco44dab882009-09-22 16:45:58 -0700578 },
579};
Grant Likely940ab882011-10-05 11:29:49 -0600580module_platform_driver(spi_ppc4xx_of_driver);
Steven A. Falco44dab882009-09-22 16:45:58 -0700581
582MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
583MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
584MODULE_LICENSE("GPL");