Dylan Reid | 3c320f3 | 2014-05-19 19:18:27 -0700 | [diff] [blame] | 1 | NVIDIA Tegra30 HDA controller |
| 2 | |
| 3 | Required properties: |
Paul Walmsley | 193c9d2 | 2015-01-30 15:11:04 -0700 | [diff] [blame] | 4 | - compatible : For Tegra30, must contain "nvidia,tegra30-hda". Otherwise, |
| 5 | must contain '"nvidia,<chip>-hda", "nvidia,tegra30-hda"', where <chip> is |
| 6 | tegra114, tegra124, or tegra132. |
Dylan Reid | 3c320f3 | 2014-05-19 19:18:27 -0700 | [diff] [blame] | 7 | - reg : Should contain the HDA registers location and length. |
| 8 | - interrupts : The interrupt from the HDA controller. |
| 9 | - clocks : Must contain an entry for each required entry in clock-names. |
| 10 | See ../clocks/clock-bindings.txt for details. |
| 11 | - clock-names : Must include the following entries: hda, hdacodec_2x, hda2hdmi |
| 12 | - resets : Must contain an entry for each entry in reset-names. |
| 13 | See ../reset/reset.txt for details. |
| 14 | - reset-names : Must include the following entries: hda, hdacodec_2x, hda2hdmi |
| 15 | |
| 16 | Example: |
| 17 | |
| 18 | hda@0,70030000 { |
| 19 | compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; |
| 20 | reg = <0x0 0x70030000 0x0 0x10000>; |
| 21 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| 22 | clocks = <&tegra_car TEGRA124_CLK_HDA>, |
| 23 | <&tegra_car TEGRA124_CLK_HDA2HDMI>, |
| 24 | <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; |
Dylan Reid | 2c6db77 | 2014-05-30 19:15:47 -0700 | [diff] [blame] | 25 | clock-names = "hda", "hda2hdmi", "hda2codec_2x"; |
Dylan Reid | 3c320f3 | 2014-05-19 19:18:27 -0700 | [diff] [blame] | 26 | resets = <&tegra_car 125>, /* hda */ |
| 27 | <&tegra_car 128>; /* hda2hdmi */ |
| 28 | <&tegra_car 111>, /* hda2codec_2x */ |
Dylan Reid | 2c6db77 | 2014-05-30 19:15:47 -0700 | [diff] [blame] | 29 | reset-names = "hda", "hda2hdmi", "hda2codec_2x"; |
Dylan Reid | 3c320f3 | 2014-05-19 19:18:27 -0700 | [diff] [blame] | 30 | }; |