Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1 | /* |
| 2 | * RTL8XXXU mac80211 USB driver |
| 3 | * |
| 4 | * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com> |
| 5 | * |
| 6 | * Portions, notably calibration code: |
| 7 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. |
| 8 | * |
| 9 | * This driver was written as a replacement for the vendor provided |
| 10 | * rtl8723au driver. As the Realtek 8xxx chips are very similar in |
| 11 | * their programming interface, I have started adding support for |
| 12 | * additional 8xxx chips like the 8192cu, 8188cus, etc. |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify it |
| 15 | * under the terms of version 2 of the GNU General Public License as |
| 16 | * published by the Free Software Foundation. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 19 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 21 | * more details. |
| 22 | */ |
| 23 | |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/sched.h> |
| 27 | #include <linux/errno.h> |
| 28 | #include <linux/slab.h> |
| 29 | #include <linux/module.h> |
| 30 | #include <linux/spinlock.h> |
| 31 | #include <linux/list.h> |
| 32 | #include <linux/usb.h> |
| 33 | #include <linux/netdevice.h> |
| 34 | #include <linux/etherdevice.h> |
| 35 | #include <linux/ethtool.h> |
| 36 | #include <linux/wireless.h> |
| 37 | #include <linux/firmware.h> |
| 38 | #include <linux/moduleparam.h> |
| 39 | #include <net/mac80211.h> |
| 40 | #include "rtl8xxxu.h" |
| 41 | #include "rtl8xxxu_regs.h" |
| 42 | |
| 43 | #define DRIVER_NAME "rtl8xxxu" |
| 44 | |
| 45 | static int rtl8xxxu_debug; |
| 46 | static bool rtl8xxxu_ht40_2g; |
| 47 | |
| 48 | MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>"); |
| 49 | MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver"); |
| 50 | MODULE_LICENSE("GPL"); |
| 51 | MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin"); |
| 52 | MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin"); |
| 53 | MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin"); |
| 54 | MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin"); |
| 55 | MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin"); |
| 56 | MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin"); |
| 57 | |
| 58 | module_param_named(debug, rtl8xxxu_debug, int, 0600); |
| 59 | MODULE_PARM_DESC(debug, "Set debug mask"); |
| 60 | module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600); |
| 61 | MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band"); |
| 62 | |
| 63 | #define USB_VENDOR_ID_REALTEK 0x0bda |
| 64 | /* Minimum IEEE80211_MAX_FRAME_LEN */ |
| 65 | #define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN |
| 66 | #define RTL8XXXU_RX_URBS 32 |
| 67 | #define RTL8XXXU_RX_URB_PENDING_WATER 8 |
| 68 | #define RTL8XXXU_TX_URBS 64 |
| 69 | #define RTL8XXXU_TX_URB_LOW_WATER 25 |
| 70 | #define RTL8XXXU_TX_URB_HIGH_WATER 32 |
| 71 | |
| 72 | static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, |
| 73 | struct rtl8xxxu_rx_urb *rx_urb); |
| 74 | |
| 75 | static struct ieee80211_rate rtl8xxxu_rates[] = { |
| 76 | { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 }, |
| 77 | { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 }, |
| 78 | { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 }, |
| 79 | { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 }, |
| 80 | { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 }, |
| 81 | { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 }, |
| 82 | { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 }, |
| 83 | { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 }, |
| 84 | { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 }, |
| 85 | { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 }, |
| 86 | { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 }, |
| 87 | { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 }, |
| 88 | }; |
| 89 | |
| 90 | static struct ieee80211_channel rtl8xxxu_channels_2g[] = { |
| 91 | { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412, |
| 92 | .hw_value = 1, .max_power = 30 }, |
| 93 | { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417, |
| 94 | .hw_value = 2, .max_power = 30 }, |
| 95 | { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422, |
| 96 | .hw_value = 3, .max_power = 30 }, |
| 97 | { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427, |
| 98 | .hw_value = 4, .max_power = 30 }, |
| 99 | { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432, |
| 100 | .hw_value = 5, .max_power = 30 }, |
| 101 | { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437, |
| 102 | .hw_value = 6, .max_power = 30 }, |
| 103 | { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442, |
| 104 | .hw_value = 7, .max_power = 30 }, |
| 105 | { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447, |
| 106 | .hw_value = 8, .max_power = 30 }, |
| 107 | { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452, |
| 108 | .hw_value = 9, .max_power = 30 }, |
| 109 | { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457, |
| 110 | .hw_value = 10, .max_power = 30 }, |
| 111 | { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462, |
| 112 | .hw_value = 11, .max_power = 30 }, |
| 113 | { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467, |
| 114 | .hw_value = 12, .max_power = 30 }, |
| 115 | { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472, |
| 116 | .hw_value = 13, .max_power = 30 }, |
| 117 | { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484, |
| 118 | .hw_value = 14, .max_power = 30 } |
| 119 | }; |
| 120 | |
| 121 | static struct ieee80211_supported_band rtl8xxxu_supported_band = { |
| 122 | .channels = rtl8xxxu_channels_2g, |
| 123 | .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g), |
| 124 | .bitrates = rtl8xxxu_rates, |
| 125 | .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates), |
| 126 | }; |
| 127 | |
| 128 | static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = { |
| 129 | {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, |
| 130 | {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, |
| 131 | {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, |
| 132 | {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, |
| 133 | {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, |
| 134 | {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, |
| 135 | {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, |
| 136 | {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, |
| 137 | {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, |
| 138 | {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, |
| 139 | {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, |
| 140 | {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, |
| 141 | {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, |
| 142 | {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, |
| 143 | {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, |
| 144 | {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, |
| 145 | {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, |
| 146 | {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, |
| 147 | {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, |
| 148 | {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, |
| 149 | {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, |
| 150 | {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff}, |
| 151 | }; |
| 152 | |
| 153 | static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = { |
| 154 | {0x800, 0x80040000}, {0x804, 0x00000003}, |
| 155 | {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, |
| 156 | {0x810, 0x10001331}, {0x814, 0x020c3d10}, |
| 157 | {0x818, 0x02200385}, {0x81c, 0x00000000}, |
| 158 | {0x820, 0x01000100}, {0x824, 0x00390004}, |
| 159 | {0x828, 0x00000000}, {0x82c, 0x00000000}, |
| 160 | {0x830, 0x00000000}, {0x834, 0x00000000}, |
| 161 | {0x838, 0x00000000}, {0x83c, 0x00000000}, |
| 162 | {0x840, 0x00010000}, {0x844, 0x00000000}, |
| 163 | {0x848, 0x00000000}, {0x84c, 0x00000000}, |
| 164 | {0x850, 0x00000000}, {0x854, 0x00000000}, |
| 165 | {0x858, 0x569a569a}, {0x85c, 0x001b25a4}, |
| 166 | {0x860, 0x66f60110}, {0x864, 0x061f0130}, |
| 167 | {0x868, 0x00000000}, {0x86c, 0x32323200}, |
| 168 | {0x870, 0x07000760}, {0x874, 0x22004000}, |
| 169 | {0x878, 0x00000808}, {0x87c, 0x00000000}, |
| 170 | {0x880, 0xc0083070}, {0x884, 0x000004d5}, |
| 171 | {0x888, 0x00000000}, {0x88c, 0xccc000c0}, |
| 172 | {0x890, 0x00000800}, {0x894, 0xfffffffe}, |
| 173 | {0x898, 0x40302010}, {0x89c, 0x00706050}, |
| 174 | {0x900, 0x00000000}, {0x904, 0x00000023}, |
| 175 | {0x908, 0x00000000}, {0x90c, 0x81121111}, |
| 176 | {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, |
| 177 | {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, |
| 178 | {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, |
| 179 | {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, |
| 180 | {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, |
| 181 | {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, |
| 182 | {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, |
| 183 | {0xa78, 0x00000900}, |
| 184 | {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, |
| 185 | {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, |
| 186 | {0xc10, 0x08800000}, {0xc14, 0x40000100}, |
| 187 | {0xc18, 0x08800000}, {0xc1c, 0x40000100}, |
| 188 | {0xc20, 0x00000000}, {0xc24, 0x00000000}, |
| 189 | {0xc28, 0x00000000}, {0xc2c, 0x00000000}, |
| 190 | {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, |
| 191 | {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, |
| 192 | {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, |
| 193 | {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, |
| 194 | {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, |
| 195 | {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, |
| 196 | {0xc60, 0x00000000}, {0xc64, 0x7112848b}, |
| 197 | {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, |
| 198 | {0xc70, 0x2c7f000d}, {0xc74, 0x018610db}, |
| 199 | {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, |
| 200 | {0xc80, 0x40000100}, {0xc84, 0x20f60000}, |
| 201 | {0xc88, 0x40000100}, {0xc8c, 0x20200000}, |
| 202 | {0xc90, 0x00121820}, {0xc94, 0x00000000}, |
| 203 | {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, |
| 204 | {0xca0, 0x00000000}, {0xca4, 0x00000080}, |
| 205 | {0xca8, 0x00000000}, {0xcac, 0x00000000}, |
| 206 | {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, |
| 207 | {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, |
| 208 | {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, |
| 209 | {0xcc8, 0x00000000}, {0xccc, 0x00000000}, |
| 210 | {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, |
| 211 | {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, |
| 212 | {0xce0, 0x00222222}, {0xce4, 0x00000000}, |
| 213 | {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, |
| 214 | {0xd00, 0x00080740}, {0xd04, 0x00020401}, |
| 215 | {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, |
| 216 | {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, |
| 217 | {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, |
| 218 | {0xd30, 0x00000000}, {0xd34, 0x80608000}, |
| 219 | {0xd38, 0x00000000}, {0xd3c, 0x00027293}, |
| 220 | {0xd40, 0x00000000}, {0xd44, 0x00000000}, |
| 221 | {0xd48, 0x00000000}, {0xd4c, 0x00000000}, |
| 222 | {0xd50, 0x6437140a}, {0xd54, 0x00000000}, |
| 223 | {0xd58, 0x00000000}, {0xd5c, 0x30032064}, |
| 224 | {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, |
| 225 | {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, |
| 226 | {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, |
| 227 | {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, |
| 228 | {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, |
| 229 | {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, |
| 230 | {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, |
| 231 | {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, |
| 232 | {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, |
| 233 | {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, |
| 234 | {0xe44, 0x01004800}, {0xe48, 0xfb000000}, |
| 235 | {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, |
| 236 | {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, |
| 237 | {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, |
| 238 | {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0}, |
| 239 | {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0}, |
| 240 | {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0}, |
| 241 | {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0}, |
| 242 | {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0}, |
| 243 | {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0}, |
| 244 | {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0}, |
| 245 | {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0}, |
| 246 | {0xf14, 0x00000003}, {0xf4c, 0x00000000}, |
| 247 | {0xf00, 0x00000300}, |
| 248 | {0xffff, 0xffffffff}, |
| 249 | }; |
| 250 | |
| 251 | static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = { |
| 252 | {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, |
| 253 | {0x800, 0x80040002}, {0x804, 0x00000003}, |
| 254 | {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, |
| 255 | {0x810, 0x10000330}, {0x814, 0x020c3d10}, |
| 256 | {0x818, 0x02200385}, {0x81c, 0x00000000}, |
| 257 | {0x820, 0x01000100}, {0x824, 0x00390004}, |
| 258 | {0x828, 0x01000100}, {0x82c, 0x00390004}, |
| 259 | {0x830, 0x27272727}, {0x834, 0x27272727}, |
| 260 | {0x838, 0x27272727}, {0x83c, 0x27272727}, |
| 261 | {0x840, 0x00010000}, {0x844, 0x00010000}, |
| 262 | {0x848, 0x27272727}, {0x84c, 0x27272727}, |
| 263 | {0x850, 0x00000000}, {0x854, 0x00000000}, |
| 264 | {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4}, |
| 265 | {0x860, 0x66e60230}, {0x864, 0x061f0130}, |
| 266 | {0x868, 0x27272727}, {0x86c, 0x2b2b2b27}, |
| 267 | {0x870, 0x07000700}, {0x874, 0x22184000}, |
| 268 | {0x878, 0x08080808}, {0x87c, 0x00000000}, |
| 269 | {0x880, 0xc0083070}, {0x884, 0x000004d5}, |
| 270 | {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, |
| 271 | {0x890, 0x00000800}, {0x894, 0xfffffffe}, |
| 272 | {0x898, 0x40302010}, {0x89c, 0x00706050}, |
| 273 | {0x900, 0x00000000}, {0x904, 0x00000023}, |
| 274 | {0x908, 0x00000000}, {0x90c, 0x81121313}, |
| 275 | {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, |
| 276 | {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, |
| 277 | {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, |
| 278 | {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, |
| 279 | {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, |
| 280 | {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, |
| 281 | {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, |
| 282 | {0xc00, 0x48071d40}, {0xc04, 0x03a05633}, |
| 283 | {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, |
| 284 | {0xc10, 0x08800000}, {0xc14, 0x40000100}, |
| 285 | {0xc18, 0x08800000}, {0xc1c, 0x40000100}, |
| 286 | {0xc20, 0x00000000}, {0xc24, 0x00000000}, |
| 287 | {0xc28, 0x00000000}, {0xc2c, 0x00000000}, |
| 288 | {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf}, |
| 289 | {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, |
| 290 | {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, |
| 291 | {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, |
| 292 | {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, |
| 293 | {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, |
| 294 | {0xc60, 0x00000000}, {0xc64, 0x5116848b}, |
| 295 | {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, |
| 296 | {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b}, |
| 297 | {0xc78, 0x0000001f}, {0xc7c, 0x00b99612}, |
| 298 | {0xc80, 0x40000100}, {0xc84, 0x20f60000}, |
| 299 | {0xc88, 0x40000100}, {0xc8c, 0xa0e40000}, |
| 300 | {0xc90, 0x00121820}, {0xc94, 0x00000000}, |
| 301 | {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, |
| 302 | {0xca0, 0x00000000}, {0xca4, 0x00000080}, |
| 303 | {0xca8, 0x00000000}, {0xcac, 0x00000000}, |
| 304 | {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, |
| 305 | {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, |
| 306 | {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, |
| 307 | {0xcc8, 0x00000000}, {0xccc, 0x00000000}, |
| 308 | {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, |
| 309 | {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, |
| 310 | {0xce0, 0x00222222}, {0xce4, 0x00000000}, |
| 311 | {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, |
| 312 | {0xd00, 0x00080740}, {0xd04, 0x00020403}, |
| 313 | {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, |
| 314 | {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, |
| 315 | {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, |
| 316 | {0xd30, 0x00000000}, {0xd34, 0x80608000}, |
| 317 | {0xd38, 0x00000000}, {0xd3c, 0x00027293}, |
| 318 | {0xd40, 0x00000000}, {0xd44, 0x00000000}, |
| 319 | {0xd48, 0x00000000}, {0xd4c, 0x00000000}, |
| 320 | {0xd50, 0x6437140a}, {0xd54, 0x00000000}, |
| 321 | {0xd58, 0x00000000}, {0xd5c, 0x30032064}, |
| 322 | {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, |
| 323 | {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, |
| 324 | {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, |
| 325 | {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, |
| 326 | {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, |
| 327 | {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, |
| 328 | {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, |
| 329 | {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, |
| 330 | {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, |
| 331 | {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, |
| 332 | {0xe44, 0x01004800}, {0xe48, 0xfb000000}, |
| 333 | {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, |
| 334 | {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, |
| 335 | {0xe5c, 0x28160d05}, {0xe60, 0x00000010}, |
| 336 | {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4}, |
| 337 | {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4}, |
| 338 | {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4}, |
| 339 | {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4}, |
| 340 | {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4}, |
| 341 | {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4}, |
| 342 | {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4}, |
| 343 | {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4}, |
| 344 | {0xf14, 0x00000003}, {0xf4c, 0x00000000}, |
| 345 | {0xf00, 0x00000300}, |
| 346 | {0xffff, 0xffffffff}, |
| 347 | }; |
| 348 | |
| 349 | static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = { |
| 350 | {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, |
| 351 | {0x040, 0x000c0004}, {0x800, 0x80040000}, |
| 352 | {0x804, 0x00000001}, {0x808, 0x0000fc00}, |
| 353 | {0x80c, 0x0000000a}, {0x810, 0x10005388}, |
| 354 | {0x814, 0x020c3d10}, {0x818, 0x02200385}, |
| 355 | {0x81c, 0x00000000}, {0x820, 0x01000100}, |
| 356 | {0x824, 0x00390204}, {0x828, 0x00000000}, |
| 357 | {0x82c, 0x00000000}, {0x830, 0x00000000}, |
| 358 | {0x834, 0x00000000}, {0x838, 0x00000000}, |
| 359 | {0x83c, 0x00000000}, {0x840, 0x00010000}, |
| 360 | {0x844, 0x00000000}, {0x848, 0x00000000}, |
| 361 | {0x84c, 0x00000000}, {0x850, 0x00000000}, |
| 362 | {0x854, 0x00000000}, {0x858, 0x569a569a}, |
| 363 | {0x85c, 0x001b25a4}, {0x860, 0x66e60230}, |
| 364 | {0x864, 0x061f0130}, {0x868, 0x00000000}, |
| 365 | {0x86c, 0x20202000}, {0x870, 0x03000300}, |
| 366 | {0x874, 0x22004000}, {0x878, 0x00000808}, |
| 367 | {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070}, |
| 368 | {0x884, 0x000004d5}, {0x888, 0x00000000}, |
| 369 | {0x88c, 0xccc000c0}, {0x890, 0x00000800}, |
| 370 | {0x894, 0xfffffffe}, {0x898, 0x40302010}, |
| 371 | {0x89c, 0x00706050}, {0x900, 0x00000000}, |
| 372 | {0x904, 0x00000023}, {0x908, 0x00000000}, |
| 373 | {0x90c, 0x81121111}, {0xa00, 0x00d047c8}, |
| 374 | {0xa04, 0x80ff000c}, {0xa08, 0x8c838300}, |
| 375 | {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78}, |
| 376 | {0xa14, 0x11144028}, {0xa18, 0x00881117}, |
| 377 | {0xa1c, 0x89140f00}, {0xa20, 0x15160000}, |
| 378 | {0xa24, 0x070b0f12}, {0xa28, 0x00000104}, |
| 379 | {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00}, |
| 380 | {0xa74, 0x00000007}, {0xc00, 0x48071d40}, |
| 381 | {0xc04, 0x03a05611}, {0xc08, 0x000000e4}, |
| 382 | {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, |
| 383 | {0xc14, 0x40000100}, {0xc18, 0x08800000}, |
| 384 | {0xc1c, 0x40000100}, {0xc20, 0x00000000}, |
| 385 | {0xc24, 0x00000000}, {0xc28, 0x00000000}, |
| 386 | {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44}, |
| 387 | {0xc34, 0x469652cf}, {0xc38, 0x49795994}, |
| 388 | {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, |
| 389 | {0xc44, 0x000100b7}, {0xc48, 0xec020107}, |
| 390 | {0xc4c, 0x007f037f}, {0xc50, 0x6954342e}, |
| 391 | {0xc54, 0x43bc0094}, {0xc58, 0x6954342f}, |
| 392 | {0xc5c, 0x433c0094}, {0xc60, 0x00000000}, |
| 393 | {0xc64, 0x5116848b}, {0xc68, 0x47c00bff}, |
| 394 | {0xc6c, 0x00000036}, {0xc70, 0x2c46000d}, |
| 395 | {0xc74, 0x018610db}, {0xc78, 0x0000001f}, |
| 396 | {0xc7c, 0x00b91612}, {0xc80, 0x24000090}, |
| 397 | {0xc84, 0x20f60000}, {0xc88, 0x24000090}, |
| 398 | {0xc8c, 0x20200000}, {0xc90, 0x00121820}, |
| 399 | {0xc94, 0x00000000}, {0xc98, 0x00121820}, |
| 400 | {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, |
| 401 | {0xca4, 0x00000080}, {0xca8, 0x00000000}, |
| 402 | {0xcac, 0x00000000}, {0xcb0, 0x00000000}, |
| 403 | {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, |
| 404 | {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, |
| 405 | {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, |
| 406 | {0xccc, 0x00000000}, {0xcd0, 0x00000000}, |
| 407 | {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, |
| 408 | {0xcdc, 0x00766932}, {0xce0, 0x00222222}, |
| 409 | {0xce4, 0x00000000}, {0xce8, 0x37644302}, |
| 410 | {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, |
| 411 | {0xd04, 0x00020401}, {0xd08, 0x0000907f}, |
| 412 | {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, |
| 413 | {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, |
| 414 | {0xd2c, 0xcc979975}, {0xd30, 0x00000000}, |
| 415 | {0xd34, 0x80608000}, {0xd38, 0x00000000}, |
| 416 | {0xd3c, 0x00027293}, {0xd40, 0x00000000}, |
| 417 | {0xd44, 0x00000000}, {0xd48, 0x00000000}, |
| 418 | {0xd4c, 0x00000000}, {0xd50, 0x6437140a}, |
| 419 | {0xd54, 0x00000000}, {0xd58, 0x00000000}, |
| 420 | {0xd5c, 0x30032064}, {0xd60, 0x4653de68}, |
| 421 | {0xd64, 0x04518a3c}, {0xd68, 0x00002101}, |
| 422 | {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e}, |
| 423 | {0xd74, 0x322c2220}, {0xd78, 0x000e3c24}, |
| 424 | {0xe00, 0x24242424}, {0xe04, 0x24242424}, |
| 425 | {0xe08, 0x03902024}, {0xe10, 0x24242424}, |
| 426 | {0xe14, 0x24242424}, {0xe18, 0x24242424}, |
| 427 | {0xe1c, 0x24242424}, {0xe28, 0x00000000}, |
| 428 | {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, |
| 429 | {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, |
| 430 | {0xe40, 0x01007c00}, {0xe44, 0x01004800}, |
| 431 | {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, |
| 432 | {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, |
| 433 | {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, |
| 434 | {0xe60, 0x00000008}, {0xe68, 0x001b25a4}, |
| 435 | {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0}, |
| 436 | {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0}, |
| 437 | {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0}, |
| 438 | {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0}, |
| 439 | {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0}, |
| 440 | {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0}, |
| 441 | {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0}, |
| 442 | {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448}, |
| 443 | {0xf14, 0x00000003}, {0xf4c, 0x00000000}, |
| 444 | {0xf00, 0x00000300}, |
| 445 | {0xffff, 0xffffffff}, |
| 446 | }; |
| 447 | |
| 448 | static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = { |
| 449 | {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, |
| 450 | {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, |
| 451 | {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, |
| 452 | {0xc78, 0x7a060001}, {0xc78, 0x79070001}, |
| 453 | {0xc78, 0x78080001}, {0xc78, 0x77090001}, |
| 454 | {0xc78, 0x760a0001}, {0xc78, 0x750b0001}, |
| 455 | {0xc78, 0x740c0001}, {0xc78, 0x730d0001}, |
| 456 | {0xc78, 0x720e0001}, {0xc78, 0x710f0001}, |
| 457 | {0xc78, 0x70100001}, {0xc78, 0x6f110001}, |
| 458 | {0xc78, 0x6e120001}, {0xc78, 0x6d130001}, |
| 459 | {0xc78, 0x6c140001}, {0xc78, 0x6b150001}, |
| 460 | {0xc78, 0x6a160001}, {0xc78, 0x69170001}, |
| 461 | {0xc78, 0x68180001}, {0xc78, 0x67190001}, |
| 462 | {0xc78, 0x661a0001}, {0xc78, 0x651b0001}, |
| 463 | {0xc78, 0x641c0001}, {0xc78, 0x631d0001}, |
| 464 | {0xc78, 0x621e0001}, {0xc78, 0x611f0001}, |
| 465 | {0xc78, 0x60200001}, {0xc78, 0x49210001}, |
| 466 | {0xc78, 0x48220001}, {0xc78, 0x47230001}, |
| 467 | {0xc78, 0x46240001}, {0xc78, 0x45250001}, |
| 468 | {0xc78, 0x44260001}, {0xc78, 0x43270001}, |
| 469 | {0xc78, 0x42280001}, {0xc78, 0x41290001}, |
| 470 | {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, |
| 471 | {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, |
| 472 | {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, |
| 473 | {0xc78, 0x21300001}, {0xc78, 0x20310001}, |
| 474 | {0xc78, 0x06320001}, {0xc78, 0x05330001}, |
| 475 | {0xc78, 0x04340001}, {0xc78, 0x03350001}, |
| 476 | {0xc78, 0x02360001}, {0xc78, 0x01370001}, |
| 477 | {0xc78, 0x00380001}, {0xc78, 0x00390001}, |
| 478 | {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, |
| 479 | {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, |
| 480 | {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, |
| 481 | {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, |
| 482 | {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, |
| 483 | {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, |
| 484 | {0xc78, 0x7a460001}, {0xc78, 0x79470001}, |
| 485 | {0xc78, 0x78480001}, {0xc78, 0x77490001}, |
| 486 | {0xc78, 0x764a0001}, {0xc78, 0x754b0001}, |
| 487 | {0xc78, 0x744c0001}, {0xc78, 0x734d0001}, |
| 488 | {0xc78, 0x724e0001}, {0xc78, 0x714f0001}, |
| 489 | {0xc78, 0x70500001}, {0xc78, 0x6f510001}, |
| 490 | {0xc78, 0x6e520001}, {0xc78, 0x6d530001}, |
| 491 | {0xc78, 0x6c540001}, {0xc78, 0x6b550001}, |
| 492 | {0xc78, 0x6a560001}, {0xc78, 0x69570001}, |
| 493 | {0xc78, 0x68580001}, {0xc78, 0x67590001}, |
| 494 | {0xc78, 0x665a0001}, {0xc78, 0x655b0001}, |
| 495 | {0xc78, 0x645c0001}, {0xc78, 0x635d0001}, |
| 496 | {0xc78, 0x625e0001}, {0xc78, 0x615f0001}, |
| 497 | {0xc78, 0x60600001}, {0xc78, 0x49610001}, |
| 498 | {0xc78, 0x48620001}, {0xc78, 0x47630001}, |
| 499 | {0xc78, 0x46640001}, {0xc78, 0x45650001}, |
| 500 | {0xc78, 0x44660001}, {0xc78, 0x43670001}, |
| 501 | {0xc78, 0x42680001}, {0xc78, 0x41690001}, |
| 502 | {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, |
| 503 | {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, |
| 504 | {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, |
| 505 | {0xc78, 0x21700001}, {0xc78, 0x20710001}, |
| 506 | {0xc78, 0x06720001}, {0xc78, 0x05730001}, |
| 507 | {0xc78, 0x04740001}, {0xc78, 0x03750001}, |
| 508 | {0xc78, 0x02760001}, {0xc78, 0x01770001}, |
| 509 | {0xc78, 0x00780001}, {0xc78, 0x00790001}, |
| 510 | {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, |
| 511 | {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, |
| 512 | {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, |
| 513 | {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, |
| 514 | {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, |
| 515 | {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, |
| 516 | {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, |
| 517 | {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, |
| 518 | {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, |
| 519 | {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, |
| 520 | {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, |
| 521 | {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, |
| 522 | {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, |
| 523 | {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, |
| 524 | {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, |
| 525 | {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, |
| 526 | {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, |
| 527 | {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, |
| 528 | {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, |
| 529 | {0xffff, 0xffffffff} |
| 530 | }; |
| 531 | |
| 532 | static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = { |
| 533 | {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, |
| 534 | {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, |
| 535 | {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, |
| 536 | {0xc78, 0x7b060001}, {0xc78, 0x7b070001}, |
| 537 | {0xc78, 0x7b080001}, {0xc78, 0x7a090001}, |
| 538 | {0xc78, 0x790a0001}, {0xc78, 0x780b0001}, |
| 539 | {0xc78, 0x770c0001}, {0xc78, 0x760d0001}, |
| 540 | {0xc78, 0x750e0001}, {0xc78, 0x740f0001}, |
| 541 | {0xc78, 0x73100001}, {0xc78, 0x72110001}, |
| 542 | {0xc78, 0x71120001}, {0xc78, 0x70130001}, |
| 543 | {0xc78, 0x6f140001}, {0xc78, 0x6e150001}, |
| 544 | {0xc78, 0x6d160001}, {0xc78, 0x6c170001}, |
| 545 | {0xc78, 0x6b180001}, {0xc78, 0x6a190001}, |
| 546 | {0xc78, 0x691a0001}, {0xc78, 0x681b0001}, |
| 547 | {0xc78, 0x671c0001}, {0xc78, 0x661d0001}, |
| 548 | {0xc78, 0x651e0001}, {0xc78, 0x641f0001}, |
| 549 | {0xc78, 0x63200001}, {0xc78, 0x62210001}, |
| 550 | {0xc78, 0x61220001}, {0xc78, 0x60230001}, |
| 551 | {0xc78, 0x46240001}, {0xc78, 0x45250001}, |
| 552 | {0xc78, 0x44260001}, {0xc78, 0x43270001}, |
| 553 | {0xc78, 0x42280001}, {0xc78, 0x41290001}, |
| 554 | {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, |
| 555 | {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, |
| 556 | {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, |
| 557 | {0xc78, 0x21300001}, {0xc78, 0x20310001}, |
| 558 | {0xc78, 0x06320001}, {0xc78, 0x05330001}, |
| 559 | {0xc78, 0x04340001}, {0xc78, 0x03350001}, |
| 560 | {0xc78, 0x02360001}, {0xc78, 0x01370001}, |
| 561 | {0xc78, 0x00380001}, {0xc78, 0x00390001}, |
| 562 | {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, |
| 563 | {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, |
| 564 | {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, |
| 565 | {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, |
| 566 | {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, |
| 567 | {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, |
| 568 | {0xc78, 0x7b460001}, {0xc78, 0x7b470001}, |
| 569 | {0xc78, 0x7b480001}, {0xc78, 0x7a490001}, |
| 570 | {0xc78, 0x794a0001}, {0xc78, 0x784b0001}, |
| 571 | {0xc78, 0x774c0001}, {0xc78, 0x764d0001}, |
| 572 | {0xc78, 0x754e0001}, {0xc78, 0x744f0001}, |
| 573 | {0xc78, 0x73500001}, {0xc78, 0x72510001}, |
| 574 | {0xc78, 0x71520001}, {0xc78, 0x70530001}, |
| 575 | {0xc78, 0x6f540001}, {0xc78, 0x6e550001}, |
| 576 | {0xc78, 0x6d560001}, {0xc78, 0x6c570001}, |
| 577 | {0xc78, 0x6b580001}, {0xc78, 0x6a590001}, |
| 578 | {0xc78, 0x695a0001}, {0xc78, 0x685b0001}, |
| 579 | {0xc78, 0x675c0001}, {0xc78, 0x665d0001}, |
| 580 | {0xc78, 0x655e0001}, {0xc78, 0x645f0001}, |
| 581 | {0xc78, 0x63600001}, {0xc78, 0x62610001}, |
| 582 | {0xc78, 0x61620001}, {0xc78, 0x60630001}, |
| 583 | {0xc78, 0x46640001}, {0xc78, 0x45650001}, |
| 584 | {0xc78, 0x44660001}, {0xc78, 0x43670001}, |
| 585 | {0xc78, 0x42680001}, {0xc78, 0x41690001}, |
| 586 | {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, |
| 587 | {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, |
| 588 | {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, |
| 589 | {0xc78, 0x21700001}, {0xc78, 0x20710001}, |
| 590 | {0xc78, 0x06720001}, {0xc78, 0x05730001}, |
| 591 | {0xc78, 0x04740001}, {0xc78, 0x03750001}, |
| 592 | {0xc78, 0x02760001}, {0xc78, 0x01770001}, |
| 593 | {0xc78, 0x00780001}, {0xc78, 0x00790001}, |
| 594 | {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, |
| 595 | {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, |
| 596 | {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, |
| 597 | {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, |
| 598 | {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, |
| 599 | {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, |
| 600 | {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, |
| 601 | {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, |
| 602 | {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, |
| 603 | {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, |
| 604 | {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, |
| 605 | {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, |
| 606 | {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, |
| 607 | {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, |
| 608 | {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, |
| 609 | {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, |
| 610 | {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, |
| 611 | {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, |
| 612 | {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, |
| 613 | {0xffff, 0xffffffff} |
| 614 | }; |
| 615 | |
| 616 | static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = { |
| 617 | {0x00, 0x00030159}, {0x01, 0x00031284}, |
| 618 | {0x02, 0x00098000}, {0x03, 0x00039c63}, |
| 619 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, |
| 620 | {0x0a, 0x0001a3f1}, {0x0b, 0x00014787}, |
| 621 | {0x0c, 0x000896fe}, {0x0d, 0x0000e02c}, |
| 622 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, |
| 623 | {0x19, 0x00000000}, {0x1a, 0x00030355}, |
| 624 | {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, |
| 625 | {0x1d, 0x000a1250}, {0x1e, 0x0000024f}, |
| 626 | {0x1f, 0x00000000}, {0x20, 0x0000b614}, |
| 627 | {0x21, 0x0006c000}, {0x22, 0x00000000}, |
| 628 | {0x23, 0x00001558}, {0x24, 0x00000060}, |
| 629 | {0x25, 0x00000483}, {0x26, 0x0004f000}, |
| 630 | {0x27, 0x000ec7d9}, {0x28, 0x00057730}, |
| 631 | {0x29, 0x00004783}, {0x2a, 0x00000001}, |
| 632 | {0x2b, 0x00021334}, {0x2a, 0x00000000}, |
| 633 | {0x2b, 0x00000054}, {0x2a, 0x00000001}, |
| 634 | {0x2b, 0x00000808}, {0x2b, 0x00053333}, |
| 635 | {0x2c, 0x0000000c}, {0x2a, 0x00000002}, |
| 636 | {0x2b, 0x00000808}, {0x2b, 0x0005b333}, |
| 637 | {0x2c, 0x0000000d}, {0x2a, 0x00000003}, |
| 638 | {0x2b, 0x00000808}, {0x2b, 0x00063333}, |
| 639 | {0x2c, 0x0000000d}, {0x2a, 0x00000004}, |
| 640 | {0x2b, 0x00000808}, {0x2b, 0x0006b333}, |
| 641 | {0x2c, 0x0000000d}, {0x2a, 0x00000005}, |
| 642 | {0x2b, 0x00000808}, {0x2b, 0x00073333}, |
| 643 | {0x2c, 0x0000000d}, {0x2a, 0x00000006}, |
| 644 | {0x2b, 0x00000709}, {0x2b, 0x0005b333}, |
| 645 | {0x2c, 0x0000000d}, {0x2a, 0x00000007}, |
| 646 | {0x2b, 0x00000709}, {0x2b, 0x00063333}, |
| 647 | {0x2c, 0x0000000d}, {0x2a, 0x00000008}, |
| 648 | {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, |
| 649 | {0x2c, 0x0000000d}, {0x2a, 0x00000009}, |
| 650 | {0x2b, 0x0000060a}, {0x2b, 0x00053333}, |
| 651 | {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, |
| 652 | {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, |
| 653 | {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, |
| 654 | {0x2b, 0x0000060a}, {0x2b, 0x00063333}, |
| 655 | {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, |
| 656 | {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, |
| 657 | {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, |
| 658 | {0x2b, 0x0000060a}, {0x2b, 0x00073333}, |
| 659 | {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, |
| 660 | {0x2b, 0x0000050b}, {0x2b, 0x00066666}, |
| 661 | {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, |
| 662 | {0x10, 0x0004000f}, {0x11, 0x000e31fc}, |
| 663 | {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, |
| 664 | {0x10, 0x0002000f}, {0x11, 0x000203f9}, |
| 665 | {0x10, 0x0003000f}, {0x11, 0x000ff500}, |
| 666 | {0x10, 0x00000000}, {0x11, 0x00000000}, |
| 667 | {0x10, 0x0008000f}, {0x11, 0x0003f100}, |
| 668 | {0x10, 0x0009000f}, {0x11, 0x00023100}, |
| 669 | {0x12, 0x00032000}, {0x12, 0x00071000}, |
| 670 | {0x12, 0x000b0000}, {0x12, 0x000fc000}, |
| 671 | {0x13, 0x000287b3}, {0x13, 0x000244b7}, |
| 672 | {0x13, 0x000204ab}, {0x13, 0x0001c49f}, |
| 673 | {0x13, 0x00018493}, {0x13, 0x0001429b}, |
| 674 | {0x13, 0x00010299}, {0x13, 0x0000c29c}, |
| 675 | {0x13, 0x000081a0}, {0x13, 0x000040ac}, |
| 676 | {0x13, 0x00000020}, {0x14, 0x0001944c}, |
| 677 | {0x14, 0x00059444}, {0x14, 0x0009944c}, |
| 678 | {0x14, 0x000d9444}, {0x15, 0x0000f474}, |
| 679 | {0x15, 0x0004f477}, {0x15, 0x0008f455}, |
| 680 | {0x15, 0x000cf455}, {0x16, 0x00000339}, |
| 681 | {0x16, 0x00040339}, {0x16, 0x00080339}, |
| 682 | {0x16, 0x000c0366}, {0x00, 0x00010159}, |
| 683 | {0x18, 0x0000f401}, {0xfe, 0x00000000}, |
| 684 | {0xfe, 0x00000000}, {0x1f, 0x00000003}, |
| 685 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, |
| 686 | {0x1e, 0x00000247}, {0x1f, 0x00000000}, |
| 687 | {0x00, 0x00030159}, |
| 688 | {0xff, 0xffffffff} |
| 689 | }; |
| 690 | |
| 691 | static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = { |
| 692 | {0x00, 0x00030159}, {0x01, 0x00031284}, |
| 693 | {0x02, 0x00098000}, {0x03, 0x00018c63}, |
| 694 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, |
| 695 | {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, |
| 696 | {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, |
| 697 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, |
| 698 | {0x19, 0x00000000}, {0x1a, 0x00010255}, |
| 699 | {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, |
| 700 | {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, |
| 701 | {0x1f, 0x00080001}, {0x20, 0x0000b614}, |
| 702 | {0x21, 0x0006c000}, {0x22, 0x00000000}, |
| 703 | {0x23, 0x00001558}, {0x24, 0x00000060}, |
| 704 | {0x25, 0x00000483}, {0x26, 0x0004f000}, |
| 705 | {0x27, 0x000ec7d9}, {0x28, 0x000577c0}, |
| 706 | {0x29, 0x00004783}, {0x2a, 0x00000001}, |
| 707 | {0x2b, 0x00021334}, {0x2a, 0x00000000}, |
| 708 | {0x2b, 0x00000054}, {0x2a, 0x00000001}, |
| 709 | {0x2b, 0x00000808}, {0x2b, 0x00053333}, |
| 710 | {0x2c, 0x0000000c}, {0x2a, 0x00000002}, |
| 711 | {0x2b, 0x00000808}, {0x2b, 0x0005b333}, |
| 712 | {0x2c, 0x0000000d}, {0x2a, 0x00000003}, |
| 713 | {0x2b, 0x00000808}, {0x2b, 0x00063333}, |
| 714 | {0x2c, 0x0000000d}, {0x2a, 0x00000004}, |
| 715 | {0x2b, 0x00000808}, {0x2b, 0x0006b333}, |
| 716 | {0x2c, 0x0000000d}, {0x2a, 0x00000005}, |
| 717 | {0x2b, 0x00000808}, {0x2b, 0x00073333}, |
| 718 | {0x2c, 0x0000000d}, {0x2a, 0x00000006}, |
| 719 | {0x2b, 0x00000709}, {0x2b, 0x0005b333}, |
| 720 | {0x2c, 0x0000000d}, {0x2a, 0x00000007}, |
| 721 | {0x2b, 0x00000709}, {0x2b, 0x00063333}, |
| 722 | {0x2c, 0x0000000d}, {0x2a, 0x00000008}, |
| 723 | {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, |
| 724 | {0x2c, 0x0000000d}, {0x2a, 0x00000009}, |
| 725 | {0x2b, 0x0000060a}, {0x2b, 0x00053333}, |
| 726 | {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, |
| 727 | {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, |
| 728 | {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, |
| 729 | {0x2b, 0x0000060a}, {0x2b, 0x00063333}, |
| 730 | {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, |
| 731 | {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, |
| 732 | {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, |
| 733 | {0x2b, 0x0000060a}, {0x2b, 0x00073333}, |
| 734 | {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, |
| 735 | {0x2b, 0x0000050b}, {0x2b, 0x00066666}, |
| 736 | {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, |
| 737 | {0x10, 0x0004000f}, {0x11, 0x000e31fc}, |
| 738 | {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, |
| 739 | {0x10, 0x0002000f}, {0x11, 0x000203f9}, |
| 740 | {0x10, 0x0003000f}, {0x11, 0x000ff500}, |
| 741 | {0x10, 0x00000000}, {0x11, 0x00000000}, |
| 742 | {0x10, 0x0008000f}, {0x11, 0x0003f100}, |
| 743 | {0x10, 0x0009000f}, {0x11, 0x00023100}, |
| 744 | {0x12, 0x00032000}, {0x12, 0x00071000}, |
| 745 | {0x12, 0x000b0000}, {0x12, 0x000fc000}, |
| 746 | {0x13, 0x000287b3}, {0x13, 0x000244b7}, |
| 747 | {0x13, 0x000204ab}, {0x13, 0x0001c49f}, |
| 748 | {0x13, 0x00018493}, {0x13, 0x0001429b}, |
| 749 | {0x13, 0x00010299}, {0x13, 0x0000c29c}, |
| 750 | {0x13, 0x000081a0}, {0x13, 0x000040ac}, |
| 751 | {0x13, 0x00000020}, {0x14, 0x0001944c}, |
| 752 | {0x14, 0x00059444}, {0x14, 0x0009944c}, |
| 753 | {0x14, 0x000d9444}, {0x15, 0x0000f424}, |
| 754 | {0x15, 0x0004f424}, {0x15, 0x0008f424}, |
| 755 | {0x15, 0x000cf424}, {0x16, 0x000e0330}, |
| 756 | {0x16, 0x000a0330}, {0x16, 0x00060330}, |
| 757 | {0x16, 0x00020330}, {0x00, 0x00010159}, |
| 758 | {0x18, 0x0000f401}, {0xfe, 0x00000000}, |
| 759 | {0xfe, 0x00000000}, {0x1f, 0x00080003}, |
| 760 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, |
| 761 | {0x1e, 0x00044457}, {0x1f, 0x00080000}, |
| 762 | {0x00, 0x00030159}, |
| 763 | {0xff, 0xffffffff} |
| 764 | }; |
| 765 | |
| 766 | static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = { |
| 767 | {0x00, 0x00030159}, {0x01, 0x00031284}, |
| 768 | {0x02, 0x00098000}, {0x03, 0x00018c63}, |
| 769 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, |
| 770 | {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, |
| 771 | {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, |
| 772 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, |
| 773 | {0x12, 0x00032000}, {0x12, 0x00071000}, |
| 774 | {0x12, 0x000b0000}, {0x12, 0x000fc000}, |
| 775 | {0x13, 0x000287af}, {0x13, 0x000244b7}, |
| 776 | {0x13, 0x000204ab}, {0x13, 0x0001c49f}, |
| 777 | {0x13, 0x00018493}, {0x13, 0x00014297}, |
| 778 | {0x13, 0x00010295}, {0x13, 0x0000c298}, |
| 779 | {0x13, 0x0000819c}, {0x13, 0x000040a8}, |
| 780 | {0x13, 0x0000001c}, {0x14, 0x0001944c}, |
| 781 | {0x14, 0x00059444}, {0x14, 0x0009944c}, |
| 782 | {0x14, 0x000d9444}, {0x15, 0x0000f424}, |
| 783 | {0x15, 0x0004f424}, {0x15, 0x0008f424}, |
| 784 | {0x15, 0x000cf424}, {0x16, 0x000e0330}, |
| 785 | {0x16, 0x000a0330}, {0x16, 0x00060330}, |
| 786 | {0x16, 0x00020330}, |
| 787 | {0xff, 0xffffffff} |
| 788 | }; |
| 789 | |
| 790 | static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = { |
| 791 | {0x00, 0x00030159}, {0x01, 0x00031284}, |
| 792 | {0x02, 0x00098000}, {0x03, 0x00018c63}, |
| 793 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, |
| 794 | {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, |
| 795 | {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, |
| 796 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, |
| 797 | {0x19, 0x00000000}, {0x1a, 0x00010255}, |
| 798 | {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, |
| 799 | {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, |
| 800 | {0x1f, 0x00080001}, {0x20, 0x0000b614}, |
| 801 | {0x21, 0x0006c000}, {0x22, 0x00000000}, |
| 802 | {0x23, 0x00001558}, {0x24, 0x00000060}, |
| 803 | {0x25, 0x00000483}, {0x26, 0x0004f000}, |
| 804 | {0x27, 0x000ec7d9}, {0x28, 0x000577c0}, |
| 805 | {0x29, 0x00004783}, {0x2a, 0x00000001}, |
| 806 | {0x2b, 0x00021334}, {0x2a, 0x00000000}, |
| 807 | {0x2b, 0x00000054}, {0x2a, 0x00000001}, |
| 808 | {0x2b, 0x00000808}, {0x2b, 0x00053333}, |
| 809 | {0x2c, 0x0000000c}, {0x2a, 0x00000002}, |
| 810 | {0x2b, 0x00000808}, {0x2b, 0x0005b333}, |
| 811 | {0x2c, 0x0000000d}, {0x2a, 0x00000003}, |
| 812 | {0x2b, 0x00000808}, {0x2b, 0x00063333}, |
| 813 | {0x2c, 0x0000000d}, {0x2a, 0x00000004}, |
| 814 | {0x2b, 0x00000808}, {0x2b, 0x0006b333}, |
| 815 | {0x2c, 0x0000000d}, {0x2a, 0x00000005}, |
| 816 | {0x2b, 0x00000808}, {0x2b, 0x00073333}, |
| 817 | {0x2c, 0x0000000d}, {0x2a, 0x00000006}, |
| 818 | {0x2b, 0x00000709}, {0x2b, 0x0005b333}, |
| 819 | {0x2c, 0x0000000d}, {0x2a, 0x00000007}, |
| 820 | {0x2b, 0x00000709}, {0x2b, 0x00063333}, |
| 821 | {0x2c, 0x0000000d}, {0x2a, 0x00000008}, |
| 822 | {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, |
| 823 | {0x2c, 0x0000000d}, {0x2a, 0x00000009}, |
| 824 | {0x2b, 0x0000060a}, {0x2b, 0x00053333}, |
| 825 | {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, |
| 826 | {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, |
| 827 | {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, |
| 828 | {0x2b, 0x0000060a}, {0x2b, 0x00063333}, |
| 829 | {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, |
| 830 | {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, |
| 831 | {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, |
| 832 | {0x2b, 0x0000060a}, {0x2b, 0x00073333}, |
| 833 | {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, |
| 834 | {0x2b, 0x0000050b}, {0x2b, 0x00066666}, |
| 835 | {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, |
| 836 | {0x10, 0x0004000f}, {0x11, 0x000e31fc}, |
| 837 | {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, |
| 838 | {0x10, 0x0002000f}, {0x11, 0x000203f9}, |
| 839 | {0x10, 0x0003000f}, {0x11, 0x000ff500}, |
| 840 | {0x10, 0x00000000}, {0x11, 0x00000000}, |
| 841 | {0x10, 0x0008000f}, {0x11, 0x0003f100}, |
| 842 | {0x10, 0x0009000f}, {0x11, 0x00023100}, |
| 843 | {0x12, 0x00032000}, {0x12, 0x00071000}, |
| 844 | {0x12, 0x000b0000}, {0x12, 0x000fc000}, |
| 845 | {0x13, 0x000287b3}, {0x13, 0x000244b7}, |
| 846 | {0x13, 0x000204ab}, {0x13, 0x0001c49f}, |
| 847 | {0x13, 0x00018493}, {0x13, 0x0001429b}, |
| 848 | {0x13, 0x00010299}, {0x13, 0x0000c29c}, |
| 849 | {0x13, 0x000081a0}, {0x13, 0x000040ac}, |
| 850 | {0x13, 0x00000020}, {0x14, 0x0001944c}, |
| 851 | {0x14, 0x00059444}, {0x14, 0x0009944c}, |
| 852 | {0x14, 0x000d9444}, {0x15, 0x0000f405}, |
| 853 | {0x15, 0x0004f405}, {0x15, 0x0008f405}, |
| 854 | {0x15, 0x000cf405}, {0x16, 0x000e0330}, |
| 855 | {0x16, 0x000a0330}, {0x16, 0x00060330}, |
| 856 | {0x16, 0x00020330}, {0x00, 0x00010159}, |
| 857 | {0x18, 0x0000f401}, {0xfe, 0x00000000}, |
| 858 | {0xfe, 0x00000000}, {0x1f, 0x00080003}, |
| 859 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, |
| 860 | {0x1e, 0x00044457}, {0x1f, 0x00080000}, |
| 861 | {0x00, 0x00030159}, |
| 862 | {0xff, 0xffffffff} |
| 863 | }; |
| 864 | |
| 865 | static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = { |
| 866 | {0x00, 0x00030159}, {0x01, 0x00031284}, |
| 867 | {0x02, 0x00098000}, {0x03, 0x00018c63}, |
| 868 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, |
| 869 | {0x0a, 0x0001adb0}, {0x0b, 0x00054867}, |
| 870 | {0x0c, 0x0008992e}, {0x0d, 0x0000e529}, |
| 871 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, |
| 872 | {0x19, 0x00000000}, {0x1a, 0x00000255}, |
| 873 | {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, |
| 874 | {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, |
| 875 | {0x1f, 0x00080001}, {0x20, 0x0000b614}, |
| 876 | {0x21, 0x0006c000}, {0x22, 0x0000083c}, |
| 877 | {0x23, 0x00001558}, {0x24, 0x00000060}, |
| 878 | {0x25, 0x00000483}, {0x26, 0x0004f000}, |
| 879 | {0x27, 0x000ec7d9}, {0x28, 0x000977c0}, |
| 880 | {0x29, 0x00004783}, {0x2a, 0x00000001}, |
| 881 | {0x2b, 0x00021334}, {0x2a, 0x00000000}, |
| 882 | {0x2b, 0x00000054}, {0x2a, 0x00000001}, |
| 883 | {0x2b, 0x00000808}, {0x2b, 0x00053333}, |
| 884 | {0x2c, 0x0000000c}, {0x2a, 0x00000002}, |
| 885 | {0x2b, 0x00000808}, {0x2b, 0x0005b333}, |
| 886 | {0x2c, 0x0000000d}, {0x2a, 0x00000003}, |
| 887 | {0x2b, 0x00000808}, {0x2b, 0x00063333}, |
| 888 | {0x2c, 0x0000000d}, {0x2a, 0x00000004}, |
| 889 | {0x2b, 0x00000808}, {0x2b, 0x0006b333}, |
| 890 | {0x2c, 0x0000000d}, {0x2a, 0x00000005}, |
| 891 | {0x2b, 0x00000808}, {0x2b, 0x00073333}, |
| 892 | {0x2c, 0x0000000d}, {0x2a, 0x00000006}, |
| 893 | {0x2b, 0x00000709}, {0x2b, 0x0005b333}, |
| 894 | {0x2c, 0x0000000d}, {0x2a, 0x00000007}, |
| 895 | {0x2b, 0x00000709}, {0x2b, 0x00063333}, |
| 896 | {0x2c, 0x0000000d}, {0x2a, 0x00000008}, |
| 897 | {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, |
| 898 | {0x2c, 0x0000000d}, {0x2a, 0x00000009}, |
| 899 | {0x2b, 0x0000060a}, {0x2b, 0x00053333}, |
| 900 | {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, |
| 901 | {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, |
| 902 | {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, |
| 903 | {0x2b, 0x0000060a}, {0x2b, 0x00063333}, |
| 904 | {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, |
| 905 | {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, |
| 906 | {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, |
| 907 | {0x2b, 0x0000060a}, {0x2b, 0x00073333}, |
| 908 | {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, |
| 909 | {0x2b, 0x0000050b}, {0x2b, 0x00066666}, |
| 910 | {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, |
| 911 | {0x10, 0x0004000f}, {0x11, 0x000e31fc}, |
| 912 | {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, |
| 913 | {0x10, 0x0002000f}, {0x11, 0x000203f9}, |
| 914 | {0x10, 0x0003000f}, {0x11, 0x000ff500}, |
| 915 | {0x10, 0x00000000}, {0x11, 0x00000000}, |
| 916 | {0x10, 0x0008000f}, {0x11, 0x0003f100}, |
| 917 | {0x10, 0x0009000f}, {0x11, 0x00023100}, |
| 918 | {0x12, 0x000d8000}, {0x12, 0x00090000}, |
| 919 | {0x12, 0x00051000}, {0x12, 0x00012000}, |
| 920 | {0x13, 0x00028fb4}, {0x13, 0x00024fa8}, |
| 921 | {0x13, 0x000207a4}, {0x13, 0x0001c3b0}, |
| 922 | {0x13, 0x000183a4}, {0x13, 0x00014398}, |
| 923 | {0x13, 0x000101a4}, {0x13, 0x0000c198}, |
| 924 | {0x13, 0x000080a4}, {0x13, 0x00004098}, |
| 925 | {0x13, 0x00000000}, {0x14, 0x0001944c}, |
| 926 | {0x14, 0x00059444}, {0x14, 0x0009944c}, |
| 927 | {0x14, 0x000d9444}, {0x15, 0x0000f405}, |
| 928 | {0x15, 0x0004f405}, {0x15, 0x0008f405}, |
| 929 | {0x15, 0x000cf405}, {0x16, 0x000e0330}, |
| 930 | {0x16, 0x000a0330}, {0x16, 0x00060330}, |
| 931 | {0x16, 0x00020330}, {0x00, 0x00010159}, |
| 932 | {0x18, 0x0000f401}, {0xfe, 0x00000000}, |
| 933 | {0xfe, 0x00000000}, {0x1f, 0x00080003}, |
| 934 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, |
| 935 | {0x1e, 0x00044457}, {0x1f, 0x00080000}, |
| 936 | {0x00, 0x00030159}, |
| 937 | {0xff, 0xffffffff} |
| 938 | }; |
| 939 | |
| 940 | static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = { |
| 941 | { /* RF_A */ |
| 942 | .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1, |
| 943 | .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2, |
| 944 | .lssiparm = REG_FPGA0_XA_LSSI_PARM, |
| 945 | .hspiread = REG_HSPI_XA_READBACK, |
| 946 | .lssiread = REG_FPGA0_XA_LSSI_READBACK, |
| 947 | .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL, |
| 948 | }, |
| 949 | { /* RF_B */ |
| 950 | .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1, |
| 951 | .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2, |
| 952 | .lssiparm = REG_FPGA0_XB_LSSI_PARM, |
| 953 | .hspiread = REG_HSPI_XB_READBACK, |
| 954 | .lssiread = REG_FPGA0_XB_LSSI_READBACK, |
| 955 | .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL, |
| 956 | }, |
| 957 | }; |
| 958 | |
| 959 | static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = { |
| 960 | REG_OFDM0_XA_RX_IQ_IMBALANCE, |
| 961 | REG_OFDM0_XB_RX_IQ_IMBALANCE, |
| 962 | REG_OFDM0_ENERGY_CCA_THRES, |
| 963 | REG_OFDM0_AGCR_SSI_TABLE, |
| 964 | REG_OFDM0_XA_TX_IQ_IMBALANCE, |
| 965 | REG_OFDM0_XB_TX_IQ_IMBALANCE, |
| 966 | REG_OFDM0_XC_TX_AFE, |
| 967 | REG_OFDM0_XD_TX_AFE, |
| 968 | REG_OFDM0_RX_IQ_EXT_ANTA |
| 969 | }; |
| 970 | |
| 971 | static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr) |
| 972 | { |
| 973 | struct usb_device *udev = priv->udev; |
| 974 | int len; |
| 975 | u8 data; |
| 976 | |
| 977 | mutex_lock(&priv->usb_buf_mutex); |
| 978 | len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), |
| 979 | REALTEK_USB_CMD_REQ, REALTEK_USB_READ, |
| 980 | addr, 0, &priv->usb_buf.val8, sizeof(u8), |
| 981 | RTW_USB_CONTROL_MSG_TIMEOUT); |
| 982 | data = priv->usb_buf.val8; |
| 983 | mutex_unlock(&priv->usb_buf_mutex); |
| 984 | |
| 985 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) |
| 986 | dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n", |
| 987 | __func__, addr, data, len); |
| 988 | return data; |
| 989 | } |
| 990 | |
| 991 | static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr) |
| 992 | { |
| 993 | struct usb_device *udev = priv->udev; |
| 994 | int len; |
| 995 | u16 data; |
| 996 | |
| 997 | mutex_lock(&priv->usb_buf_mutex); |
| 998 | len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), |
| 999 | REALTEK_USB_CMD_REQ, REALTEK_USB_READ, |
| 1000 | addr, 0, &priv->usb_buf.val16, sizeof(u16), |
| 1001 | RTW_USB_CONTROL_MSG_TIMEOUT); |
| 1002 | data = le16_to_cpu(priv->usb_buf.val16); |
| 1003 | mutex_unlock(&priv->usb_buf_mutex); |
| 1004 | |
| 1005 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) |
| 1006 | dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n", |
| 1007 | __func__, addr, data, len); |
| 1008 | return data; |
| 1009 | } |
| 1010 | |
| 1011 | static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr) |
| 1012 | { |
| 1013 | struct usb_device *udev = priv->udev; |
| 1014 | int len; |
| 1015 | u32 data; |
| 1016 | |
| 1017 | mutex_lock(&priv->usb_buf_mutex); |
| 1018 | len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), |
| 1019 | REALTEK_USB_CMD_REQ, REALTEK_USB_READ, |
| 1020 | addr, 0, &priv->usb_buf.val32, sizeof(u32), |
| 1021 | RTW_USB_CONTROL_MSG_TIMEOUT); |
| 1022 | data = le32_to_cpu(priv->usb_buf.val32); |
| 1023 | mutex_unlock(&priv->usb_buf_mutex); |
| 1024 | |
| 1025 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) |
| 1026 | dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n", |
| 1027 | __func__, addr, data, len); |
| 1028 | return data; |
| 1029 | } |
| 1030 | |
| 1031 | static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val) |
| 1032 | { |
| 1033 | struct usb_device *udev = priv->udev; |
| 1034 | int ret; |
| 1035 | |
| 1036 | mutex_lock(&priv->usb_buf_mutex); |
| 1037 | priv->usb_buf.val8 = val; |
| 1038 | ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), |
| 1039 | REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, |
| 1040 | addr, 0, &priv->usb_buf.val8, sizeof(u8), |
| 1041 | RTW_USB_CONTROL_MSG_TIMEOUT); |
| 1042 | |
| 1043 | mutex_unlock(&priv->usb_buf_mutex); |
| 1044 | |
| 1045 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) |
| 1046 | dev_info(&udev->dev, "%s(%04x) = 0x%02x\n", |
| 1047 | __func__, addr, val); |
| 1048 | return ret; |
| 1049 | } |
| 1050 | |
| 1051 | static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val) |
| 1052 | { |
| 1053 | struct usb_device *udev = priv->udev; |
| 1054 | int ret; |
| 1055 | |
| 1056 | mutex_lock(&priv->usb_buf_mutex); |
| 1057 | priv->usb_buf.val16 = cpu_to_le16(val); |
| 1058 | ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), |
| 1059 | REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, |
| 1060 | addr, 0, &priv->usb_buf.val16, sizeof(u16), |
| 1061 | RTW_USB_CONTROL_MSG_TIMEOUT); |
| 1062 | mutex_unlock(&priv->usb_buf_mutex); |
| 1063 | |
| 1064 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) |
| 1065 | dev_info(&udev->dev, "%s(%04x) = 0x%04x\n", |
| 1066 | __func__, addr, val); |
| 1067 | return ret; |
| 1068 | } |
| 1069 | |
| 1070 | static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val) |
| 1071 | { |
| 1072 | struct usb_device *udev = priv->udev; |
| 1073 | int ret; |
| 1074 | |
| 1075 | mutex_lock(&priv->usb_buf_mutex); |
| 1076 | priv->usb_buf.val32 = cpu_to_le32(val); |
| 1077 | ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), |
| 1078 | REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, |
| 1079 | addr, 0, &priv->usb_buf.val32, sizeof(u32), |
| 1080 | RTW_USB_CONTROL_MSG_TIMEOUT); |
| 1081 | mutex_unlock(&priv->usb_buf_mutex); |
| 1082 | |
| 1083 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) |
| 1084 | dev_info(&udev->dev, "%s(%04x) = 0x%08x\n", |
| 1085 | __func__, addr, val); |
| 1086 | return ret; |
| 1087 | } |
| 1088 | |
| 1089 | static int |
| 1090 | rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len) |
| 1091 | { |
| 1092 | struct usb_device *udev = priv->udev; |
| 1093 | int blocksize = priv->fops->writeN_block_size; |
| 1094 | int ret, i, count, remainder; |
| 1095 | |
| 1096 | count = len / blocksize; |
| 1097 | remainder = len % blocksize; |
| 1098 | |
| 1099 | for (i = 0; i < count; i++) { |
| 1100 | ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), |
| 1101 | REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, |
| 1102 | addr, 0, buf, blocksize, |
| 1103 | RTW_USB_CONTROL_MSG_TIMEOUT); |
| 1104 | if (ret != blocksize) |
| 1105 | goto write_error; |
| 1106 | |
| 1107 | addr += blocksize; |
| 1108 | buf += blocksize; |
| 1109 | } |
| 1110 | |
| 1111 | if (remainder) { |
| 1112 | ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), |
| 1113 | REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, |
| 1114 | addr, 0, buf, remainder, |
| 1115 | RTW_USB_CONTROL_MSG_TIMEOUT); |
| 1116 | if (ret != remainder) |
| 1117 | goto write_error; |
| 1118 | } |
| 1119 | |
| 1120 | return len; |
| 1121 | |
| 1122 | write_error: |
| 1123 | dev_info(&udev->dev, |
| 1124 | "%s: Failed to write block at addr: %04x size: %04x\n", |
| 1125 | __func__, addr, blocksize); |
| 1126 | return -EAGAIN; |
| 1127 | } |
| 1128 | |
| 1129 | static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, |
| 1130 | enum rtl8xxxu_rfpath path, u8 reg) |
| 1131 | { |
| 1132 | u32 hssia, val32, retval; |
| 1133 | |
| 1134 | hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); |
| 1135 | if (path != RF_A) |
| 1136 | val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2); |
| 1137 | else |
| 1138 | val32 = hssia; |
| 1139 | |
| 1140 | val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK; |
| 1141 | val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT); |
| 1142 | val32 |= FPGA0_HSSI_PARM2_EDGE_READ; |
| 1143 | hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ; |
| 1144 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); |
| 1145 | |
| 1146 | udelay(10); |
| 1147 | |
| 1148 | rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32); |
| 1149 | udelay(100); |
| 1150 | |
| 1151 | hssia |= FPGA0_HSSI_PARM2_EDGE_READ; |
| 1152 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); |
| 1153 | udelay(10); |
| 1154 | |
| 1155 | val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1); |
| 1156 | if (val32 & FPGA0_HSSI_PARM1_PI) |
| 1157 | retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread); |
| 1158 | else |
| 1159 | retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread); |
| 1160 | |
| 1161 | retval &= 0xfffff; |
| 1162 | |
| 1163 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ) |
| 1164 | dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", |
| 1165 | __func__, reg, retval); |
| 1166 | return retval; |
| 1167 | } |
| 1168 | |
| 1169 | static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, |
| 1170 | enum rtl8xxxu_rfpath path, u8 reg, u32 data) |
| 1171 | { |
| 1172 | int ret, retval; |
| 1173 | u32 dataaddr; |
| 1174 | |
| 1175 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE) |
| 1176 | dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", |
| 1177 | __func__, reg, data); |
| 1178 | |
| 1179 | data &= FPGA0_LSSI_PARM_DATA_MASK; |
| 1180 | dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data; |
| 1181 | |
| 1182 | /* Use XB for path B */ |
| 1183 | ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr); |
| 1184 | if (ret != sizeof(dataaddr)) |
| 1185 | retval = -EIO; |
| 1186 | else |
| 1187 | retval = 0; |
| 1188 | |
| 1189 | udelay(1); |
| 1190 | |
| 1191 | return retval; |
| 1192 | } |
| 1193 | |
| 1194 | static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c) |
| 1195 | { |
| 1196 | struct device *dev = &priv->udev->dev; |
| 1197 | int mbox_nr, retry, retval = 0; |
| 1198 | int mbox_reg, mbox_ext_reg; |
| 1199 | u8 val8; |
| 1200 | |
| 1201 | mutex_lock(&priv->h2c_mutex); |
| 1202 | |
| 1203 | mbox_nr = priv->next_mbox; |
| 1204 | mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); |
| 1205 | mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2); |
| 1206 | |
| 1207 | /* |
| 1208 | * MBOX ready? |
| 1209 | */ |
| 1210 | retry = 100; |
| 1211 | do { |
| 1212 | val8 = rtl8xxxu_read8(priv, REG_HMTFR); |
| 1213 | if (!(val8 & BIT(mbox_nr))) |
| 1214 | break; |
| 1215 | } while (retry--); |
| 1216 | |
| 1217 | if (!retry) { |
| 1218 | dev_dbg(dev, "%s: Mailbox busy\n", __func__); |
| 1219 | retval = -EBUSY; |
| 1220 | goto error; |
| 1221 | } |
| 1222 | |
| 1223 | /* |
| 1224 | * Need to swap as it's being swapped again by rtl8xxxu_write16/32() |
| 1225 | */ |
| 1226 | if (h2c->cmd.cmd & H2C_EXT) { |
| 1227 | rtl8xxxu_write16(priv, mbox_ext_reg, |
| 1228 | le16_to_cpu(h2c->raw.ext)); |
| 1229 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) |
| 1230 | dev_info(dev, "H2C_EXT %04x\n", |
| 1231 | le16_to_cpu(h2c->raw.ext)); |
| 1232 | } |
| 1233 | rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); |
| 1234 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) |
| 1235 | dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); |
| 1236 | |
| 1237 | priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; |
| 1238 | |
| 1239 | error: |
| 1240 | mutex_unlock(&priv->h2c_mutex); |
| 1241 | return retval; |
| 1242 | } |
| 1243 | |
| 1244 | static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv) |
| 1245 | { |
| 1246 | u8 val8; |
| 1247 | u32 val32; |
| 1248 | |
| 1249 | val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); |
| 1250 | val8 |= BIT(0) | BIT(3); |
| 1251 | rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8); |
| 1252 | |
| 1253 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); |
| 1254 | val32 &= ~(BIT(4) | BIT(5)); |
| 1255 | val32 |= BIT(3); |
| 1256 | if (priv->rf_paths == 2) { |
| 1257 | val32 &= ~(BIT(20) | BIT(21)); |
| 1258 | val32 |= BIT(19); |
| 1259 | } |
| 1260 | rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); |
| 1261 | |
| 1262 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); |
| 1263 | val32 &= ~OFDM_RF_PATH_TX_MASK; |
| 1264 | if (priv->tx_paths == 2) |
| 1265 | val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; |
| 1266 | else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c) |
| 1267 | val32 |= OFDM_RF_PATH_TX_B; |
| 1268 | else |
| 1269 | val32 |= OFDM_RF_PATH_TX_A; |
| 1270 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); |
| 1271 | |
| 1272 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 1273 | val32 &= ~FPGA_RF_MODE_JAPAN; |
| 1274 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); |
| 1275 | |
| 1276 | if (priv->rf_paths == 2) |
| 1277 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0); |
| 1278 | else |
| 1279 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0); |
| 1280 | |
| 1281 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95); |
| 1282 | if (priv->rf_paths == 2) |
| 1283 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95); |
| 1284 | |
| 1285 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); |
| 1286 | } |
| 1287 | |
| 1288 | static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv) |
| 1289 | { |
| 1290 | u8 sps0; |
| 1291 | u32 val32; |
| 1292 | |
| 1293 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); |
| 1294 | |
| 1295 | sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); |
| 1296 | |
| 1297 | /* RF RX code for preamble power saving */ |
| 1298 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); |
| 1299 | val32 &= ~(BIT(3) | BIT(4) | BIT(5)); |
| 1300 | if (priv->rf_paths == 2) |
| 1301 | val32 &= ~(BIT(19) | BIT(20) | BIT(21)); |
| 1302 | rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); |
| 1303 | |
| 1304 | /* Disable TX for four paths */ |
| 1305 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); |
| 1306 | val32 &= ~OFDM_RF_PATH_TX_MASK; |
| 1307 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); |
| 1308 | |
| 1309 | /* Enable power saving */ |
| 1310 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 1311 | val32 |= FPGA_RF_MODE_JAPAN; |
| 1312 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); |
| 1313 | |
| 1314 | /* AFE control register to power down bits [30:22] */ |
| 1315 | if (priv->rf_paths == 2) |
| 1316 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0); |
| 1317 | else |
| 1318 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0); |
| 1319 | |
| 1320 | /* Power down RF module */ |
| 1321 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); |
| 1322 | if (priv->rf_paths == 2) |
| 1323 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0); |
| 1324 | |
| 1325 | sps0 &= ~(BIT(0) | BIT(3)); |
| 1326 | rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0); |
| 1327 | } |
| 1328 | |
| 1329 | |
| 1330 | static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv) |
| 1331 | { |
| 1332 | u8 val8; |
| 1333 | |
| 1334 | val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); |
| 1335 | val8 &= ~BIT(6); |
| 1336 | rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); |
| 1337 | |
| 1338 | rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64); |
| 1339 | val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); |
| 1340 | val8 &= ~BIT(0); |
| 1341 | rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); |
| 1342 | } |
| 1343 | |
| 1344 | |
| 1345 | /* |
| 1346 | * The rtl8723a has 3 channel groups for it's efuse settings. It only |
| 1347 | * supports the 2.4GHz band, so channels 1 - 14: |
| 1348 | * group 0: channels 1 - 3 |
| 1349 | * group 1: channels 4 - 9 |
| 1350 | * group 2: channels 10 - 14 |
| 1351 | * |
| 1352 | * Note: We index from 0 in the code |
| 1353 | */ |
| 1354 | static int rtl8723a_channel_to_group(int channel) |
| 1355 | { |
| 1356 | int group; |
| 1357 | |
| 1358 | if (channel < 4) |
| 1359 | group = 0; |
| 1360 | else if (channel < 10) |
| 1361 | group = 1; |
| 1362 | else |
| 1363 | group = 2; |
| 1364 | |
| 1365 | return group; |
| 1366 | } |
| 1367 | |
| 1368 | static void rtl8723au_config_channel(struct ieee80211_hw *hw) |
| 1369 | { |
| 1370 | struct rtl8xxxu_priv *priv = hw->priv; |
| 1371 | u32 val32, rsr; |
| 1372 | u8 val8, opmode; |
| 1373 | bool ht = true; |
| 1374 | int sec_ch_above, channel; |
| 1375 | int i; |
| 1376 | |
| 1377 | opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); |
| 1378 | rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); |
| 1379 | channel = hw->conf.chandef.chan->hw_value; |
| 1380 | |
| 1381 | switch (hw->conf.chandef.width) { |
| 1382 | case NL80211_CHAN_WIDTH_20_NOHT: |
| 1383 | ht = false; |
| 1384 | case NL80211_CHAN_WIDTH_20: |
| 1385 | opmode |= BW_OPMODE_20MHZ; |
| 1386 | rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); |
| 1387 | |
| 1388 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 1389 | val32 &= ~FPGA_RF_MODE; |
| 1390 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); |
| 1391 | |
| 1392 | val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); |
| 1393 | val32 &= ~FPGA_RF_MODE; |
| 1394 | rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); |
| 1395 | |
| 1396 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); |
| 1397 | val32 |= FPGA0_ANALOG2_20MHZ; |
| 1398 | rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); |
| 1399 | break; |
| 1400 | case NL80211_CHAN_WIDTH_40: |
| 1401 | if (hw->conf.chandef.center_freq1 > |
| 1402 | hw->conf.chandef.chan->center_freq) { |
| 1403 | sec_ch_above = 1; |
| 1404 | channel += 2; |
| 1405 | } else { |
| 1406 | sec_ch_above = 0; |
| 1407 | channel -= 2; |
| 1408 | } |
| 1409 | |
| 1410 | opmode &= ~BW_OPMODE_20MHZ; |
| 1411 | rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); |
| 1412 | rsr &= ~RSR_RSC_BANDWIDTH_40M; |
| 1413 | if (sec_ch_above) |
| 1414 | rsr |= RSR_RSC_UPPER_SUB_CHANNEL; |
| 1415 | else |
| 1416 | rsr |= RSR_RSC_LOWER_SUB_CHANNEL; |
| 1417 | rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); |
| 1418 | |
| 1419 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 1420 | val32 |= FPGA_RF_MODE; |
| 1421 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); |
| 1422 | |
| 1423 | val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); |
| 1424 | val32 |= FPGA_RF_MODE; |
| 1425 | rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); |
| 1426 | |
| 1427 | /* |
| 1428 | * Set Control channel to upper or lower. These settings |
| 1429 | * are required only for 40MHz |
| 1430 | */ |
| 1431 | val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); |
| 1432 | val32 &= ~CCK0_SIDEBAND; |
| 1433 | if (!sec_ch_above) |
| 1434 | val32 |= CCK0_SIDEBAND; |
| 1435 | rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); |
| 1436 | |
| 1437 | val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); |
| 1438 | val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ |
| 1439 | if (sec_ch_above) |
| 1440 | val32 |= OFDM_LSTF_PRIME_CH_LOW; |
| 1441 | else |
| 1442 | val32 |= OFDM_LSTF_PRIME_CH_HIGH; |
| 1443 | rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); |
| 1444 | |
| 1445 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); |
| 1446 | val32 &= ~FPGA0_ANALOG2_20MHZ; |
| 1447 | rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); |
| 1448 | |
| 1449 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); |
| 1450 | val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); |
| 1451 | if (sec_ch_above) |
| 1452 | val32 |= FPGA0_PS_UPPER_CHANNEL; |
| 1453 | else |
| 1454 | val32 |= FPGA0_PS_LOWER_CHANNEL; |
| 1455 | rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); |
| 1456 | break; |
| 1457 | |
| 1458 | default: |
| 1459 | break; |
| 1460 | } |
| 1461 | |
| 1462 | for (i = RF_A; i < priv->rf_paths; i++) { |
| 1463 | val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); |
| 1464 | val32 &= ~MODE_AG_CHANNEL_MASK; |
| 1465 | val32 |= channel; |
| 1466 | rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); |
| 1467 | } |
| 1468 | |
| 1469 | if (ht) |
| 1470 | val8 = 0x0e; |
| 1471 | else |
| 1472 | val8 = 0x0a; |
| 1473 | |
| 1474 | rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); |
| 1475 | rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); |
| 1476 | |
| 1477 | rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); |
| 1478 | rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); |
| 1479 | |
| 1480 | for (i = RF_A; i < priv->rf_paths; i++) { |
| 1481 | val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); |
| 1482 | if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) |
| 1483 | val32 &= ~MODE_AG_CHANNEL_20MHZ; |
| 1484 | else |
| 1485 | val32 |= MODE_AG_CHANNEL_20MHZ; |
| 1486 | rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); |
| 1487 | } |
| 1488 | } |
| 1489 | |
| 1490 | static void |
| 1491 | rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) |
| 1492 | { |
| 1493 | u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS]; |
| 1494 | u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS]; |
| 1495 | u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b; |
| 1496 | u8 val8; |
| 1497 | int group, i; |
| 1498 | |
| 1499 | group = rtl8723a_channel_to_group(channel); |
| 1500 | |
| 1501 | cck[0] = priv->cck_tx_power_index_A[group]; |
| 1502 | cck[1] = priv->cck_tx_power_index_B[group]; |
| 1503 | |
| 1504 | ofdm[0] = priv->ht40_1s_tx_power_index_A[group]; |
| 1505 | ofdm[1] = priv->ht40_1s_tx_power_index_B[group]; |
| 1506 | |
| 1507 | ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a; |
| 1508 | ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b; |
| 1509 | |
| 1510 | mcsbase[0] = ofdm[0]; |
| 1511 | mcsbase[1] = ofdm[1]; |
| 1512 | if (!ht40) { |
| 1513 | mcsbase[0] += priv->ht20_tx_power_index_diff[group].a; |
| 1514 | mcsbase[1] += priv->ht20_tx_power_index_diff[group].b; |
| 1515 | } |
| 1516 | |
| 1517 | if (priv->tx_paths > 1) { |
| 1518 | if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a) |
| 1519 | ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a; |
| 1520 | if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b) |
| 1521 | ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b; |
| 1522 | } |
| 1523 | |
| 1524 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) |
| 1525 | dev_info(&priv->udev->dev, |
| 1526 | "%s: Setting TX power CCK A: %02x, " |
| 1527 | "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n", |
| 1528 | __func__, cck[0], cck[1], ofdm[0], ofdm[1]); |
| 1529 | |
| 1530 | for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) { |
| 1531 | if (cck[i] > RF6052_MAX_TX_PWR) |
| 1532 | cck[i] = RF6052_MAX_TX_PWR; |
| 1533 | if (ofdm[i] > RF6052_MAX_TX_PWR) |
| 1534 | ofdm[i] = RF6052_MAX_TX_PWR; |
| 1535 | } |
| 1536 | |
| 1537 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); |
| 1538 | val32 &= 0xffff00ff; |
| 1539 | val32 |= (cck[0] << 8); |
| 1540 | rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); |
| 1541 | |
| 1542 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); |
| 1543 | val32 &= 0xff; |
| 1544 | val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24)); |
| 1545 | rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); |
| 1546 | |
| 1547 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); |
| 1548 | val32 &= 0xffffff00; |
| 1549 | val32 |= cck[1]; |
| 1550 | rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); |
| 1551 | |
| 1552 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); |
| 1553 | val32 &= 0xff; |
| 1554 | val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24)); |
| 1555 | rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); |
| 1556 | |
| 1557 | ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 | |
| 1558 | ofdmbase[0] << 16 | ofdmbase[0] << 24; |
| 1559 | ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 | |
| 1560 | ofdmbase[1] << 16 | ofdmbase[1] << 24; |
| 1561 | rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a); |
| 1562 | rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b); |
| 1563 | |
| 1564 | rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a); |
| 1565 | rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b); |
| 1566 | |
| 1567 | mcs_a = mcsbase[0] | mcsbase[0] << 8 | |
| 1568 | mcsbase[0] << 16 | mcsbase[0] << 24; |
| 1569 | mcs_b = mcsbase[1] | mcsbase[1] << 8 | |
| 1570 | mcsbase[1] << 16 | mcsbase[1] << 24; |
| 1571 | |
| 1572 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a); |
| 1573 | rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b); |
| 1574 | |
| 1575 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a); |
| 1576 | rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b); |
| 1577 | |
| 1578 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a); |
| 1579 | rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b); |
| 1580 | |
| 1581 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a); |
| 1582 | for (i = 0; i < 3; i++) { |
| 1583 | if (i != 2) |
| 1584 | val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0; |
| 1585 | else |
| 1586 | val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0; |
| 1587 | rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8); |
| 1588 | } |
| 1589 | rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b); |
| 1590 | for (i = 0; i < 3; i++) { |
| 1591 | if (i != 2) |
| 1592 | val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0; |
| 1593 | else |
| 1594 | val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0; |
| 1595 | rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8); |
| 1596 | } |
| 1597 | } |
| 1598 | |
| 1599 | static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv, |
| 1600 | enum nl80211_iftype linktype) |
| 1601 | { |
| 1602 | u16 val8; |
| 1603 | |
| 1604 | val8 = rtl8xxxu_read16(priv, REG_MSR); |
| 1605 | val8 &= ~MSR_LINKTYPE_MASK; |
| 1606 | |
| 1607 | switch (linktype) { |
| 1608 | case NL80211_IFTYPE_UNSPECIFIED: |
| 1609 | val8 |= MSR_LINKTYPE_NONE; |
| 1610 | break; |
| 1611 | case NL80211_IFTYPE_ADHOC: |
| 1612 | val8 |= MSR_LINKTYPE_ADHOC; |
| 1613 | break; |
| 1614 | case NL80211_IFTYPE_STATION: |
| 1615 | val8 |= MSR_LINKTYPE_STATION; |
| 1616 | break; |
| 1617 | case NL80211_IFTYPE_AP: |
| 1618 | val8 |= MSR_LINKTYPE_AP; |
| 1619 | break; |
| 1620 | default: |
| 1621 | goto out; |
| 1622 | } |
| 1623 | |
| 1624 | rtl8xxxu_write8(priv, REG_MSR, val8); |
| 1625 | out: |
| 1626 | return; |
| 1627 | } |
| 1628 | |
| 1629 | static void |
| 1630 | rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry) |
| 1631 | { |
| 1632 | u16 val16; |
| 1633 | |
| 1634 | val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) & |
| 1635 | RETRY_LIMIT_SHORT_MASK) | |
| 1636 | ((long_retry << RETRY_LIMIT_LONG_SHIFT) & |
| 1637 | RETRY_LIMIT_LONG_MASK); |
| 1638 | |
| 1639 | rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); |
| 1640 | } |
| 1641 | |
| 1642 | static void |
| 1643 | rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm) |
| 1644 | { |
| 1645 | u16 val16; |
| 1646 | |
| 1647 | val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) | |
| 1648 | ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK); |
| 1649 | |
| 1650 | rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16); |
| 1651 | } |
| 1652 | |
| 1653 | static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv) |
| 1654 | { |
| 1655 | struct device *dev = &priv->udev->dev; |
| 1656 | char *cut; |
| 1657 | |
| 1658 | switch (priv->chip_cut) { |
| 1659 | case 0: |
| 1660 | cut = "A"; |
| 1661 | break; |
| 1662 | case 1: |
| 1663 | cut = "B"; |
| 1664 | break; |
| 1665 | default: |
| 1666 | cut = "unknown"; |
| 1667 | } |
| 1668 | |
| 1669 | dev_info(dev, |
| 1670 | "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n", |
| 1671 | priv->chip_name, cut, priv->vendor_umc ? "UMC" : "TSMC", |
| 1672 | priv->tx_paths, priv->rx_paths, priv->ep_tx_count, |
| 1673 | priv->has_wifi, priv->has_bluetooth, priv->has_gps, |
| 1674 | priv->hi_pa); |
| 1675 | |
| 1676 | dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr); |
| 1677 | } |
| 1678 | |
| 1679 | static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv) |
| 1680 | { |
| 1681 | struct device *dev = &priv->udev->dev; |
| 1682 | u32 val32, bonding; |
| 1683 | u16 val16; |
| 1684 | |
| 1685 | val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); |
| 1686 | priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >> |
| 1687 | SYS_CFG_CHIP_VERSION_SHIFT; |
| 1688 | if (val32 & SYS_CFG_TRP_VAUX_EN) { |
| 1689 | dev_info(dev, "Unsupported test chip\n"); |
| 1690 | return -ENOTSUPP; |
| 1691 | } |
| 1692 | |
| 1693 | if (val32 & SYS_CFG_BT_FUNC) { |
| 1694 | sprintf(priv->chip_name, "8723AU"); |
| 1695 | priv->rf_paths = 1; |
| 1696 | priv->rx_paths = 1; |
| 1697 | priv->tx_paths = 1; |
| 1698 | priv->rtlchip = 0x8723a; |
| 1699 | |
| 1700 | val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); |
| 1701 | if (val32 & MULTI_WIFI_FUNC_EN) |
| 1702 | priv->has_wifi = 1; |
| 1703 | if (val32 & MULTI_BT_FUNC_EN) |
| 1704 | priv->has_bluetooth = 1; |
| 1705 | if (val32 & MULTI_GPS_FUNC_EN) |
| 1706 | priv->has_gps = 1; |
| 1707 | } else if (val32 & SYS_CFG_TYPE_ID) { |
| 1708 | bonding = rtl8xxxu_read32(priv, REG_HPON_FSM); |
| 1709 | bonding &= HPON_FSM_BONDING_MASK; |
| 1710 | if (bonding == HPON_FSM_BONDING_1T2R) { |
| 1711 | sprintf(priv->chip_name, "8191CU"); |
| 1712 | priv->rf_paths = 2; |
| 1713 | priv->rx_paths = 2; |
| 1714 | priv->tx_paths = 1; |
| 1715 | priv->rtlchip = 0x8191c; |
| 1716 | } else { |
| 1717 | sprintf(priv->chip_name, "8192CU"); |
| 1718 | priv->rf_paths = 2; |
| 1719 | priv->rx_paths = 2; |
| 1720 | priv->tx_paths = 2; |
| 1721 | priv->rtlchip = 0x8192c; |
| 1722 | } |
| 1723 | priv->has_wifi = 1; |
| 1724 | } else { |
| 1725 | sprintf(priv->chip_name, "8188CU"); |
| 1726 | priv->rf_paths = 1; |
| 1727 | priv->rx_paths = 1; |
| 1728 | priv->tx_paths = 1; |
| 1729 | priv->rtlchip = 0x8188c; |
| 1730 | priv->has_wifi = 1; |
| 1731 | } |
| 1732 | |
| 1733 | if (val32 & SYS_CFG_VENDOR_ID) |
| 1734 | priv->vendor_umc = 1; |
| 1735 | |
| 1736 | val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); |
| 1737 | priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28; |
| 1738 | |
| 1739 | val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX); |
| 1740 | if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) { |
| 1741 | priv->ep_tx_high_queue = 1; |
| 1742 | priv->ep_tx_count++; |
| 1743 | } |
| 1744 | |
| 1745 | if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) { |
| 1746 | priv->ep_tx_normal_queue = 1; |
| 1747 | priv->ep_tx_count++; |
| 1748 | } |
| 1749 | |
| 1750 | if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) { |
| 1751 | priv->ep_tx_low_queue = 1; |
| 1752 | priv->ep_tx_count++; |
| 1753 | } |
| 1754 | |
| 1755 | /* |
| 1756 | * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX |
| 1757 | */ |
| 1758 | if (!priv->ep_tx_count) { |
| 1759 | switch (priv->nr_out_eps) { |
| 1760 | case 3: |
| 1761 | priv->ep_tx_low_queue = 1; |
| 1762 | priv->ep_tx_count++; |
| 1763 | case 2: |
| 1764 | priv->ep_tx_normal_queue = 1; |
| 1765 | priv->ep_tx_count++; |
| 1766 | case 1: |
| 1767 | priv->ep_tx_high_queue = 1; |
| 1768 | priv->ep_tx_count++; |
| 1769 | break; |
| 1770 | default: |
| 1771 | dev_info(dev, "Unsupported USB TX end-points\n"); |
| 1772 | return -ENOTSUPP; |
| 1773 | } |
| 1774 | } |
| 1775 | |
| 1776 | return 0; |
| 1777 | } |
| 1778 | |
| 1779 | static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv) |
| 1780 | { |
| 1781 | if (priv->efuse_wifi.efuse8723.rtl_id != cpu_to_le16(0x8129)) |
| 1782 | return -EINVAL; |
| 1783 | |
| 1784 | ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723.mac_addr); |
| 1785 | |
| 1786 | memcpy(priv->cck_tx_power_index_A, |
| 1787 | priv->efuse_wifi.efuse8723.cck_tx_power_index_A, |
| 1788 | sizeof(priv->cck_tx_power_index_A)); |
| 1789 | memcpy(priv->cck_tx_power_index_B, |
| 1790 | priv->efuse_wifi.efuse8723.cck_tx_power_index_B, |
| 1791 | sizeof(priv->cck_tx_power_index_B)); |
| 1792 | |
| 1793 | memcpy(priv->ht40_1s_tx_power_index_A, |
| 1794 | priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_A, |
| 1795 | sizeof(priv->ht40_1s_tx_power_index_A)); |
| 1796 | memcpy(priv->ht40_1s_tx_power_index_B, |
| 1797 | priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_B, |
| 1798 | sizeof(priv->ht40_1s_tx_power_index_B)); |
| 1799 | |
| 1800 | memcpy(priv->ht20_tx_power_index_diff, |
| 1801 | priv->efuse_wifi.efuse8723.ht20_tx_power_index_diff, |
| 1802 | sizeof(priv->ht20_tx_power_index_diff)); |
| 1803 | memcpy(priv->ofdm_tx_power_index_diff, |
| 1804 | priv->efuse_wifi.efuse8723.ofdm_tx_power_index_diff, |
| 1805 | sizeof(priv->ofdm_tx_power_index_diff)); |
| 1806 | |
| 1807 | memcpy(priv->ht40_max_power_offset, |
| 1808 | priv->efuse_wifi.efuse8723.ht40_max_power_offset, |
| 1809 | sizeof(priv->ht40_max_power_offset)); |
| 1810 | memcpy(priv->ht20_max_power_offset, |
| 1811 | priv->efuse_wifi.efuse8723.ht20_max_power_offset, |
| 1812 | sizeof(priv->ht20_max_power_offset)); |
| 1813 | |
| 1814 | dev_info(&priv->udev->dev, "Vendor: %.7s\n", |
| 1815 | priv->efuse_wifi.efuse8723.vendor_name); |
| 1816 | dev_info(&priv->udev->dev, "Product: %.41s\n", |
| 1817 | priv->efuse_wifi.efuse8723.device_name); |
| 1818 | return 0; |
| 1819 | } |
| 1820 | |
Kalle Valo | c096377 | 2015-10-25 18:24:38 +0200 | [diff] [blame] | 1821 | #ifdef CONFIG_RTL8XXXU_UNTESTED |
| 1822 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1823 | static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv) |
| 1824 | { |
| 1825 | int i; |
| 1826 | |
| 1827 | if (priv->efuse_wifi.efuse8192.rtl_id != cpu_to_le16(0x8129)) |
| 1828 | return -EINVAL; |
| 1829 | |
| 1830 | ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192.mac_addr); |
| 1831 | |
| 1832 | memcpy(priv->cck_tx_power_index_A, |
| 1833 | priv->efuse_wifi.efuse8192.cck_tx_power_index_A, |
| 1834 | sizeof(priv->cck_tx_power_index_A)); |
| 1835 | memcpy(priv->cck_tx_power_index_B, |
| 1836 | priv->efuse_wifi.efuse8192.cck_tx_power_index_B, |
| 1837 | sizeof(priv->cck_tx_power_index_B)); |
| 1838 | |
| 1839 | memcpy(priv->ht40_1s_tx_power_index_A, |
| 1840 | priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_A, |
| 1841 | sizeof(priv->ht40_1s_tx_power_index_A)); |
| 1842 | memcpy(priv->ht40_1s_tx_power_index_B, |
| 1843 | priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_B, |
| 1844 | sizeof(priv->ht40_1s_tx_power_index_B)); |
| 1845 | memcpy(priv->ht40_2s_tx_power_index_diff, |
| 1846 | priv->efuse_wifi.efuse8192.ht40_2s_tx_power_index_diff, |
| 1847 | sizeof(priv->ht40_2s_tx_power_index_diff)); |
| 1848 | |
| 1849 | memcpy(priv->ht20_tx_power_index_diff, |
| 1850 | priv->efuse_wifi.efuse8192.ht20_tx_power_index_diff, |
| 1851 | sizeof(priv->ht20_tx_power_index_diff)); |
| 1852 | memcpy(priv->ofdm_tx_power_index_diff, |
| 1853 | priv->efuse_wifi.efuse8192.ofdm_tx_power_index_diff, |
| 1854 | sizeof(priv->ofdm_tx_power_index_diff)); |
| 1855 | |
| 1856 | memcpy(priv->ht40_max_power_offset, |
| 1857 | priv->efuse_wifi.efuse8192.ht40_max_power_offset, |
| 1858 | sizeof(priv->ht40_max_power_offset)); |
| 1859 | memcpy(priv->ht20_max_power_offset, |
| 1860 | priv->efuse_wifi.efuse8192.ht20_max_power_offset, |
| 1861 | sizeof(priv->ht20_max_power_offset)); |
| 1862 | |
| 1863 | dev_info(&priv->udev->dev, "Vendor: %.7s\n", |
| 1864 | priv->efuse_wifi.efuse8192.vendor_name); |
| 1865 | dev_info(&priv->udev->dev, "Product: %.20s\n", |
| 1866 | priv->efuse_wifi.efuse8192.device_name); |
| 1867 | |
| 1868 | if (priv->efuse_wifi.efuse8192.rf_regulatory & 0x20) { |
| 1869 | sprintf(priv->chip_name, "8188RU"); |
| 1870 | priv->hi_pa = 1; |
| 1871 | } |
| 1872 | |
| 1873 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) { |
| 1874 | unsigned char *raw = priv->efuse_wifi.raw; |
| 1875 | |
| 1876 | dev_info(&priv->udev->dev, |
| 1877 | "%s: dumping efuse (0x%02zx bytes):\n", |
| 1878 | __func__, sizeof(struct rtl8192cu_efuse)); |
| 1879 | for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) { |
| 1880 | dev_info(&priv->udev->dev, "%02x: " |
| 1881 | "%02x %02x %02x %02x %02x %02x %02x %02x\n", i, |
| 1882 | raw[i], raw[i + 1], raw[i + 2], |
| 1883 | raw[i + 3], raw[i + 4], raw[i + 5], |
| 1884 | raw[i + 6], raw[i + 7]); |
| 1885 | } |
| 1886 | } |
| 1887 | return 0; |
| 1888 | } |
| 1889 | |
Kalle Valo | c096377 | 2015-10-25 18:24:38 +0200 | [diff] [blame] | 1890 | #endif |
| 1891 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1892 | static int |
| 1893 | rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) |
| 1894 | { |
| 1895 | int i; |
| 1896 | u8 val8; |
| 1897 | u32 val32; |
| 1898 | |
| 1899 | /* Write Address */ |
| 1900 | rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff); |
| 1901 | val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2); |
| 1902 | val8 &= 0xfc; |
| 1903 | val8 |= (offset >> 8) & 0x03; |
| 1904 | rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8); |
| 1905 | |
| 1906 | val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3); |
| 1907 | rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f); |
| 1908 | |
| 1909 | /* Poll for data read */ |
| 1910 | val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); |
| 1911 | for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) { |
| 1912 | val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); |
| 1913 | if (val32 & BIT(31)) |
| 1914 | break; |
| 1915 | } |
| 1916 | |
| 1917 | if (i == RTL8XXXU_MAX_REG_POLL) |
| 1918 | return -EIO; |
| 1919 | |
| 1920 | udelay(50); |
| 1921 | val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); |
| 1922 | |
| 1923 | *data = val32 & 0xff; |
| 1924 | return 0; |
| 1925 | } |
| 1926 | |
| 1927 | static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv) |
| 1928 | { |
| 1929 | struct device *dev = &priv->udev->dev; |
| 1930 | int i, ret = 0; |
| 1931 | u8 val8, word_mask, header, extheader; |
| 1932 | u16 val16, efuse_addr, offset; |
| 1933 | u32 val32; |
| 1934 | |
| 1935 | val16 = rtl8xxxu_read16(priv, REG_9346CR); |
| 1936 | if (val16 & EEPROM_ENABLE) |
| 1937 | priv->has_eeprom = 1; |
| 1938 | if (val16 & EEPROM_BOOT) |
| 1939 | priv->boot_eeprom = 1; |
| 1940 | |
| 1941 | val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST); |
| 1942 | val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT; |
| 1943 | rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32); |
| 1944 | |
| 1945 | dev_dbg(dev, "Booting from %s\n", |
| 1946 | priv->boot_eeprom ? "EEPROM" : "EFUSE"); |
| 1947 | |
| 1948 | rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE); |
| 1949 | |
| 1950 | /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */ |
| 1951 | val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); |
| 1952 | if (!(val16 & SYS_ISO_PWC_EV12V)) { |
| 1953 | val16 |= SYS_ISO_PWC_EV12V; |
| 1954 | rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); |
| 1955 | } |
| 1956 | /* Reset: 0x0000[28], default valid */ |
| 1957 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 1958 | if (!(val16 & SYS_FUNC_ELDR)) { |
| 1959 | val16 |= SYS_FUNC_ELDR; |
| 1960 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); |
| 1961 | } |
| 1962 | |
| 1963 | /* |
| 1964 | * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid |
| 1965 | */ |
| 1966 | val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); |
| 1967 | if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) { |
| 1968 | val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M); |
| 1969 | rtl8xxxu_write16(priv, REG_SYS_CLKR, val16); |
| 1970 | } |
| 1971 | |
| 1972 | /* Default value is 0xff */ |
| 1973 | memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN_8723A); |
| 1974 | |
| 1975 | efuse_addr = 0; |
| 1976 | while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) { |
| 1977 | ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header); |
| 1978 | if (ret || header == 0xff) |
| 1979 | goto exit; |
| 1980 | |
| 1981 | if ((header & 0x1f) == 0x0f) { /* extended header */ |
| 1982 | offset = (header & 0xe0) >> 5; |
| 1983 | |
| 1984 | ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, |
| 1985 | &extheader); |
| 1986 | if (ret) |
| 1987 | goto exit; |
| 1988 | /* All words disabled */ |
| 1989 | if ((extheader & 0x0f) == 0x0f) |
| 1990 | continue; |
| 1991 | |
| 1992 | offset |= ((extheader & 0xf0) >> 1); |
| 1993 | word_mask = extheader & 0x0f; |
| 1994 | } else { |
| 1995 | offset = (header >> 4) & 0x0f; |
| 1996 | word_mask = header & 0x0f; |
| 1997 | } |
| 1998 | |
| 1999 | if (offset < EFUSE_MAX_SECTION_8723A) { |
| 2000 | u16 map_addr; |
| 2001 | /* Get word enable value from PG header */ |
| 2002 | |
| 2003 | /* We have 8 bits to indicate validity */ |
| 2004 | map_addr = offset * 8; |
| 2005 | if (map_addr >= EFUSE_MAP_LEN_8723A) { |
| 2006 | dev_warn(dev, "%s: Illegal map_addr (%04x), " |
| 2007 | "efuse corrupt!\n", |
| 2008 | __func__, map_addr); |
| 2009 | ret = -EINVAL; |
| 2010 | goto exit; |
| 2011 | } |
| 2012 | for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { |
| 2013 | /* Check word enable condition in the section */ |
| 2014 | if (!(word_mask & BIT(i))) { |
| 2015 | ret = rtl8xxxu_read_efuse8(priv, |
| 2016 | efuse_addr++, |
| 2017 | &val8); |
| 2018 | if (ret) |
| 2019 | goto exit; |
| 2020 | priv->efuse_wifi.raw[map_addr++] = val8; |
| 2021 | |
| 2022 | ret = rtl8xxxu_read_efuse8(priv, |
| 2023 | efuse_addr++, |
| 2024 | &val8); |
| 2025 | if (ret) |
| 2026 | goto exit; |
| 2027 | priv->efuse_wifi.raw[map_addr++] = val8; |
| 2028 | } else |
| 2029 | map_addr += 2; |
| 2030 | } |
| 2031 | } else { |
| 2032 | dev_warn(dev, |
| 2033 | "%s: Illegal offset (%04x), efuse corrupt!\n", |
| 2034 | __func__, offset); |
| 2035 | ret = -EINVAL; |
| 2036 | goto exit; |
| 2037 | } |
| 2038 | } |
| 2039 | |
| 2040 | exit: |
| 2041 | rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE); |
| 2042 | |
| 2043 | return ret; |
| 2044 | } |
| 2045 | |
| 2046 | static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv) |
| 2047 | { |
| 2048 | struct device *dev = &priv->udev->dev; |
| 2049 | int ret = 0, i; |
| 2050 | u32 val32; |
| 2051 | |
| 2052 | /* Poll checksum report */ |
| 2053 | for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { |
| 2054 | val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); |
| 2055 | if (val32 & MCU_FW_DL_CSUM_REPORT) |
| 2056 | break; |
| 2057 | } |
| 2058 | |
| 2059 | if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { |
| 2060 | dev_warn(dev, "Firmware checksum poll timed out\n"); |
| 2061 | ret = -EAGAIN; |
| 2062 | goto exit; |
| 2063 | } |
| 2064 | |
| 2065 | val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); |
| 2066 | val32 |= MCU_FW_DL_READY; |
| 2067 | val32 &= ~MCU_WINT_INIT_READY; |
| 2068 | rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32); |
| 2069 | |
| 2070 | /* Wait for firmware to become ready */ |
| 2071 | for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { |
| 2072 | val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); |
| 2073 | if (val32 & MCU_WINT_INIT_READY) |
| 2074 | break; |
| 2075 | |
| 2076 | udelay(100); |
| 2077 | } |
| 2078 | |
| 2079 | if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { |
| 2080 | dev_warn(dev, "Firmware failed to start\n"); |
| 2081 | ret = -EAGAIN; |
| 2082 | goto exit; |
| 2083 | } |
| 2084 | |
| 2085 | exit: |
| 2086 | return ret; |
| 2087 | } |
| 2088 | |
| 2089 | static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv) |
| 2090 | { |
| 2091 | int pages, remainder, i, ret; |
| 2092 | u8 val8; |
| 2093 | u16 val16; |
| 2094 | u32 val32; |
| 2095 | u8 *fwptr; |
| 2096 | |
| 2097 | val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1); |
| 2098 | val8 |= 4; |
| 2099 | rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8); |
| 2100 | |
| 2101 | /* 8051 enable */ |
| 2102 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 2103 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16 | SYS_FUNC_CPU_ENABLE); |
| 2104 | |
| 2105 | /* MCU firmware download enable */ |
| 2106 | val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); |
| 2107 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8 | MCU_FW_DL_ENABLE); |
| 2108 | |
| 2109 | /* 8051 reset */ |
| 2110 | val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); |
| 2111 | rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32 & ~BIT(19)); |
| 2112 | |
| 2113 | /* Reset firmware download checksum */ |
| 2114 | val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); |
| 2115 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8 | MCU_FW_DL_CSUM_REPORT); |
| 2116 | |
| 2117 | pages = priv->fw_size / RTL_FW_PAGE_SIZE; |
| 2118 | remainder = priv->fw_size % RTL_FW_PAGE_SIZE; |
| 2119 | |
| 2120 | fwptr = priv->fw_data->data; |
| 2121 | |
| 2122 | for (i = 0; i < pages; i++) { |
| 2123 | val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8; |
| 2124 | rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8 | i); |
| 2125 | |
| 2126 | ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS, |
| 2127 | fwptr, RTL_FW_PAGE_SIZE); |
| 2128 | if (ret != RTL_FW_PAGE_SIZE) { |
| 2129 | ret = -EAGAIN; |
| 2130 | goto fw_abort; |
| 2131 | } |
| 2132 | |
| 2133 | fwptr += RTL_FW_PAGE_SIZE; |
| 2134 | } |
| 2135 | |
| 2136 | if (remainder) { |
| 2137 | val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8; |
| 2138 | rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8 | i); |
| 2139 | ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS, |
| 2140 | fwptr, remainder); |
| 2141 | if (ret != remainder) { |
| 2142 | ret = -EAGAIN; |
| 2143 | goto fw_abort; |
| 2144 | } |
| 2145 | } |
| 2146 | |
| 2147 | ret = 0; |
| 2148 | fw_abort: |
| 2149 | /* MCU firmware download disable */ |
| 2150 | val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL); |
| 2151 | rtl8xxxu_write16(priv, REG_MCU_FW_DL, |
| 2152 | val16 & (~MCU_FW_DL_ENABLE & 0xff)); |
| 2153 | |
| 2154 | return ret; |
| 2155 | } |
| 2156 | |
| 2157 | static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name) |
| 2158 | { |
| 2159 | struct device *dev = &priv->udev->dev; |
| 2160 | const struct firmware *fw; |
| 2161 | int ret = 0; |
| 2162 | u16 signature; |
| 2163 | |
| 2164 | dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name); |
| 2165 | if (request_firmware(&fw, fw_name, &priv->udev->dev)) { |
| 2166 | dev_warn(dev, "request_firmware(%s) failed\n", fw_name); |
| 2167 | ret = -EAGAIN; |
| 2168 | goto exit; |
| 2169 | } |
| 2170 | if (!fw) { |
| 2171 | dev_warn(dev, "Firmware data not available\n"); |
| 2172 | ret = -EINVAL; |
| 2173 | goto exit; |
| 2174 | } |
| 2175 | |
| 2176 | priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL); |
| 2177 | priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header); |
| 2178 | |
| 2179 | signature = le16_to_cpu(priv->fw_data->signature); |
| 2180 | switch (signature & 0xfff0) { |
| 2181 | case 0x92c0: |
| 2182 | case 0x88c0: |
| 2183 | case 0x2300: |
| 2184 | break; |
| 2185 | default: |
| 2186 | ret = -EINVAL; |
| 2187 | dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n", |
| 2188 | __func__, signature); |
| 2189 | } |
| 2190 | |
| 2191 | dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n", |
| 2192 | le16_to_cpu(priv->fw_data->major_version), |
| 2193 | priv->fw_data->minor_version, signature); |
| 2194 | |
| 2195 | exit: |
| 2196 | release_firmware(fw); |
| 2197 | return ret; |
| 2198 | } |
| 2199 | |
| 2200 | static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv) |
| 2201 | { |
| 2202 | char *fw_name; |
| 2203 | int ret; |
| 2204 | |
| 2205 | switch (priv->chip_cut) { |
| 2206 | case 0: |
| 2207 | fw_name = "rtlwifi/rtl8723aufw_A.bin"; |
| 2208 | break; |
| 2209 | case 1: |
| 2210 | if (priv->enable_bluetooth) |
| 2211 | fw_name = "rtlwifi/rtl8723aufw_B.bin"; |
| 2212 | else |
| 2213 | fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin"; |
| 2214 | |
| 2215 | break; |
| 2216 | default: |
| 2217 | return -EINVAL; |
| 2218 | } |
| 2219 | |
| 2220 | ret = rtl8xxxu_load_firmware(priv, fw_name); |
| 2221 | return ret; |
| 2222 | } |
| 2223 | |
Kalle Valo | c096377 | 2015-10-25 18:24:38 +0200 | [diff] [blame] | 2224 | #ifdef CONFIG_RTL8XXXU_UNTESTED |
| 2225 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2226 | static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv) |
| 2227 | { |
| 2228 | char *fw_name; |
| 2229 | int ret; |
| 2230 | |
| 2231 | if (!priv->vendor_umc) |
| 2232 | fw_name = "rtlwifi/rtl8192cufw_TMSC.bin"; |
| 2233 | else if (priv->chip_cut || priv->rtlchip == 0x8192c) |
| 2234 | fw_name = "rtlwifi/rtl8192cufw_B.bin"; |
| 2235 | else |
| 2236 | fw_name = "rtlwifi/rtl8192cufw_A.bin"; |
| 2237 | |
| 2238 | ret = rtl8xxxu_load_firmware(priv, fw_name); |
| 2239 | |
| 2240 | return ret; |
| 2241 | } |
| 2242 | |
Kalle Valo | c096377 | 2015-10-25 18:24:38 +0200 | [diff] [blame] | 2243 | #endif |
| 2244 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2245 | static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv) |
| 2246 | { |
| 2247 | u16 val16; |
| 2248 | int i = 100; |
| 2249 | |
| 2250 | /* Inform 8051 to perform reset */ |
| 2251 | rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20); |
| 2252 | |
| 2253 | for (i = 100; i > 0; i--) { |
| 2254 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 2255 | |
| 2256 | if (!(val16 & SYS_FUNC_CPU_ENABLE)) { |
| 2257 | dev_dbg(&priv->udev->dev, |
| 2258 | "%s: Firmware self reset success!\n", __func__); |
| 2259 | break; |
| 2260 | } |
| 2261 | udelay(50); |
| 2262 | } |
| 2263 | |
| 2264 | if (!i) { |
| 2265 | /* Force firmware reset */ |
| 2266 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 2267 | val16 &= ~SYS_FUNC_CPU_ENABLE; |
| 2268 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); |
| 2269 | } |
| 2270 | } |
| 2271 | |
| 2272 | static int |
| 2273 | rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array) |
| 2274 | { |
| 2275 | int i, ret; |
| 2276 | u16 reg; |
| 2277 | u8 val; |
| 2278 | |
| 2279 | for (i = 0; ; i++) { |
| 2280 | reg = array[i].reg; |
| 2281 | val = array[i].val; |
| 2282 | |
| 2283 | if (reg == 0xffff && val == 0xff) |
| 2284 | break; |
| 2285 | |
| 2286 | ret = rtl8xxxu_write8(priv, reg, val); |
| 2287 | if (ret != 1) { |
| 2288 | dev_warn(&priv->udev->dev, |
| 2289 | "Failed to initialize MAC\n"); |
| 2290 | return -EAGAIN; |
| 2291 | } |
| 2292 | } |
| 2293 | |
| 2294 | rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a); |
| 2295 | |
| 2296 | return 0; |
| 2297 | } |
| 2298 | |
| 2299 | static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, |
| 2300 | struct rtl8xxxu_reg32val *array) |
| 2301 | { |
| 2302 | int i, ret; |
| 2303 | u16 reg; |
| 2304 | u32 val; |
| 2305 | |
| 2306 | for (i = 0; ; i++) { |
| 2307 | reg = array[i].reg; |
| 2308 | val = array[i].val; |
| 2309 | |
| 2310 | if (reg == 0xffff && val == 0xffffffff) |
| 2311 | break; |
| 2312 | |
| 2313 | ret = rtl8xxxu_write32(priv, reg, val); |
| 2314 | if (ret != sizeof(val)) { |
| 2315 | dev_warn(&priv->udev->dev, |
| 2316 | "Failed to initialize PHY\n"); |
| 2317 | return -EAGAIN; |
| 2318 | } |
| 2319 | udelay(1); |
| 2320 | } |
| 2321 | |
| 2322 | return 0; |
| 2323 | } |
| 2324 | |
| 2325 | /* |
| 2326 | * Most of this is black magic retrieved from the old rtl8723au driver |
| 2327 | */ |
| 2328 | static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv) |
| 2329 | { |
| 2330 | u8 val8, ldoa15, ldov12d, lpldo, ldohci12; |
| 2331 | u32 val32; |
| 2332 | |
| 2333 | /* |
| 2334 | * Todo: The vendor driver maintains a table of PHY register |
| 2335 | * addresses, which is initialized here. Do we need this? |
| 2336 | */ |
| 2337 | |
| 2338 | val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); |
| 2339 | udelay(2); |
| 2340 | val8 |= AFE_PLL_320_ENABLE; |
| 2341 | rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); |
| 2342 | udelay(2); |
| 2343 | |
| 2344 | rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff); |
| 2345 | udelay(2); |
| 2346 | |
| 2347 | val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); |
| 2348 | val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; |
| 2349 | rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); |
| 2350 | |
| 2351 | /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */ |
| 2352 | val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); |
| 2353 | val32 &= ~AFE_XTAL_RF_GATE; |
| 2354 | if (priv->has_bluetooth) |
| 2355 | val32 &= ~AFE_XTAL_BT_GATE; |
| 2356 | rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); |
| 2357 | |
| 2358 | /* 6. 0x1f[7:0] = 0x07 */ |
| 2359 | val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; |
| 2360 | rtl8xxxu_write8(priv, REG_RF_CTRL, val8); |
| 2361 | |
| 2362 | if (priv->hi_pa) |
| 2363 | rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table); |
| 2364 | else if (priv->tx_paths == 2) |
| 2365 | rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table); |
| 2366 | else |
| 2367 | rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table); |
| 2368 | |
| 2369 | |
| 2370 | if (priv->rtlchip == 0x8188c && priv->hi_pa && |
| 2371 | priv->vendor_umc && priv->chip_cut == 1) |
| 2372 | rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50); |
| 2373 | |
| 2374 | if (priv->tx_paths == 1 && priv->rx_paths == 2) { |
| 2375 | /* |
| 2376 | * For 1T2R boards, patch the registers. |
| 2377 | * |
| 2378 | * It looks like 8191/2 1T2R boards use path B for TX |
| 2379 | */ |
| 2380 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO); |
| 2381 | val32 &= ~(BIT(0) | BIT(1)); |
| 2382 | val32 |= BIT(1); |
| 2383 | rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32); |
| 2384 | |
| 2385 | val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO); |
| 2386 | val32 &= ~0x300033; |
| 2387 | val32 |= 0x200022; |
| 2388 | rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32); |
| 2389 | |
| 2390 | val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); |
| 2391 | val32 &= 0xff000000; |
| 2392 | val32 |= 0x45000000; |
| 2393 | rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); |
| 2394 | |
| 2395 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); |
| 2396 | val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); |
| 2397 | val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | |
| 2398 | OFDM_RF_PATH_TX_B); |
| 2399 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); |
| 2400 | |
| 2401 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1); |
| 2402 | val32 &= ~(BIT(4) | BIT(5)); |
| 2403 | val32 |= BIT(4); |
| 2404 | rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32); |
| 2405 | |
| 2406 | val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON); |
| 2407 | val32 &= ~(BIT(27) | BIT(26)); |
| 2408 | val32 |= BIT(27); |
| 2409 | rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32); |
| 2410 | |
| 2411 | val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON); |
| 2412 | val32 &= ~(BIT(27) | BIT(26)); |
| 2413 | val32 |= BIT(27); |
| 2414 | rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32); |
| 2415 | |
| 2416 | val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON); |
| 2417 | val32 &= ~(BIT(27) | BIT(26)); |
| 2418 | val32 |= BIT(27); |
| 2419 | rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32); |
| 2420 | |
| 2421 | val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON); |
| 2422 | val32 &= ~(BIT(27) | BIT(26)); |
| 2423 | val32 |= BIT(27); |
| 2424 | rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32); |
| 2425 | |
| 2426 | val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX); |
| 2427 | val32 &= ~(BIT(27) | BIT(26)); |
| 2428 | val32 |= BIT(27); |
| 2429 | rtl8xxxu_write32(priv, REG_TX_TO_TX, val32); |
| 2430 | } |
| 2431 | |
| 2432 | if (priv->hi_pa) |
| 2433 | rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table); |
| 2434 | else |
| 2435 | rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table); |
| 2436 | |
| 2437 | if (priv->rtlchip == 0x8723a && |
| 2438 | priv->efuse_wifi.efuse8723.version >= 0x01) { |
| 2439 | val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL); |
| 2440 | |
| 2441 | val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f; |
| 2442 | val32 &= 0xff000fff; |
| 2443 | val32 |= ((val8 | (val8 << 6)) << 12); |
| 2444 | |
| 2445 | rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32); |
| 2446 | } |
| 2447 | |
| 2448 | ldoa15 = LDOA15_ENABLE | LDOA15_OBUF; |
| 2449 | ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT); |
| 2450 | ldohci12 = 0x57; |
| 2451 | lpldo = 1; |
| 2452 | val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15; |
| 2453 | |
| 2454 | rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32); |
| 2455 | |
| 2456 | return 0; |
| 2457 | } |
| 2458 | |
| 2459 | static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv, |
| 2460 | struct rtl8xxxu_rfregval *array, |
| 2461 | enum rtl8xxxu_rfpath path) |
| 2462 | { |
| 2463 | int i, ret; |
| 2464 | u8 reg; |
| 2465 | u32 val; |
| 2466 | |
| 2467 | for (i = 0; ; i++) { |
| 2468 | reg = array[i].reg; |
| 2469 | val = array[i].val; |
| 2470 | |
| 2471 | if (reg == 0xff && val == 0xffffffff) |
| 2472 | break; |
| 2473 | |
| 2474 | switch (reg) { |
| 2475 | case 0xfe: |
| 2476 | msleep(50); |
| 2477 | continue; |
| 2478 | case 0xfd: |
| 2479 | mdelay(5); |
| 2480 | continue; |
| 2481 | case 0xfc: |
| 2482 | mdelay(1); |
| 2483 | continue; |
| 2484 | case 0xfb: |
| 2485 | udelay(50); |
| 2486 | continue; |
| 2487 | case 0xfa: |
| 2488 | udelay(5); |
| 2489 | continue; |
| 2490 | case 0xf9: |
| 2491 | udelay(1); |
| 2492 | continue; |
| 2493 | } |
| 2494 | |
| 2495 | reg &= 0x3f; |
| 2496 | |
| 2497 | ret = rtl8xxxu_write_rfreg(priv, path, reg, val); |
| 2498 | if (ret) { |
| 2499 | dev_warn(&priv->udev->dev, |
| 2500 | "Failed to initialize RF\n"); |
| 2501 | return -EAGAIN; |
| 2502 | } |
| 2503 | udelay(1); |
| 2504 | } |
| 2505 | |
| 2506 | return 0; |
| 2507 | } |
| 2508 | |
| 2509 | static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, |
| 2510 | struct rtl8xxxu_rfregval *table, |
| 2511 | enum rtl8xxxu_rfpath path) |
| 2512 | { |
| 2513 | u32 val32; |
| 2514 | u16 val16, rfsi_rfenv; |
| 2515 | u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2; |
| 2516 | |
| 2517 | switch (path) { |
| 2518 | case RF_A: |
| 2519 | reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL; |
| 2520 | reg_int_oe = REG_FPGA0_XA_RF_INT_OE; |
| 2521 | reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2; |
| 2522 | break; |
| 2523 | case RF_B: |
| 2524 | reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL; |
| 2525 | reg_int_oe = REG_FPGA0_XB_RF_INT_OE; |
| 2526 | reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2; |
| 2527 | break; |
| 2528 | default: |
| 2529 | dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n", |
| 2530 | __func__, path + 'A'); |
| 2531 | return -EINVAL; |
| 2532 | } |
| 2533 | /* For path B, use XB */ |
| 2534 | rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl); |
| 2535 | rfsi_rfenv &= FPGA0_RF_RFENV; |
| 2536 | |
| 2537 | /* |
| 2538 | * These two we might be able to optimize into one |
| 2539 | */ |
| 2540 | val32 = rtl8xxxu_read32(priv, reg_int_oe); |
| 2541 | val32 |= BIT(20); /* 0x10 << 16 */ |
| 2542 | rtl8xxxu_write32(priv, reg_int_oe, val32); |
| 2543 | udelay(1); |
| 2544 | |
| 2545 | val32 = rtl8xxxu_read32(priv, reg_int_oe); |
| 2546 | val32 |= BIT(4); |
| 2547 | rtl8xxxu_write32(priv, reg_int_oe, val32); |
| 2548 | udelay(1); |
| 2549 | |
| 2550 | /* |
| 2551 | * These two we might be able to optimize into one |
| 2552 | */ |
| 2553 | val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); |
| 2554 | val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN; |
| 2555 | rtl8xxxu_write32(priv, reg_hssi_parm2, val32); |
| 2556 | udelay(1); |
| 2557 | |
| 2558 | val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); |
| 2559 | val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN; |
| 2560 | rtl8xxxu_write32(priv, reg_hssi_parm2, val32); |
| 2561 | udelay(1); |
| 2562 | |
| 2563 | rtl8xxxu_init_rf_regs(priv, table, path); |
| 2564 | |
| 2565 | /* For path B, use XB */ |
| 2566 | val16 = rtl8xxxu_read16(priv, reg_sw_ctrl); |
| 2567 | val16 &= ~FPGA0_RF_RFENV; |
| 2568 | val16 |= rfsi_rfenv; |
| 2569 | rtl8xxxu_write16(priv, reg_sw_ctrl, val16); |
| 2570 | |
| 2571 | return 0; |
| 2572 | } |
| 2573 | |
| 2574 | static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data) |
| 2575 | { |
| 2576 | int ret = -EBUSY; |
| 2577 | int count = 0; |
| 2578 | u32 value; |
| 2579 | |
| 2580 | value = LLT_OP_WRITE | address << 8 | data; |
| 2581 | |
| 2582 | rtl8xxxu_write32(priv, REG_LLT_INIT, value); |
| 2583 | |
| 2584 | do { |
| 2585 | value = rtl8xxxu_read32(priv, REG_LLT_INIT); |
| 2586 | if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) { |
| 2587 | ret = 0; |
| 2588 | break; |
| 2589 | } |
| 2590 | } while (count++ < 20); |
| 2591 | |
| 2592 | return ret; |
| 2593 | } |
| 2594 | |
| 2595 | static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page) |
| 2596 | { |
| 2597 | int ret; |
| 2598 | int i; |
| 2599 | |
| 2600 | for (i = 0; i < last_tx_page; i++) { |
| 2601 | ret = rtl8xxxu_llt_write(priv, i, i + 1); |
| 2602 | if (ret) |
| 2603 | goto exit; |
| 2604 | } |
| 2605 | |
| 2606 | ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff); |
| 2607 | if (ret) |
| 2608 | goto exit; |
| 2609 | |
| 2610 | /* Mark remaining pages as a ring buffer */ |
| 2611 | for (i = last_tx_page + 1; i < 0xff; i++) { |
| 2612 | ret = rtl8xxxu_llt_write(priv, i, (i + 1)); |
| 2613 | if (ret) |
| 2614 | goto exit; |
| 2615 | } |
| 2616 | |
| 2617 | /* Let last entry point to the start entry of ring buffer */ |
| 2618 | ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1); |
| 2619 | if (ret) |
| 2620 | goto exit; |
| 2621 | |
| 2622 | exit: |
| 2623 | return ret; |
| 2624 | } |
| 2625 | |
| 2626 | static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv) |
| 2627 | { |
| 2628 | u16 val16, hi, lo; |
| 2629 | u16 hiq, mgq, bkq, beq, viq, voq; |
| 2630 | int hip, mgp, bkp, bep, vip, vop; |
| 2631 | int ret = 0; |
| 2632 | |
| 2633 | switch (priv->ep_tx_count) { |
| 2634 | case 1: |
| 2635 | if (priv->ep_tx_high_queue) { |
| 2636 | hi = TRXDMA_QUEUE_HIGH; |
| 2637 | } else if (priv->ep_tx_low_queue) { |
| 2638 | hi = TRXDMA_QUEUE_LOW; |
| 2639 | } else if (priv->ep_tx_normal_queue) { |
| 2640 | hi = TRXDMA_QUEUE_NORMAL; |
| 2641 | } else { |
| 2642 | hi = 0; |
| 2643 | ret = -EINVAL; |
| 2644 | } |
| 2645 | |
| 2646 | hiq = hi; |
| 2647 | mgq = hi; |
| 2648 | bkq = hi; |
| 2649 | beq = hi; |
| 2650 | viq = hi; |
| 2651 | voq = hi; |
| 2652 | |
| 2653 | hip = 0; |
| 2654 | mgp = 0; |
| 2655 | bkp = 0; |
| 2656 | bep = 0; |
| 2657 | vip = 0; |
| 2658 | vop = 0; |
| 2659 | break; |
| 2660 | case 2: |
| 2661 | if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) { |
| 2662 | hi = TRXDMA_QUEUE_HIGH; |
| 2663 | lo = TRXDMA_QUEUE_LOW; |
| 2664 | } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) { |
| 2665 | hi = TRXDMA_QUEUE_NORMAL; |
| 2666 | lo = TRXDMA_QUEUE_LOW; |
| 2667 | } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) { |
| 2668 | hi = TRXDMA_QUEUE_HIGH; |
| 2669 | lo = TRXDMA_QUEUE_NORMAL; |
| 2670 | } else { |
| 2671 | ret = -EINVAL; |
| 2672 | hi = 0; |
| 2673 | lo = 0; |
| 2674 | } |
| 2675 | |
| 2676 | hiq = hi; |
| 2677 | mgq = hi; |
| 2678 | bkq = lo; |
| 2679 | beq = lo; |
| 2680 | viq = hi; |
| 2681 | voq = hi; |
| 2682 | |
| 2683 | hip = 0; |
| 2684 | mgp = 0; |
| 2685 | bkp = 1; |
| 2686 | bep = 1; |
| 2687 | vip = 0; |
| 2688 | vop = 0; |
| 2689 | break; |
| 2690 | case 3: |
| 2691 | beq = TRXDMA_QUEUE_LOW; |
| 2692 | bkq = TRXDMA_QUEUE_LOW; |
| 2693 | viq = TRXDMA_QUEUE_NORMAL; |
| 2694 | voq = TRXDMA_QUEUE_HIGH; |
| 2695 | mgq = TRXDMA_QUEUE_HIGH; |
| 2696 | hiq = TRXDMA_QUEUE_HIGH; |
| 2697 | |
| 2698 | hip = hiq ^ 3; |
| 2699 | mgp = mgq ^ 3; |
| 2700 | bkp = bkq ^ 3; |
| 2701 | bep = beq ^ 3; |
| 2702 | vip = viq ^ 3; |
| 2703 | vop = viq ^ 3; |
| 2704 | break; |
| 2705 | default: |
| 2706 | ret = -EINVAL; |
| 2707 | } |
| 2708 | |
| 2709 | /* |
| 2710 | * None of the vendor drivers are configuring the beacon |
| 2711 | * queue here .... why? |
| 2712 | */ |
| 2713 | if (!ret) { |
| 2714 | val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL); |
| 2715 | val16 &= 0x7; |
| 2716 | val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) | |
| 2717 | (viq << TRXDMA_CTRL_VIQ_SHIFT) | |
| 2718 | (beq << TRXDMA_CTRL_BEQ_SHIFT) | |
| 2719 | (bkq << TRXDMA_CTRL_BKQ_SHIFT) | |
| 2720 | (mgq << TRXDMA_CTRL_MGQ_SHIFT) | |
| 2721 | (hiq << TRXDMA_CTRL_HIQ_SHIFT); |
| 2722 | rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16); |
| 2723 | |
| 2724 | priv->pipe_out[TXDESC_QUEUE_VO] = |
| 2725 | usb_sndbulkpipe(priv->udev, priv->out_ep[vop]); |
| 2726 | priv->pipe_out[TXDESC_QUEUE_VI] = |
| 2727 | usb_sndbulkpipe(priv->udev, priv->out_ep[vip]); |
| 2728 | priv->pipe_out[TXDESC_QUEUE_BE] = |
| 2729 | usb_sndbulkpipe(priv->udev, priv->out_ep[bep]); |
| 2730 | priv->pipe_out[TXDESC_QUEUE_BK] = |
| 2731 | usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]); |
| 2732 | priv->pipe_out[TXDESC_QUEUE_BEACON] = |
| 2733 | usb_sndbulkpipe(priv->udev, priv->out_ep[0]); |
| 2734 | priv->pipe_out[TXDESC_QUEUE_MGNT] = |
| 2735 | usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]); |
| 2736 | priv->pipe_out[TXDESC_QUEUE_HIGH] = |
| 2737 | usb_sndbulkpipe(priv->udev, priv->out_ep[hip]); |
| 2738 | priv->pipe_out[TXDESC_QUEUE_CMD] = |
| 2739 | usb_sndbulkpipe(priv->udev, priv->out_ep[0]); |
| 2740 | } |
| 2741 | |
| 2742 | return ret; |
| 2743 | } |
| 2744 | |
| 2745 | static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, |
| 2746 | bool iqk_ok, int result[][8], |
| 2747 | int candidate, bool tx_only) |
| 2748 | { |
| 2749 | u32 oldval, x, tx0_a, reg; |
| 2750 | int y, tx0_c; |
| 2751 | u32 val32; |
| 2752 | |
| 2753 | if (!iqk_ok) |
| 2754 | return; |
| 2755 | |
| 2756 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); |
| 2757 | oldval = val32 >> 22; |
| 2758 | |
| 2759 | x = result[candidate][0]; |
| 2760 | if ((x & 0x00000200) != 0) |
| 2761 | x = x | 0xfffffc00; |
| 2762 | tx0_a = (x * oldval) >> 8; |
| 2763 | |
| 2764 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); |
| 2765 | val32 &= ~0x3ff; |
| 2766 | val32 |= tx0_a; |
| 2767 | rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); |
| 2768 | |
| 2769 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); |
| 2770 | val32 &= ~BIT(31); |
| 2771 | if ((x * oldval >> 7) & 0x1) |
| 2772 | val32 |= BIT(31); |
| 2773 | rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); |
| 2774 | |
| 2775 | y = result[candidate][1]; |
| 2776 | if ((y & 0x00000200) != 0) |
| 2777 | y = y | 0xfffffc00; |
| 2778 | tx0_c = (y * oldval) >> 8; |
| 2779 | |
| 2780 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE); |
| 2781 | val32 &= ~0xf0000000; |
| 2782 | val32 |= (((tx0_c & 0x3c0) >> 6) << 28); |
| 2783 | rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32); |
| 2784 | |
| 2785 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); |
| 2786 | val32 &= ~0x003f0000; |
| 2787 | val32 |= ((tx0_c & 0x3f) << 16); |
| 2788 | rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); |
| 2789 | |
| 2790 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); |
| 2791 | val32 &= ~BIT(29); |
| 2792 | if ((y * oldval >> 7) & 0x1) |
| 2793 | val32 |= BIT(29); |
| 2794 | rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); |
| 2795 | |
| 2796 | if (tx_only) { |
| 2797 | dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); |
| 2798 | return; |
| 2799 | } |
| 2800 | |
| 2801 | reg = result[candidate][2]; |
| 2802 | |
| 2803 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); |
| 2804 | val32 &= ~0x3ff; |
| 2805 | val32 |= (reg & 0x3ff); |
| 2806 | rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); |
| 2807 | |
| 2808 | reg = result[candidate][3] & 0x3F; |
| 2809 | |
| 2810 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); |
| 2811 | val32 &= ~0xfc00; |
| 2812 | val32 |= ((reg << 10) & 0xfc00); |
| 2813 | rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); |
| 2814 | |
| 2815 | reg = (result[candidate][3] >> 6) & 0xF; |
| 2816 | |
| 2817 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA); |
| 2818 | val32 &= ~0xf0000000; |
| 2819 | val32 |= (reg << 28); |
| 2820 | rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32); |
| 2821 | } |
| 2822 | |
| 2823 | static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, |
| 2824 | bool iqk_ok, int result[][8], |
| 2825 | int candidate, bool tx_only) |
| 2826 | { |
| 2827 | u32 oldval, x, tx1_a, reg; |
| 2828 | int y, tx1_c; |
| 2829 | u32 val32; |
| 2830 | |
| 2831 | if (!iqk_ok) |
| 2832 | return; |
| 2833 | |
| 2834 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); |
| 2835 | oldval = val32 >> 22; |
| 2836 | |
| 2837 | x = result[candidate][4]; |
| 2838 | if ((x & 0x00000200) != 0) |
| 2839 | x = x | 0xfffffc00; |
| 2840 | tx1_a = (x * oldval) >> 8; |
| 2841 | |
| 2842 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); |
| 2843 | val32 &= ~0x3ff; |
| 2844 | val32 |= tx1_a; |
| 2845 | rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); |
| 2846 | |
| 2847 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); |
| 2848 | val32 &= ~BIT(27); |
| 2849 | if ((x * oldval >> 7) & 0x1) |
| 2850 | val32 |= BIT(27); |
| 2851 | rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); |
| 2852 | |
| 2853 | y = result[candidate][5]; |
| 2854 | if ((y & 0x00000200) != 0) |
| 2855 | y = y | 0xfffffc00; |
| 2856 | tx1_c = (y * oldval) >> 8; |
| 2857 | |
| 2858 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE); |
| 2859 | val32 &= ~0xf0000000; |
| 2860 | val32 |= (((tx1_c & 0x3c0) >> 6) << 28); |
| 2861 | rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32); |
| 2862 | |
| 2863 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); |
| 2864 | val32 &= ~0x003f0000; |
| 2865 | val32 |= ((tx1_c & 0x3f) << 16); |
| 2866 | rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); |
| 2867 | |
| 2868 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); |
| 2869 | val32 &= ~BIT(25); |
| 2870 | if ((y * oldval >> 7) & 0x1) |
| 2871 | val32 |= BIT(25); |
| 2872 | rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); |
| 2873 | |
| 2874 | if (tx_only) { |
| 2875 | dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); |
| 2876 | return; |
| 2877 | } |
| 2878 | |
| 2879 | reg = result[candidate][6]; |
| 2880 | |
| 2881 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); |
| 2882 | val32 &= ~0x3ff; |
| 2883 | val32 |= (reg & 0x3ff); |
| 2884 | rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); |
| 2885 | |
| 2886 | reg = result[candidate][7] & 0x3f; |
| 2887 | |
| 2888 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); |
| 2889 | val32 &= ~0xfc00; |
| 2890 | val32 |= ((reg << 10) & 0xfc00); |
| 2891 | rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); |
| 2892 | |
| 2893 | reg = (result[candidate][7] >> 6) & 0xf; |
| 2894 | |
| 2895 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE); |
| 2896 | val32 &= ~0x0000f000; |
| 2897 | val32 |= (reg << 12); |
| 2898 | rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32); |
| 2899 | } |
| 2900 | |
| 2901 | #define MAX_TOLERANCE 5 |
| 2902 | |
| 2903 | static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, |
| 2904 | int result[][8], int c1, int c2) |
| 2905 | { |
| 2906 | u32 i, j, diff, simubitmap, bound = 0; |
| 2907 | int candidate[2] = {-1, -1}; /* for path A and path B */ |
| 2908 | bool retval = true; |
| 2909 | |
| 2910 | if (priv->tx_paths > 1) |
| 2911 | bound = 8; |
| 2912 | else |
| 2913 | bound = 4; |
| 2914 | |
| 2915 | simubitmap = 0; |
| 2916 | |
| 2917 | for (i = 0; i < bound; i++) { |
| 2918 | diff = (result[c1][i] > result[c2][i]) ? |
| 2919 | (result[c1][i] - result[c2][i]) : |
| 2920 | (result[c2][i] - result[c1][i]); |
| 2921 | if (diff > MAX_TOLERANCE) { |
| 2922 | if ((i == 2 || i == 6) && !simubitmap) { |
| 2923 | if (result[c1][i] + result[c1][i + 1] == 0) |
| 2924 | candidate[(i / 4)] = c2; |
| 2925 | else if (result[c2][i] + result[c2][i + 1] == 0) |
| 2926 | candidate[(i / 4)] = c1; |
| 2927 | else |
| 2928 | simubitmap = simubitmap | (1 << i); |
| 2929 | } else { |
| 2930 | simubitmap = simubitmap | (1 << i); |
| 2931 | } |
| 2932 | } |
| 2933 | } |
| 2934 | |
| 2935 | if (simubitmap == 0) { |
| 2936 | for (i = 0; i < (bound / 4); i++) { |
| 2937 | if (candidate[i] >= 0) { |
| 2938 | for (j = i * 4; j < (i + 1) * 4 - 2; j++) |
| 2939 | result[3][j] = result[candidate[i]][j]; |
| 2940 | retval = false; |
| 2941 | } |
| 2942 | } |
| 2943 | return retval; |
| 2944 | } else if (!(simubitmap & 0x0f)) { |
| 2945 | /* path A OK */ |
| 2946 | for (i = 0; i < 4; i++) |
| 2947 | result[3][i] = result[c1][i]; |
| 2948 | } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) { |
| 2949 | /* path B OK */ |
| 2950 | for (i = 4; i < 8; i++) |
| 2951 | result[3][i] = result[c1][i]; |
| 2952 | } |
| 2953 | |
| 2954 | return false; |
| 2955 | } |
| 2956 | |
| 2957 | static void |
| 2958 | rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup) |
| 2959 | { |
| 2960 | int i; |
| 2961 | |
| 2962 | for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) |
| 2963 | backup[i] = rtl8xxxu_read8(priv, reg[i]); |
| 2964 | |
| 2965 | backup[i] = rtl8xxxu_read32(priv, reg[i]); |
| 2966 | } |
| 2967 | |
| 2968 | static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, |
| 2969 | const u32 *reg, u32 *backup) |
| 2970 | { |
| 2971 | int i; |
| 2972 | |
| 2973 | for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) |
| 2974 | rtl8xxxu_write8(priv, reg[i], backup[i]); |
| 2975 | |
| 2976 | rtl8xxxu_write32(priv, reg[i], backup[i]); |
| 2977 | } |
| 2978 | |
| 2979 | static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, |
| 2980 | u32 *backup, int count) |
| 2981 | { |
| 2982 | int i; |
| 2983 | |
| 2984 | for (i = 0; i < count; i++) |
| 2985 | backup[i] = rtl8xxxu_read32(priv, regs[i]); |
| 2986 | } |
| 2987 | |
| 2988 | static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, |
| 2989 | u32 *backup, int count) |
| 2990 | { |
| 2991 | int i; |
| 2992 | |
| 2993 | for (i = 0; i < count; i++) |
| 2994 | rtl8xxxu_write32(priv, regs[i], backup[i]); |
| 2995 | } |
| 2996 | |
| 2997 | |
| 2998 | static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, |
| 2999 | bool path_a_on) |
| 3000 | { |
| 3001 | u32 path_on; |
| 3002 | int i; |
| 3003 | |
| 3004 | path_on = path_a_on ? 0x04db25a4 : 0x0b1b25a4; |
| 3005 | if (priv->tx_paths == 1) { |
| 3006 | path_on = 0x0bdb25a0; |
| 3007 | rtl8xxxu_write32(priv, regs[0], 0x0b1b25a0); |
| 3008 | } else { |
| 3009 | rtl8xxxu_write32(priv, regs[0], path_on); |
| 3010 | } |
| 3011 | |
| 3012 | for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++) |
| 3013 | rtl8xxxu_write32(priv, regs[i], path_on); |
| 3014 | } |
| 3015 | |
| 3016 | static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, |
| 3017 | const u32 *regs, u32 *backup) |
| 3018 | { |
| 3019 | int i = 0; |
| 3020 | |
| 3021 | rtl8xxxu_write8(priv, regs[i], 0x3f); |
| 3022 | |
| 3023 | for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++) |
| 3024 | rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3))); |
| 3025 | |
| 3026 | rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5))); |
| 3027 | } |
| 3028 | |
| 3029 | static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv) |
| 3030 | { |
| 3031 | u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32; |
| 3032 | int result = 0; |
| 3033 | |
| 3034 | /* path-A IQK setting */ |
| 3035 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f); |
| 3036 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f); |
| 3037 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102); |
| 3038 | |
| 3039 | val32 = (priv->rf_paths > 1) ? 0x28160202 : |
| 3040 | /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */ |
| 3041 | 0x28160502; |
| 3042 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32); |
| 3043 | |
| 3044 | /* path-B IQK setting */ |
| 3045 | if (priv->rf_paths > 1) { |
| 3046 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22); |
| 3047 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22); |
| 3048 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102); |
| 3049 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202); |
| 3050 | } |
| 3051 | |
| 3052 | /* LO calibration setting */ |
| 3053 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1); |
| 3054 | |
| 3055 | /* One shot, path A LOK & IQK */ |
| 3056 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); |
| 3057 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); |
| 3058 | |
| 3059 | mdelay(1); |
| 3060 | |
| 3061 | /* Check failed */ |
| 3062 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
| 3063 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); |
| 3064 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); |
| 3065 | reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); |
| 3066 | |
| 3067 | if (!(reg_eac & BIT(28)) && |
| 3068 | ((reg_e94 & 0x03ff0000) != 0x01420000) && |
| 3069 | ((reg_e9c & 0x03ff0000) != 0x00420000)) |
| 3070 | result |= 0x01; |
| 3071 | else /* If TX not OK, ignore RX */ |
| 3072 | goto out; |
| 3073 | |
| 3074 | /* If TX is OK, check whether RX is OK */ |
| 3075 | if (!(reg_eac & BIT(27)) && |
| 3076 | ((reg_ea4 & 0x03ff0000) != 0x01320000) && |
| 3077 | ((reg_eac & 0x03ff0000) != 0x00360000)) |
| 3078 | result |= 0x02; |
| 3079 | else |
| 3080 | dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", |
| 3081 | __func__); |
| 3082 | out: |
| 3083 | return result; |
| 3084 | } |
| 3085 | |
| 3086 | static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv) |
| 3087 | { |
| 3088 | u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; |
| 3089 | int result = 0; |
| 3090 | |
| 3091 | /* One shot, path B LOK & IQK */ |
| 3092 | rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002); |
| 3093 | rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000); |
| 3094 | |
| 3095 | mdelay(1); |
| 3096 | |
| 3097 | /* Check failed */ |
| 3098 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
| 3099 | reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); |
| 3100 | reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); |
| 3101 | reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); |
| 3102 | reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); |
| 3103 | |
| 3104 | if (!(reg_eac & BIT(31)) && |
| 3105 | ((reg_eb4 & 0x03ff0000) != 0x01420000) && |
| 3106 | ((reg_ebc & 0x03ff0000) != 0x00420000)) |
| 3107 | result |= 0x01; |
| 3108 | else |
| 3109 | goto out; |
| 3110 | |
| 3111 | if (!(reg_eac & BIT(30)) && |
| 3112 | (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) && |
| 3113 | (((reg_ecc & 0x03ff0000) >> 16) != 0x36)) |
| 3114 | result |= 0x02; |
| 3115 | else |
| 3116 | dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", |
| 3117 | __func__); |
| 3118 | out: |
| 3119 | return result; |
| 3120 | } |
| 3121 | |
| 3122 | static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, |
| 3123 | int result[][8], int t) |
| 3124 | { |
| 3125 | struct device *dev = &priv->udev->dev; |
| 3126 | u32 i, val32; |
| 3127 | int path_a_ok, path_b_ok; |
| 3128 | int retry = 2; |
| 3129 | const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { |
| 3130 | REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, |
| 3131 | REG_RX_WAIT_CCA, REG_TX_CCK_RFON, |
| 3132 | REG_TX_CCK_BBON, REG_TX_OFDM_RFON, |
| 3133 | REG_TX_OFDM_BBON, REG_TX_TO_RX, |
| 3134 | REG_TX_TO_TX, REG_RX_CCK, |
| 3135 | REG_RX_OFDM, REG_RX_WAIT_RIFS, |
| 3136 | REG_RX_TO_RX, REG_STANDBY, |
| 3137 | REG_SLEEP, REG_PMPD_ANAEN |
| 3138 | }; |
| 3139 | const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { |
| 3140 | REG_TXPAUSE, REG_BEACON_CTRL, |
| 3141 | REG_BEACON_CTRL_1, REG_GPIO_MUXCFG |
| 3142 | }; |
| 3143 | const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { |
| 3144 | REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, |
| 3145 | REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, |
| 3146 | REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, |
| 3147 | REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE |
| 3148 | }; |
| 3149 | |
| 3150 | /* |
| 3151 | * Note: IQ calibration must be performed after loading |
| 3152 | * PHY_REG.txt , and radio_a, radio_b.txt |
| 3153 | */ |
| 3154 | |
| 3155 | if (t == 0) { |
| 3156 | /* Save ADDA parameters, turn Path A ADDA on */ |
| 3157 | rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, |
| 3158 | RTL8XXXU_ADDA_REGS); |
| 3159 | rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); |
| 3160 | rtl8xxxu_save_regs(priv, iqk_bb_regs, |
| 3161 | priv->bb_backup, RTL8XXXU_BB_REGS); |
| 3162 | } |
| 3163 | |
| 3164 | rtl8xxxu_path_adda_on(priv, adda_regs, true); |
| 3165 | |
| 3166 | if (t == 0) { |
| 3167 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); |
| 3168 | if (val32 & FPGA0_HSSI_PARM1_PI) |
| 3169 | priv->pi_enabled = 1; |
| 3170 | } |
| 3171 | |
| 3172 | if (!priv->pi_enabled) { |
| 3173 | /* Switch BB to PI mode to do IQ Calibration. */ |
| 3174 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); |
| 3175 | rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); |
| 3176 | } |
| 3177 | |
| 3178 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 3179 | val32 &= ~FPGA_RF_MODE_CCK; |
| 3180 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); |
| 3181 | |
| 3182 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); |
| 3183 | rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); |
| 3184 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); |
| 3185 | |
| 3186 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); |
| 3187 | val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); |
| 3188 | rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); |
| 3189 | |
| 3190 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); |
| 3191 | val32 &= ~BIT(10); |
| 3192 | rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); |
| 3193 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); |
| 3194 | val32 &= ~BIT(10); |
| 3195 | rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); |
| 3196 | |
| 3197 | if (priv->tx_paths > 1) { |
| 3198 | rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); |
| 3199 | rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000); |
| 3200 | } |
| 3201 | |
| 3202 | /* MAC settings */ |
| 3203 | rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); |
| 3204 | |
| 3205 | /* Page B init */ |
| 3206 | rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000); |
| 3207 | |
| 3208 | if (priv->tx_paths > 1) |
| 3209 | rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000); |
| 3210 | |
| 3211 | /* IQ calibration setting */ |
| 3212 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); |
| 3213 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); |
| 3214 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); |
| 3215 | |
| 3216 | for (i = 0; i < retry; i++) { |
| 3217 | path_a_ok = rtl8xxxu_iqk_path_a(priv); |
| 3218 | if (path_a_ok == 0x03) { |
| 3219 | val32 = rtl8xxxu_read32(priv, |
| 3220 | REG_TX_POWER_BEFORE_IQK_A); |
| 3221 | result[t][0] = (val32 >> 16) & 0x3ff; |
| 3222 | val32 = rtl8xxxu_read32(priv, |
| 3223 | REG_TX_POWER_AFTER_IQK_A); |
| 3224 | result[t][1] = (val32 >> 16) & 0x3ff; |
| 3225 | val32 = rtl8xxxu_read32(priv, |
| 3226 | REG_RX_POWER_BEFORE_IQK_A_2); |
| 3227 | result[t][2] = (val32 >> 16) & 0x3ff; |
| 3228 | val32 = rtl8xxxu_read32(priv, |
| 3229 | REG_RX_POWER_AFTER_IQK_A_2); |
| 3230 | result[t][3] = (val32 >> 16) & 0x3ff; |
| 3231 | break; |
| 3232 | } else if (i == (retry - 1) && path_a_ok == 0x01) { |
| 3233 | /* TX IQK OK */ |
| 3234 | dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n", |
| 3235 | __func__); |
| 3236 | |
| 3237 | val32 = rtl8xxxu_read32(priv, |
| 3238 | REG_TX_POWER_BEFORE_IQK_A); |
| 3239 | result[t][0] = (val32 >> 16) & 0x3ff; |
| 3240 | val32 = rtl8xxxu_read32(priv, |
| 3241 | REG_TX_POWER_AFTER_IQK_A); |
| 3242 | result[t][1] = (val32 >> 16) & 0x3ff; |
| 3243 | } |
| 3244 | } |
| 3245 | |
| 3246 | if (!path_a_ok) |
| 3247 | dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); |
| 3248 | |
| 3249 | if (priv->tx_paths > 1) { |
| 3250 | /* |
| 3251 | * Path A into standby |
| 3252 | */ |
| 3253 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0); |
| 3254 | rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); |
| 3255 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); |
| 3256 | |
| 3257 | /* Turn Path B ADDA on */ |
| 3258 | rtl8xxxu_path_adda_on(priv, adda_regs, false); |
| 3259 | |
| 3260 | for (i = 0; i < retry; i++) { |
| 3261 | path_b_ok = rtl8xxxu_iqk_path_b(priv); |
| 3262 | if (path_b_ok == 0x03) { |
| 3263 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); |
| 3264 | result[t][4] = (val32 >> 16) & 0x3ff; |
| 3265 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); |
| 3266 | result[t][5] = (val32 >> 16) & 0x3ff; |
| 3267 | val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); |
| 3268 | result[t][6] = (val32 >> 16) & 0x3ff; |
| 3269 | val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); |
| 3270 | result[t][7] = (val32 >> 16) & 0x3ff; |
| 3271 | break; |
| 3272 | } else if (i == (retry - 1) && path_b_ok == 0x01) { |
| 3273 | /* TX IQK OK */ |
| 3274 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); |
| 3275 | result[t][4] = (val32 >> 16) & 0x3ff; |
| 3276 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); |
| 3277 | result[t][5] = (val32 >> 16) & 0x3ff; |
| 3278 | } |
| 3279 | } |
| 3280 | |
| 3281 | if (!path_b_ok) |
| 3282 | dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); |
| 3283 | } |
| 3284 | |
| 3285 | /* Back to BB mode, load original value */ |
| 3286 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); |
| 3287 | |
| 3288 | if (t) { |
| 3289 | if (!priv->pi_enabled) { |
| 3290 | /* |
| 3291 | * Switch back BB to SI mode after finishing |
| 3292 | * IQ Calibration |
| 3293 | */ |
| 3294 | val32 = 0x01000000; |
| 3295 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); |
| 3296 | rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); |
| 3297 | } |
| 3298 | |
| 3299 | /* Reload ADDA power saving parameters */ |
| 3300 | rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, |
| 3301 | RTL8XXXU_ADDA_REGS); |
| 3302 | |
| 3303 | /* Reload MAC parameters */ |
| 3304 | rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); |
| 3305 | |
| 3306 | /* Reload BB parameters */ |
| 3307 | rtl8xxxu_restore_regs(priv, iqk_bb_regs, |
| 3308 | priv->bb_backup, RTL8XXXU_BB_REGS); |
| 3309 | |
| 3310 | /* Restore RX initial gain */ |
| 3311 | rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); |
| 3312 | |
| 3313 | if (priv->tx_paths > 1) { |
| 3314 | rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, |
| 3315 | 0x00032ed3); |
| 3316 | } |
| 3317 | |
| 3318 | /* Load 0xe30 IQC default value */ |
| 3319 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); |
| 3320 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); |
| 3321 | } |
| 3322 | } |
| 3323 | |
| 3324 | static void rtl8723a_phy_iq_calibrate(struct rtl8xxxu_priv *priv) |
| 3325 | { |
| 3326 | struct device *dev = &priv->udev->dev; |
| 3327 | int result[4][8]; /* last is final result */ |
| 3328 | int i, candidate; |
| 3329 | bool path_a_ok, path_b_ok; |
| 3330 | u32 reg_e94, reg_e9c, reg_ea4, reg_eac; |
| 3331 | u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; |
| 3332 | s32 reg_tmp = 0; |
| 3333 | bool simu; |
| 3334 | |
| 3335 | memset(result, 0, sizeof(result)); |
| 3336 | candidate = -1; |
| 3337 | |
| 3338 | path_a_ok = false; |
| 3339 | path_b_ok = false; |
| 3340 | |
| 3341 | rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 3342 | |
| 3343 | for (i = 0; i < 3; i++) { |
| 3344 | rtl8xxxu_phy_iqcalibrate(priv, result, i); |
| 3345 | |
| 3346 | if (i == 1) { |
| 3347 | simu = rtl8xxxu_simularity_compare(priv, result, 0, 1); |
| 3348 | if (simu) { |
| 3349 | candidate = 0; |
| 3350 | break; |
| 3351 | } |
| 3352 | } |
| 3353 | |
| 3354 | if (i == 2) { |
| 3355 | simu = rtl8xxxu_simularity_compare(priv, result, 0, 2); |
| 3356 | if (simu) { |
| 3357 | candidate = 0; |
| 3358 | break; |
| 3359 | } |
| 3360 | |
| 3361 | simu = rtl8xxxu_simularity_compare(priv, result, 1, 2); |
| 3362 | if (simu) { |
| 3363 | candidate = 1; |
| 3364 | } else { |
| 3365 | for (i = 0; i < 8; i++) |
| 3366 | reg_tmp += result[3][i]; |
| 3367 | |
| 3368 | if (reg_tmp) |
| 3369 | candidate = 3; |
| 3370 | else |
| 3371 | candidate = -1; |
| 3372 | } |
| 3373 | } |
| 3374 | } |
| 3375 | |
| 3376 | for (i = 0; i < 4; i++) { |
| 3377 | reg_e94 = result[i][0]; |
| 3378 | reg_e9c = result[i][1]; |
| 3379 | reg_ea4 = result[i][2]; |
| 3380 | reg_eac = result[i][3]; |
| 3381 | reg_eb4 = result[i][4]; |
| 3382 | reg_ebc = result[i][5]; |
| 3383 | reg_ec4 = result[i][6]; |
| 3384 | reg_ecc = result[i][7]; |
| 3385 | } |
| 3386 | |
| 3387 | if (candidate >= 0) { |
| 3388 | reg_e94 = result[candidate][0]; |
| 3389 | priv->rege94 = reg_e94; |
| 3390 | reg_e9c = result[candidate][1]; |
| 3391 | priv->rege9c = reg_e9c; |
| 3392 | reg_ea4 = result[candidate][2]; |
| 3393 | reg_eac = result[candidate][3]; |
| 3394 | reg_eb4 = result[candidate][4]; |
| 3395 | priv->regeb4 = reg_eb4; |
| 3396 | reg_ebc = result[candidate][5]; |
| 3397 | priv->regebc = reg_ebc; |
| 3398 | reg_ec4 = result[candidate][6]; |
| 3399 | reg_ecc = result[candidate][7]; |
| 3400 | dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); |
| 3401 | dev_dbg(dev, |
| 3402 | "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x " |
| 3403 | "ecc=%x\n ", __func__, reg_e94, reg_e9c, |
| 3404 | reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); |
| 3405 | path_a_ok = true; |
| 3406 | path_b_ok = true; |
| 3407 | } else { |
| 3408 | reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; |
| 3409 | reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; |
| 3410 | } |
| 3411 | |
| 3412 | if (reg_e94 && candidate >= 0) |
| 3413 | rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, |
| 3414 | candidate, (reg_ea4 == 0)); |
| 3415 | |
| 3416 | if (priv->tx_paths > 1 && reg_eb4) |
| 3417 | rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, |
| 3418 | candidate, (reg_ec4 == 0)); |
| 3419 | |
| 3420 | rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg, |
| 3421 | priv->bb_recovery_backup, RTL8XXXU_BB_REGS); |
| 3422 | } |
| 3423 | |
| 3424 | static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv) |
| 3425 | { |
| 3426 | u32 val32; |
| 3427 | u32 rf_amode, rf_bmode = 0, lstf; |
| 3428 | |
| 3429 | /* Check continuous TX and Packet TX */ |
| 3430 | lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); |
| 3431 | |
| 3432 | if (lstf & OFDM_LSTF_MASK) { |
| 3433 | /* Disable all continuous TX */ |
| 3434 | val32 = lstf & ~OFDM_LSTF_MASK; |
| 3435 | rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); |
| 3436 | |
| 3437 | /* Read original RF mode Path A */ |
| 3438 | rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC); |
| 3439 | |
| 3440 | /* Set RF mode to standby Path A */ |
| 3441 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, |
| 3442 | (rf_amode & 0x8ffff) | 0x10000); |
| 3443 | |
| 3444 | /* Path-B */ |
| 3445 | if (priv->tx_paths > 1) { |
| 3446 | rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B, |
| 3447 | RF6052_REG_AC); |
| 3448 | |
| 3449 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, |
| 3450 | (rf_bmode & 0x8ffff) | 0x10000); |
| 3451 | } |
| 3452 | } else { |
| 3453 | /* Deal with Packet TX case */ |
| 3454 | /* block all queues */ |
| 3455 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); |
| 3456 | } |
| 3457 | |
| 3458 | /* Start LC calibration */ |
| 3459 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); |
| 3460 | val32 |= 0x08000; |
| 3461 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); |
| 3462 | |
| 3463 | msleep(100); |
| 3464 | |
| 3465 | /* Restore original parameters */ |
| 3466 | if (lstf & OFDM_LSTF_MASK) { |
| 3467 | /* Path-A */ |
| 3468 | rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); |
| 3469 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode); |
| 3470 | |
| 3471 | /* Path-B */ |
| 3472 | if (priv->tx_paths > 1) |
| 3473 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, |
| 3474 | rf_bmode); |
| 3475 | } else /* Deal with Packet TX case */ |
| 3476 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); |
| 3477 | } |
| 3478 | |
| 3479 | static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv) |
| 3480 | { |
| 3481 | int i; |
| 3482 | u16 reg; |
| 3483 | |
| 3484 | reg = REG_MACID; |
| 3485 | |
| 3486 | for (i = 0; i < ETH_ALEN; i++) |
| 3487 | rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]); |
| 3488 | |
| 3489 | return 0; |
| 3490 | } |
| 3491 | |
| 3492 | static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid) |
| 3493 | { |
| 3494 | int i; |
| 3495 | u16 reg; |
| 3496 | |
| 3497 | dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid); |
| 3498 | |
| 3499 | reg = REG_BSSID; |
| 3500 | |
| 3501 | for (i = 0; i < ETH_ALEN; i++) |
| 3502 | rtl8xxxu_write8(priv, reg + i, bssid[i]); |
| 3503 | |
| 3504 | return 0; |
| 3505 | } |
| 3506 | |
| 3507 | static void |
| 3508 | rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor) |
| 3509 | { |
| 3510 | u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 }; |
| 3511 | u8 max_agg = 0xf; |
| 3512 | int i; |
| 3513 | |
| 3514 | ampdu_factor = 1 << (ampdu_factor + 2); |
| 3515 | if (ampdu_factor > max_agg) |
| 3516 | ampdu_factor = max_agg; |
| 3517 | |
| 3518 | for (i = 0; i < 4; i++) { |
| 3519 | if ((vals[i] & 0xf0) > (ampdu_factor << 4)) |
| 3520 | vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4); |
| 3521 | |
| 3522 | if ((vals[i] & 0x0f) > ampdu_factor) |
| 3523 | vals[i] = (vals[i] & 0xf0) | ampdu_factor; |
| 3524 | |
| 3525 | rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]); |
| 3526 | } |
| 3527 | } |
| 3528 | |
| 3529 | static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density) |
| 3530 | { |
| 3531 | u8 val8; |
| 3532 | |
| 3533 | val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE); |
| 3534 | val8 &= 0xf8; |
| 3535 | val8 |= density; |
| 3536 | rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8); |
| 3537 | } |
| 3538 | |
| 3539 | static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv) |
| 3540 | { |
| 3541 | u8 val8; |
| 3542 | int count, ret; |
| 3543 | |
| 3544 | /* Start of rtl8723AU_card_enable_flow */ |
| 3545 | /* Act to Cardemu sequence*/ |
| 3546 | /* Turn off RF */ |
| 3547 | rtl8xxxu_write8(priv, REG_RF_CTRL, 0); |
| 3548 | |
| 3549 | /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */ |
| 3550 | val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); |
| 3551 | val8 &= ~LEDCFG2_DPDT_SELECT; |
| 3552 | rtl8xxxu_write8(priv, REG_LEDCFG2, val8); |
| 3553 | |
| 3554 | /* 0x0005[1] = 1 turn off MAC by HW state machine*/ |
| 3555 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 3556 | val8 |= BIT(1); |
| 3557 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 3558 | |
| 3559 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
| 3560 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 3561 | if ((val8 & BIT(1)) == 0) |
| 3562 | break; |
| 3563 | udelay(10); |
| 3564 | } |
| 3565 | |
| 3566 | if (!count) { |
| 3567 | dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", |
| 3568 | __func__); |
| 3569 | ret = -EBUSY; |
| 3570 | goto exit; |
| 3571 | } |
| 3572 | |
| 3573 | /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ |
| 3574 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); |
| 3575 | val8 |= SYS_ISO_ANALOG_IPS; |
| 3576 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); |
| 3577 | |
| 3578 | /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ |
| 3579 | val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); |
| 3580 | val8 &= ~LDOA15_ENABLE; |
| 3581 | rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); |
| 3582 | |
| 3583 | exit: |
| 3584 | return ret; |
| 3585 | } |
| 3586 | |
| 3587 | static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv) |
| 3588 | { |
| 3589 | u8 val8; |
| 3590 | u8 val32; |
| 3591 | int count, ret; |
| 3592 | |
| 3593 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); |
| 3594 | |
| 3595 | /* |
| 3596 | * Poll - wait for RX packet to complete |
| 3597 | */ |
| 3598 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
| 3599 | val32 = rtl8xxxu_read32(priv, 0x5f8); |
| 3600 | if (!val32) |
| 3601 | break; |
| 3602 | udelay(10); |
| 3603 | } |
| 3604 | |
| 3605 | if (!count) { |
| 3606 | dev_warn(&priv->udev->dev, |
| 3607 | "%s: RX poll timed out (0x05f8)\n", __func__); |
| 3608 | ret = -EBUSY; |
| 3609 | goto exit; |
| 3610 | } |
| 3611 | |
| 3612 | /* Disable CCK and OFDM, clock gated */ |
| 3613 | val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); |
| 3614 | val8 &= ~SYS_FUNC_BBRSTB; |
| 3615 | rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); |
| 3616 | |
| 3617 | udelay(2); |
| 3618 | |
| 3619 | /* Reset baseband */ |
| 3620 | val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); |
| 3621 | val8 &= ~SYS_FUNC_BB_GLB_RSTN; |
| 3622 | rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); |
| 3623 | |
| 3624 | /* Reset MAC TRX */ |
| 3625 | val8 = rtl8xxxu_read8(priv, REG_CR); |
| 3626 | val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE; |
| 3627 | rtl8xxxu_write8(priv, REG_CR, val8); |
| 3628 | |
| 3629 | /* Reset MAC TRX */ |
| 3630 | val8 = rtl8xxxu_read8(priv, REG_CR + 1); |
| 3631 | val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */ |
| 3632 | rtl8xxxu_write8(priv, REG_CR + 1, val8); |
| 3633 | |
| 3634 | /* Respond TX OK to scheduler */ |
| 3635 | val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); |
| 3636 | val8 |= DUAL_TSF_TX_OK; |
| 3637 | rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); |
| 3638 | |
| 3639 | exit: |
| 3640 | return ret; |
| 3641 | } |
| 3642 | |
| 3643 | static void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv) |
| 3644 | { |
| 3645 | u8 val8; |
| 3646 | |
| 3647 | /* Clear suspend enable and power down enable*/ |
| 3648 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 3649 | val8 &= ~(BIT(3) | BIT(7)); |
| 3650 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 3651 | |
| 3652 | /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ |
| 3653 | val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); |
| 3654 | val8 &= ~BIT(0); |
| 3655 | rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); |
| 3656 | |
| 3657 | /* 0x04[12:11] = 11 enable WL suspend*/ |
| 3658 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 3659 | val8 &= ~(BIT(3) | BIT(4)); |
| 3660 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 3661 | } |
| 3662 | |
| 3663 | static int rtl8xxxu_emu_to_active(struct rtl8xxxu_priv *priv) |
| 3664 | { |
| 3665 | u8 val8; |
| 3666 | u32 val32; |
| 3667 | int count, ret = 0; |
| 3668 | |
| 3669 | /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/ |
| 3670 | val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); |
| 3671 | val8 |= LDOA15_ENABLE; |
| 3672 | rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); |
| 3673 | |
| 3674 | /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/ |
| 3675 | val8 = rtl8xxxu_read8(priv, 0x0067); |
| 3676 | val8 &= ~BIT(4); |
| 3677 | rtl8xxxu_write8(priv, 0x0067, val8); |
| 3678 | |
| 3679 | mdelay(1); |
| 3680 | |
| 3681 | /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */ |
| 3682 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); |
| 3683 | val8 &= ~SYS_ISO_ANALOG_IPS; |
| 3684 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); |
| 3685 | |
| 3686 | /* disable SW LPS 0x04[10]= 0 */ |
| 3687 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 3688 | val8 &= ~BIT(2); |
| 3689 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 3690 | |
| 3691 | /* wait till 0x04[17] = 1 power ready*/ |
| 3692 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
| 3693 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 3694 | if (val32 & BIT(17)) |
| 3695 | break; |
| 3696 | |
| 3697 | udelay(10); |
| 3698 | } |
| 3699 | |
| 3700 | if (!count) { |
| 3701 | ret = -EBUSY; |
| 3702 | goto exit; |
| 3703 | } |
| 3704 | |
| 3705 | /* We should be able to optimize the following three entries into one */ |
| 3706 | |
| 3707 | /* release WLON reset 0x04[16]= 1*/ |
| 3708 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); |
| 3709 | val8 |= BIT(0); |
| 3710 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); |
| 3711 | |
| 3712 | /* disable HWPDN 0x04[15]= 0*/ |
| 3713 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 3714 | val8 &= ~BIT(7); |
| 3715 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 3716 | |
| 3717 | /* disable WL suspend*/ |
| 3718 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 3719 | val8 &= ~(BIT(3) | BIT(4)); |
| 3720 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 3721 | |
| 3722 | /* set, then poll until 0 */ |
| 3723 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 3724 | val32 |= APS_FSMCO_MAC_ENABLE; |
| 3725 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); |
| 3726 | |
| 3727 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
| 3728 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 3729 | if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { |
| 3730 | ret = 0; |
| 3731 | break; |
| 3732 | } |
| 3733 | udelay(10); |
| 3734 | } |
| 3735 | |
| 3736 | if (!count) { |
| 3737 | ret = -EBUSY; |
| 3738 | goto exit; |
| 3739 | } |
| 3740 | |
| 3741 | /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */ |
| 3742 | /* |
| 3743 | * Note: Vendor driver actually clears this bit, despite the |
| 3744 | * documentation claims it's being set! |
| 3745 | */ |
| 3746 | val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); |
| 3747 | val8 |= LEDCFG2_DPDT_SELECT; |
| 3748 | val8 &= ~LEDCFG2_DPDT_SELECT; |
| 3749 | rtl8xxxu_write8(priv, REG_LEDCFG2, val8); |
| 3750 | |
| 3751 | exit: |
| 3752 | return ret; |
| 3753 | } |
| 3754 | |
| 3755 | static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv) |
| 3756 | { |
| 3757 | u8 val8; |
| 3758 | |
| 3759 | /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */ |
| 3760 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20); |
| 3761 | |
| 3762 | /* 0x04[12:11] = 01 enable WL suspend */ |
| 3763 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 3764 | val8 &= ~BIT(4); |
| 3765 | val8 |= BIT(3); |
| 3766 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 3767 | |
| 3768 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 3769 | val8 |= BIT(7); |
| 3770 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 3771 | |
| 3772 | /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ |
| 3773 | val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); |
| 3774 | val8 |= BIT(0); |
| 3775 | rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); |
| 3776 | |
| 3777 | return 0; |
| 3778 | } |
| 3779 | |
| 3780 | static int rtl8723au_power_on(struct rtl8xxxu_priv *priv) |
| 3781 | { |
| 3782 | u8 val8; |
| 3783 | u16 val16; |
| 3784 | u32 val32; |
| 3785 | int ret; |
| 3786 | |
| 3787 | /* |
| 3788 | * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register |
| 3789 | */ |
| 3790 | rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0); |
| 3791 | |
| 3792 | rtl8xxxu_disabled_to_emu(priv); |
| 3793 | |
| 3794 | ret = rtl8xxxu_emu_to_active(priv); |
| 3795 | if (ret) |
| 3796 | goto exit; |
| 3797 | |
| 3798 | /* |
| 3799 | * 0x0004[19] = 1, reset 8051 |
| 3800 | */ |
| 3801 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); |
| 3802 | val8 |= BIT(3); |
| 3803 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); |
| 3804 | |
| 3805 | /* |
| 3806 | * Enable MAC DMA/WMAC/SCHEDULE/SEC block |
| 3807 | * Set CR bit10 to enable 32k calibration. |
| 3808 | */ |
| 3809 | val16 = rtl8xxxu_read16(priv, REG_CR); |
| 3810 | val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | |
| 3811 | CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | |
| 3812 | CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | |
| 3813 | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | |
| 3814 | CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); |
| 3815 | rtl8xxxu_write16(priv, REG_CR, val16); |
| 3816 | |
| 3817 | /* For EFuse PG */ |
| 3818 | val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); |
| 3819 | val32 &= ~(BIT(28) | BIT(29) | BIT(30)); |
| 3820 | val32 |= (0x06 << 28); |
| 3821 | rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32); |
| 3822 | exit: |
| 3823 | return ret; |
| 3824 | } |
| 3825 | |
Kalle Valo | c096377 | 2015-10-25 18:24:38 +0200 | [diff] [blame] | 3826 | #ifdef CONFIG_RTL8XXXU_UNTESTED |
| 3827 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3828 | static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv) |
| 3829 | { |
| 3830 | u8 val8; |
| 3831 | u16 val16; |
| 3832 | u32 val32; |
| 3833 | int i; |
| 3834 | |
| 3835 | for (i = 100; i; i--) { |
| 3836 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO); |
| 3837 | if (val8 & APS_FSMCO_PFM_ALDN) |
| 3838 | break; |
| 3839 | } |
| 3840 | |
| 3841 | if (!i) { |
| 3842 | pr_info("%s: Poll failed\n", __func__); |
| 3843 | return -ENODEV; |
| 3844 | } |
| 3845 | |
| 3846 | /* |
| 3847 | * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register |
| 3848 | */ |
| 3849 | rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0); |
| 3850 | rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b); |
| 3851 | udelay(100); |
| 3852 | |
| 3853 | val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL); |
| 3854 | if (!(val8 & LDOV12D_ENABLE)) { |
| 3855 | pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8); |
| 3856 | val8 |= LDOV12D_ENABLE; |
| 3857 | rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8); |
| 3858 | |
| 3859 | udelay(100); |
| 3860 | |
| 3861 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); |
| 3862 | val8 &= ~SYS_ISO_MD2PP; |
| 3863 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); |
| 3864 | } |
| 3865 | |
| 3866 | /* |
| 3867 | * Auto enable WLAN |
| 3868 | */ |
| 3869 | val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); |
| 3870 | val16 |= APS_FSMCO_MAC_ENABLE; |
| 3871 | rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); |
| 3872 | |
| 3873 | for (i = 1000; i; i--) { |
| 3874 | val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); |
| 3875 | if (!(val16 & APS_FSMCO_MAC_ENABLE)) |
| 3876 | break; |
| 3877 | } |
| 3878 | if (!i) { |
| 3879 | pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__); |
| 3880 | return -EBUSY; |
| 3881 | } |
| 3882 | |
| 3883 | /* |
| 3884 | * Enable radio, GPIO, LED |
| 3885 | */ |
| 3886 | val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN | |
| 3887 | APS_FSMCO_PFM_ALDN; |
| 3888 | rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); |
| 3889 | |
| 3890 | /* |
| 3891 | * Release RF digital isolation |
| 3892 | */ |
| 3893 | val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); |
| 3894 | val16 &= ~SYS_ISO_DIOR; |
| 3895 | rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); |
| 3896 | |
| 3897 | val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL); |
| 3898 | val8 &= ~APSD_CTRL_OFF; |
| 3899 | rtl8xxxu_write8(priv, REG_APSD_CTRL, val8); |
| 3900 | for (i = 200; i; i--) { |
| 3901 | val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL); |
| 3902 | if (!(val8 & APSD_CTRL_OFF_STATUS)) |
| 3903 | break; |
| 3904 | } |
| 3905 | |
| 3906 | if (!i) { |
| 3907 | pr_info("%s: APSD_CTRL poll failed\n", __func__); |
| 3908 | return -EBUSY; |
| 3909 | } |
| 3910 | |
| 3911 | /* |
| 3912 | * Enable MAC DMA/WMAC/SCHEDULE/SEC block |
| 3913 | */ |
| 3914 | val16 = rtl8xxxu_read16(priv, REG_CR); |
| 3915 | val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | |
| 3916 | CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE | |
| 3917 | CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE; |
| 3918 | rtl8xxxu_write16(priv, REG_CR, val16); |
| 3919 | |
| 3920 | /* |
| 3921 | * Workaround for 8188RU LNA power leakage problem. |
| 3922 | */ |
| 3923 | if (priv->rtlchip == 0x8188c && priv->hi_pa) { |
| 3924 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); |
| 3925 | val32 &= ~BIT(1); |
| 3926 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); |
| 3927 | } |
| 3928 | return 0; |
| 3929 | } |
| 3930 | |
Kalle Valo | c096377 | 2015-10-25 18:24:38 +0200 | [diff] [blame] | 3931 | #endif |
| 3932 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3933 | static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv) |
| 3934 | { |
| 3935 | u8 val8; |
| 3936 | u16 val16; |
| 3937 | u32 val32; |
| 3938 | |
| 3939 | /* |
| 3940 | * Workaround for 8188RU LNA power leakage problem. |
| 3941 | */ |
| 3942 | if (priv->rtlchip == 0x8188c && priv->hi_pa) { |
| 3943 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); |
| 3944 | val32 |= BIT(1); |
| 3945 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); |
| 3946 | } |
| 3947 | |
| 3948 | rtl8xxxu_active_to_lps(priv); |
| 3949 | |
| 3950 | /* Turn off RF */ |
| 3951 | rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); |
| 3952 | |
| 3953 | /* Reset Firmware if running in RAM */ |
| 3954 | if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) |
| 3955 | rtl8xxxu_firmware_self_reset(priv); |
| 3956 | |
| 3957 | /* Reset MCU */ |
| 3958 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 3959 | val16 &= ~SYS_FUNC_CPU_ENABLE; |
| 3960 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); |
| 3961 | |
| 3962 | /* Reset MCU ready status */ |
| 3963 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); |
| 3964 | |
| 3965 | rtl8xxxu_active_to_emu(priv); |
| 3966 | rtl8xxxu_emu_to_disabled(priv); |
| 3967 | |
| 3968 | /* Reset MCU IO Wrapper */ |
| 3969 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); |
| 3970 | val8 &= ~BIT(0); |
| 3971 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); |
| 3972 | |
| 3973 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); |
| 3974 | val8 |= BIT(0); |
| 3975 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); |
| 3976 | |
| 3977 | /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */ |
| 3978 | rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e); |
| 3979 | } |
| 3980 | |
| 3981 | static void rtl8xxxu_init_bt(struct rtl8xxxu_priv *priv) |
| 3982 | { |
| 3983 | if (!priv->has_bluetooth) |
| 3984 | return; |
| 3985 | } |
| 3986 | |
| 3987 | static int rtl8xxxu_init_device(struct ieee80211_hw *hw) |
| 3988 | { |
| 3989 | struct rtl8xxxu_priv *priv = hw->priv; |
| 3990 | struct device *dev = &priv->udev->dev; |
| 3991 | struct rtl8xxxu_rfregval *rftable; |
| 3992 | bool macpower; |
| 3993 | int ret; |
| 3994 | u8 val8; |
| 3995 | u16 val16; |
| 3996 | u32 val32; |
| 3997 | |
| 3998 | /* Check if MAC is already powered on */ |
| 3999 | val8 = rtl8xxxu_read8(priv, REG_CR); |
| 4000 | |
| 4001 | /* |
| 4002 | * Fix 92DU-VC S3 hang with the reason is that secondary mac is not |
| 4003 | * initialized. First MAC returns 0xea, second MAC returns 0x00 |
| 4004 | */ |
| 4005 | if (val8 == 0xea) |
| 4006 | macpower = false; |
| 4007 | else |
| 4008 | macpower = true; |
| 4009 | |
| 4010 | ret = priv->fops->power_on(priv); |
| 4011 | if (ret < 0) { |
| 4012 | dev_warn(dev, "%s: Failed power on\n", __func__); |
| 4013 | goto exit; |
| 4014 | } |
| 4015 | |
| 4016 | dev_dbg(dev, "%s: macpower %i\n", __func__, macpower); |
| 4017 | if (!macpower) { |
| 4018 | ret = rtl8xxxu_init_llt_table(priv, TX_TOTAL_PAGE_NUM); |
| 4019 | if (ret) { |
| 4020 | dev_warn(dev, "%s: LLT table init failed\n", __func__); |
| 4021 | goto exit; |
| 4022 | } |
| 4023 | } |
| 4024 | |
| 4025 | ret = rtl8xxxu_download_firmware(priv); |
| 4026 | dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret); |
| 4027 | if (ret) |
| 4028 | goto exit; |
| 4029 | ret = rtl8xxxu_start_firmware(priv); |
| 4030 | dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret); |
| 4031 | if (ret) |
| 4032 | goto exit; |
| 4033 | |
| 4034 | ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table); |
| 4035 | dev_dbg(dev, "%s: init_mac %i\n", __func__, ret); |
| 4036 | if (ret) |
| 4037 | goto exit; |
| 4038 | |
| 4039 | ret = rtl8xxxu_init_phy_bb(priv); |
| 4040 | dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret); |
| 4041 | if (ret) |
| 4042 | goto exit; |
| 4043 | |
| 4044 | switch(priv->rtlchip) { |
| 4045 | case 0x8723a: |
| 4046 | rftable = rtl8723au_radioa_1t_init_table; |
| 4047 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); |
| 4048 | break; |
| 4049 | case 0x8188c: |
| 4050 | if (priv->hi_pa) |
| 4051 | rftable = rtl8188ru_radioa_1t_highpa_table; |
| 4052 | else |
| 4053 | rftable = rtl8192cu_radioa_1t_init_table; |
| 4054 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); |
| 4055 | break; |
| 4056 | case 0x8191c: |
| 4057 | rftable = rtl8192cu_radioa_1t_init_table; |
| 4058 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); |
| 4059 | break; |
| 4060 | case 0x8192c: |
| 4061 | rftable = rtl8192cu_radioa_2t_init_table; |
| 4062 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); |
| 4063 | if (ret) |
| 4064 | break; |
| 4065 | rftable = rtl8192cu_radiob_2t_init_table; |
| 4066 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B); |
| 4067 | break; |
| 4068 | default: |
| 4069 | ret = -EINVAL; |
| 4070 | } |
| 4071 | |
| 4072 | if (ret) |
| 4073 | goto exit; |
| 4074 | |
| 4075 | /* Reduce 80M spur */ |
| 4076 | rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d); |
| 4077 | rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); |
| 4078 | rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82); |
| 4079 | rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); |
| 4080 | |
| 4081 | /* RFSW Control - clear bit 14 ?? */ |
| 4082 | rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003); |
| 4083 | /* 0x07000760 */ |
| 4084 | val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW | |
| 4085 | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE | |
| 4086 | ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) << |
| 4087 | FPGA0_RF_BD_CTRL_SHIFT); |
| 4088 | rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); |
| 4089 | /* 0x860[6:5]= 00 - why? - this sets antenna B */ |
| 4090 | rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210); |
| 4091 | |
| 4092 | priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A, |
| 4093 | RF6052_REG_MODE_AG); |
| 4094 | |
| 4095 | dev_dbg(dev, "%s: macpower %i\n", __func__, macpower); |
| 4096 | if (!macpower) { |
| 4097 | if (priv->ep_tx_normal_queue) |
| 4098 | val8 = TX_PAGE_NUM_NORM_PQ; |
| 4099 | else |
| 4100 | val8 = 0; |
| 4101 | |
| 4102 | rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8); |
| 4103 | |
| 4104 | val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD; |
| 4105 | |
| 4106 | if (priv->ep_tx_high_queue) |
| 4107 | val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT); |
| 4108 | if (priv->ep_tx_low_queue) |
| 4109 | val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT); |
| 4110 | |
| 4111 | rtl8xxxu_write32(priv, REG_RQPN, val32); |
| 4112 | |
| 4113 | /* |
| 4114 | * Set TX buffer boundary |
| 4115 | */ |
| 4116 | val8 = TX_TOTAL_PAGE_NUM + 1; |
| 4117 | rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8); |
| 4118 | rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8); |
| 4119 | rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8); |
| 4120 | rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8); |
| 4121 | rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8); |
| 4122 | } |
| 4123 | |
| 4124 | ret = rtl8xxxu_init_queue_priority(priv); |
| 4125 | dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret); |
| 4126 | if (ret) |
| 4127 | goto exit; |
| 4128 | |
| 4129 | /* |
| 4130 | * Set RX page boundary |
| 4131 | */ |
| 4132 | rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff); |
| 4133 | /* |
| 4134 | * Transfer page size is always 128 |
| 4135 | */ |
| 4136 | val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) | |
| 4137 | (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT); |
| 4138 | rtl8xxxu_write8(priv, REG_PBP, val8); |
| 4139 | |
| 4140 | /* |
| 4141 | * Unit in 8 bytes, not obvious what it is used for |
| 4142 | */ |
| 4143 | rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4); |
| 4144 | |
| 4145 | /* |
| 4146 | * Enable all interrupts - not obvious USB needs to do this |
| 4147 | */ |
| 4148 | rtl8xxxu_write32(priv, REG_HISR, 0xffffffff); |
| 4149 | rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff); |
| 4150 | |
| 4151 | rtl8xxxu_set_mac(priv); |
| 4152 | rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION); |
| 4153 | |
| 4154 | /* |
| 4155 | * Configure initial WMAC settings |
| 4156 | */ |
| 4157 | val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST | |
| 4158 | /* RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON | */ |
| 4159 | RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL | |
| 4160 | RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; |
| 4161 | rtl8xxxu_write32(priv, REG_RCR, val32); |
| 4162 | |
| 4163 | /* |
| 4164 | * Accept all multicast |
| 4165 | */ |
| 4166 | rtl8xxxu_write32(priv, REG_MAR, 0xffffffff); |
| 4167 | rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); |
| 4168 | |
| 4169 | /* |
| 4170 | * Init adaptive controls |
| 4171 | */ |
| 4172 | val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); |
| 4173 | val32 &= ~RESPONSE_RATE_BITMAP_ALL; |
| 4174 | val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M; |
| 4175 | rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); |
| 4176 | |
| 4177 | /* CCK = 0x0a, OFDM = 0x10 */ |
| 4178 | rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10); |
| 4179 | rtl8xxxu_set_retry(priv, 0x30, 0x30); |
| 4180 | rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10); |
| 4181 | |
| 4182 | /* |
| 4183 | * Init EDCA |
| 4184 | */ |
| 4185 | rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a); |
| 4186 | |
| 4187 | /* Set CCK SIFS */ |
| 4188 | rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a); |
| 4189 | |
| 4190 | /* Set OFDM SIFS */ |
| 4191 | rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a); |
| 4192 | |
| 4193 | /* TXOP */ |
| 4194 | rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b); |
| 4195 | rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f); |
| 4196 | rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324); |
| 4197 | rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226); |
| 4198 | |
| 4199 | /* Set data auto rate fallback retry count */ |
| 4200 | rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000); |
| 4201 | rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404); |
| 4202 | rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201); |
| 4203 | rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605); |
| 4204 | |
| 4205 | val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL); |
| 4206 | val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY; |
| 4207 | rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8); |
| 4208 | |
| 4209 | /* Set ACK timeout */ |
| 4210 | rtl8xxxu_write8(priv, REG_ACKTO, 0x40); |
| 4211 | |
| 4212 | /* |
| 4213 | * Initialize beacon parameters |
| 4214 | */ |
| 4215 | val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8); |
| 4216 | rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16); |
| 4217 | rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404); |
| 4218 | rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME); |
| 4219 | rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME); |
| 4220 | rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F); |
| 4221 | |
| 4222 | /* |
| 4223 | * Enable CCK and OFDM block |
| 4224 | */ |
| 4225 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 4226 | val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM); |
| 4227 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); |
| 4228 | |
| 4229 | /* |
| 4230 | * Invalidate all CAM entries - bit 30 is undocumented |
| 4231 | */ |
| 4232 | rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30)); |
| 4233 | |
| 4234 | /* |
| 4235 | * Start out with default power levels for channel 6, 20MHz |
| 4236 | */ |
| 4237 | rtl8723a_set_tx_power(priv, 1, false); |
| 4238 | |
| 4239 | /* Let the 8051 take control of antenna setting */ |
| 4240 | val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); |
| 4241 | val8 |= LEDCFG2_DPDT_SELECT; |
| 4242 | rtl8xxxu_write8(priv, REG_LEDCFG2, val8); |
| 4243 | |
| 4244 | rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff); |
| 4245 | |
| 4246 | /* Disable BAR - not sure if this has any effect on USB */ |
| 4247 | rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff); |
| 4248 | |
| 4249 | rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0); |
| 4250 | |
| 4251 | /* |
| 4252 | * Not sure if we should get into this at all |
| 4253 | */ |
| 4254 | if (priv->iqk_initialized) { |
| 4255 | rtl8xxxu_restore_regs(priv, rtl8723au_iqk_phy_iq_bb_reg, |
| 4256 | priv->bb_recovery_backup, |
| 4257 | RTL8XXXU_BB_REGS); |
| 4258 | } else { |
| 4259 | rtl8723a_phy_iq_calibrate(priv); |
| 4260 | priv->iqk_initialized = true; |
| 4261 | } |
| 4262 | |
| 4263 | /* |
| 4264 | * This should enable thermal meter |
| 4265 | */ |
| 4266 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60); |
| 4267 | |
| 4268 | rtl8723a_phy_lc_calibrate(priv); |
| 4269 | |
| 4270 | /* fix USB interface interference issue */ |
| 4271 | rtl8xxxu_write8(priv, 0xfe40, 0xe0); |
| 4272 | rtl8xxxu_write8(priv, 0xfe41, 0x8d); |
| 4273 | rtl8xxxu_write8(priv, 0xfe42, 0x80); |
| 4274 | rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320); |
| 4275 | |
| 4276 | /* Solve too many protocol error on USB bus */ |
| 4277 | /* Can't do this for 8188/8192 UMC A cut parts */ |
| 4278 | rtl8xxxu_write8(priv, 0xfe40, 0xe6); |
| 4279 | rtl8xxxu_write8(priv, 0xfe41, 0x94); |
| 4280 | rtl8xxxu_write8(priv, 0xfe42, 0x80); |
| 4281 | |
| 4282 | rtl8xxxu_write8(priv, 0xfe40, 0xe0); |
| 4283 | rtl8xxxu_write8(priv, 0xfe41, 0x19); |
| 4284 | rtl8xxxu_write8(priv, 0xfe42, 0x80); |
| 4285 | |
| 4286 | rtl8xxxu_write8(priv, 0xfe40, 0xe5); |
| 4287 | rtl8xxxu_write8(priv, 0xfe41, 0x91); |
| 4288 | rtl8xxxu_write8(priv, 0xfe42, 0x80); |
| 4289 | |
| 4290 | rtl8xxxu_write8(priv, 0xfe40, 0xe2); |
| 4291 | rtl8xxxu_write8(priv, 0xfe41, 0x81); |
| 4292 | rtl8xxxu_write8(priv, 0xfe42, 0x80); |
| 4293 | |
| 4294 | /* Init BT hw config. */ |
| 4295 | rtl8xxxu_init_bt(priv); |
| 4296 | |
| 4297 | /* |
| 4298 | * Not sure if we really need to save these parameters, but the |
| 4299 | * vendor driver does |
| 4300 | */ |
| 4301 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); |
| 4302 | if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR) |
| 4303 | priv->path_a_hi_power = 1; |
| 4304 | |
| 4305 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); |
| 4306 | priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK; |
| 4307 | |
| 4308 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); |
| 4309 | priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK; |
| 4310 | |
| 4311 | /* Set NAV_UPPER to 30000us */ |
| 4312 | val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT); |
| 4313 | rtl8xxxu_write8(priv, REG_NAV_UPPER, val8); |
| 4314 | |
| 4315 | /* |
| 4316 | * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, |
| 4317 | * but we need to fin root cause. |
| 4318 | */ |
| 4319 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 4320 | if ((val32 & 0xff000000) != 0x83000000) { |
| 4321 | val32 |= FPGA_RF_MODE_CCK; |
| 4322 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); |
| 4323 | } |
| 4324 | |
| 4325 | val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL); |
| 4326 | val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK; |
| 4327 | /* ack for xmit mgmt frames. */ |
| 4328 | rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32); |
| 4329 | |
| 4330 | exit: |
| 4331 | return ret; |
| 4332 | } |
| 4333 | |
| 4334 | static void rtl8xxxu_disable_device(struct ieee80211_hw *hw) |
| 4335 | { |
| 4336 | struct rtl8xxxu_priv *priv = hw->priv; |
| 4337 | |
| 4338 | rtl8xxxu_power_off(priv); |
| 4339 | } |
| 4340 | |
| 4341 | static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv, |
| 4342 | struct ieee80211_key_conf *key, const u8 *mac) |
| 4343 | { |
| 4344 | u32 cmd, val32, addr, ctrl; |
| 4345 | int j, i, tmp_debug; |
| 4346 | |
| 4347 | tmp_debug = rtl8xxxu_debug; |
| 4348 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY) |
| 4349 | rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE; |
| 4350 | |
| 4351 | /* |
| 4352 | * This is a bit of a hack - the lower bits of the cipher |
| 4353 | * suite selector happens to match the cipher index in the CAM |
| 4354 | */ |
| 4355 | addr = key->keyidx << CAM_CMD_KEY_SHIFT; |
| 4356 | ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID; |
| 4357 | |
| 4358 | for (j = 5; j >= 0; j--) { |
| 4359 | switch (j) { |
| 4360 | case 0: |
| 4361 | val32 = ctrl | (mac[0] << 16) | (mac[1] << 24); |
| 4362 | break; |
| 4363 | case 1: |
| 4364 | val32 = mac[2] | (mac[3] << 8) | |
| 4365 | (mac[4] << 16) | (mac[5] << 24); |
| 4366 | break; |
| 4367 | default: |
| 4368 | i = (j - 2) << 2; |
| 4369 | val32 = key->key[i] | (key->key[i + 1] << 8) | |
| 4370 | key->key[i + 2] << 16 | key->key[i + 3] << 24; |
| 4371 | break; |
| 4372 | } |
| 4373 | |
| 4374 | rtl8xxxu_write32(priv, REG_CAM_WRITE, val32); |
| 4375 | cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j); |
| 4376 | rtl8xxxu_write32(priv, REG_CAM_CMD, cmd); |
| 4377 | udelay(100); |
| 4378 | } |
| 4379 | |
| 4380 | rtl8xxxu_debug = tmp_debug; |
| 4381 | } |
| 4382 | |
| 4383 | static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw, |
| 4384 | struct ieee80211_vif *vif, const u8* mac) |
| 4385 | { |
| 4386 | struct rtl8xxxu_priv *priv = hw->priv; |
| 4387 | u8 val8; |
| 4388 | |
| 4389 | val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); |
| 4390 | val8 |= BEACON_DISABLE_TSF_UPDATE; |
| 4391 | rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); |
| 4392 | } |
| 4393 | |
| 4394 | static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw, |
| 4395 | struct ieee80211_vif *vif) |
| 4396 | { |
| 4397 | struct rtl8xxxu_priv *priv = hw->priv; |
| 4398 | u8 val8; |
| 4399 | |
| 4400 | val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); |
| 4401 | val8 &= ~BEACON_DISABLE_TSF_UPDATE; |
| 4402 | rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); |
| 4403 | } |
| 4404 | |
| 4405 | static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, |
| 4406 | u32 ramask, int sgi) |
| 4407 | { |
| 4408 | struct h2c_cmd h2c; |
| 4409 | |
| 4410 | h2c.ramask.cmd = H2C_SET_RATE_MASK; |
| 4411 | h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff); |
| 4412 | h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16); |
| 4413 | |
| 4414 | h2c.ramask.arg = 0x80; |
| 4415 | if (sgi) |
| 4416 | h2c.ramask.arg |= 0x20; |
| 4417 | |
| 4418 | dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x\n", __func__, |
| 4419 | ramask, h2c.ramask.arg); |
| 4420 | rtl8723a_h2c_cmd(priv, &h2c); |
| 4421 | } |
| 4422 | |
| 4423 | static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg) |
| 4424 | { |
| 4425 | u32 val32; |
| 4426 | u8 rate_idx = 0; |
| 4427 | |
| 4428 | rate_cfg &= RESPONSE_RATE_BITMAP_ALL; |
| 4429 | |
| 4430 | val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); |
| 4431 | val32 &= ~RESPONSE_RATE_BITMAP_ALL; |
| 4432 | val32 |= rate_cfg; |
| 4433 | rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); |
| 4434 | |
| 4435 | dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg); |
| 4436 | |
| 4437 | while (rate_cfg) { |
| 4438 | rate_cfg = (rate_cfg >> 1); |
| 4439 | rate_idx++; |
| 4440 | } |
| 4441 | rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx); |
| 4442 | } |
| 4443 | |
| 4444 | static void |
| 4445 | rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 4446 | struct ieee80211_bss_conf *bss_conf, u32 changed) |
| 4447 | { |
| 4448 | struct rtl8xxxu_priv *priv = hw->priv; |
| 4449 | struct device *dev = &priv->udev->dev; |
| 4450 | struct ieee80211_sta *sta; |
| 4451 | u32 val32; |
| 4452 | u8 val8; |
| 4453 | |
| 4454 | if (changed & BSS_CHANGED_ASSOC) { |
| 4455 | struct h2c_cmd h2c; |
| 4456 | |
| 4457 | dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc); |
| 4458 | |
| 4459 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 4460 | rtl8xxxu_set_linktype(priv, vif->type); |
| 4461 | |
| 4462 | if (bss_conf->assoc) { |
| 4463 | u32 ramask; |
| 4464 | int sgi = 0; |
| 4465 | |
| 4466 | rcu_read_lock(); |
| 4467 | sta = ieee80211_find_sta(vif, bss_conf->bssid); |
| 4468 | if (!sta) { |
| 4469 | dev_info(dev, "%s: ASSOC no sta found\n", |
| 4470 | __func__); |
| 4471 | rcu_read_unlock(); |
| 4472 | goto error; |
| 4473 | } |
| 4474 | |
| 4475 | if (sta->ht_cap.ht_supported) |
| 4476 | dev_info(dev, "%s: HT supported\n", __func__); |
| 4477 | if (sta->vht_cap.vht_supported) |
| 4478 | dev_info(dev, "%s: VHT supported\n", __func__); |
| 4479 | |
| 4480 | /* TODO: Set bits 28-31 for rate adaptive id */ |
| 4481 | ramask = (sta->supp_rates[0] & 0xfff) | |
| 4482 | sta->ht_cap.mcs.rx_mask[0] << 12 | |
| 4483 | sta->ht_cap.mcs.rx_mask[1] << 20; |
| 4484 | if (sta->ht_cap.cap & |
| 4485 | (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) |
| 4486 | sgi = 1; |
| 4487 | rcu_read_unlock(); |
| 4488 | |
| 4489 | rtl8xxxu_update_rate_mask(priv, ramask, sgi); |
| 4490 | |
| 4491 | val32 = rtl8xxxu_read32(priv, REG_RCR); |
| 4492 | val32 |= RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON; |
| 4493 | rtl8xxxu_write32(priv, REG_RCR, val32); |
| 4494 | |
| 4495 | /* Enable RX of data frames */ |
| 4496 | rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); |
| 4497 | |
| 4498 | rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff); |
| 4499 | |
| 4500 | rtl8723a_stop_tx_beacon(priv); |
| 4501 | |
| 4502 | /* joinbss sequence */ |
| 4503 | rtl8xxxu_write16(priv, REG_BCN_PSR_RPT, |
| 4504 | 0xc000 | bss_conf->aid); |
| 4505 | |
| 4506 | h2c.joinbss.data = H2C_JOIN_BSS_CONNECT; |
| 4507 | } else { |
| 4508 | val32 = rtl8xxxu_read32(priv, REG_RCR); |
| 4509 | val32 &= ~(RCR_CHECK_BSSID_MATCH | |
| 4510 | RCR_CHECK_BSSID_BEACON); |
| 4511 | rtl8xxxu_write32(priv, REG_RCR, val32); |
| 4512 | |
| 4513 | val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); |
| 4514 | val8 |= BEACON_DISABLE_TSF_UPDATE; |
| 4515 | rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); |
| 4516 | |
| 4517 | /* Disable RX of data frames */ |
| 4518 | rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); |
| 4519 | h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT; |
| 4520 | } |
| 4521 | h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT; |
| 4522 | rtl8723a_h2c_cmd(priv, &h2c); |
| 4523 | } |
| 4524 | |
| 4525 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
| 4526 | dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n", |
| 4527 | bss_conf->use_short_preamble); |
| 4528 | val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); |
| 4529 | if (bss_conf->use_short_preamble) |
| 4530 | val32 |= RSR_ACK_SHORT_PREAMBLE; |
| 4531 | else |
| 4532 | val32 &= ~RSR_ACK_SHORT_PREAMBLE; |
| 4533 | rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); |
| 4534 | } |
| 4535 | |
| 4536 | if (changed & BSS_CHANGED_ERP_SLOT) { |
| 4537 | dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n", |
| 4538 | bss_conf->use_short_slot); |
| 4539 | |
| 4540 | if (bss_conf->use_short_slot) |
| 4541 | val8 = 9; |
| 4542 | else |
| 4543 | val8 = 20; |
| 4544 | rtl8xxxu_write8(priv, REG_SLOT, val8); |
| 4545 | } |
| 4546 | |
| 4547 | if (changed & BSS_CHANGED_BSSID) { |
| 4548 | dev_dbg(dev, "Changed BSSID!\n"); |
| 4549 | rtl8xxxu_set_bssid(priv, bss_conf->bssid); |
| 4550 | } |
| 4551 | |
| 4552 | if (changed & BSS_CHANGED_BASIC_RATES) { |
| 4553 | dev_dbg(dev, "Changed BASIC_RATES!\n"); |
| 4554 | rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates); |
| 4555 | } |
| 4556 | error: |
| 4557 | return; |
| 4558 | } |
| 4559 | |
| 4560 | static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue) |
| 4561 | { |
| 4562 | u32 rtlqueue; |
| 4563 | |
| 4564 | switch (queue) { |
| 4565 | case IEEE80211_AC_VO: |
| 4566 | rtlqueue = TXDESC_QUEUE_VO; |
| 4567 | break; |
| 4568 | case IEEE80211_AC_VI: |
| 4569 | rtlqueue = TXDESC_QUEUE_VI; |
| 4570 | break; |
| 4571 | case IEEE80211_AC_BE: |
| 4572 | rtlqueue = TXDESC_QUEUE_BE; |
| 4573 | break; |
| 4574 | case IEEE80211_AC_BK: |
| 4575 | rtlqueue = TXDESC_QUEUE_BK; |
| 4576 | break; |
| 4577 | default: |
| 4578 | rtlqueue = TXDESC_QUEUE_BE; |
| 4579 | } |
| 4580 | |
| 4581 | return rtlqueue; |
| 4582 | } |
| 4583 | |
| 4584 | static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb) |
| 4585 | { |
| 4586 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
| 4587 | u32 queue; |
| 4588 | |
| 4589 | if (ieee80211_is_mgmt(hdr->frame_control)) |
| 4590 | queue = TXDESC_QUEUE_MGNT; |
| 4591 | else |
| 4592 | queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb)); |
| 4593 | |
| 4594 | return queue; |
| 4595 | } |
| 4596 | |
| 4597 | static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc) |
| 4598 | { |
| 4599 | __le16 *ptr = (__le16 *)tx_desc; |
| 4600 | u16 csum = 0; |
| 4601 | int i; |
| 4602 | |
| 4603 | /* |
| 4604 | * Clear csum field before calculation, as the csum field is |
| 4605 | * in the middle of the struct. |
| 4606 | */ |
| 4607 | tx_desc->csum = cpu_to_le16(0); |
| 4608 | |
| 4609 | for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++) |
| 4610 | csum = csum ^ le16_to_cpu(ptr[i]); |
| 4611 | |
| 4612 | tx_desc->csum |= cpu_to_le16(csum); |
| 4613 | } |
| 4614 | |
| 4615 | static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv) |
| 4616 | { |
| 4617 | struct rtl8xxxu_tx_urb *tx_urb, *tmp; |
| 4618 | unsigned long flags; |
| 4619 | |
| 4620 | spin_lock_irqsave(&priv->tx_urb_lock, flags); |
| 4621 | list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) { |
| 4622 | list_del(&tx_urb->list); |
| 4623 | priv->tx_urb_free_count--; |
| 4624 | usb_free_urb(&tx_urb->urb); |
| 4625 | } |
| 4626 | spin_unlock_irqrestore(&priv->tx_urb_lock, flags); |
| 4627 | } |
| 4628 | |
| 4629 | static struct rtl8xxxu_tx_urb * |
| 4630 | rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv) |
| 4631 | { |
| 4632 | struct rtl8xxxu_tx_urb *tx_urb; |
| 4633 | unsigned long flags; |
| 4634 | |
| 4635 | spin_lock_irqsave(&priv->tx_urb_lock, flags); |
| 4636 | tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list, |
| 4637 | struct rtl8xxxu_tx_urb, list); |
| 4638 | if (tx_urb) { |
| 4639 | list_del(&tx_urb->list); |
| 4640 | priv->tx_urb_free_count--; |
| 4641 | if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER && |
| 4642 | !priv->tx_stopped) { |
| 4643 | priv->tx_stopped = true; |
| 4644 | ieee80211_stop_queues(priv->hw); |
| 4645 | } |
| 4646 | } |
| 4647 | |
| 4648 | spin_unlock_irqrestore(&priv->tx_urb_lock, flags); |
| 4649 | |
| 4650 | return tx_urb; |
| 4651 | } |
| 4652 | |
| 4653 | static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv, |
| 4654 | struct rtl8xxxu_tx_urb *tx_urb) |
| 4655 | { |
| 4656 | unsigned long flags; |
| 4657 | |
| 4658 | INIT_LIST_HEAD(&tx_urb->list); |
| 4659 | |
| 4660 | spin_lock_irqsave(&priv->tx_urb_lock, flags); |
| 4661 | |
| 4662 | list_add(&tx_urb->list, &priv->tx_urb_free_list); |
| 4663 | priv->tx_urb_free_count++; |
| 4664 | if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER && |
| 4665 | priv->tx_stopped) { |
| 4666 | priv->tx_stopped = false; |
| 4667 | ieee80211_wake_queues(priv->hw); |
| 4668 | } |
| 4669 | |
| 4670 | spin_unlock_irqrestore(&priv->tx_urb_lock, flags); |
| 4671 | } |
| 4672 | |
| 4673 | static void rtl8xxxu_tx_complete(struct urb *urb) |
| 4674 | { |
| 4675 | struct sk_buff *skb = (struct sk_buff *)urb->context; |
| 4676 | struct ieee80211_tx_info *tx_info; |
| 4677 | struct ieee80211_hw *hw; |
| 4678 | struct rtl8xxxu_tx_urb *tx_urb = |
| 4679 | container_of(urb, struct rtl8xxxu_tx_urb, urb); |
| 4680 | |
| 4681 | tx_info = IEEE80211_SKB_CB(skb); |
| 4682 | hw = tx_info->rate_driver_data[0]; |
| 4683 | |
| 4684 | skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc)); |
| 4685 | |
| 4686 | ieee80211_tx_info_clear_status(tx_info); |
| 4687 | tx_info->status.rates[0].idx = -1; |
| 4688 | tx_info->status.rates[0].count = 0; |
| 4689 | |
| 4690 | if (!urb->status) |
| 4691 | tx_info->flags |= IEEE80211_TX_STAT_ACK; |
| 4692 | |
| 4693 | ieee80211_tx_status_irqsafe(hw, skb); |
| 4694 | |
| 4695 | rtl8xxxu_free_tx_urb(hw->priv, tx_urb); |
| 4696 | } |
| 4697 | |
| 4698 | static void rtl8xxxu_dump_action(struct device *dev, |
| 4699 | struct ieee80211_hdr *hdr) |
| 4700 | { |
| 4701 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr; |
| 4702 | u16 cap, timeout; |
| 4703 | |
| 4704 | if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION)) |
| 4705 | return; |
| 4706 | |
| 4707 | switch (mgmt->u.action.u.addba_resp.action_code) { |
| 4708 | case WLAN_ACTION_ADDBA_RESP: |
| 4709 | cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab); |
| 4710 | timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout); |
| 4711 | dev_info(dev, "WLAN_ACTION_ADDBA_RESP: " |
| 4712 | "timeout %i, tid %02x, buf_size %02x, policy %02x, " |
| 4713 | "status %02x\n", |
| 4714 | timeout, |
| 4715 | (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, |
| 4716 | (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, |
| 4717 | (cap >> 1) & 0x1, |
| 4718 | le16_to_cpu(mgmt->u.action.u.addba_resp.status)); |
| 4719 | break; |
| 4720 | case WLAN_ACTION_ADDBA_REQ: |
| 4721 | cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab); |
| 4722 | timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout); |
| 4723 | dev_info(dev, "WLAN_ACTION_ADDBA_REQ: " |
| 4724 | "timeout %i, tid %02x, buf_size %02x, policy %02x\n", |
| 4725 | timeout, |
| 4726 | (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, |
| 4727 | (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, |
| 4728 | (cap >> 1) & 0x1); |
| 4729 | break; |
| 4730 | default: |
| 4731 | dev_info(dev, "action frame %02x\n", |
| 4732 | mgmt->u.action.u.addba_resp.action_code); |
| 4733 | break; |
| 4734 | } |
| 4735 | } |
| 4736 | |
| 4737 | static void rtl8xxxu_tx(struct ieee80211_hw *hw, |
| 4738 | struct ieee80211_tx_control *control, |
| 4739 | struct sk_buff *skb) |
| 4740 | { |
| 4741 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
| 4742 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
| 4743 | struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info); |
| 4744 | struct rtl8xxxu_priv *priv = hw->priv; |
| 4745 | struct rtl8xxxu_tx_desc *tx_desc; |
| 4746 | struct rtl8xxxu_tx_urb *tx_urb; |
| 4747 | struct ieee80211_sta *sta = NULL; |
| 4748 | struct ieee80211_vif *vif = tx_info->control.vif; |
| 4749 | struct device *dev = &priv->udev->dev; |
| 4750 | u32 queue, rate; |
| 4751 | u16 pktlen = skb->len; |
| 4752 | u16 seq_number; |
| 4753 | u16 rate_flag = tx_info->control.rates[0].flags; |
| 4754 | int ret; |
| 4755 | |
| 4756 | if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) { |
| 4757 | dev_warn(dev, |
| 4758 | "%s: Not enough headroom (%i) for tx descriptor\n", |
| 4759 | __func__, skb_headroom(skb)); |
| 4760 | goto error; |
| 4761 | } |
| 4762 | |
| 4763 | if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) { |
| 4764 | dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n", |
| 4765 | __func__, skb->len); |
| 4766 | goto error; |
| 4767 | } |
| 4768 | |
| 4769 | tx_urb = rtl8xxxu_alloc_tx_urb(priv); |
| 4770 | if (!tx_urb) { |
| 4771 | dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__); |
| 4772 | goto error; |
| 4773 | } |
| 4774 | |
| 4775 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) |
| 4776 | dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n", |
| 4777 | __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen); |
| 4778 | |
| 4779 | if (ieee80211_is_action(hdr->frame_control)) |
| 4780 | rtl8xxxu_dump_action(dev, hdr); |
| 4781 | |
| 4782 | tx_info->rate_driver_data[0] = hw; |
| 4783 | |
| 4784 | if (control && control->sta) |
| 4785 | sta = control->sta; |
| 4786 | |
| 4787 | tx_desc = (struct rtl8xxxu_tx_desc *) |
| 4788 | skb_push(skb, sizeof(struct rtl8xxxu_tx_desc)); |
| 4789 | |
| 4790 | memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc)); |
| 4791 | tx_desc->pkt_size = cpu_to_le16(pktlen); |
| 4792 | tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc); |
| 4793 | |
| 4794 | tx_desc->txdw0 = |
| 4795 | TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT; |
| 4796 | if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || |
| 4797 | is_broadcast_ether_addr(ieee80211_get_DA(hdr))) |
| 4798 | tx_desc->txdw0 |= TXDESC_BROADMULTICAST; |
| 4799 | |
| 4800 | queue = rtl8xxxu_queue_select(hw, skb); |
| 4801 | tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT); |
| 4802 | |
| 4803 | if (tx_info->control.hw_key) { |
| 4804 | switch (tx_info->control.hw_key->cipher) { |
| 4805 | case WLAN_CIPHER_SUITE_WEP40: |
| 4806 | case WLAN_CIPHER_SUITE_WEP104: |
| 4807 | case WLAN_CIPHER_SUITE_TKIP: |
| 4808 | tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4); |
| 4809 | break; |
| 4810 | case WLAN_CIPHER_SUITE_CCMP: |
| 4811 | tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES); |
| 4812 | break; |
| 4813 | default: |
| 4814 | break; |
| 4815 | } |
| 4816 | } |
| 4817 | |
| 4818 | seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); |
| 4819 | tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT); |
| 4820 | |
| 4821 | if (rate_flag & IEEE80211_TX_RC_MCS) |
| 4822 | rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0; |
| 4823 | else |
| 4824 | rate = tx_rate->hw_value; |
| 4825 | tx_desc->txdw5 = cpu_to_le32(rate); |
| 4826 | |
| 4827 | if (ieee80211_is_data(hdr->frame_control)) |
| 4828 | tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); |
| 4829 | |
| 4830 | /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */ |
| 4831 | if (ieee80211_is_data_qos(hdr->frame_control) && sta) { |
| 4832 | if (sta->ht_cap.ht_supported) { |
| 4833 | u32 ampdu, val32; |
| 4834 | |
| 4835 | ampdu = (u32)sta->ht_cap.ampdu_density; |
| 4836 | val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT; |
| 4837 | tx_desc->txdw2 |= cpu_to_le32(val32); |
| 4838 | tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE); |
| 4839 | } else |
| 4840 | tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK); |
| 4841 | } else |
| 4842 | tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK); |
| 4843 | |
| 4844 | if (ieee80211_is_data_qos(hdr->frame_control)) |
| 4845 | tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS); |
| 4846 | if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE || |
| 4847 | (sta && vif && vif->bss_conf.use_short_preamble)) |
| 4848 | tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE); |
| 4849 | if (rate_flag & IEEE80211_TX_RC_SHORT_GI || |
| 4850 | (ieee80211_is_data_qos(hdr->frame_control) && |
| 4851 | sta && sta->ht_cap.cap & |
| 4852 | (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) { |
| 4853 | tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI); |
| 4854 | } |
| 4855 | if (ieee80211_is_mgmt(hdr->frame_control)) { |
| 4856 | tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value); |
| 4857 | tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE); |
| 4858 | tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT); |
| 4859 | tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE); |
| 4860 | } |
| 4861 | |
| 4862 | if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) { |
| 4863 | /* Use RTS rate 24M - does the mac80211 tell us which to use? */ |
| 4864 | tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M); |
| 4865 | tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE); |
| 4866 | tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE); |
| 4867 | } |
| 4868 | |
| 4869 | rtl8xxxu_calc_tx_desc_csum(tx_desc); |
| 4870 | |
| 4871 | usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue], |
| 4872 | skb->data, skb->len, rtl8xxxu_tx_complete, skb); |
| 4873 | |
| 4874 | usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor); |
| 4875 | ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC); |
| 4876 | if (ret) { |
| 4877 | usb_unanchor_urb(&tx_urb->urb); |
| 4878 | rtl8xxxu_free_tx_urb(priv, tx_urb); |
| 4879 | goto error; |
| 4880 | } |
| 4881 | return; |
| 4882 | error: |
| 4883 | dev_kfree_skb(skb); |
| 4884 | } |
| 4885 | |
| 4886 | static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv, |
| 4887 | struct ieee80211_rx_status *rx_status, |
| 4888 | struct rtl8xxxu_rx_desc *rx_desc, |
| 4889 | struct rtl8723au_phy_stats *phy_stats) |
| 4890 | { |
| 4891 | if (phy_stats->sgi_en) |
| 4892 | rx_status->flag |= RX_FLAG_SHORT_GI; |
| 4893 | |
| 4894 | if (rx_desc->rxmcs < DESC_RATE_6M) { |
| 4895 | /* |
| 4896 | * Handle PHY stats for CCK rates |
| 4897 | */ |
| 4898 | u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; |
| 4899 | |
| 4900 | switch (cck_agc_rpt & 0xc0) { |
| 4901 | case 0xc0: |
| 4902 | rx_status->signal = -46 - (cck_agc_rpt & 0x3e); |
| 4903 | break; |
| 4904 | case 0x80: |
| 4905 | rx_status->signal = -26 - (cck_agc_rpt & 0x3e); |
| 4906 | break; |
| 4907 | case 0x40: |
| 4908 | rx_status->signal = -12 - (cck_agc_rpt & 0x3e); |
| 4909 | break; |
| 4910 | case 0x00: |
| 4911 | rx_status->signal = 16 - (cck_agc_rpt & 0x3e); |
| 4912 | break; |
| 4913 | } |
| 4914 | } else { |
| 4915 | rx_status->signal = |
| 4916 | (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110; |
| 4917 | } |
| 4918 | } |
| 4919 | |
| 4920 | static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv) |
| 4921 | { |
| 4922 | struct rtl8xxxu_rx_urb *rx_urb, *tmp; |
| 4923 | unsigned long flags; |
| 4924 | |
| 4925 | spin_lock_irqsave(&priv->rx_urb_lock, flags); |
| 4926 | |
| 4927 | list_for_each_entry_safe(rx_urb, tmp, |
| 4928 | &priv->rx_urb_pending_list, list) { |
| 4929 | list_del(&rx_urb->list); |
| 4930 | priv->rx_urb_pending_count--; |
| 4931 | usb_free_urb(&rx_urb->urb); |
| 4932 | } |
| 4933 | |
| 4934 | spin_unlock_irqrestore(&priv->rx_urb_lock, flags); |
| 4935 | } |
| 4936 | |
| 4937 | static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv, |
| 4938 | struct rtl8xxxu_rx_urb *rx_urb) |
| 4939 | { |
| 4940 | struct sk_buff *skb; |
| 4941 | unsigned long flags; |
| 4942 | int pending = 0; |
| 4943 | |
| 4944 | spin_lock_irqsave(&priv->rx_urb_lock, flags); |
| 4945 | |
| 4946 | if (!priv->shutdown) { |
| 4947 | list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list); |
| 4948 | priv->rx_urb_pending_count++; |
| 4949 | pending = priv->rx_urb_pending_count; |
| 4950 | } else { |
| 4951 | skb = (struct sk_buff *)rx_urb->urb.context; |
| 4952 | dev_kfree_skb(skb); |
| 4953 | usb_free_urb(&rx_urb->urb); |
| 4954 | } |
| 4955 | |
| 4956 | spin_unlock_irqrestore(&priv->rx_urb_lock, flags); |
| 4957 | |
| 4958 | if (pending > RTL8XXXU_RX_URB_PENDING_WATER) |
| 4959 | schedule_work(&priv->rx_urb_wq); |
| 4960 | } |
| 4961 | |
| 4962 | static void rtl8xxxu_rx_urb_work(struct work_struct *work) |
| 4963 | { |
| 4964 | struct rtl8xxxu_priv *priv; |
| 4965 | struct rtl8xxxu_rx_urb *rx_urb, *tmp; |
| 4966 | struct list_head local; |
| 4967 | struct sk_buff *skb; |
| 4968 | unsigned long flags; |
| 4969 | int ret; |
| 4970 | |
| 4971 | priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq); |
| 4972 | INIT_LIST_HEAD(&local); |
| 4973 | |
| 4974 | spin_lock_irqsave(&priv->rx_urb_lock, flags); |
| 4975 | |
| 4976 | list_splice_init(&priv->rx_urb_pending_list, &local); |
| 4977 | priv->rx_urb_pending_count = 0; |
| 4978 | |
| 4979 | spin_unlock_irqrestore(&priv->rx_urb_lock, flags); |
| 4980 | |
| 4981 | list_for_each_entry_safe(rx_urb, tmp, &local, list) { |
| 4982 | list_del_init(&rx_urb->list); |
| 4983 | ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); |
| 4984 | /* |
| 4985 | * If out of memory or temporary error, put it back on the |
| 4986 | * queue and try again. Otherwise the device is dead/gone |
| 4987 | * and we should drop it. |
| 4988 | */ |
| 4989 | switch (ret) { |
| 4990 | case 0: |
| 4991 | break; |
| 4992 | case -ENOMEM: |
| 4993 | case -EAGAIN: |
| 4994 | rtl8xxxu_queue_rx_urb(priv, rx_urb); |
| 4995 | break; |
| 4996 | default: |
| 4997 | pr_info("failed to requeue urb %i\n", ret); |
| 4998 | skb = (struct sk_buff *)rx_urb->urb.context; |
| 4999 | dev_kfree_skb(skb); |
| 5000 | usb_free_urb(&rx_urb->urb); |
| 5001 | } |
| 5002 | } |
| 5003 | } |
| 5004 | |
| 5005 | static void rtl8xxxu_rx_complete(struct urb *urb) |
| 5006 | { |
| 5007 | struct rtl8xxxu_rx_urb *rx_urb = |
| 5008 | container_of(urb, struct rtl8xxxu_rx_urb, urb); |
| 5009 | struct ieee80211_hw *hw = rx_urb->hw; |
| 5010 | struct rtl8xxxu_priv *priv = hw->priv; |
| 5011 | struct sk_buff *skb = (struct sk_buff *)urb->context; |
| 5012 | struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data; |
| 5013 | struct rtl8723au_phy_stats *phy_stats; |
| 5014 | struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); |
| 5015 | struct ieee80211_mgmt *mgmt; |
| 5016 | struct device *dev = &priv->udev->dev; |
| 5017 | __le32 *_rx_desc_le = (__le32 *)skb->data; |
| 5018 | u32 *_rx_desc = (u32 *)skb->data; |
| 5019 | int cnt, len, drvinfo_sz, desc_shift, i; |
| 5020 | |
| 5021 | for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++) |
| 5022 | _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); |
| 5023 | |
| 5024 | cnt = rx_desc->frag; |
| 5025 | len = rx_desc->pktlen; |
| 5026 | drvinfo_sz = rx_desc->drvinfo_sz * 8; |
| 5027 | desc_shift = rx_desc->shift; |
| 5028 | skb_put(skb, urb->actual_length); |
| 5029 | |
| 5030 | if (urb->status == 0) { |
| 5031 | skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc)); |
| 5032 | phy_stats = (struct rtl8723au_phy_stats *)skb->data; |
| 5033 | |
| 5034 | skb_pull(skb, drvinfo_sz + desc_shift); |
| 5035 | |
| 5036 | mgmt = (struct ieee80211_mgmt *)skb->data; |
| 5037 | |
| 5038 | memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); |
| 5039 | |
| 5040 | if (rx_desc->phy_stats) |
| 5041 | rtl8xxxu_rx_parse_phystats(priv, rx_status, |
| 5042 | rx_desc, phy_stats); |
| 5043 | |
| 5044 | rx_status->freq = hw->conf.chandef.chan->center_freq; |
| 5045 | rx_status->band = hw->conf.chandef.chan->band; |
| 5046 | |
| 5047 | rx_status->mactime = le32_to_cpu(rx_desc->tsfl); |
| 5048 | rx_status->flag |= RX_FLAG_MACTIME_START; |
| 5049 | |
| 5050 | if (!rx_desc->swdec) |
| 5051 | rx_status->flag |= RX_FLAG_DECRYPTED; |
| 5052 | if (rx_desc->crc32) |
| 5053 | rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; |
| 5054 | if (rx_desc->bw) |
| 5055 | rx_status->flag |= RX_FLAG_40MHZ; |
| 5056 | |
| 5057 | if (rx_desc->rxht) { |
| 5058 | rx_status->flag |= RX_FLAG_HT; |
| 5059 | rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; |
| 5060 | } else { |
| 5061 | rx_status->rate_idx = rx_desc->rxmcs; |
| 5062 | } |
| 5063 | |
| 5064 | ieee80211_rx_irqsafe(hw, skb); |
| 5065 | skb = NULL; |
| 5066 | rx_urb->urb.context = NULL; |
| 5067 | rtl8xxxu_queue_rx_urb(priv, rx_urb); |
| 5068 | } else { |
| 5069 | dev_dbg(dev, "%s: status %i\n", __func__, urb->status); |
| 5070 | goto cleanup; |
| 5071 | } |
| 5072 | return; |
| 5073 | |
| 5074 | cleanup: |
| 5075 | usb_free_urb(urb); |
| 5076 | dev_kfree_skb(skb); |
| 5077 | return; |
| 5078 | } |
| 5079 | |
| 5080 | static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, |
| 5081 | struct rtl8xxxu_rx_urb *rx_urb) |
| 5082 | { |
| 5083 | struct sk_buff *skb; |
| 5084 | int skb_size; |
| 5085 | int ret; |
| 5086 | |
| 5087 | skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE; |
| 5088 | skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL); |
| 5089 | if (!skb) |
| 5090 | return -ENOMEM; |
| 5091 | |
| 5092 | memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc)); |
| 5093 | usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data, |
| 5094 | skb_size, rtl8xxxu_rx_complete, skb); |
| 5095 | usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor); |
| 5096 | ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC); |
| 5097 | if (ret) |
| 5098 | usb_unanchor_urb(&rx_urb->urb); |
| 5099 | return ret; |
| 5100 | } |
| 5101 | |
| 5102 | static void rtl8xxxu_int_complete(struct urb *urb) |
| 5103 | { |
| 5104 | struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context; |
| 5105 | struct device *dev = &priv->udev->dev; |
| 5106 | int ret; |
| 5107 | |
| 5108 | dev_dbg(dev, "%s: status %i\n", __func__, urb->status); |
| 5109 | if (urb->status == 0) { |
| 5110 | usb_anchor_urb(urb, &priv->int_anchor); |
| 5111 | ret = usb_submit_urb(urb, GFP_ATOMIC); |
| 5112 | if (ret) |
| 5113 | usb_unanchor_urb(urb); |
| 5114 | } else { |
| 5115 | dev_info(dev, "%s: Error %i\n", __func__, urb->status); |
| 5116 | } |
| 5117 | } |
| 5118 | |
| 5119 | |
| 5120 | static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw) |
| 5121 | { |
| 5122 | struct rtl8xxxu_priv *priv = hw->priv; |
| 5123 | struct urb *urb; |
| 5124 | u32 val32; |
| 5125 | int ret; |
| 5126 | |
| 5127 | urb = usb_alloc_urb(0, GFP_KERNEL); |
| 5128 | if (!urb) |
| 5129 | return -ENOMEM; |
| 5130 | |
| 5131 | usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt, |
| 5132 | priv->int_buf, USB_INTR_CONTENT_LENGTH, |
| 5133 | rtl8xxxu_int_complete, priv, 1); |
| 5134 | usb_anchor_urb(urb, &priv->int_anchor); |
| 5135 | ret = usb_submit_urb(urb, GFP_KERNEL); |
| 5136 | if (ret) { |
| 5137 | usb_unanchor_urb(urb); |
| 5138 | goto error; |
| 5139 | } |
| 5140 | |
| 5141 | val32 = rtl8xxxu_read32(priv, REG_USB_HIMR); |
| 5142 | val32 |= USB_HIMR_CPWM; |
| 5143 | rtl8xxxu_write32(priv, REG_USB_HIMR, val32); |
| 5144 | |
| 5145 | error: |
| 5146 | return ret; |
| 5147 | } |
| 5148 | |
| 5149 | static int rtl8xxxu_add_interface(struct ieee80211_hw *hw, |
| 5150 | struct ieee80211_vif *vif) |
| 5151 | { |
| 5152 | struct rtl8xxxu_priv *priv = hw->priv; |
| 5153 | int ret; |
| 5154 | u8 val8; |
| 5155 | |
| 5156 | switch (vif->type) { |
| 5157 | case NL80211_IFTYPE_STATION: |
| 5158 | rtl8723a_stop_tx_beacon(priv); |
| 5159 | |
| 5160 | val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); |
| 5161 | val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE | |
| 5162 | BEACON_DISABLE_TSF_UPDATE; |
| 5163 | rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); |
| 5164 | ret = 0; |
| 5165 | break; |
| 5166 | default: |
| 5167 | ret = -EOPNOTSUPP; |
| 5168 | } |
| 5169 | |
| 5170 | rtl8xxxu_set_linktype(priv, vif->type); |
| 5171 | |
| 5172 | return ret; |
| 5173 | } |
| 5174 | |
| 5175 | static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw, |
| 5176 | struct ieee80211_vif *vif) |
| 5177 | { |
| 5178 | struct rtl8xxxu_priv *priv = hw->priv; |
| 5179 | |
| 5180 | dev_dbg(&priv->udev->dev, "%s\n", __func__); |
| 5181 | } |
| 5182 | |
| 5183 | static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed) |
| 5184 | { |
| 5185 | struct rtl8xxxu_priv *priv = hw->priv; |
| 5186 | struct device *dev = &priv->udev->dev; |
| 5187 | u16 val16; |
| 5188 | int ret = 0, channel; |
| 5189 | bool ht40; |
| 5190 | |
| 5191 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) |
| 5192 | dev_info(dev, |
| 5193 | "%s: channel: %i (changed %08x chandef.width %02x)\n", |
| 5194 | __func__, hw->conf.chandef.chan->hw_value, |
| 5195 | changed, hw->conf.chandef.width); |
| 5196 | |
| 5197 | if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) { |
| 5198 | val16 = ((hw->conf.long_frame_max_tx_count << |
| 5199 | RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) | |
| 5200 | ((hw->conf.short_frame_max_tx_count << |
| 5201 | RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK); |
| 5202 | rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); |
| 5203 | } |
| 5204 | |
| 5205 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
| 5206 | switch (hw->conf.chandef.width) { |
| 5207 | case NL80211_CHAN_WIDTH_20_NOHT: |
| 5208 | case NL80211_CHAN_WIDTH_20: |
| 5209 | ht40 = false; |
| 5210 | break; |
| 5211 | case NL80211_CHAN_WIDTH_40: |
| 5212 | ht40 = true; |
| 5213 | break; |
| 5214 | default: |
| 5215 | ret = -ENOTSUPP; |
| 5216 | goto exit; |
| 5217 | } |
| 5218 | |
| 5219 | channel = hw->conf.chandef.chan->hw_value; |
| 5220 | |
| 5221 | rtl8723a_set_tx_power(priv, channel, ht40); |
| 5222 | |
| 5223 | rtl8723au_config_channel(hw); |
| 5224 | } |
| 5225 | |
| 5226 | exit: |
| 5227 | return ret; |
| 5228 | } |
| 5229 | |
| 5230 | static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw, |
| 5231 | struct ieee80211_vif *vif, u16 queue, |
| 5232 | const struct ieee80211_tx_queue_params *param) |
| 5233 | { |
| 5234 | struct rtl8xxxu_priv *priv = hw->priv; |
| 5235 | struct device *dev = &priv->udev->dev; |
| 5236 | u32 val32; |
| 5237 | u8 aifs, acm_ctrl, acm_bit; |
| 5238 | |
| 5239 | aifs = param->aifs; |
| 5240 | |
| 5241 | val32 = aifs | |
| 5242 | fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT | |
| 5243 | fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT | |
| 5244 | (u32)param->txop << EDCA_PARAM_TXOP_SHIFT; |
| 5245 | |
| 5246 | acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL); |
| 5247 | dev_dbg(dev, |
| 5248 | "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n", |
| 5249 | __func__, queue, val32, param->acm, acm_ctrl); |
| 5250 | |
| 5251 | switch (queue) { |
| 5252 | case IEEE80211_AC_VO: |
| 5253 | acm_bit = ACM_HW_CTRL_VO; |
| 5254 | rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32); |
| 5255 | break; |
| 5256 | case IEEE80211_AC_VI: |
| 5257 | acm_bit = ACM_HW_CTRL_VI; |
| 5258 | rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32); |
| 5259 | break; |
| 5260 | case IEEE80211_AC_BE: |
| 5261 | acm_bit = ACM_HW_CTRL_BE; |
| 5262 | rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32); |
| 5263 | break; |
| 5264 | case IEEE80211_AC_BK: |
| 5265 | acm_bit = ACM_HW_CTRL_BK; |
| 5266 | rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32); |
| 5267 | break; |
| 5268 | default: |
| 5269 | acm_bit = 0; |
| 5270 | break; |
| 5271 | } |
| 5272 | |
| 5273 | if (param->acm) |
| 5274 | acm_ctrl |= acm_bit; |
| 5275 | else |
| 5276 | acm_ctrl &= ~acm_bit; |
| 5277 | rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl); |
| 5278 | |
| 5279 | return 0; |
| 5280 | } |
| 5281 | |
| 5282 | static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, |
| 5283 | unsigned int changed_flags, |
| 5284 | unsigned int *total_flags, u64 multicast) |
| 5285 | { |
| 5286 | struct rtl8xxxu_priv *priv = hw->priv; |
| 5287 | |
| 5288 | dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n", |
| 5289 | __func__, changed_flags, *total_flags); |
| 5290 | |
| 5291 | *total_flags &= (FIF_ALLMULTI | FIF_CONTROL | FIF_BCN_PRBRESP_PROMISC); |
| 5292 | } |
| 5293 | |
| 5294 | static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts) |
| 5295 | { |
| 5296 | if (rts > 2347) |
| 5297 | return -EINVAL; |
| 5298 | |
| 5299 | return 0; |
| 5300 | } |
| 5301 | |
| 5302 | static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
| 5303 | struct ieee80211_vif *vif, |
| 5304 | struct ieee80211_sta *sta, |
| 5305 | struct ieee80211_key_conf *key) |
| 5306 | { |
| 5307 | struct rtl8xxxu_priv *priv = hw->priv; |
| 5308 | struct device *dev = &priv->udev->dev; |
| 5309 | u8 mac_addr[ETH_ALEN]; |
| 5310 | u8 val8; |
| 5311 | u16 val16; |
| 5312 | u32 val32; |
| 5313 | int retval = -EOPNOTSUPP; |
| 5314 | |
| 5315 | dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n", |
| 5316 | __func__, cmd, key->cipher, key->keyidx); |
| 5317 | |
| 5318 | if (vif->type != NL80211_IFTYPE_STATION) |
| 5319 | return -EOPNOTSUPP; |
| 5320 | |
| 5321 | if (key->keyidx > 3) |
| 5322 | return -EOPNOTSUPP; |
| 5323 | |
| 5324 | switch (key->cipher) { |
| 5325 | case WLAN_CIPHER_SUITE_WEP40: |
| 5326 | case WLAN_CIPHER_SUITE_WEP104: |
| 5327 | |
| 5328 | break; |
| 5329 | case WLAN_CIPHER_SUITE_CCMP: |
| 5330 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; |
| 5331 | break; |
| 5332 | case WLAN_CIPHER_SUITE_TKIP: |
| 5333 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
| 5334 | default: |
| 5335 | return -EOPNOTSUPP; |
| 5336 | } |
| 5337 | |
| 5338 | if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { |
| 5339 | dev_dbg(dev, "%s: pairwise key\n", __func__); |
| 5340 | ether_addr_copy(mac_addr, sta->addr); |
| 5341 | } else { |
| 5342 | dev_dbg(dev, "%s: group key\n", __func__); |
| 5343 | eth_broadcast_addr(mac_addr); |
| 5344 | } |
| 5345 | |
| 5346 | val16 = rtl8xxxu_read16(priv, REG_CR); |
| 5347 | val16 |= CR_SECURITY_ENABLE; |
| 5348 | rtl8xxxu_write16(priv, REG_CR, val16); |
| 5349 | |
| 5350 | val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY | |
| 5351 | SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY; |
| 5352 | val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY; |
| 5353 | rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8); |
| 5354 | |
| 5355 | switch (cmd) { |
| 5356 | case SET_KEY: |
| 5357 | key->hw_key_idx = key->keyidx; |
| 5358 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; |
| 5359 | rtl8xxxu_cam_write(priv, key, mac_addr); |
| 5360 | retval = 0; |
| 5361 | break; |
| 5362 | case DISABLE_KEY: |
| 5363 | rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000); |
| 5364 | val32 = CAM_CMD_POLLING | CAM_CMD_WRITE | |
| 5365 | key->keyidx << CAM_CMD_KEY_SHIFT; |
| 5366 | rtl8xxxu_write32(priv, REG_CAM_CMD, val32); |
| 5367 | retval = 0; |
| 5368 | break; |
| 5369 | default: |
| 5370 | dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd); |
| 5371 | } |
| 5372 | |
| 5373 | return retval; |
| 5374 | } |
| 5375 | |
| 5376 | static int |
| 5377 | rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 5378 | enum ieee80211_ampdu_mlme_action action, |
| 5379 | struct ieee80211_sta *sta, u16 tid, u16 *ssn, u8 buf_size, |
| 5380 | bool amsdu) |
| 5381 | { |
| 5382 | struct rtl8xxxu_priv *priv = hw->priv; |
| 5383 | struct device *dev = &priv->udev->dev; |
| 5384 | u8 ampdu_factor, ampdu_density; |
| 5385 | |
| 5386 | switch (action) { |
| 5387 | case IEEE80211_AMPDU_TX_START: |
| 5388 | dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__); |
| 5389 | ampdu_factor = sta->ht_cap.ampdu_factor; |
| 5390 | ampdu_density = sta->ht_cap.ampdu_density; |
| 5391 | rtl8xxxu_set_ampdu_factor(priv, ampdu_factor); |
| 5392 | rtl8xxxu_set_ampdu_min_space(priv, ampdu_density); |
| 5393 | dev_dbg(dev, |
| 5394 | "Changed HT: ampdu_factor %02x, ampdu_density %02x\n", |
| 5395 | ampdu_factor, ampdu_density); |
| 5396 | break; |
| 5397 | case IEEE80211_AMPDU_TX_STOP_FLUSH: |
| 5398 | dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__); |
| 5399 | rtl8xxxu_set_ampdu_factor(priv, 0); |
| 5400 | rtl8xxxu_set_ampdu_min_space(priv, 0); |
| 5401 | break; |
| 5402 | case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: |
| 5403 | dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n", |
| 5404 | __func__); |
| 5405 | rtl8xxxu_set_ampdu_factor(priv, 0); |
| 5406 | rtl8xxxu_set_ampdu_min_space(priv, 0); |
| 5407 | break; |
| 5408 | case IEEE80211_AMPDU_RX_START: |
| 5409 | dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__); |
| 5410 | break; |
| 5411 | case IEEE80211_AMPDU_RX_STOP: |
| 5412 | dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__); |
| 5413 | break; |
| 5414 | default: |
| 5415 | break; |
| 5416 | } |
| 5417 | return 0; |
| 5418 | } |
| 5419 | |
| 5420 | static int rtl8xxxu_start(struct ieee80211_hw *hw) |
| 5421 | { |
| 5422 | struct rtl8xxxu_priv *priv = hw->priv; |
| 5423 | struct rtl8xxxu_rx_urb *rx_urb; |
| 5424 | struct rtl8xxxu_tx_urb *tx_urb; |
| 5425 | unsigned long flags; |
| 5426 | int ret, i; |
| 5427 | |
| 5428 | ret = 0; |
| 5429 | |
| 5430 | init_usb_anchor(&priv->rx_anchor); |
| 5431 | init_usb_anchor(&priv->tx_anchor); |
| 5432 | init_usb_anchor(&priv->int_anchor); |
| 5433 | |
| 5434 | rtl8723a_enable_rf(priv); |
| 5435 | ret = rtl8xxxu_submit_int_urb(hw); |
| 5436 | if (ret) |
| 5437 | goto exit; |
| 5438 | |
| 5439 | for (i = 0; i < RTL8XXXU_TX_URBS; i++) { |
| 5440 | tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL); |
| 5441 | if (!tx_urb) { |
| 5442 | if (!i) |
| 5443 | ret = -ENOMEM; |
| 5444 | |
| 5445 | goto error_out; |
| 5446 | } |
| 5447 | usb_init_urb(&tx_urb->urb); |
| 5448 | INIT_LIST_HEAD(&tx_urb->list); |
| 5449 | tx_urb->hw = hw; |
| 5450 | list_add(&tx_urb->list, &priv->tx_urb_free_list); |
| 5451 | priv->tx_urb_free_count++; |
| 5452 | } |
| 5453 | |
| 5454 | priv->tx_stopped = false; |
| 5455 | |
| 5456 | spin_lock_irqsave(&priv->rx_urb_lock, flags); |
| 5457 | priv->shutdown = false; |
| 5458 | spin_unlock_irqrestore(&priv->rx_urb_lock, flags); |
| 5459 | |
| 5460 | for (i = 0; i < RTL8XXXU_RX_URBS; i++) { |
| 5461 | rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL); |
| 5462 | if (!rx_urb) { |
| 5463 | if (!i) |
| 5464 | ret = -ENOMEM; |
| 5465 | |
| 5466 | goto error_out; |
| 5467 | } |
| 5468 | usb_init_urb(&rx_urb->urb); |
| 5469 | INIT_LIST_HEAD(&rx_urb->list); |
| 5470 | rx_urb->hw = hw; |
| 5471 | |
| 5472 | ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); |
| 5473 | } |
| 5474 | exit: |
| 5475 | /* |
| 5476 | * Disable all data frames |
| 5477 | */ |
| 5478 | rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); |
| 5479 | /* |
| 5480 | * Accept all mgmt frames |
| 5481 | */ |
| 5482 | rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); |
| 5483 | |
| 5484 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e); |
| 5485 | |
| 5486 | return ret; |
| 5487 | |
| 5488 | error_out: |
| 5489 | rtl8xxxu_free_tx_resources(priv); |
| 5490 | /* |
| 5491 | * Disable all data and mgmt frames |
| 5492 | */ |
| 5493 | rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); |
| 5494 | rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); |
| 5495 | |
| 5496 | return ret; |
| 5497 | } |
| 5498 | |
| 5499 | static void rtl8xxxu_stop(struct ieee80211_hw *hw) |
| 5500 | { |
| 5501 | struct rtl8xxxu_priv *priv = hw->priv; |
| 5502 | unsigned long flags; |
| 5503 | |
| 5504 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); |
| 5505 | |
| 5506 | rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); |
| 5507 | rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); |
| 5508 | |
| 5509 | spin_lock_irqsave(&priv->rx_urb_lock, flags); |
| 5510 | priv->shutdown = true; |
| 5511 | spin_unlock_irqrestore(&priv->rx_urb_lock, flags); |
| 5512 | |
| 5513 | usb_kill_anchored_urbs(&priv->rx_anchor); |
| 5514 | usb_kill_anchored_urbs(&priv->tx_anchor); |
| 5515 | usb_kill_anchored_urbs(&priv->int_anchor); |
| 5516 | |
| 5517 | rtl8723a_disable_rf(priv); |
| 5518 | |
| 5519 | /* |
| 5520 | * Disable interrupts |
| 5521 | */ |
| 5522 | rtl8xxxu_write32(priv, REG_USB_HIMR, 0); |
| 5523 | |
| 5524 | rtl8xxxu_free_rx_resources(priv); |
| 5525 | rtl8xxxu_free_tx_resources(priv); |
| 5526 | } |
| 5527 | |
| 5528 | static const struct ieee80211_ops rtl8xxxu_ops = { |
| 5529 | .tx = rtl8xxxu_tx, |
| 5530 | .add_interface = rtl8xxxu_add_interface, |
| 5531 | .remove_interface = rtl8xxxu_remove_interface, |
| 5532 | .config = rtl8xxxu_config, |
| 5533 | .conf_tx = rtl8xxxu_conf_tx, |
| 5534 | .bss_info_changed = rtl8xxxu_bss_info_changed, |
| 5535 | .configure_filter = rtl8xxxu_configure_filter, |
| 5536 | .set_rts_threshold = rtl8xxxu_set_rts_threshold, |
| 5537 | .start = rtl8xxxu_start, |
| 5538 | .stop = rtl8xxxu_stop, |
| 5539 | .sw_scan_start = rtl8xxxu_sw_scan_start, |
| 5540 | .sw_scan_complete = rtl8xxxu_sw_scan_complete, |
| 5541 | .set_key = rtl8xxxu_set_key, |
| 5542 | .ampdu_action = rtl8xxxu_ampdu_action, |
| 5543 | }; |
| 5544 | |
| 5545 | static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv, |
| 5546 | struct usb_interface *interface) |
| 5547 | { |
| 5548 | struct usb_interface_descriptor *interface_desc; |
| 5549 | struct usb_host_interface *host_interface; |
| 5550 | struct usb_endpoint_descriptor *endpoint; |
| 5551 | struct device *dev = &priv->udev->dev; |
| 5552 | int i, j = 0, endpoints; |
| 5553 | u8 dir, xtype, num; |
| 5554 | int ret = 0; |
| 5555 | |
| 5556 | host_interface = &interface->altsetting[0]; |
| 5557 | interface_desc = &host_interface->desc; |
| 5558 | endpoints = interface_desc->bNumEndpoints; |
| 5559 | |
| 5560 | for (i = 0; i < endpoints; i++) { |
| 5561 | endpoint = &host_interface->endpoint[i].desc; |
| 5562 | |
| 5563 | dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK; |
| 5564 | num = usb_endpoint_num(endpoint); |
| 5565 | xtype = usb_endpoint_type(endpoint); |
| 5566 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) |
| 5567 | dev_dbg(dev, |
| 5568 | "%s: endpoint: dir %02x, # %02x, type %02x\n", |
| 5569 | __func__, dir, num, xtype); |
| 5570 | if (usb_endpoint_dir_in(endpoint) && |
| 5571 | usb_endpoint_xfer_bulk(endpoint)) { |
| 5572 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) |
| 5573 | dev_dbg(dev, "%s: in endpoint num %i\n", |
| 5574 | __func__, num); |
| 5575 | |
| 5576 | if (priv->pipe_in) { |
| 5577 | dev_warn(dev, |
| 5578 | "%s: Too many IN pipes\n", __func__); |
| 5579 | ret = -EINVAL; |
| 5580 | goto exit; |
| 5581 | } |
| 5582 | |
| 5583 | priv->pipe_in = usb_rcvbulkpipe(priv->udev, num); |
| 5584 | } |
| 5585 | |
| 5586 | if (usb_endpoint_dir_in(endpoint) && |
| 5587 | usb_endpoint_xfer_int(endpoint)) { |
| 5588 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) |
| 5589 | dev_dbg(dev, "%s: interrupt endpoint num %i\n", |
| 5590 | __func__, num); |
| 5591 | |
| 5592 | if (priv->pipe_interrupt) { |
| 5593 | dev_warn(dev, "%s: Too many INTERRUPT pipes\n", |
| 5594 | __func__); |
| 5595 | ret = -EINVAL; |
| 5596 | goto exit; |
| 5597 | } |
| 5598 | |
| 5599 | priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num); |
| 5600 | } |
| 5601 | |
| 5602 | if (usb_endpoint_dir_out(endpoint) && |
| 5603 | usb_endpoint_xfer_bulk(endpoint)) { |
| 5604 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) |
| 5605 | dev_dbg(dev, "%s: out endpoint num %i\n", |
| 5606 | __func__, num); |
| 5607 | if (j >= RTL8XXXU_OUT_ENDPOINTS) { |
| 5608 | dev_warn(dev, |
| 5609 | "%s: Too many OUT pipes\n", __func__); |
| 5610 | ret = -EINVAL; |
| 5611 | goto exit; |
| 5612 | } |
| 5613 | priv->out_ep[j++] = num; |
| 5614 | } |
| 5615 | } |
| 5616 | exit: |
| 5617 | priv->nr_out_eps = j; |
| 5618 | return ret; |
| 5619 | } |
| 5620 | |
| 5621 | static int rtl8xxxu_probe(struct usb_interface *interface, |
| 5622 | const struct usb_device_id *id) |
| 5623 | { |
| 5624 | struct rtl8xxxu_priv *priv; |
| 5625 | struct ieee80211_hw *hw; |
| 5626 | struct usb_device *udev; |
| 5627 | struct ieee80211_supported_band *sband; |
| 5628 | int ret = 0; |
| 5629 | int untested = 1; |
| 5630 | |
| 5631 | udev = usb_get_dev(interface_to_usbdev(interface)); |
| 5632 | |
| 5633 | switch (id->idVendor) { |
| 5634 | case USB_VENDOR_ID_REALTEK: |
| 5635 | switch(id->idProduct) { |
| 5636 | case 0x1724: |
| 5637 | case 0x8176: |
| 5638 | case 0x8178: |
| 5639 | case 0x817f: |
| 5640 | untested = 0; |
| 5641 | break; |
| 5642 | } |
| 5643 | break; |
| 5644 | case 0x7392: |
| 5645 | if (id->idProduct == 0x7811) |
| 5646 | untested = 0; |
| 5647 | break; |
| 5648 | default: |
| 5649 | break; |
| 5650 | } |
| 5651 | |
| 5652 | if (untested) { |
| 5653 | rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE; |
| 5654 | dev_info(&udev->dev, |
| 5655 | "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n", |
| 5656 | id->idVendor, id->idProduct); |
| 5657 | dev_info(&udev->dev, |
| 5658 | "Please report results to Jes.Sorensen@gmail.com\n"); |
| 5659 | } |
| 5660 | |
| 5661 | hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops); |
| 5662 | if (!hw) { |
| 5663 | ret = -ENOMEM; |
| 5664 | goto exit; |
| 5665 | } |
| 5666 | |
| 5667 | priv = hw->priv; |
| 5668 | priv->hw = hw; |
| 5669 | priv->udev = udev; |
| 5670 | priv->fops = (struct rtl8xxxu_fileops *)id->driver_info; |
| 5671 | mutex_init(&priv->usb_buf_mutex); |
| 5672 | mutex_init(&priv->h2c_mutex); |
| 5673 | INIT_LIST_HEAD(&priv->tx_urb_free_list); |
| 5674 | spin_lock_init(&priv->tx_urb_lock); |
| 5675 | INIT_LIST_HEAD(&priv->rx_urb_pending_list); |
| 5676 | spin_lock_init(&priv->rx_urb_lock); |
| 5677 | INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work); |
| 5678 | |
| 5679 | usb_set_intfdata(interface, hw); |
| 5680 | |
| 5681 | ret = rtl8xxxu_parse_usb(priv, interface); |
| 5682 | if (ret) |
| 5683 | goto exit; |
| 5684 | |
| 5685 | ret = rtl8xxxu_identify_chip(priv); |
| 5686 | if (ret) { |
| 5687 | dev_err(&udev->dev, "Fatal - failed to identify chip\n"); |
| 5688 | goto exit; |
| 5689 | } |
| 5690 | |
| 5691 | ret = rtl8xxxu_read_efuse(priv); |
| 5692 | if (ret) { |
| 5693 | dev_err(&udev->dev, "Fatal - failed to read EFuse\n"); |
| 5694 | goto exit; |
| 5695 | } |
| 5696 | |
| 5697 | ret = priv->fops->parse_efuse(priv); |
| 5698 | if (ret) { |
| 5699 | dev_err(&udev->dev, "Fatal - failed to parse EFuse\n"); |
| 5700 | goto exit; |
| 5701 | } |
| 5702 | |
| 5703 | rtl8xxxu_print_chipinfo(priv); |
| 5704 | |
| 5705 | ret = priv->fops->load_firmware(priv); |
| 5706 | if (ret) { |
| 5707 | dev_err(&udev->dev, "Fatal - failed to load firmware\n"); |
| 5708 | goto exit; |
| 5709 | } |
| 5710 | |
| 5711 | ret = rtl8xxxu_init_device(hw); |
| 5712 | |
| 5713 | hw->wiphy->max_scan_ssids = 1; |
| 5714 | hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; |
| 5715 | hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); |
| 5716 | hw->queues = 4; |
| 5717 | |
| 5718 | sband = &rtl8xxxu_supported_band; |
| 5719 | sband->ht_cap.ht_supported = true; |
| 5720 | sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
| 5721 | sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; |
| 5722 | sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40; |
| 5723 | memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs)); |
| 5724 | sband->ht_cap.mcs.rx_mask[0] = 0xff; |
| 5725 | sband->ht_cap.mcs.rx_mask[4] = 0x01; |
| 5726 | if (priv->rf_paths > 1) { |
| 5727 | sband->ht_cap.mcs.rx_mask[1] = 0xff; |
| 5728 | sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40; |
| 5729 | } |
| 5730 | sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; |
| 5731 | /* |
| 5732 | * Some APs will negotiate HT20_40 in a noisy environment leading |
| 5733 | * to miserable performance. Rather than defaulting to this, only |
| 5734 | * enable it if explicitly requested at module load time. |
| 5735 | */ |
| 5736 | if (rtl8xxxu_ht40_2g) { |
| 5737 | dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n"); |
| 5738 | sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; |
| 5739 | } |
| 5740 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; |
| 5741 | |
| 5742 | hw->wiphy->rts_threshold = 2347; |
| 5743 | |
| 5744 | SET_IEEE80211_DEV(priv->hw, &interface->dev); |
| 5745 | SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr); |
| 5746 | |
| 5747 | hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc); |
| 5748 | ieee80211_hw_set(hw, SIGNAL_DBM); |
| 5749 | /* |
| 5750 | * The firmware handles rate control |
| 5751 | */ |
| 5752 | ieee80211_hw_set(hw, HAS_RATE_CONTROL); |
| 5753 | ieee80211_hw_set(hw, AMPDU_AGGREGATION); |
| 5754 | |
| 5755 | ret = ieee80211_register_hw(priv->hw); |
| 5756 | if (ret) { |
| 5757 | dev_err(&udev->dev, "%s: Failed to register: %i\n", |
| 5758 | __func__, ret); |
| 5759 | goto exit; |
| 5760 | } |
| 5761 | |
| 5762 | exit: |
| 5763 | if (ret < 0) |
| 5764 | usb_put_dev(udev); |
| 5765 | return ret; |
| 5766 | } |
| 5767 | |
| 5768 | static void rtl8xxxu_disconnect(struct usb_interface *interface) |
| 5769 | { |
| 5770 | struct rtl8xxxu_priv *priv; |
| 5771 | struct ieee80211_hw *hw; |
| 5772 | |
| 5773 | hw = usb_get_intfdata(interface); |
| 5774 | priv = hw->priv; |
| 5775 | |
| 5776 | rtl8xxxu_disable_device(hw); |
| 5777 | usb_set_intfdata(interface, NULL); |
| 5778 | |
| 5779 | dev_info(&priv->udev->dev, "disconnecting\n"); |
| 5780 | |
| 5781 | ieee80211_unregister_hw(hw); |
| 5782 | |
| 5783 | kfree(priv->fw_data); |
| 5784 | mutex_destroy(&priv->usb_buf_mutex); |
| 5785 | mutex_destroy(&priv->h2c_mutex); |
| 5786 | |
| 5787 | usb_put_dev(priv->udev); |
| 5788 | ieee80211_free_hw(hw); |
| 5789 | } |
| 5790 | |
| 5791 | static struct rtl8xxxu_fileops rtl8723au_fops = { |
| 5792 | .parse_efuse = rtl8723au_parse_efuse, |
| 5793 | .load_firmware = rtl8723au_load_firmware, |
| 5794 | .power_on = rtl8723au_power_on, |
| 5795 | .writeN_block_size = 1024, |
| 5796 | }; |
| 5797 | |
Kalle Valo | c096377 | 2015-10-25 18:24:38 +0200 | [diff] [blame] | 5798 | #ifdef CONFIG_RTL8XXXU_UNTESTED |
| 5799 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 5800 | static struct rtl8xxxu_fileops rtl8192cu_fops = { |
| 5801 | .parse_efuse = rtl8192cu_parse_efuse, |
| 5802 | .load_firmware = rtl8192cu_load_firmware, |
| 5803 | .power_on = rtl8192cu_power_on, |
| 5804 | .writeN_block_size = 128, |
| 5805 | }; |
| 5806 | |
Kalle Valo | c096377 | 2015-10-25 18:24:38 +0200 | [diff] [blame] | 5807 | #endif |
| 5808 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 5809 | static struct usb_device_id dev_table[] = { |
| 5810 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff), |
| 5811 | .driver_info = (unsigned long)&rtl8723au_fops}, |
| 5812 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff), |
| 5813 | .driver_info = (unsigned long)&rtl8723au_fops}, |
| 5814 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff), |
| 5815 | .driver_info = (unsigned long)&rtl8723au_fops}, |
Kalle Valo | 033695b | 2015-10-23 20:27:58 +0300 | [diff] [blame] | 5816 | #ifdef CONFIG_RTL8XXXU_UNTESTED |
| 5817 | /* Still supported by rtlwifi */ |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 5818 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff), |
| 5819 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5820 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff), |
| 5821 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5822 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff), |
| 5823 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5824 | /* Tested by Larry Finger */ |
| 5825 | {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff), |
| 5826 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 5827 | /* Currently untested 8188 series devices */ |
| 5828 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff), |
| 5829 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5830 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff), |
| 5831 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5832 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff), |
| 5833 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5834 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff), |
| 5835 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5836 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff), |
| 5837 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5838 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff), |
| 5839 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5840 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff), |
| 5841 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5842 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff), |
| 5843 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5844 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff), |
| 5845 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5846 | {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff), |
| 5847 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5848 | {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff), |
| 5849 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5850 | {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff), |
| 5851 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5852 | {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff), |
| 5853 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5854 | {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff), |
| 5855 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5856 | {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff), |
| 5857 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5858 | {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff), |
| 5859 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5860 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff), |
| 5861 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5862 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff), |
| 5863 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5864 | {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff), |
| 5865 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5866 | {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff), |
| 5867 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5868 | {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff), |
| 5869 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5870 | {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff), |
| 5871 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5872 | {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff), |
| 5873 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5874 | {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff), |
| 5875 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5876 | {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff), |
| 5877 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5878 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff), |
| 5879 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5880 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff), |
| 5881 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5882 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff), |
| 5883 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5884 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff), |
| 5885 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5886 | {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff), |
| 5887 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5888 | {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff), |
| 5889 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5890 | {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff), |
| 5891 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5892 | {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff), |
| 5893 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5894 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff), |
| 5895 | .driver_info = (unsigned long)&rtl8192cu_fops}, /* Netcore 8188RU */ |
| 5896 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff), |
| 5897 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5898 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff), |
| 5899 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5900 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff), |
| 5901 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5902 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff), |
| 5903 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5904 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff), |
| 5905 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5906 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff), |
| 5907 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5908 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff), |
| 5909 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5910 | /* Currently untested 8192 series devices */ |
| 5911 | {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff), |
| 5912 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5913 | {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff), |
| 5914 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5915 | {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff), |
| 5916 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5917 | {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff), |
| 5918 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5919 | {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff), |
| 5920 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5921 | {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff), |
| 5922 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5923 | {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff), |
| 5924 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5925 | {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff), |
| 5926 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5927 | {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff), |
| 5928 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5929 | {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff), |
| 5930 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5931 | {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff), |
| 5932 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5933 | {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff), |
| 5934 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5935 | {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff), |
| 5936 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5937 | {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff), |
| 5938 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5939 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff), |
| 5940 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5941 | {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff), |
| 5942 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5943 | {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff), |
| 5944 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5945 | {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff), |
| 5946 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5947 | {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff), |
| 5948 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5949 | {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff), |
| 5950 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5951 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff), |
| 5952 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5953 | {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff), |
| 5954 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5955 | {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff), |
| 5956 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5957 | {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff), |
| 5958 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5959 | {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff), |
| 5960 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 5961 | #endif |
| 5962 | { } |
| 5963 | }; |
| 5964 | |
| 5965 | static struct usb_driver rtl8xxxu_driver = { |
| 5966 | .name = DRIVER_NAME, |
| 5967 | .probe = rtl8xxxu_probe, |
| 5968 | .disconnect = rtl8xxxu_disconnect, |
| 5969 | .id_table = dev_table, |
| 5970 | .disable_hub_initiated_lpm = 1, |
| 5971 | }; |
| 5972 | |
| 5973 | static int __init rtl8xxxu_module_init(void) |
| 5974 | { |
| 5975 | int res; |
| 5976 | |
| 5977 | res = usb_register(&rtl8xxxu_driver); |
| 5978 | if (res < 0) |
| 5979 | pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res); |
| 5980 | |
| 5981 | return res; |
| 5982 | } |
| 5983 | |
| 5984 | static void __exit rtl8xxxu_module_exit(void) |
| 5985 | { |
| 5986 | usb_deregister(&rtl8xxxu_driver); |
| 5987 | } |
| 5988 | |
| 5989 | |
| 5990 | MODULE_DEVICE_TABLE(usb, dev_table); |
| 5991 | |
| 5992 | module_init(rtl8xxxu_module_init); |
| 5993 | module_exit(rtl8xxxu_module_exit); |