Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1 | /* |
Ivo van Doorn | 811aa9c | 2008-02-03 15:42:53 +0100 | [diff] [blame] | 2 | Copyright (C) 2004 - 2008 rt2x00 SourceForge Project |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 3 | <http://rt2x00.serialmonkey.com> |
| 4 | |
| 5 | This program is free software; you can redistribute it and/or modify |
| 6 | it under the terms of the GNU General Public License as published by |
| 7 | the Free Software Foundation; either version 2 of the License, or |
| 8 | (at your option) any later version. |
| 9 | |
| 10 | This program is distributed in the hope that it will be useful, |
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | GNU General Public License for more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License |
| 16 | along with this program; if not, write to the |
| 17 | Free Software Foundation, Inc., |
| 18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | Module: rt61pci |
| 23 | Abstract: rt61pci device specific routines. |
| 24 | Supported chipsets: RT2561, RT2561s, RT2661. |
| 25 | */ |
| 26 | |
Ivo van Doorn | a7f3a06 | 2008-03-09 22:44:54 +0100 | [diff] [blame] | 27 | #include <linux/crc-itu-t.h> |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 28 | #include <linux/delay.h> |
| 29 | #include <linux/etherdevice.h> |
| 30 | #include <linux/init.h> |
| 31 | #include <linux/kernel.h> |
| 32 | #include <linux/module.h> |
| 33 | #include <linux/pci.h> |
| 34 | #include <linux/eeprom_93cx6.h> |
| 35 | |
| 36 | #include "rt2x00.h" |
| 37 | #include "rt2x00pci.h" |
| 38 | #include "rt61pci.h" |
| 39 | |
| 40 | /* |
| 41 | * Register access. |
| 42 | * BBP and RF register require indirect register access, |
| 43 | * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this. |
| 44 | * These indirect registers work with busy bits, |
| 45 | * and we will try maximal REGISTER_BUSY_COUNT times to access |
| 46 | * the register while taking a REGISTER_BUSY_DELAY us delay |
| 47 | * between each attampt. When the busy bit is still set at that time, |
| 48 | * the access attempt is considered to have failed, |
| 49 | * and we will print an error. |
| 50 | */ |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 51 | static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 52 | { |
| 53 | u32 reg; |
| 54 | unsigned int i; |
| 55 | |
| 56 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
| 57 | rt2x00pci_register_read(rt2x00dev, PHY_CSR3, ®); |
| 58 | if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY)) |
| 59 | break; |
| 60 | udelay(REGISTER_BUSY_DELAY); |
| 61 | } |
| 62 | |
| 63 | return reg; |
| 64 | } |
| 65 | |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 66 | static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 67 | const unsigned int word, const u8 value) |
| 68 | { |
| 69 | u32 reg; |
| 70 | |
| 71 | /* |
| 72 | * Wait until the BBP becomes ready. |
| 73 | */ |
| 74 | reg = rt61pci_bbp_check(rt2x00dev); |
| 75 | if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) { |
| 76 | ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n"); |
| 77 | return; |
| 78 | } |
| 79 | |
| 80 | /* |
| 81 | * Write the data into the BBP. |
| 82 | */ |
| 83 | reg = 0; |
| 84 | rt2x00_set_field32(®, PHY_CSR3_VALUE, value); |
| 85 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); |
| 86 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); |
| 87 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); |
| 88 | |
| 89 | rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg); |
| 90 | } |
| 91 | |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 92 | static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 93 | const unsigned int word, u8 *value) |
| 94 | { |
| 95 | u32 reg; |
| 96 | |
| 97 | /* |
| 98 | * Wait until the BBP becomes ready. |
| 99 | */ |
| 100 | reg = rt61pci_bbp_check(rt2x00dev); |
| 101 | if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) { |
| 102 | ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n"); |
| 103 | return; |
| 104 | } |
| 105 | |
| 106 | /* |
| 107 | * Write the request into the BBP. |
| 108 | */ |
| 109 | reg = 0; |
| 110 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); |
| 111 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); |
| 112 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); |
| 113 | |
| 114 | rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg); |
| 115 | |
| 116 | /* |
| 117 | * Wait until the BBP becomes ready. |
| 118 | */ |
| 119 | reg = rt61pci_bbp_check(rt2x00dev); |
| 120 | if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) { |
| 121 | ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n"); |
| 122 | *value = 0xff; |
| 123 | return; |
| 124 | } |
| 125 | |
| 126 | *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); |
| 127 | } |
| 128 | |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 129 | static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 130 | const unsigned int word, const u32 value) |
| 131 | { |
| 132 | u32 reg; |
| 133 | unsigned int i; |
| 134 | |
| 135 | if (!word) |
| 136 | return; |
| 137 | |
| 138 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
| 139 | rt2x00pci_register_read(rt2x00dev, PHY_CSR4, ®); |
| 140 | if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY)) |
| 141 | goto rf_write; |
| 142 | udelay(REGISTER_BUSY_DELAY); |
| 143 | } |
| 144 | |
| 145 | ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n"); |
| 146 | return; |
| 147 | |
| 148 | rf_write: |
| 149 | reg = 0; |
| 150 | rt2x00_set_field32(®, PHY_CSR4_VALUE, value); |
| 151 | rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21); |
| 152 | rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); |
| 153 | rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); |
| 154 | |
| 155 | rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg); |
| 156 | rt2x00_rf_write(rt2x00dev, word, value); |
| 157 | } |
| 158 | |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 159 | #ifdef CONFIG_RT61PCI_LEDS |
| 160 | /* |
| 161 | * This function is only called from rt61pci_led_brightness() |
| 162 | * make gcc happy by placing this function inside the |
| 163 | * same ifdef statement as the caller. |
| 164 | */ |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 165 | static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 166 | const u8 command, const u8 token, |
| 167 | const u8 arg0, const u8 arg1) |
| 168 | { |
| 169 | u32 reg; |
| 170 | |
| 171 | rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, ®); |
| 172 | |
| 173 | if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) { |
| 174 | ERROR(rt2x00dev, "mcu request error. " |
| 175 | "Request 0x%02x failed for token 0x%02x.\n", |
| 176 | command, token); |
| 177 | return; |
| 178 | } |
| 179 | |
| 180 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); |
| 181 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); |
| 182 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); |
| 183 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); |
| 184 | rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); |
| 185 | |
| 186 | rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®); |
| 187 | rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); |
| 188 | rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1); |
| 189 | rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg); |
| 190 | } |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 191 | #endif /* CONFIG_RT61PCI_LEDS */ |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 192 | |
| 193 | static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom) |
| 194 | { |
| 195 | struct rt2x00_dev *rt2x00dev = eeprom->data; |
| 196 | u32 reg; |
| 197 | |
| 198 | rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®); |
| 199 | |
| 200 | eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); |
| 201 | eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); |
| 202 | eeprom->reg_data_clock = |
| 203 | !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK); |
| 204 | eeprom->reg_chip_select = |
| 205 | !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT); |
| 206 | } |
| 207 | |
| 208 | static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom) |
| 209 | { |
| 210 | struct rt2x00_dev *rt2x00dev = eeprom->data; |
| 211 | u32 reg = 0; |
| 212 | |
| 213 | rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); |
| 214 | rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); |
| 215 | rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, |
| 216 | !!eeprom->reg_data_clock); |
| 217 | rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT, |
| 218 | !!eeprom->reg_chip_select); |
| 219 | |
| 220 | rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg); |
| 221 | } |
| 222 | |
| 223 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
| 224 | #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) ) |
| 225 | |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 226 | static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 227 | const unsigned int word, u32 *data) |
| 228 | { |
| 229 | rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data); |
| 230 | } |
| 231 | |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 232 | static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 233 | const unsigned int word, u32 data) |
| 234 | { |
| 235 | rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data); |
| 236 | } |
| 237 | |
| 238 | static const struct rt2x00debug rt61pci_rt2x00debug = { |
| 239 | .owner = THIS_MODULE, |
| 240 | .csr = { |
| 241 | .read = rt61pci_read_csr, |
| 242 | .write = rt61pci_write_csr, |
| 243 | .word_size = sizeof(u32), |
| 244 | .word_count = CSR_REG_SIZE / sizeof(u32), |
| 245 | }, |
| 246 | .eeprom = { |
| 247 | .read = rt2x00_eeprom_read, |
| 248 | .write = rt2x00_eeprom_write, |
| 249 | .word_size = sizeof(u16), |
| 250 | .word_count = EEPROM_SIZE / sizeof(u16), |
| 251 | }, |
| 252 | .bbp = { |
| 253 | .read = rt61pci_bbp_read, |
| 254 | .write = rt61pci_bbp_write, |
| 255 | .word_size = sizeof(u8), |
| 256 | .word_count = BBP_SIZE / sizeof(u8), |
| 257 | }, |
| 258 | .rf = { |
| 259 | .read = rt2x00_rf_read, |
| 260 | .write = rt61pci_rf_write, |
| 261 | .word_size = sizeof(u32), |
| 262 | .word_count = RF_SIZE / sizeof(u32), |
| 263 | }, |
| 264 | }; |
| 265 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
| 266 | |
| 267 | #ifdef CONFIG_RT61PCI_RFKILL |
| 268 | static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) |
| 269 | { |
| 270 | u32 reg; |
| 271 | |
| 272 | rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 273 | return rt2x00_get_field32(reg, MAC_CSR13_BIT5); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 274 | } |
Ivo van Doorn | 81873e9 | 2007-10-06 14:14:06 +0200 | [diff] [blame] | 275 | #else |
| 276 | #define rt61pci_rfkill_poll NULL |
Ivo van Doorn | dcf5475 | 2007-09-25 20:57:25 +0200 | [diff] [blame] | 277 | #endif /* CONFIG_RT61PCI_RFKILL */ |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 278 | |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 279 | #ifdef CONFIG_RT61PCI_LEDS |
Ivo van Doorn | a2e1d52 | 2008-03-31 15:53:44 +0200 | [diff] [blame] | 280 | static void rt61pci_brightness_set(struct led_classdev *led_cdev, |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 281 | enum led_brightness brightness) |
| 282 | { |
| 283 | struct rt2x00_led *led = |
| 284 | container_of(led_cdev, struct rt2x00_led, led_dev); |
| 285 | unsigned int enabled = brightness != LED_OFF; |
| 286 | unsigned int a_mode = |
| 287 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); |
| 288 | unsigned int bg_mode = |
| 289 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); |
| 290 | |
| 291 | if (led->type == LED_TYPE_RADIO) { |
| 292 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, |
| 293 | MCU_LEDCS_RADIO_STATUS, enabled); |
| 294 | |
| 295 | rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, |
| 296 | (led->rt2x00dev->led_mcu_reg & 0xff), |
| 297 | ((led->rt2x00dev->led_mcu_reg >> 8))); |
| 298 | } else if (led->type == LED_TYPE_ASSOC) { |
| 299 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, |
| 300 | MCU_LEDCS_LINK_BG_STATUS, bg_mode); |
| 301 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, |
| 302 | MCU_LEDCS_LINK_A_STATUS, a_mode); |
| 303 | |
| 304 | rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, |
| 305 | (led->rt2x00dev->led_mcu_reg & 0xff), |
| 306 | ((led->rt2x00dev->led_mcu_reg >> 8))); |
| 307 | } else if (led->type == LED_TYPE_QUALITY) { |
| 308 | /* |
| 309 | * The brightness is divided into 6 levels (0 - 5), |
| 310 | * this means we need to convert the brightness |
| 311 | * argument into the matching level within that range. |
| 312 | */ |
| 313 | rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, |
| 314 | brightness / (LED_FULL / 6), 0); |
| 315 | } |
| 316 | } |
Ivo van Doorn | a2e1d52 | 2008-03-31 15:53:44 +0200 | [diff] [blame] | 317 | |
| 318 | static int rt61pci_blink_set(struct led_classdev *led_cdev, |
| 319 | unsigned long *delay_on, |
| 320 | unsigned long *delay_off) |
| 321 | { |
| 322 | struct rt2x00_led *led = |
| 323 | container_of(led_cdev, struct rt2x00_led, led_dev); |
| 324 | u32 reg; |
| 325 | |
| 326 | rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, ®); |
| 327 | rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); |
| 328 | rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); |
| 329 | rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg); |
| 330 | |
| 331 | return 0; |
| 332 | } |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 333 | #endif /* CONFIG_RT61PCI_LEDS */ |
| 334 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 335 | /* |
| 336 | * Configuration handlers. |
| 337 | */ |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 338 | static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev, |
| 339 | const unsigned int filter_flags) |
| 340 | { |
| 341 | u32 reg; |
| 342 | |
| 343 | /* |
| 344 | * Start configuration steps. |
| 345 | * Note that the version error will always be dropped |
| 346 | * and broadcast frames will always be accepted since |
| 347 | * there is no filter for it at this time. |
| 348 | */ |
| 349 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); |
| 350 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, |
| 351 | !(filter_flags & FIF_FCSFAIL)); |
| 352 | rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, |
| 353 | !(filter_flags & FIF_PLCPFAIL)); |
| 354 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, |
| 355 | !(filter_flags & FIF_CONTROL)); |
| 356 | rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, |
| 357 | !(filter_flags & FIF_PROMISC_IN_BSS)); |
| 358 | rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, |
Ivo van Doorn | e0b005f | 2008-03-31 15:24:53 +0200 | [diff] [blame] | 359 | !(filter_flags & FIF_PROMISC_IN_BSS) && |
| 360 | !rt2x00dev->intf_ap_count); |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 361 | rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); |
| 362 | rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, |
| 363 | !(filter_flags & FIF_ALLMULTI)); |
| 364 | rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); |
| 365 | rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, |
| 366 | !(filter_flags & FIF_CONTROL)); |
| 367 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); |
| 368 | } |
| 369 | |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 370 | static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev, |
| 371 | struct rt2x00_intf *intf, |
| 372 | struct rt2x00intf_conf *conf, |
| 373 | const unsigned int flags) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 374 | { |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 375 | unsigned int beacon_base; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 376 | u32 reg; |
| 377 | |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 378 | if (flags & CONFIG_UPDATE_TYPE) { |
| 379 | /* |
| 380 | * Clear current synchronisation setup. |
| 381 | * For the Beacon base registers we only need to clear |
| 382 | * the first byte since that byte contains the VALID and OWNER |
| 383 | * bits which (when set to 0) will invalidate the entire beacon. |
| 384 | */ |
| 385 | beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx); |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 386 | rt2x00pci_register_write(rt2x00dev, beacon_base, 0); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 387 | |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 388 | /* |
| 389 | * Enable synchronisation. |
| 390 | */ |
| 391 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); |
Ivo van Doorn | fd3c91c | 2008-03-09 22:47:43 +0100 | [diff] [blame] | 392 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 393 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); |
Ivo van Doorn | fd3c91c | 2008-03-09 22:47:43 +0100 | [diff] [blame] | 394 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 395 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); |
| 396 | } |
| 397 | |
| 398 | if (flags & CONFIG_UPDATE_MAC) { |
| 399 | reg = le32_to_cpu(conf->mac[1]); |
| 400 | rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); |
| 401 | conf->mac[1] = cpu_to_le32(reg); |
| 402 | |
| 403 | rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, |
| 404 | conf->mac, sizeof(conf->mac)); |
| 405 | } |
| 406 | |
| 407 | if (flags & CONFIG_UPDATE_BSSID) { |
| 408 | reg = le32_to_cpu(conf->bssid[1]); |
| 409 | rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); |
| 410 | conf->bssid[1] = cpu_to_le32(reg); |
| 411 | |
| 412 | rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, |
| 413 | conf->bssid, sizeof(conf->bssid)); |
| 414 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 415 | } |
| 416 | |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 417 | static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev, |
| 418 | struct rt2x00lib_erp *erp) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 419 | { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 420 | u32 reg; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 421 | |
| 422 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); |
Ivo van Doorn | 7281037 | 2008-03-09 22:46:18 +0100 | [diff] [blame] | 423 | rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 424 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); |
| 425 | |
| 426 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®); |
Ivo van Doorn | 4f5af6eb | 2007-10-06 14:16:30 +0200 | [diff] [blame] | 427 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, |
Ivo van Doorn | 7281037 | 2008-03-09 22:46:18 +0100 | [diff] [blame] | 428 | !!erp->short_preamble); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 429 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); |
| 430 | } |
| 431 | |
| 432 | static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 433 | const int basic_rate_mask) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 434 | { |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 435 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 436 | } |
| 437 | |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 438 | static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev, |
| 439 | struct rf_channel *rf, const int txpower) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 440 | { |
| 441 | u8 r3; |
| 442 | u8 r94; |
| 443 | u8 smart; |
| 444 | |
| 445 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); |
| 446 | rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); |
| 447 | |
| 448 | smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) || |
| 449 | rt2x00_rf(&rt2x00dev->chip, RF2527)); |
| 450 | |
| 451 | rt61pci_bbp_read(rt2x00dev, 3, &r3); |
| 452 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart); |
| 453 | rt61pci_bbp_write(rt2x00dev, 3, r3); |
| 454 | |
| 455 | r94 = 6; |
| 456 | if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94)) |
| 457 | r94 += txpower - MAX_TXPOWER; |
| 458 | else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94)) |
| 459 | r94 += txpower; |
| 460 | rt61pci_bbp_write(rt2x00dev, 94, r94); |
| 461 | |
| 462 | rt61pci_rf_write(rt2x00dev, 1, rf->rf1); |
| 463 | rt61pci_rf_write(rt2x00dev, 2, rf->rf2); |
| 464 | rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); |
| 465 | rt61pci_rf_write(rt2x00dev, 4, rf->rf4); |
| 466 | |
| 467 | udelay(200); |
| 468 | |
| 469 | rt61pci_rf_write(rt2x00dev, 1, rf->rf1); |
| 470 | rt61pci_rf_write(rt2x00dev, 2, rf->rf2); |
| 471 | rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); |
| 472 | rt61pci_rf_write(rt2x00dev, 4, rf->rf4); |
| 473 | |
| 474 | udelay(200); |
| 475 | |
| 476 | rt61pci_rf_write(rt2x00dev, 1, rf->rf1); |
| 477 | rt61pci_rf_write(rt2x00dev, 2, rf->rf2); |
| 478 | rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); |
| 479 | rt61pci_rf_write(rt2x00dev, 4, rf->rf4); |
| 480 | |
| 481 | msleep(1); |
| 482 | } |
| 483 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 484 | static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev, |
| 485 | const int txpower) |
| 486 | { |
| 487 | struct rf_channel rf; |
| 488 | |
| 489 | rt2x00_rf_read(rt2x00dev, 1, &rf.rf1); |
| 490 | rt2x00_rf_read(rt2x00dev, 2, &rf.rf2); |
| 491 | rt2x00_rf_read(rt2x00dev, 3, &rf.rf3); |
| 492 | rt2x00_rf_read(rt2x00dev, 4, &rf.rf4); |
| 493 | |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 494 | rt61pci_config_channel(rt2x00dev, &rf, txpower); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 495 | } |
| 496 | |
| 497 | static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | addc81bd | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 498 | struct antenna_setup *ant) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 499 | { |
| 500 | u8 r3; |
| 501 | u8 r4; |
| 502 | u8 r77; |
| 503 | |
| 504 | rt61pci_bbp_read(rt2x00dev, 3, &r3); |
| 505 | rt61pci_bbp_read(rt2x00dev, 4, &r4); |
| 506 | rt61pci_bbp_read(rt2x00dev, 77, &r77); |
| 507 | |
| 508 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 509 | rt2x00_rf(&rt2x00dev->chip, RF5325)); |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 510 | |
| 511 | /* |
| 512 | * Configure the RX antenna. |
| 513 | */ |
Ivo van Doorn | addc81bd | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 514 | switch (ant->rx) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 515 | case ANTENNA_HW_DIVERSITY: |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 516 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 517 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 518 | (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 519 | break; |
| 520 | case ANTENNA_A: |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 521 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 522 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 523 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 524 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
| 525 | else |
| 526 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 527 | break; |
| 528 | case ANTENNA_B: |
Ivo van Doorn | a4fe07d | 2008-03-09 22:45:21 +0100 | [diff] [blame] | 529 | default: |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 530 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 531 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 532 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 533 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
| 534 | else |
| 535 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 536 | break; |
| 537 | } |
| 538 | |
| 539 | rt61pci_bbp_write(rt2x00dev, 77, r77); |
| 540 | rt61pci_bbp_write(rt2x00dev, 3, r3); |
| 541 | rt61pci_bbp_write(rt2x00dev, 4, r4); |
| 542 | } |
| 543 | |
| 544 | static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | addc81bd | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 545 | struct antenna_setup *ant) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 546 | { |
| 547 | u8 r3; |
| 548 | u8 r4; |
| 549 | u8 r77; |
| 550 | |
| 551 | rt61pci_bbp_read(rt2x00dev, 3, &r3); |
| 552 | rt61pci_bbp_read(rt2x00dev, 4, &r4); |
| 553 | rt61pci_bbp_read(rt2x00dev, 77, &r77); |
| 554 | |
| 555 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 556 | rt2x00_rf(&rt2x00dev->chip, RF2529)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 557 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, |
| 558 | !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)); |
| 559 | |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 560 | /* |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 561 | * Configure the RX antenna. |
| 562 | */ |
Ivo van Doorn | addc81bd | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 563 | switch (ant->rx) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 564 | case ANTENNA_HW_DIVERSITY: |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 565 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 566 | break; |
| 567 | case ANTENNA_A: |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 568 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
| 569 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 570 | break; |
| 571 | case ANTENNA_B: |
Ivo van Doorn | a4fe07d | 2008-03-09 22:45:21 +0100 | [diff] [blame] | 572 | default: |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 573 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
| 574 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 575 | break; |
| 576 | } |
| 577 | |
| 578 | rt61pci_bbp_write(rt2x00dev, 77, r77); |
| 579 | rt61pci_bbp_write(rt2x00dev, 3, r3); |
| 580 | rt61pci_bbp_write(rt2x00dev, 4, r4); |
| 581 | } |
| 582 | |
| 583 | static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev, |
| 584 | const int p1, const int p2) |
| 585 | { |
| 586 | u32 reg; |
| 587 | |
| 588 | rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®); |
| 589 | |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 590 | rt2x00_set_field32(®, MAC_CSR13_BIT4, p1); |
| 591 | rt2x00_set_field32(®, MAC_CSR13_BIT12, 0); |
| 592 | |
| 593 | rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2); |
| 594 | rt2x00_set_field32(®, MAC_CSR13_BIT11, 0); |
| 595 | |
| 596 | rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 597 | } |
| 598 | |
| 599 | static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | addc81bd | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 600 | struct antenna_setup *ant) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 601 | { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 602 | u8 r3; |
| 603 | u8 r4; |
| 604 | u8 r77; |
| 605 | |
| 606 | rt61pci_bbp_read(rt2x00dev, 3, &r3); |
| 607 | rt61pci_bbp_read(rt2x00dev, 4, &r4); |
| 608 | rt61pci_bbp_read(rt2x00dev, 77, &r77); |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 609 | |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 610 | /* |
| 611 | * Configure the RX antenna. |
| 612 | */ |
| 613 | switch (ant->rx) { |
| 614 | case ANTENNA_A: |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 615 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
| 616 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
| 617 | rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0); |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 618 | break; |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 619 | case ANTENNA_HW_DIVERSITY: |
| 620 | /* |
Ivo van Doorn | a4fe07d | 2008-03-09 22:45:21 +0100 | [diff] [blame] | 621 | * FIXME: Antenna selection for the rf 2529 is very confusing |
| 622 | * in the legacy driver. Just default to antenna B until the |
| 623 | * legacy code can be properly translated into rt2x00 code. |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 624 | */ |
| 625 | case ANTENNA_B: |
Ivo van Doorn | a4fe07d | 2008-03-09 22:45:21 +0100 | [diff] [blame] | 626 | default: |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 627 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
| 628 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
| 629 | rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1); |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 630 | break; |
| 631 | } |
| 632 | |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 633 | rt61pci_bbp_write(rt2x00dev, 77, r77); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 634 | rt61pci_bbp_write(rt2x00dev, 3, r3); |
| 635 | rt61pci_bbp_write(rt2x00dev, 4, r4); |
| 636 | } |
| 637 | |
| 638 | struct antenna_sel { |
| 639 | u8 word; |
| 640 | /* |
| 641 | * value[0] -> non-LNA |
| 642 | * value[1] -> LNA |
| 643 | */ |
| 644 | u8 value[2]; |
| 645 | }; |
| 646 | |
| 647 | static const struct antenna_sel antenna_sel_a[] = { |
| 648 | { 96, { 0x58, 0x78 } }, |
| 649 | { 104, { 0x38, 0x48 } }, |
| 650 | { 75, { 0xfe, 0x80 } }, |
| 651 | { 86, { 0xfe, 0x80 } }, |
| 652 | { 88, { 0xfe, 0x80 } }, |
| 653 | { 35, { 0x60, 0x60 } }, |
| 654 | { 97, { 0x58, 0x58 } }, |
| 655 | { 98, { 0x58, 0x58 } }, |
| 656 | }; |
| 657 | |
| 658 | static const struct antenna_sel antenna_sel_bg[] = { |
| 659 | { 96, { 0x48, 0x68 } }, |
| 660 | { 104, { 0x2c, 0x3c } }, |
| 661 | { 75, { 0xfe, 0x80 } }, |
| 662 | { 86, { 0xfe, 0x80 } }, |
| 663 | { 88, { 0xfe, 0x80 } }, |
| 664 | { 35, { 0x50, 0x50 } }, |
| 665 | { 97, { 0x48, 0x48 } }, |
| 666 | { 98, { 0x48, 0x48 } }, |
| 667 | }; |
| 668 | |
| 669 | static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | addc81bd | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 670 | struct antenna_setup *ant) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 671 | { |
| 672 | const struct antenna_sel *sel; |
| 673 | unsigned int lna; |
| 674 | unsigned int i; |
| 675 | u32 reg; |
| 676 | |
Ivo van Doorn | a4fe07d | 2008-03-09 22:45:21 +0100 | [diff] [blame] | 677 | /* |
| 678 | * We should never come here because rt2x00lib is supposed |
| 679 | * to catch this and send us the correct antenna explicitely. |
| 680 | */ |
| 681 | BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || |
| 682 | ant->tx == ANTENNA_SW_DIVERSITY); |
| 683 | |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 684 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 685 | sel = antenna_sel_a; |
| 686 | lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 687 | } else { |
| 688 | sel = antenna_sel_bg; |
| 689 | lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 690 | } |
| 691 | |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 692 | for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) |
| 693 | rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); |
| 694 | |
| 695 | rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®); |
| 696 | |
Ivo van Doorn | ddc827f | 2007-10-13 16:26:42 +0200 | [diff] [blame] | 697 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 698 | rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); |
Ivo van Doorn | ddc827f | 2007-10-13 16:26:42 +0200 | [diff] [blame] | 699 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 700 | rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); |
Ivo van Doorn | ddc827f | 2007-10-13 16:26:42 +0200 | [diff] [blame] | 701 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 702 | rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg); |
| 703 | |
| 704 | if (rt2x00_rf(&rt2x00dev->chip, RF5225) || |
| 705 | rt2x00_rf(&rt2x00dev->chip, RF5325)) |
Ivo van Doorn | addc81bd | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 706 | rt61pci_config_antenna_5x(rt2x00dev, ant); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 707 | else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) |
Ivo van Doorn | addc81bd | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 708 | rt61pci_config_antenna_2x(rt2x00dev, ant); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 709 | else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) { |
| 710 | if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) |
Ivo van Doorn | addc81bd | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 711 | rt61pci_config_antenna_2x(rt2x00dev, ant); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 712 | else |
Ivo van Doorn | addc81bd | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 713 | rt61pci_config_antenna_2529(rt2x00dev, ant); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 714 | } |
| 715 | } |
| 716 | |
| 717 | static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 718 | struct rt2x00lib_conf *libconf) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 719 | { |
| 720 | u32 reg; |
| 721 | |
| 722 | rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®); |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 723 | rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, libconf->slot_time); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 724 | rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg); |
| 725 | |
| 726 | rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®); |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 727 | rt2x00_set_field32(®, MAC_CSR8_SIFS, libconf->sifs); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 728 | rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 729 | rt2x00_set_field32(®, MAC_CSR8_EIFS, libconf->eifs); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 730 | rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg); |
| 731 | |
| 732 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); |
| 733 | rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); |
| 734 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); |
| 735 | |
| 736 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®); |
| 737 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); |
| 738 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); |
| 739 | |
| 740 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 741 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, |
| 742 | libconf->conf->beacon_int * 16); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 743 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); |
| 744 | } |
| 745 | |
| 746 | static void rt61pci_config(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 747 | struct rt2x00lib_conf *libconf, |
| 748 | const unsigned int flags) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 749 | { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 750 | if (flags & CONFIG_UPDATE_PHYMODE) |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 751 | rt61pci_config_phymode(rt2x00dev, libconf->basic_rates); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 752 | if (flags & CONFIG_UPDATE_CHANNEL) |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 753 | rt61pci_config_channel(rt2x00dev, &libconf->rf, |
| 754 | libconf->conf->power_level); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 755 | if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL)) |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 756 | rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 757 | if (flags & CONFIG_UPDATE_ANTENNA) |
Ivo van Doorn | addc81bd | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 758 | rt61pci_config_antenna(rt2x00dev, &libconf->ant); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 759 | if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT)) |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 760 | rt61pci_config_duration(rt2x00dev, libconf); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 761 | } |
| 762 | |
| 763 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 764 | * Link tuning |
| 765 | */ |
Ivo van Doorn | ebcf26d | 2007-10-13 16:26:12 +0200 | [diff] [blame] | 766 | static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev, |
| 767 | struct link_qual *qual) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 768 | { |
| 769 | u32 reg; |
| 770 | |
| 771 | /* |
| 772 | * Update FCS error count from register. |
| 773 | */ |
| 774 | rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®); |
Ivo van Doorn | ebcf26d | 2007-10-13 16:26:12 +0200 | [diff] [blame] | 775 | qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 776 | |
| 777 | /* |
| 778 | * Update False CCA count from register. |
| 779 | */ |
| 780 | rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®); |
Ivo van Doorn | ebcf26d | 2007-10-13 16:26:12 +0200 | [diff] [blame] | 781 | qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 782 | } |
| 783 | |
| 784 | static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev) |
| 785 | { |
| 786 | rt61pci_bbp_write(rt2x00dev, 17, 0x20); |
| 787 | rt2x00dev->link.vgc_level = 0x20; |
| 788 | } |
| 789 | |
| 790 | static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev) |
| 791 | { |
| 792 | int rssi = rt2x00_get_link_rssi(&rt2x00dev->link); |
| 793 | u8 r17; |
| 794 | u8 up_bound; |
| 795 | u8 low_bound; |
| 796 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 797 | rt61pci_bbp_read(rt2x00dev, 17, &r17); |
| 798 | |
| 799 | /* |
| 800 | * Determine r17 bounds. |
| 801 | */ |
Ivo van Doorn | 1497074 | 2008-02-25 23:20:33 +0100 | [diff] [blame] | 802 | if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 803 | low_bound = 0x28; |
| 804 | up_bound = 0x48; |
| 805 | if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) { |
| 806 | low_bound += 0x10; |
| 807 | up_bound += 0x10; |
| 808 | } |
| 809 | } else { |
| 810 | low_bound = 0x20; |
| 811 | up_bound = 0x40; |
| 812 | if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { |
| 813 | low_bound += 0x10; |
| 814 | up_bound += 0x10; |
| 815 | } |
| 816 | } |
| 817 | |
| 818 | /* |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 819 | * If we are not associated, we should go straight to the |
| 820 | * dynamic CCA tuning. |
| 821 | */ |
| 822 | if (!rt2x00dev->intf_associated) |
| 823 | goto dynamic_cca_tune; |
| 824 | |
| 825 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 826 | * Special big-R17 for very short distance |
| 827 | */ |
| 828 | if (rssi >= -35) { |
| 829 | if (r17 != 0x60) |
| 830 | rt61pci_bbp_write(rt2x00dev, 17, 0x60); |
| 831 | return; |
| 832 | } |
| 833 | |
| 834 | /* |
| 835 | * Special big-R17 for short distance |
| 836 | */ |
| 837 | if (rssi >= -58) { |
| 838 | if (r17 != up_bound) |
| 839 | rt61pci_bbp_write(rt2x00dev, 17, up_bound); |
| 840 | return; |
| 841 | } |
| 842 | |
| 843 | /* |
| 844 | * Special big-R17 for middle-short distance |
| 845 | */ |
| 846 | if (rssi >= -66) { |
| 847 | low_bound += 0x10; |
| 848 | if (r17 != low_bound) |
| 849 | rt61pci_bbp_write(rt2x00dev, 17, low_bound); |
| 850 | return; |
| 851 | } |
| 852 | |
| 853 | /* |
| 854 | * Special mid-R17 for middle distance |
| 855 | */ |
| 856 | if (rssi >= -74) { |
| 857 | low_bound += 0x08; |
| 858 | if (r17 != low_bound) |
| 859 | rt61pci_bbp_write(rt2x00dev, 17, low_bound); |
| 860 | return; |
| 861 | } |
| 862 | |
| 863 | /* |
| 864 | * Special case: Change up_bound based on the rssi. |
| 865 | * Lower up_bound when rssi is weaker then -74 dBm. |
| 866 | */ |
| 867 | up_bound -= 2 * (-74 - rssi); |
| 868 | if (low_bound > up_bound) |
| 869 | up_bound = low_bound; |
| 870 | |
| 871 | if (r17 > up_bound) { |
| 872 | rt61pci_bbp_write(rt2x00dev, 17, up_bound); |
| 873 | return; |
| 874 | } |
| 875 | |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 876 | dynamic_cca_tune: |
| 877 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 878 | /* |
| 879 | * r17 does not yet exceed upper limit, continue and base |
| 880 | * the r17 tuning on the false CCA count. |
| 881 | */ |
Ivo van Doorn | ebcf26d | 2007-10-13 16:26:12 +0200 | [diff] [blame] | 882 | if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 883 | if (++r17 > up_bound) |
| 884 | r17 = up_bound; |
| 885 | rt61pci_bbp_write(rt2x00dev, 17, r17); |
Ivo van Doorn | ebcf26d | 2007-10-13 16:26:12 +0200 | [diff] [blame] | 886 | } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 887 | if (--r17 < low_bound) |
| 888 | r17 = low_bound; |
| 889 | rt61pci_bbp_write(rt2x00dev, 17, r17); |
| 890 | } |
| 891 | } |
| 892 | |
| 893 | /* |
Ivo van Doorn | a7f3a06 | 2008-03-09 22:44:54 +0100 | [diff] [blame] | 894 | * Firmware functions |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 895 | */ |
| 896 | static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) |
| 897 | { |
| 898 | char *fw_name; |
| 899 | |
| 900 | switch (rt2x00dev->chip.rt) { |
| 901 | case RT2561: |
| 902 | fw_name = FIRMWARE_RT2561; |
| 903 | break; |
| 904 | case RT2561s: |
| 905 | fw_name = FIRMWARE_RT2561s; |
| 906 | break; |
| 907 | case RT2661: |
| 908 | fw_name = FIRMWARE_RT2661; |
| 909 | break; |
| 910 | default: |
| 911 | fw_name = NULL; |
| 912 | break; |
| 913 | } |
| 914 | |
| 915 | return fw_name; |
| 916 | } |
| 917 | |
Ivo van Doorn | a7f3a06 | 2008-03-09 22:44:54 +0100 | [diff] [blame] | 918 | static u16 rt61pci_get_firmware_crc(void *data, const size_t len) |
| 919 | { |
| 920 | u16 crc; |
| 921 | |
| 922 | /* |
| 923 | * Use the crc itu-t algorithm. |
| 924 | * The last 2 bytes in the firmware array are the crc checksum itself, |
| 925 | * this means that we should never pass those 2 bytes to the crc |
| 926 | * algorithm. |
| 927 | */ |
| 928 | crc = crc_itu_t(0, data, len - 2); |
| 929 | crc = crc_itu_t_byte(crc, 0); |
| 930 | crc = crc_itu_t_byte(crc, 0); |
| 931 | |
| 932 | return crc; |
| 933 | } |
| 934 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 935 | static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data, |
| 936 | const size_t len) |
| 937 | { |
| 938 | int i; |
| 939 | u32 reg; |
| 940 | |
| 941 | /* |
| 942 | * Wait for stable hardware. |
| 943 | */ |
| 944 | for (i = 0; i < 100; i++) { |
| 945 | rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®); |
| 946 | if (reg) |
| 947 | break; |
| 948 | msleep(1); |
| 949 | } |
| 950 | |
| 951 | if (!reg) { |
| 952 | ERROR(rt2x00dev, "Unstable hardware.\n"); |
| 953 | return -EBUSY; |
| 954 | } |
| 955 | |
| 956 | /* |
| 957 | * Prepare MCU and mailbox for firmware loading. |
| 958 | */ |
| 959 | reg = 0; |
| 960 | rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); |
| 961 | rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); |
| 962 | rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); |
| 963 | rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); |
| 964 | rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0); |
| 965 | |
| 966 | /* |
| 967 | * Write firmware to device. |
| 968 | */ |
| 969 | reg = 0; |
| 970 | rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); |
| 971 | rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1); |
| 972 | rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); |
| 973 | |
| 974 | rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, |
| 975 | data, len); |
| 976 | |
| 977 | rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0); |
| 978 | rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); |
| 979 | |
| 980 | rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0); |
| 981 | rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); |
| 982 | |
| 983 | for (i = 0; i < 100; i++) { |
| 984 | rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®); |
| 985 | if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY)) |
| 986 | break; |
| 987 | msleep(1); |
| 988 | } |
| 989 | |
| 990 | if (i == 100) { |
| 991 | ERROR(rt2x00dev, "MCU Control register not ready.\n"); |
| 992 | return -EBUSY; |
| 993 | } |
| 994 | |
| 995 | /* |
| 996 | * Reset MAC and BBP registers. |
| 997 | */ |
| 998 | reg = 0; |
| 999 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); |
| 1000 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); |
| 1001 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); |
| 1002 | |
| 1003 | rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); |
| 1004 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); |
| 1005 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); |
| 1006 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); |
| 1007 | |
| 1008 | rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); |
| 1009 | rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); |
| 1010 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); |
| 1011 | |
| 1012 | return 0; |
| 1013 | } |
| 1014 | |
Ivo van Doorn | a7f3a06 | 2008-03-09 22:44:54 +0100 | [diff] [blame] | 1015 | /* |
| 1016 | * Initialization functions. |
| 1017 | */ |
Ivo van Doorn | 837e7f2 | 2008-01-06 23:41:45 +0100 | [diff] [blame] | 1018 | static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1019 | struct queue_entry *entry) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1020 | { |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1021 | struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1022 | u32 word; |
| 1023 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1024 | rt2x00_desc_read(priv_rx->desc, 5, &word); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 1025 | rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, |
| 1026 | priv_rx->data_dma); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1027 | rt2x00_desc_write(priv_rx->desc, 5, word); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1028 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1029 | rt2x00_desc_read(priv_rx->desc, 0, &word); |
Ivo van Doorn | 837e7f2 | 2008-01-06 23:41:45 +0100 | [diff] [blame] | 1030 | rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1031 | rt2x00_desc_write(priv_rx->desc, 0, word); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1032 | } |
| 1033 | |
Ivo van Doorn | 837e7f2 | 2008-01-06 23:41:45 +0100 | [diff] [blame] | 1034 | static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1035 | struct queue_entry *entry) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1036 | { |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1037 | struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1038 | u32 word; |
| 1039 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1040 | rt2x00_desc_read(priv_tx->desc, 1, &word); |
Ivo van Doorn | 837e7f2 | 2008-01-06 23:41:45 +0100 | [diff] [blame] | 1041 | rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1042 | rt2x00_desc_write(priv_tx->desc, 1, word); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1043 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1044 | rt2x00_desc_read(priv_tx->desc, 5, &word); |
| 1045 | rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid); |
Ivo van Doorn | 837e7f2 | 2008-01-06 23:41:45 +0100 | [diff] [blame] | 1046 | rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1047 | rt2x00_desc_write(priv_tx->desc, 5, word); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1048 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1049 | rt2x00_desc_read(priv_tx->desc, 6, &word); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 1050 | rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, |
| 1051 | priv_tx->data_dma); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1052 | rt2x00_desc_write(priv_tx->desc, 6, word); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1053 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1054 | rt2x00_desc_read(priv_tx->desc, 0, &word); |
Ivo van Doorn | 837e7f2 | 2008-01-06 23:41:45 +0100 | [diff] [blame] | 1055 | rt2x00_set_field32(&word, TXD_W0_VALID, 0); |
| 1056 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1057 | rt2x00_desc_write(priv_tx->desc, 0, word); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1058 | } |
| 1059 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1060 | static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1061 | { |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1062 | struct queue_entry_priv_pci_rx *priv_rx; |
| 1063 | struct queue_entry_priv_pci_tx *priv_tx; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1064 | u32 reg; |
| 1065 | |
| 1066 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1067 | * Initialize registers. |
| 1068 | */ |
| 1069 | rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®); |
| 1070 | rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1071 | rt2x00dev->tx[0].limit); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1072 | rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1073 | rt2x00dev->tx[1].limit); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1074 | rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1075 | rt2x00dev->tx[2].limit); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1076 | rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1077 | rt2x00dev->tx[3].limit); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1078 | rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg); |
| 1079 | |
| 1080 | rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1081 | rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1082 | rt2x00dev->tx[0].desc_size / 4); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1083 | rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg); |
| 1084 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1085 | priv_tx = rt2x00dev->tx[0].entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1086 | rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 1087 | rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER, |
| 1088 | priv_tx->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1089 | rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg); |
| 1090 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1091 | priv_tx = rt2x00dev->tx[1].entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1092 | rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 1093 | rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER, |
| 1094 | priv_tx->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1095 | rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg); |
| 1096 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1097 | priv_tx = rt2x00dev->tx[2].entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1098 | rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 1099 | rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER, |
| 1100 | priv_tx->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1101 | rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg); |
| 1102 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1103 | priv_tx = rt2x00dev->tx[3].entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1104 | rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 1105 | rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER, |
| 1106 | priv_tx->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1107 | rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg); |
| 1108 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1109 | rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1110 | rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1111 | rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE, |
| 1112 | rt2x00dev->rx->desc_size / 4); |
| 1113 | rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); |
| 1114 | rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg); |
| 1115 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1116 | priv_rx = rt2x00dev->rx->entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1117 | rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 1118 | rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER, |
| 1119 | priv_rx->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1120 | rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg); |
| 1121 | |
| 1122 | rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®); |
| 1123 | rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2); |
| 1124 | rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2); |
| 1125 | rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2); |
| 1126 | rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1127 | rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); |
| 1128 | |
| 1129 | rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®); |
| 1130 | rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1); |
| 1131 | rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1); |
| 1132 | rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1); |
| 1133 | rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1134 | rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); |
| 1135 | |
| 1136 | rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®); |
| 1137 | rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1); |
| 1138 | rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg); |
| 1139 | |
| 1140 | return 0; |
| 1141 | } |
| 1142 | |
| 1143 | static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev) |
| 1144 | { |
| 1145 | u32 reg; |
| 1146 | |
| 1147 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); |
| 1148 | rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); |
| 1149 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); |
| 1150 | rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); |
| 1151 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); |
| 1152 | |
| 1153 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®); |
| 1154 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ |
| 1155 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); |
| 1156 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ |
| 1157 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); |
| 1158 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ |
| 1159 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); |
| 1160 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ |
| 1161 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); |
| 1162 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg); |
| 1163 | |
| 1164 | /* |
| 1165 | * CCK TXD BBP registers |
| 1166 | */ |
| 1167 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®); |
| 1168 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); |
| 1169 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); |
| 1170 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); |
| 1171 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); |
| 1172 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); |
| 1173 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); |
| 1174 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); |
| 1175 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); |
| 1176 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg); |
| 1177 | |
| 1178 | /* |
| 1179 | * OFDM TXD BBP registers |
| 1180 | */ |
| 1181 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®); |
| 1182 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); |
| 1183 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); |
| 1184 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); |
| 1185 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); |
| 1186 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); |
| 1187 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); |
| 1188 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg); |
| 1189 | |
| 1190 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®); |
| 1191 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); |
| 1192 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); |
| 1193 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); |
| 1194 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); |
| 1195 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg); |
| 1196 | |
| 1197 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®); |
| 1198 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); |
| 1199 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); |
| 1200 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); |
| 1201 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); |
| 1202 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg); |
| 1203 | |
| 1204 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); |
| 1205 | |
| 1206 | rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff); |
| 1207 | |
| 1208 | rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®); |
| 1209 | rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); |
| 1210 | rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg); |
| 1211 | |
| 1212 | rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c); |
| 1213 | |
| 1214 | if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) |
| 1215 | return -EBUSY; |
| 1216 | |
| 1217 | rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000); |
| 1218 | |
| 1219 | /* |
| 1220 | * Invalidate all Shared Keys (SEC_CSR0), |
| 1221 | * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) |
| 1222 | */ |
| 1223 | rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000); |
| 1224 | rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000); |
| 1225 | rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000); |
| 1226 | |
| 1227 | rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0); |
| 1228 | rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c); |
| 1229 | rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606); |
| 1230 | rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08); |
| 1231 | |
| 1232 | rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404); |
| 1233 | |
| 1234 | rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200); |
| 1235 | |
| 1236 | rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); |
| 1237 | |
| 1238 | rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, ®); |
| 1239 | rt2x00_set_field32(®, AC_TXOP_CSR0_AC0_TX_OP, 0); |
| 1240 | rt2x00_set_field32(®, AC_TXOP_CSR0_AC1_TX_OP, 0); |
| 1241 | rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg); |
| 1242 | |
| 1243 | rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, ®); |
| 1244 | rt2x00_set_field32(®, AC_TXOP_CSR1_AC2_TX_OP, 192); |
| 1245 | rt2x00_set_field32(®, AC_TXOP_CSR1_AC3_TX_OP, 48); |
| 1246 | rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg); |
| 1247 | |
| 1248 | /* |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 1249 | * Clear all beacons |
| 1250 | * For the Beacon base registers we only need to clear |
| 1251 | * the first byte since that byte contains the VALID and OWNER |
| 1252 | * bits which (when set to 0) will invalidate the entire beacon. |
| 1253 | */ |
| 1254 | rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0); |
| 1255 | rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0); |
| 1256 | rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0); |
| 1257 | rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0); |
| 1258 | |
| 1259 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1260 | * We must clear the error counters. |
| 1261 | * These registers are cleared on read, |
| 1262 | * so we may pass a useless variable to store the value. |
| 1263 | */ |
| 1264 | rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®); |
| 1265 | rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®); |
| 1266 | rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®); |
| 1267 | |
| 1268 | /* |
| 1269 | * Reset MAC and BBP registers. |
| 1270 | */ |
| 1271 | rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); |
| 1272 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); |
| 1273 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); |
| 1274 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); |
| 1275 | |
| 1276 | rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); |
| 1277 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); |
| 1278 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); |
| 1279 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); |
| 1280 | |
| 1281 | rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); |
| 1282 | rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); |
| 1283 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); |
| 1284 | |
| 1285 | return 0; |
| 1286 | } |
| 1287 | |
| 1288 | static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev) |
| 1289 | { |
| 1290 | unsigned int i; |
| 1291 | u16 eeprom; |
| 1292 | u8 reg_id; |
| 1293 | u8 value; |
| 1294 | |
| 1295 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
| 1296 | rt61pci_bbp_read(rt2x00dev, 0, &value); |
| 1297 | if ((value != 0xff) && (value != 0x00)) |
| 1298 | goto continue_csr_init; |
| 1299 | NOTICE(rt2x00dev, "Waiting for BBP register.\n"); |
| 1300 | udelay(REGISTER_BUSY_DELAY); |
| 1301 | } |
| 1302 | |
| 1303 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); |
| 1304 | return -EACCES; |
| 1305 | |
| 1306 | continue_csr_init: |
| 1307 | rt61pci_bbp_write(rt2x00dev, 3, 0x00); |
| 1308 | rt61pci_bbp_write(rt2x00dev, 15, 0x30); |
| 1309 | rt61pci_bbp_write(rt2x00dev, 21, 0xc8); |
| 1310 | rt61pci_bbp_write(rt2x00dev, 22, 0x38); |
| 1311 | rt61pci_bbp_write(rt2x00dev, 23, 0x06); |
| 1312 | rt61pci_bbp_write(rt2x00dev, 24, 0xfe); |
| 1313 | rt61pci_bbp_write(rt2x00dev, 25, 0x0a); |
| 1314 | rt61pci_bbp_write(rt2x00dev, 26, 0x0d); |
| 1315 | rt61pci_bbp_write(rt2x00dev, 34, 0x12); |
| 1316 | rt61pci_bbp_write(rt2x00dev, 37, 0x07); |
| 1317 | rt61pci_bbp_write(rt2x00dev, 39, 0xf8); |
| 1318 | rt61pci_bbp_write(rt2x00dev, 41, 0x60); |
| 1319 | rt61pci_bbp_write(rt2x00dev, 53, 0x10); |
| 1320 | rt61pci_bbp_write(rt2x00dev, 54, 0x18); |
| 1321 | rt61pci_bbp_write(rt2x00dev, 60, 0x10); |
| 1322 | rt61pci_bbp_write(rt2x00dev, 61, 0x04); |
| 1323 | rt61pci_bbp_write(rt2x00dev, 62, 0x04); |
| 1324 | rt61pci_bbp_write(rt2x00dev, 75, 0xfe); |
| 1325 | rt61pci_bbp_write(rt2x00dev, 86, 0xfe); |
| 1326 | rt61pci_bbp_write(rt2x00dev, 88, 0xfe); |
| 1327 | rt61pci_bbp_write(rt2x00dev, 90, 0x0f); |
| 1328 | rt61pci_bbp_write(rt2x00dev, 99, 0x00); |
| 1329 | rt61pci_bbp_write(rt2x00dev, 102, 0x16); |
| 1330 | rt61pci_bbp_write(rt2x00dev, 107, 0x04); |
| 1331 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1332 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { |
| 1333 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); |
| 1334 | |
| 1335 | if (eeprom != 0xffff && eeprom != 0x0000) { |
| 1336 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); |
| 1337 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1338 | rt61pci_bbp_write(rt2x00dev, reg_id, value); |
| 1339 | } |
| 1340 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1341 | |
| 1342 | return 0; |
| 1343 | } |
| 1344 | |
| 1345 | /* |
| 1346 | * Device state switch handlers. |
| 1347 | */ |
| 1348 | static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev, |
| 1349 | enum dev_state state) |
| 1350 | { |
| 1351 | u32 reg; |
| 1352 | |
| 1353 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); |
| 1354 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, |
| 1355 | state == STATE_RADIO_RX_OFF); |
| 1356 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); |
| 1357 | } |
| 1358 | |
| 1359 | static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev, |
| 1360 | enum dev_state state) |
| 1361 | { |
| 1362 | int mask = (state == STATE_RADIO_IRQ_OFF); |
| 1363 | u32 reg; |
| 1364 | |
| 1365 | /* |
| 1366 | * When interrupts are being enabled, the interrupt registers |
| 1367 | * should clear the register to assure a clean state. |
| 1368 | */ |
| 1369 | if (state == STATE_RADIO_IRQ_ON) { |
| 1370 | rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®); |
| 1371 | rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); |
| 1372 | |
| 1373 | rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®); |
| 1374 | rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); |
| 1375 | } |
| 1376 | |
| 1377 | /* |
| 1378 | * Only toggle the interrupts bits we are going to use. |
| 1379 | * Non-checked interrupt bits are disabled by default. |
| 1380 | */ |
| 1381 | rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®); |
| 1382 | rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask); |
| 1383 | rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask); |
| 1384 | rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask); |
| 1385 | rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); |
| 1386 | rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); |
| 1387 | |
| 1388 | rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); |
| 1389 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask); |
| 1390 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask); |
| 1391 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask); |
| 1392 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask); |
| 1393 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask); |
| 1394 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask); |
| 1395 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask); |
| 1396 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask); |
| 1397 | rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); |
| 1398 | } |
| 1399 | |
| 1400 | static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev) |
| 1401 | { |
| 1402 | u32 reg; |
| 1403 | |
| 1404 | /* |
| 1405 | * Initialize all registers. |
| 1406 | */ |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1407 | if (rt61pci_init_queues(rt2x00dev) || |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1408 | rt61pci_init_registers(rt2x00dev) || |
| 1409 | rt61pci_init_bbp(rt2x00dev)) { |
| 1410 | ERROR(rt2x00dev, "Register initialization failed.\n"); |
| 1411 | return -EIO; |
| 1412 | } |
| 1413 | |
| 1414 | /* |
| 1415 | * Enable interrupts. |
| 1416 | */ |
| 1417 | rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON); |
| 1418 | |
| 1419 | /* |
| 1420 | * Enable RX. |
| 1421 | */ |
| 1422 | rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®); |
| 1423 | rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1); |
| 1424 | rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg); |
| 1425 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1426 | return 0; |
| 1427 | } |
| 1428 | |
| 1429 | static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev) |
| 1430 | { |
| 1431 | u32 reg; |
| 1432 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1433 | rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818); |
| 1434 | |
| 1435 | /* |
| 1436 | * Disable synchronisation. |
| 1437 | */ |
| 1438 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0); |
| 1439 | |
| 1440 | /* |
| 1441 | * Cancel RX and TX. |
| 1442 | */ |
| 1443 | rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®); |
| 1444 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1); |
| 1445 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1); |
| 1446 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1); |
| 1447 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1448 | rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
| 1449 | |
| 1450 | /* |
| 1451 | * Disable interrupts. |
| 1452 | */ |
| 1453 | rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF); |
| 1454 | } |
| 1455 | |
| 1456 | static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) |
| 1457 | { |
| 1458 | u32 reg; |
| 1459 | unsigned int i; |
| 1460 | char put_to_sleep; |
| 1461 | char current_state; |
| 1462 | |
| 1463 | put_to_sleep = (state != STATE_AWAKE); |
| 1464 | |
| 1465 | rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®); |
| 1466 | rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); |
| 1467 | rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); |
| 1468 | rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg); |
| 1469 | |
| 1470 | /* |
| 1471 | * Device is not guaranteed to be in the requested state yet. |
| 1472 | * We must wait until the register indicates that the |
| 1473 | * device has entered the correct state. |
| 1474 | */ |
| 1475 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
| 1476 | rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®); |
| 1477 | current_state = |
| 1478 | rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE); |
| 1479 | if (current_state == !put_to_sleep) |
| 1480 | return 0; |
| 1481 | msleep(10); |
| 1482 | } |
| 1483 | |
| 1484 | NOTICE(rt2x00dev, "Device failed to enter state %d, " |
| 1485 | "current device state %d.\n", !put_to_sleep, current_state); |
| 1486 | |
| 1487 | return -EBUSY; |
| 1488 | } |
| 1489 | |
| 1490 | static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev, |
| 1491 | enum dev_state state) |
| 1492 | { |
| 1493 | int retval = 0; |
| 1494 | |
| 1495 | switch (state) { |
| 1496 | case STATE_RADIO_ON: |
| 1497 | retval = rt61pci_enable_radio(rt2x00dev); |
| 1498 | break; |
| 1499 | case STATE_RADIO_OFF: |
| 1500 | rt61pci_disable_radio(rt2x00dev); |
| 1501 | break; |
| 1502 | case STATE_RADIO_RX_ON: |
Ivo van Doorn | 61667d8 | 2008-02-25 23:15:05 +0100 | [diff] [blame] | 1503 | case STATE_RADIO_RX_ON_LINK: |
| 1504 | rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON); |
| 1505 | break; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1506 | case STATE_RADIO_RX_OFF: |
Ivo van Doorn | 61667d8 | 2008-02-25 23:15:05 +0100 | [diff] [blame] | 1507 | case STATE_RADIO_RX_OFF_LINK: |
| 1508 | rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1509 | break; |
| 1510 | case STATE_DEEP_SLEEP: |
| 1511 | case STATE_SLEEP: |
| 1512 | case STATE_STANDBY: |
| 1513 | case STATE_AWAKE: |
| 1514 | retval = rt61pci_set_state(rt2x00dev, state); |
| 1515 | break; |
| 1516 | default: |
| 1517 | retval = -ENOTSUPP; |
| 1518 | break; |
| 1519 | } |
| 1520 | |
| 1521 | return retval; |
| 1522 | } |
| 1523 | |
| 1524 | /* |
| 1525 | * TX descriptor initialization |
| 1526 | */ |
| 1527 | static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | dd3193e | 2008-01-06 23:41:10 +0100 | [diff] [blame] | 1528 | struct sk_buff *skb, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1529 | struct txentry_desc *txdesc, |
Ivo van Doorn | dd3193e | 2008-01-06 23:41:10 +0100 | [diff] [blame] | 1530 | struct ieee80211_tx_control *control) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1531 | { |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1532 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); |
Ivo van Doorn | dd3193e | 2008-01-06 23:41:10 +0100 | [diff] [blame] | 1533 | __le32 *txd = skbdesc->desc; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1534 | u32 word; |
| 1535 | |
| 1536 | /* |
| 1537 | * Start writing the descriptor words. |
| 1538 | */ |
| 1539 | rt2x00_desc_read(txd, 1, &word); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1540 | rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue); |
| 1541 | rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs); |
| 1542 | rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min); |
| 1543 | rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1544 | rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER); |
| 1545 | rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1); |
| 1546 | rt2x00_desc_write(txd, 1, word); |
| 1547 | |
| 1548 | rt2x00_desc_read(txd, 2, &word); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1549 | rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal); |
| 1550 | rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service); |
| 1551 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low); |
| 1552 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1553 | rt2x00_desc_write(txd, 2, word); |
| 1554 | |
| 1555 | rt2x00_desc_read(txd, 5, &word); |
| 1556 | rt2x00_set_field32(&word, TXD_W5_TX_POWER, |
Ivo van Doorn | ac1aa7e | 2008-02-17 17:31:48 +0100 | [diff] [blame] | 1557 | TXPOWER_TO_DEV(rt2x00dev->tx_power)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1558 | rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); |
| 1559 | rt2x00_desc_write(txd, 5, word); |
| 1560 | |
Adam Baker | d7bafff | 2008-02-03 15:46:24 +0100 | [diff] [blame] | 1561 | if (skbdesc->desc_len > TXINFO_SIZE) { |
| 1562 | rt2x00_desc_read(txd, 11, &word); |
| 1563 | rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len); |
| 1564 | rt2x00_desc_write(txd, 11, word); |
| 1565 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1566 | |
| 1567 | rt2x00_desc_read(txd, 0, &word); |
| 1568 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); |
| 1569 | rt2x00_set_field32(&word, TXD_W0_VALID, 1); |
| 1570 | rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1571 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1572 | rt2x00_set_field32(&word, TXD_W0_ACK, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1573 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1574 | rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1575 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1576 | rt2x00_set_field32(&word, TXD_W0_OFDM, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1577 | test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags)); |
| 1578 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1579 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
| 1580 | !!(control->flags & |
| 1581 | IEEE80211_TXCTL_LONG_RETRY_LIMIT)); |
| 1582 | rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0); |
Ivo van Doorn | dd3193e | 2008-01-06 23:41:10 +0100 | [diff] [blame] | 1583 | rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1584 | rt2x00_set_field32(&word, TXD_W0_BURST, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1585 | test_bit(ENTRY_TXD_BURST, &txdesc->flags)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1586 | rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); |
| 1587 | rt2x00_desc_write(txd, 0, word); |
| 1588 | } |
| 1589 | |
| 1590 | /* |
| 1591 | * TX data initialization |
| 1592 | */ |
| 1593 | static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 5957da4c | 2008-02-03 15:54:57 +0100 | [diff] [blame] | 1594 | const unsigned int queue) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1595 | { |
| 1596 | u32 reg; |
| 1597 | |
Ivo van Doorn | 5957da4c | 2008-02-03 15:54:57 +0100 | [diff] [blame] | 1598 | if (queue == RT2X00_BCN_QUEUE_BEACON) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1599 | /* |
| 1600 | * For Wi-Fi faily generated beacons between participating |
| 1601 | * stations. Set TBTT phase adaptive adjustment step to 8us. |
| 1602 | */ |
| 1603 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); |
| 1604 | |
| 1605 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); |
| 1606 | if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) { |
Ivo van Doorn | 8af244c | 2008-03-09 22:42:59 +0100 | [diff] [blame] | 1607 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); |
| 1608 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1609 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); |
| 1610 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); |
| 1611 | } |
| 1612 | return; |
| 1613 | } |
| 1614 | |
| 1615 | rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®); |
Ivo van Doorn | ddc827f | 2007-10-13 16:26:42 +0200 | [diff] [blame] | 1616 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, |
| 1617 | (queue == IEEE80211_TX_QUEUE_DATA0)); |
| 1618 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, |
| 1619 | (queue == IEEE80211_TX_QUEUE_DATA1)); |
| 1620 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, |
| 1621 | (queue == IEEE80211_TX_QUEUE_DATA2)); |
| 1622 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, |
| 1623 | (queue == IEEE80211_TX_QUEUE_DATA3)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1624 | rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
| 1625 | } |
| 1626 | |
| 1627 | /* |
| 1628 | * RX control handlers |
| 1629 | */ |
| 1630 | static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1) |
| 1631 | { |
| 1632 | u16 eeprom; |
| 1633 | u8 offset; |
| 1634 | u8 lna; |
| 1635 | |
| 1636 | lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA); |
| 1637 | switch (lna) { |
| 1638 | case 3: |
| 1639 | offset = 90; |
| 1640 | break; |
| 1641 | case 2: |
| 1642 | offset = 74; |
| 1643 | break; |
| 1644 | case 1: |
| 1645 | offset = 64; |
| 1646 | break; |
| 1647 | default: |
| 1648 | return 0; |
| 1649 | } |
| 1650 | |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 1651 | if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1652 | if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) |
| 1653 | offset += 14; |
| 1654 | |
| 1655 | if (lna == 3 || lna == 2) |
| 1656 | offset += 10; |
| 1657 | |
| 1658 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom); |
| 1659 | offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1); |
| 1660 | } else { |
| 1661 | if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) |
| 1662 | offset += 14; |
| 1663 | |
| 1664 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom); |
| 1665 | offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1); |
| 1666 | } |
| 1667 | |
| 1668 | return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset; |
| 1669 | } |
| 1670 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1671 | static void rt61pci_fill_rxdone(struct queue_entry *entry, |
| 1672 | struct rxdone_entry_desc *rxdesc) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1673 | { |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1674 | struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1675 | u32 word0; |
| 1676 | u32 word1; |
| 1677 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1678 | rt2x00_desc_read(priv_rx->desc, 0, &word0); |
| 1679 | rt2x00_desc_read(priv_rx->desc, 1, &word1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1680 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1681 | rxdesc->flags = 0; |
Johannes Berg | 4150c57 | 2007-09-17 01:29:23 -0400 | [diff] [blame] | 1682 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1683 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1684 | |
| 1685 | /* |
| 1686 | * Obtain the status about this packet. |
Ivo van Doorn | 8999389 | 2008-03-09 22:49:04 +0100 | [diff] [blame] | 1687 | * When frame was received with an OFDM bitrate, |
| 1688 | * the signal is the PLCP value. If it was received with |
| 1689 | * a CCK bitrate the signal is the rate in 100kbit/s. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1690 | */ |
Ivo van Doorn | 8999389 | 2008-03-09 22:49:04 +0100 | [diff] [blame] | 1691 | rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL); |
Ivo van Doorn | 8999389 | 2008-03-09 22:49:04 +0100 | [diff] [blame] | 1692 | rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1693 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); |
Ivo van Doorn | 19d30e0 | 2008-03-15 21:38:07 +0100 | [diff] [blame] | 1694 | |
| 1695 | rxdesc->dev_flags = 0; |
| 1696 | if (rt2x00_get_field32(word0, RXD_W0_OFDM)) |
| 1697 | rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; |
| 1698 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) |
| 1699 | rxdesc->dev_flags |= RXDONE_MY_BSS; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1700 | } |
| 1701 | |
| 1702 | /* |
| 1703 | * Interrupt functions. |
| 1704 | */ |
| 1705 | static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev) |
| 1706 | { |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1707 | struct data_queue *queue; |
| 1708 | struct queue_entry *entry; |
| 1709 | struct queue_entry *entry_done; |
| 1710 | struct queue_entry_priv_pci_tx *priv_tx; |
| 1711 | struct txdone_entry_desc txdesc; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1712 | u32 word; |
| 1713 | u32 reg; |
| 1714 | u32 old_reg; |
| 1715 | int type; |
| 1716 | int index; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1717 | |
| 1718 | /* |
| 1719 | * During each loop we will compare the freshly read |
| 1720 | * STA_CSR4 register value with the value read from |
| 1721 | * the previous loop. If the 2 values are equal then |
| 1722 | * we should stop processing because the chance it |
| 1723 | * quite big that the device has been unplugged and |
| 1724 | * we risk going into an endless loop. |
| 1725 | */ |
| 1726 | old_reg = 0; |
| 1727 | |
| 1728 | while (1) { |
| 1729 | rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®); |
| 1730 | if (!rt2x00_get_field32(reg, STA_CSR4_VALID)) |
| 1731 | break; |
| 1732 | |
| 1733 | if (old_reg == reg) |
| 1734 | break; |
| 1735 | old_reg = reg; |
| 1736 | |
| 1737 | /* |
| 1738 | * Skip this entry when it contains an invalid |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1739 | * queue identication number. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1740 | */ |
| 1741 | type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1742 | queue = rt2x00queue_get_queue(rt2x00dev, type); |
| 1743 | if (unlikely(!queue)) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1744 | continue; |
| 1745 | |
| 1746 | /* |
| 1747 | * Skip this entry when it contains an invalid |
| 1748 | * index number. |
| 1749 | */ |
| 1750 | index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1751 | if (unlikely(index >= queue->limit)) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1752 | continue; |
| 1753 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1754 | entry = &queue->entries[index]; |
| 1755 | priv_tx = entry->priv_data; |
| 1756 | rt2x00_desc_read(priv_tx->desc, 0, &word); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1757 | |
| 1758 | if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || |
| 1759 | !rt2x00_get_field32(word, TXD_W0_VALID)) |
| 1760 | return; |
| 1761 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1762 | entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); |
Mattias Nissler | 62bc060 | 2007-11-12 15:03:12 +0100 | [diff] [blame] | 1763 | while (entry != entry_done) { |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1764 | /* Catch up. |
| 1765 | * Just report any entries we missed as failed. |
| 1766 | */ |
Mattias Nissler | 62bc060 | 2007-11-12 15:03:12 +0100 | [diff] [blame] | 1767 | WARNING(rt2x00dev, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1768 | "TX status report missed for entry %d\n", |
| 1769 | entry_done->entry_idx); |
| 1770 | |
| 1771 | txdesc.status = TX_FAIL_OTHER; |
| 1772 | txdesc.retry = 0; |
| 1773 | |
| 1774 | rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc); |
| 1775 | entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); |
Mattias Nissler | 62bc060 | 2007-11-12 15:03:12 +0100 | [diff] [blame] | 1776 | } |
| 1777 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1778 | /* |
| 1779 | * Obtain the status about this packet. |
| 1780 | */ |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1781 | txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT); |
| 1782 | txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1783 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1784 | rt2x00pci_txdone(rt2x00dev, entry, &txdesc); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1785 | } |
| 1786 | } |
| 1787 | |
| 1788 | static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance) |
| 1789 | { |
| 1790 | struct rt2x00_dev *rt2x00dev = dev_instance; |
| 1791 | u32 reg_mcu; |
| 1792 | u32 reg; |
| 1793 | |
| 1794 | /* |
| 1795 | * Get the interrupt sources & saved to local variable. |
| 1796 | * Write register value back to clear pending interrupts. |
| 1797 | */ |
| 1798 | rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu); |
| 1799 | rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu); |
| 1800 | |
| 1801 | rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®); |
| 1802 | rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); |
| 1803 | |
| 1804 | if (!reg && !reg_mcu) |
| 1805 | return IRQ_NONE; |
| 1806 | |
| 1807 | if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags)) |
| 1808 | return IRQ_HANDLED; |
| 1809 | |
| 1810 | /* |
| 1811 | * Handle interrupts, walk through all bits |
| 1812 | * and run the tasks, the bits are checked in order of |
| 1813 | * priority. |
| 1814 | */ |
| 1815 | |
| 1816 | /* |
| 1817 | * 1 - Rx ring done interrupt. |
| 1818 | */ |
| 1819 | if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE)) |
| 1820 | rt2x00pci_rxdone(rt2x00dev); |
| 1821 | |
| 1822 | /* |
| 1823 | * 2 - Tx ring done interrupt. |
| 1824 | */ |
| 1825 | if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE)) |
| 1826 | rt61pci_txdone(rt2x00dev); |
| 1827 | |
| 1828 | /* |
| 1829 | * 3 - Handle MCU command done. |
| 1830 | */ |
| 1831 | if (reg_mcu) |
| 1832 | rt2x00pci_register_write(rt2x00dev, |
| 1833 | M2H_CMD_DONE_CSR, 0xffffffff); |
| 1834 | |
| 1835 | return IRQ_HANDLED; |
| 1836 | } |
| 1837 | |
| 1838 | /* |
| 1839 | * Device probe functions. |
| 1840 | */ |
| 1841 | static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) |
| 1842 | { |
| 1843 | struct eeprom_93cx6 eeprom; |
| 1844 | u32 reg; |
| 1845 | u16 word; |
| 1846 | u8 *mac; |
| 1847 | s8 value; |
| 1848 | |
| 1849 | rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®); |
| 1850 | |
| 1851 | eeprom.data = rt2x00dev; |
| 1852 | eeprom.register_read = rt61pci_eepromregister_read; |
| 1853 | eeprom.register_write = rt61pci_eepromregister_write; |
| 1854 | eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ? |
| 1855 | PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66; |
| 1856 | eeprom.reg_data_in = 0; |
| 1857 | eeprom.reg_data_out = 0; |
| 1858 | eeprom.reg_data_clock = 0; |
| 1859 | eeprom.reg_chip_select = 0; |
| 1860 | |
| 1861 | eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, |
| 1862 | EEPROM_SIZE / sizeof(u16)); |
| 1863 | |
| 1864 | /* |
| 1865 | * Start validation of the data that has been read. |
| 1866 | */ |
| 1867 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); |
| 1868 | if (!is_valid_ether_addr(mac)) { |
Joe Perches | 0795af5 | 2007-10-03 17:59:30 -0700 | [diff] [blame] | 1869 | DECLARE_MAC_BUF(macbuf); |
| 1870 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1871 | random_ether_addr(mac); |
Joe Perches | 0795af5 | 2007-10-03 17:59:30 -0700 | [diff] [blame] | 1872 | EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1873 | } |
| 1874 | |
| 1875 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); |
| 1876 | if (word == 0xffff) { |
| 1877 | rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); |
Ivo van Doorn | 362f3b6 | 2007-10-13 16:26:18 +0200 | [diff] [blame] | 1878 | rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, |
| 1879 | ANTENNA_B); |
| 1880 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, |
| 1881 | ANTENNA_B); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1882 | rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0); |
| 1883 | rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); |
| 1884 | rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); |
| 1885 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225); |
| 1886 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); |
| 1887 | EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); |
| 1888 | } |
| 1889 | |
| 1890 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); |
| 1891 | if (word == 0xffff) { |
| 1892 | rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0); |
| 1893 | rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0); |
| 1894 | rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0); |
| 1895 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0); |
| 1896 | rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); |
| 1897 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0); |
| 1898 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); |
| 1899 | EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); |
| 1900 | } |
| 1901 | |
| 1902 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word); |
| 1903 | if (word == 0xffff) { |
| 1904 | rt2x00_set_field16(&word, EEPROM_LED_LED_MODE, |
| 1905 | LED_MODE_DEFAULT); |
| 1906 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word); |
| 1907 | EEPROM(rt2x00dev, "Led: 0x%04x\n", word); |
| 1908 | } |
| 1909 | |
| 1910 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); |
| 1911 | if (word == 0xffff) { |
| 1912 | rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); |
| 1913 | rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0); |
| 1914 | rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); |
| 1915 | EEPROM(rt2x00dev, "Freq: 0x%04x\n", word); |
| 1916 | } |
| 1917 | |
| 1918 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word); |
| 1919 | if (word == 0xffff) { |
| 1920 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); |
| 1921 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); |
| 1922 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); |
| 1923 | EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); |
| 1924 | } else { |
| 1925 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1); |
| 1926 | if (value < -10 || value > 10) |
| 1927 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); |
| 1928 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2); |
| 1929 | if (value < -10 || value > 10) |
| 1930 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); |
| 1931 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); |
| 1932 | } |
| 1933 | |
| 1934 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word); |
| 1935 | if (word == 0xffff) { |
| 1936 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); |
| 1937 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); |
| 1938 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); |
Ivo van Doorn | 417f412 | 2008-02-10 22:50:58 +0100 | [diff] [blame] | 1939 | EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1940 | } else { |
| 1941 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1); |
| 1942 | if (value < -10 || value > 10) |
| 1943 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); |
| 1944 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2); |
| 1945 | if (value < -10 || value > 10) |
| 1946 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); |
| 1947 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); |
| 1948 | } |
| 1949 | |
| 1950 | return 0; |
| 1951 | } |
| 1952 | |
| 1953 | static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev) |
| 1954 | { |
| 1955 | u32 reg; |
| 1956 | u16 value; |
| 1957 | u16 eeprom; |
| 1958 | u16 device; |
| 1959 | |
| 1960 | /* |
| 1961 | * Read EEPROM word for configuration. |
| 1962 | */ |
| 1963 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); |
| 1964 | |
| 1965 | /* |
| 1966 | * Identify RF chipset. |
| 1967 | * To determine the RT chip we have to read the |
| 1968 | * PCI header of the device. |
| 1969 | */ |
| 1970 | pci_read_config_word(rt2x00dev_pci(rt2x00dev), |
| 1971 | PCI_CONFIG_HEADER_DEVICE, &device); |
| 1972 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); |
| 1973 | rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®); |
| 1974 | rt2x00_set_chip(rt2x00dev, device, value, reg); |
| 1975 | |
| 1976 | if (!rt2x00_rf(&rt2x00dev->chip, RF5225) && |
| 1977 | !rt2x00_rf(&rt2x00dev->chip, RF5325) && |
| 1978 | !rt2x00_rf(&rt2x00dev->chip, RF2527) && |
| 1979 | !rt2x00_rf(&rt2x00dev->chip, RF2529)) { |
| 1980 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); |
| 1981 | return -ENODEV; |
| 1982 | } |
| 1983 | |
| 1984 | /* |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 1985 | * Determine number of antenna's. |
| 1986 | */ |
| 1987 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2) |
| 1988 | __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags); |
| 1989 | |
| 1990 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1991 | * Identify default antenna configuration. |
| 1992 | */ |
Ivo van Doorn | addc81bd | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 1993 | rt2x00dev->default_ant.tx = |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1994 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); |
Ivo van Doorn | addc81bd | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 1995 | rt2x00dev->default_ant.rx = |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1996 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); |
| 1997 | |
| 1998 | /* |
| 1999 | * Read the Frame type. |
| 2000 | */ |
| 2001 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE)) |
| 2002 | __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags); |
| 2003 | |
| 2004 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2005 | * Detect if this device has an hardware controlled radio. |
| 2006 | */ |
Ivo van Doorn | 81873e9 | 2007-10-06 14:14:06 +0200 | [diff] [blame] | 2007 | #ifdef CONFIG_RT61PCI_RFKILL |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2008 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) |
Ivo van Doorn | 066cb63 | 2007-09-25 20:55:39 +0200 | [diff] [blame] | 2009 | __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); |
Ivo van Doorn | 81873e9 | 2007-10-06 14:14:06 +0200 | [diff] [blame] | 2010 | #endif /* CONFIG_RT61PCI_RFKILL */ |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2011 | |
| 2012 | /* |
| 2013 | * Read frequency offset and RF programming sequence. |
| 2014 | */ |
| 2015 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); |
| 2016 | if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ)) |
| 2017 | __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags); |
| 2018 | |
| 2019 | rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); |
| 2020 | |
| 2021 | /* |
| 2022 | * Read external LNA informations. |
| 2023 | */ |
| 2024 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); |
| 2025 | |
| 2026 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A)) |
| 2027 | __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); |
| 2028 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG)) |
| 2029 | __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); |
| 2030 | |
| 2031 | /* |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 2032 | * When working with a RF2529 chip without double antenna |
| 2033 | * the antenna settings should be gathered from the NIC |
| 2034 | * eeprom word. |
| 2035 | */ |
| 2036 | if (rt2x00_rf(&rt2x00dev->chip, RF2529) && |
| 2037 | !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) { |
| 2038 | switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) { |
| 2039 | case 0: |
| 2040 | rt2x00dev->default_ant.tx = ANTENNA_B; |
| 2041 | rt2x00dev->default_ant.rx = ANTENNA_A; |
| 2042 | break; |
| 2043 | case 1: |
| 2044 | rt2x00dev->default_ant.tx = ANTENNA_B; |
| 2045 | rt2x00dev->default_ant.rx = ANTENNA_B; |
| 2046 | break; |
| 2047 | case 2: |
| 2048 | rt2x00dev->default_ant.tx = ANTENNA_A; |
| 2049 | rt2x00dev->default_ant.rx = ANTENNA_A; |
| 2050 | break; |
| 2051 | case 3: |
| 2052 | rt2x00dev->default_ant.tx = ANTENNA_A; |
| 2053 | rt2x00dev->default_ant.rx = ANTENNA_B; |
| 2054 | break; |
| 2055 | } |
| 2056 | |
| 2057 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) |
| 2058 | rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY; |
| 2059 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY)) |
| 2060 | rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY; |
| 2061 | } |
| 2062 | |
| 2063 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2064 | * Store led settings, for correct led behaviour. |
| 2065 | * If the eeprom value is invalid, |
| 2066 | * switch to default led mode. |
| 2067 | */ |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2068 | #ifdef CONFIG_RT61PCI_LEDS |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2069 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2070 | value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2071 | |
Ivo van Doorn | a2e1d52 | 2008-03-31 15:53:44 +0200 | [diff] [blame] | 2072 | rt2x00dev->led_radio.rt2x00dev = rt2x00dev; |
| 2073 | rt2x00dev->led_radio.type = LED_TYPE_RADIO; |
| 2074 | rt2x00dev->led_radio.led_dev.brightness_set = |
| 2075 | rt61pci_brightness_set; |
| 2076 | rt2x00dev->led_radio.led_dev.blink_set = |
| 2077 | rt61pci_blink_set; |
| 2078 | rt2x00dev->led_radio.flags = LED_INITIALIZED; |
| 2079 | |
| 2080 | rt2x00dev->led_assoc.rt2x00dev = rt2x00dev; |
| 2081 | rt2x00dev->led_assoc.type = LED_TYPE_ASSOC; |
| 2082 | rt2x00dev->led_assoc.led_dev.brightness_set = |
| 2083 | rt61pci_brightness_set; |
| 2084 | rt2x00dev->led_assoc.led_dev.blink_set = |
| 2085 | rt61pci_blink_set; |
| 2086 | rt2x00dev->led_assoc.flags = LED_INITIALIZED; |
| 2087 | |
| 2088 | if (value == LED_MODE_SIGNAL_STRENGTH) { |
| 2089 | rt2x00dev->led_qual.rt2x00dev = rt2x00dev; |
Ivo van Doorn | 61c2b68 | 2008-04-21 19:01:09 +0200 | [diff] [blame] | 2090 | rt2x00dev->led_qual.type = LED_TYPE_QUALITY; |
Ivo van Doorn | a2e1d52 | 2008-03-31 15:53:44 +0200 | [diff] [blame] | 2091 | rt2x00dev->led_qual.led_dev.brightness_set = |
| 2092 | rt61pci_brightness_set; |
| 2093 | rt2x00dev->led_qual.led_dev.blink_set = |
| 2094 | rt61pci_blink_set; |
| 2095 | rt2x00dev->led_qual.flags = LED_INITIALIZED; |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2096 | } |
| 2097 | |
| 2098 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); |
| 2099 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2100 | rt2x00_get_field16(eeprom, |
| 2101 | EEPROM_LED_POLARITY_GPIO_0)); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2102 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2103 | rt2x00_get_field16(eeprom, |
| 2104 | EEPROM_LED_POLARITY_GPIO_1)); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2105 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2106 | rt2x00_get_field16(eeprom, |
| 2107 | EEPROM_LED_POLARITY_GPIO_2)); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2108 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2109 | rt2x00_get_field16(eeprom, |
| 2110 | EEPROM_LED_POLARITY_GPIO_3)); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2111 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2112 | rt2x00_get_field16(eeprom, |
| 2113 | EEPROM_LED_POLARITY_GPIO_4)); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2114 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2115 | rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT)); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2116 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2117 | rt2x00_get_field16(eeprom, |
| 2118 | EEPROM_LED_POLARITY_RDY_G)); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2119 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2120 | rt2x00_get_field16(eeprom, |
| 2121 | EEPROM_LED_POLARITY_RDY_A)); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2122 | #endif /* CONFIG_RT61PCI_LEDS */ |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2123 | |
| 2124 | return 0; |
| 2125 | } |
| 2126 | |
| 2127 | /* |
| 2128 | * RF value list for RF5225 & RF5325 |
| 2129 | * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled |
| 2130 | */ |
| 2131 | static const struct rf_channel rf_vals_noseq[] = { |
| 2132 | { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, |
| 2133 | { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, |
| 2134 | { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, |
| 2135 | { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, |
| 2136 | { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, |
| 2137 | { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, |
| 2138 | { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, |
| 2139 | { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, |
| 2140 | { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, |
| 2141 | { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, |
| 2142 | { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, |
| 2143 | { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, |
| 2144 | { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, |
| 2145 | { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, |
| 2146 | |
| 2147 | /* 802.11 UNI / HyperLan 2 */ |
| 2148 | { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 }, |
| 2149 | { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 }, |
| 2150 | { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b }, |
| 2151 | { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 }, |
| 2152 | { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b }, |
| 2153 | { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 }, |
| 2154 | { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 }, |
| 2155 | { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b }, |
| 2156 | |
| 2157 | /* 802.11 HyperLan 2 */ |
| 2158 | { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 }, |
| 2159 | { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b }, |
| 2160 | { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 }, |
| 2161 | { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b }, |
| 2162 | { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 }, |
| 2163 | { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 }, |
| 2164 | { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b }, |
| 2165 | { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 }, |
| 2166 | { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b }, |
| 2167 | { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 }, |
| 2168 | |
| 2169 | /* 802.11 UNII */ |
| 2170 | { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 }, |
| 2171 | { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f }, |
| 2172 | { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 }, |
| 2173 | { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 }, |
| 2174 | { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f }, |
| 2175 | { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 }, |
| 2176 | |
| 2177 | /* MMAC(Japan)J52 ch 34,38,42,46 */ |
| 2178 | { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b }, |
| 2179 | { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 }, |
| 2180 | { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b }, |
| 2181 | { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 }, |
| 2182 | }; |
| 2183 | |
| 2184 | /* |
| 2185 | * RF value list for RF5225 & RF5325 |
| 2186 | * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled |
| 2187 | */ |
| 2188 | static const struct rf_channel rf_vals_seq[] = { |
| 2189 | { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, |
| 2190 | { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, |
| 2191 | { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, |
| 2192 | { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, |
| 2193 | { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, |
| 2194 | { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, |
| 2195 | { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, |
| 2196 | { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, |
| 2197 | { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, |
| 2198 | { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, |
| 2199 | { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, |
| 2200 | { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, |
| 2201 | { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, |
| 2202 | { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, |
| 2203 | |
| 2204 | /* 802.11 UNI / HyperLan 2 */ |
| 2205 | { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 }, |
| 2206 | { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 }, |
| 2207 | { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b }, |
| 2208 | { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b }, |
| 2209 | { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 }, |
| 2210 | { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 }, |
| 2211 | { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 }, |
| 2212 | { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b }, |
| 2213 | |
| 2214 | /* 802.11 HyperLan 2 */ |
| 2215 | { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 }, |
| 2216 | { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 }, |
| 2217 | { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 }, |
| 2218 | { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 }, |
| 2219 | { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 }, |
| 2220 | { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 }, |
| 2221 | { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b }, |
| 2222 | { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b }, |
| 2223 | { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 }, |
| 2224 | { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 }, |
| 2225 | |
| 2226 | /* 802.11 UNII */ |
| 2227 | { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 }, |
| 2228 | { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b }, |
| 2229 | { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b }, |
| 2230 | { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 }, |
| 2231 | { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 }, |
| 2232 | { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 }, |
| 2233 | |
| 2234 | /* MMAC(Japan)J52 ch 34,38,42,46 */ |
| 2235 | { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b }, |
| 2236 | { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 }, |
| 2237 | { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b }, |
| 2238 | { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 }, |
| 2239 | }; |
| 2240 | |
| 2241 | static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
| 2242 | { |
| 2243 | struct hw_mode_spec *spec = &rt2x00dev->spec; |
| 2244 | u8 *txpower; |
| 2245 | unsigned int i; |
| 2246 | |
| 2247 | /* |
| 2248 | * Initialize all hw fields. |
| 2249 | */ |
| 2250 | rt2x00dev->hw->flags = |
| 2251 | IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE | |
Johannes Berg | 4150c57 | 2007-09-17 01:29:23 -0400 | [diff] [blame] | 2252 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2253 | rt2x00dev->hw->extra_tx_headroom = 0; |
| 2254 | rt2x00dev->hw->max_signal = MAX_SIGNAL; |
| 2255 | rt2x00dev->hw->max_rssi = MAX_RX_SSI; |
Ivo van Doorn | 871ff6e | 2008-02-03 15:51:47 +0100 | [diff] [blame] | 2256 | rt2x00dev->hw->queues = 4; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2257 | |
| 2258 | SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev); |
| 2259 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
| 2260 | rt2x00_eeprom_addr(rt2x00dev, |
| 2261 | EEPROM_MAC_ADDR_0)); |
| 2262 | |
| 2263 | /* |
| 2264 | * Convert tx_power array in eeprom. |
| 2265 | */ |
| 2266 | txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); |
| 2267 | for (i = 0; i < 14; i++) |
| 2268 | txpower[i] = TXPOWER_FROM_DEV(txpower[i]); |
| 2269 | |
| 2270 | /* |
| 2271 | * Initialize hw_mode information. |
| 2272 | */ |
Ivo van Doorn | 31562e8 | 2008-02-17 17:35:05 +0100 | [diff] [blame] | 2273 | spec->supported_bands = SUPPORT_BAND_2GHZ; |
| 2274 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2275 | spec->tx_power_a = NULL; |
| 2276 | spec->tx_power_bg = txpower; |
| 2277 | spec->tx_power_default = DEFAULT_TXPOWER; |
| 2278 | |
| 2279 | if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) { |
| 2280 | spec->num_channels = 14; |
| 2281 | spec->channels = rf_vals_noseq; |
| 2282 | } else { |
| 2283 | spec->num_channels = 14; |
| 2284 | spec->channels = rf_vals_seq; |
| 2285 | } |
| 2286 | |
| 2287 | if (rt2x00_rf(&rt2x00dev->chip, RF5225) || |
| 2288 | rt2x00_rf(&rt2x00dev->chip, RF5325)) { |
Ivo van Doorn | 31562e8 | 2008-02-17 17:35:05 +0100 | [diff] [blame] | 2289 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2290 | spec->num_channels = ARRAY_SIZE(rf_vals_seq); |
| 2291 | |
| 2292 | txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); |
| 2293 | for (i = 0; i < 14; i++) |
| 2294 | txpower[i] = TXPOWER_FROM_DEV(txpower[i]); |
| 2295 | |
| 2296 | spec->tx_power_a = txpower; |
| 2297 | } |
| 2298 | } |
| 2299 | |
| 2300 | static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev) |
| 2301 | { |
| 2302 | int retval; |
| 2303 | |
| 2304 | /* |
| 2305 | * Allocate eeprom data. |
| 2306 | */ |
| 2307 | retval = rt61pci_validate_eeprom(rt2x00dev); |
| 2308 | if (retval) |
| 2309 | return retval; |
| 2310 | |
| 2311 | retval = rt61pci_init_eeprom(rt2x00dev); |
| 2312 | if (retval) |
| 2313 | return retval; |
| 2314 | |
| 2315 | /* |
| 2316 | * Initialize hw specifications. |
| 2317 | */ |
| 2318 | rt61pci_probe_hw_mode(rt2x00dev); |
| 2319 | |
| 2320 | /* |
Ivo van Doorn | 9404ef3 | 2008-02-03 15:48:38 +0100 | [diff] [blame] | 2321 | * This device requires firmware. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2322 | */ |
Ivo van Doorn | 066cb63 | 2007-09-25 20:55:39 +0200 | [diff] [blame] | 2323 | __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2324 | |
| 2325 | /* |
| 2326 | * Set the rssi offset. |
| 2327 | */ |
| 2328 | rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; |
| 2329 | |
| 2330 | return 0; |
| 2331 | } |
| 2332 | |
| 2333 | /* |
| 2334 | * IEEE80211 stack callback functions. |
| 2335 | */ |
| 2336 | static int rt61pci_set_retry_limit(struct ieee80211_hw *hw, |
| 2337 | u32 short_retry, u32 long_retry) |
| 2338 | { |
| 2339 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 2340 | u32 reg; |
| 2341 | |
| 2342 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®); |
| 2343 | rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry); |
| 2344 | rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry); |
| 2345 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); |
| 2346 | |
| 2347 | return 0; |
| 2348 | } |
| 2349 | |
| 2350 | static u64 rt61pci_get_tsf(struct ieee80211_hw *hw) |
| 2351 | { |
| 2352 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 2353 | u64 tsf; |
| 2354 | u32 reg; |
| 2355 | |
| 2356 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®); |
| 2357 | tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; |
| 2358 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®); |
| 2359 | tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); |
| 2360 | |
| 2361 | return tsf; |
| 2362 | } |
| 2363 | |
Ivo van Doorn | 2484591 | 2007-09-25 20:53:43 +0200 | [diff] [blame] | 2364 | static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2365 | struct ieee80211_tx_control *control) |
| 2366 | { |
| 2367 | struct rt2x00_dev *rt2x00dev = hw->priv; |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 2368 | struct rt2x00_intf *intf = vif_to_intf(control->vif); |
Ivo van Doorn | 7872089 | 2008-05-05 17:23:31 +0200 | [diff] [blame] | 2369 | struct queue_entry_priv_pci_tx *priv_tx; |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2370 | struct skb_frame_desc *skbdesc; |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 2371 | unsigned int beacon_base; |
Ivo van Doorn | 8af244c | 2008-03-09 22:42:59 +0100 | [diff] [blame] | 2372 | u32 reg; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2373 | |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 2374 | if (unlikely(!intf->beacon)) |
| 2375 | return -ENOBUFS; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2376 | |
Ivo van Doorn | 7872089 | 2008-05-05 17:23:31 +0200 | [diff] [blame] | 2377 | priv_tx = intf->beacon->priv_data; |
| 2378 | memset(priv_tx->desc, 0, intf->beacon->queue->desc_size); |
Ivo van Doorn | c22eb87 | 2007-10-06 14:18:22 +0200 | [diff] [blame] | 2379 | |
Ivo van Doorn | 08992f7 | 2008-01-24 01:56:25 -0800 | [diff] [blame] | 2380 | /* |
| 2381 | * Fill in skb descriptor |
| 2382 | */ |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2383 | skbdesc = get_skb_frame_desc(skb); |
| 2384 | memset(skbdesc, 0, sizeof(*skbdesc)); |
Ivo van Doorn | baf26a7 | 2008-02-17 17:32:08 +0100 | [diff] [blame] | 2385 | skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED; |
Ivo van Doorn | 7872089 | 2008-05-05 17:23:31 +0200 | [diff] [blame] | 2386 | skbdesc->data = skb->data; |
| 2387 | skbdesc->data_len = skb->len; |
| 2388 | skbdesc->desc = priv_tx->desc; |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 2389 | skbdesc->desc_len = intf->beacon->queue->desc_size; |
| 2390 | skbdesc->entry = intf->beacon; |
Ivo van Doorn | 08992f7 | 2008-01-24 01:56:25 -0800 | [diff] [blame] | 2391 | |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 2392 | /* |
Ivo van Doorn | 8af244c | 2008-03-09 22:42:59 +0100 | [diff] [blame] | 2393 | * Disable beaconing while we are reloading the beacon data, |
| 2394 | * otherwise we might be sending out invalid data. |
| 2395 | */ |
| 2396 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); |
| 2397 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); |
| 2398 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); |
| 2399 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); |
| 2400 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); |
| 2401 | |
| 2402 | /* |
Ivo van Doorn | 5957da4c | 2008-02-03 15:54:57 +0100 | [diff] [blame] | 2403 | * mac80211 doesn't provide the control->queue variable |
| 2404 | * for beacons. Set our own queue identification so |
| 2405 | * it can be used during descriptor initialization. |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 2406 | */ |
Ivo van Doorn | 5957da4c | 2008-02-03 15:54:57 +0100 | [diff] [blame] | 2407 | control->queue = RT2X00_BCN_QUEUE_BEACON; |
Ivo van Doorn | 08992f7 | 2008-01-24 01:56:25 -0800 | [diff] [blame] | 2408 | rt2x00lib_write_tx_desc(rt2x00dev, skb, control); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2409 | |
| 2410 | /* |
| 2411 | * Write entire beacon with descriptor to register, |
| 2412 | * and kick the beacon generator. |
| 2413 | */ |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 2414 | beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx); |
| 2415 | rt2x00pci_register_multiwrite(rt2x00dev, beacon_base, |
Ivo van Doorn | 7872089 | 2008-05-05 17:23:31 +0200 | [diff] [blame] | 2416 | skbdesc->desc, skbdesc->desc_len); |
| 2417 | rt2x00pci_register_multiwrite(rt2x00dev, |
| 2418 | beacon_base + skbdesc->desc_len, |
| 2419 | skbdesc->data, skbdesc->data_len); |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 2420 | rt61pci_kick_tx_queue(rt2x00dev, control->queue); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2421 | |
| 2422 | return 0; |
| 2423 | } |
| 2424 | |
| 2425 | static const struct ieee80211_ops rt61pci_mac80211_ops = { |
| 2426 | .tx = rt2x00mac_tx, |
Johannes Berg | 4150c57 | 2007-09-17 01:29:23 -0400 | [diff] [blame] | 2427 | .start = rt2x00mac_start, |
| 2428 | .stop = rt2x00mac_stop, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2429 | .add_interface = rt2x00mac_add_interface, |
| 2430 | .remove_interface = rt2x00mac_remove_interface, |
| 2431 | .config = rt2x00mac_config, |
| 2432 | .config_interface = rt2x00mac_config_interface, |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 2433 | .configure_filter = rt2x00mac_configure_filter, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2434 | .get_stats = rt2x00mac_get_stats, |
| 2435 | .set_retry_limit = rt61pci_set_retry_limit, |
Johannes Berg | 471b3ef | 2007-12-28 14:32:58 +0100 | [diff] [blame] | 2436 | .bss_info_changed = rt2x00mac_bss_info_changed, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2437 | .conf_tx = rt2x00mac_conf_tx, |
| 2438 | .get_tx_stats = rt2x00mac_get_tx_stats, |
| 2439 | .get_tsf = rt61pci_get_tsf, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2440 | .beacon_update = rt61pci_beacon_update, |
| 2441 | }; |
| 2442 | |
| 2443 | static const struct rt2x00lib_ops rt61pci_rt2x00_ops = { |
| 2444 | .irq_handler = rt61pci_interrupt, |
| 2445 | .probe_hw = rt61pci_probe_hw, |
| 2446 | .get_firmware_name = rt61pci_get_firmware_name, |
Ivo van Doorn | a7f3a06 | 2008-03-09 22:44:54 +0100 | [diff] [blame] | 2447 | .get_firmware_crc = rt61pci_get_firmware_crc, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2448 | .load_firmware = rt61pci_load_firmware, |
| 2449 | .initialize = rt2x00pci_initialize, |
| 2450 | .uninitialize = rt2x00pci_uninitialize, |
Ivo van Doorn | 837e7f2 | 2008-01-06 23:41:45 +0100 | [diff] [blame] | 2451 | .init_rxentry = rt61pci_init_rxentry, |
| 2452 | .init_txentry = rt61pci_init_txentry, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2453 | .set_device_state = rt61pci_set_device_state, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2454 | .rfkill_poll = rt61pci_rfkill_poll, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2455 | .link_stats = rt61pci_link_stats, |
| 2456 | .reset_tuner = rt61pci_reset_tuner, |
| 2457 | .link_tuner = rt61pci_link_tuner, |
| 2458 | .write_tx_desc = rt61pci_write_tx_desc, |
| 2459 | .write_tx_data = rt2x00pci_write_tx_data, |
| 2460 | .kick_tx_queue = rt61pci_kick_tx_queue, |
| 2461 | .fill_rxdone = rt61pci_fill_rxdone, |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 2462 | .config_filter = rt61pci_config_filter, |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 2463 | .config_intf = rt61pci_config_intf, |
Ivo van Doorn | 7281037 | 2008-03-09 22:46:18 +0100 | [diff] [blame] | 2464 | .config_erp = rt61pci_config_erp, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2465 | .config = rt61pci_config, |
| 2466 | }; |
| 2467 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2468 | static const struct data_queue_desc rt61pci_queue_rx = { |
| 2469 | .entry_num = RX_ENTRIES, |
| 2470 | .data_size = DATA_FRAME_SIZE, |
| 2471 | .desc_size = RXD_DESC_SIZE, |
| 2472 | .priv_size = sizeof(struct queue_entry_priv_pci_rx), |
| 2473 | }; |
| 2474 | |
| 2475 | static const struct data_queue_desc rt61pci_queue_tx = { |
| 2476 | .entry_num = TX_ENTRIES, |
| 2477 | .data_size = DATA_FRAME_SIZE, |
| 2478 | .desc_size = TXD_DESC_SIZE, |
| 2479 | .priv_size = sizeof(struct queue_entry_priv_pci_tx), |
| 2480 | }; |
| 2481 | |
| 2482 | static const struct data_queue_desc rt61pci_queue_bcn = { |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 2483 | .entry_num = 4 * BEACON_ENTRIES, |
Ivo van Doorn | 7872089 | 2008-05-05 17:23:31 +0200 | [diff] [blame] | 2484 | .data_size = 0, /* No DMA required for beacons */ |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2485 | .desc_size = TXINFO_SIZE, |
| 2486 | .priv_size = sizeof(struct queue_entry_priv_pci_tx), |
| 2487 | }; |
| 2488 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2489 | static const struct rt2x00_ops rt61pci_ops = { |
Ivo van Doorn | 2360157 | 2007-11-27 21:47:34 +0100 | [diff] [blame] | 2490 | .name = KBUILD_MODNAME, |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 2491 | .max_sta_intf = 1, |
| 2492 | .max_ap_intf = 4, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2493 | .eeprom_size = EEPROM_SIZE, |
| 2494 | .rf_size = RF_SIZE, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2495 | .rx = &rt61pci_queue_rx, |
| 2496 | .tx = &rt61pci_queue_tx, |
| 2497 | .bcn = &rt61pci_queue_bcn, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2498 | .lib = &rt61pci_rt2x00_ops, |
| 2499 | .hw = &rt61pci_mac80211_ops, |
| 2500 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
| 2501 | .debugfs = &rt61pci_rt2x00debug, |
| 2502 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
| 2503 | }; |
| 2504 | |
| 2505 | /* |
| 2506 | * RT61pci module information. |
| 2507 | */ |
| 2508 | static struct pci_device_id rt61pci_device_table[] = { |
| 2509 | /* RT2561s */ |
| 2510 | { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) }, |
| 2511 | /* RT2561 v2 */ |
| 2512 | { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) }, |
| 2513 | /* RT2661 */ |
| 2514 | { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) }, |
| 2515 | { 0, } |
| 2516 | }; |
| 2517 | |
| 2518 | MODULE_AUTHOR(DRV_PROJECT); |
| 2519 | MODULE_VERSION(DRV_VERSION); |
| 2520 | MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver."); |
| 2521 | MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 " |
| 2522 | "PCI & PCMCIA chipset based cards"); |
| 2523 | MODULE_DEVICE_TABLE(pci, rt61pci_device_table); |
| 2524 | MODULE_FIRMWARE(FIRMWARE_RT2561); |
| 2525 | MODULE_FIRMWARE(FIRMWARE_RT2561s); |
| 2526 | MODULE_FIRMWARE(FIRMWARE_RT2661); |
| 2527 | MODULE_LICENSE("GPL"); |
| 2528 | |
| 2529 | static struct pci_driver rt61pci_driver = { |
Ivo van Doorn | 2360157 | 2007-11-27 21:47:34 +0100 | [diff] [blame] | 2530 | .name = KBUILD_MODNAME, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2531 | .id_table = rt61pci_device_table, |
| 2532 | .probe = rt2x00pci_probe, |
| 2533 | .remove = __devexit_p(rt2x00pci_remove), |
| 2534 | .suspend = rt2x00pci_suspend, |
| 2535 | .resume = rt2x00pci_resume, |
| 2536 | }; |
| 2537 | |
| 2538 | static int __init rt61pci_init(void) |
| 2539 | { |
| 2540 | return pci_register_driver(&rt61pci_driver); |
| 2541 | } |
| 2542 | |
| 2543 | static void __exit rt61pci_exit(void) |
| 2544 | { |
| 2545 | pci_unregister_driver(&rt61pci_driver); |
| 2546 | } |
| 2547 | |
| 2548 | module_init(rt61pci_init); |
| 2549 | module_exit(rt61pci_exit); |