Jishnu Prakash | a5f6af2 | 2019-03-08 11:00:51 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 14 | |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/regmap.h> |
| 17 | #include <linux/of.h> |
| 18 | #include <linux/err.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/slab.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/mutex.h> |
| 23 | #include <linux/types.h> |
| 24 | #include <linux/hwmon.h> |
| 25 | #include <linux/module.h> |
| 26 | #include <linux/debugfs.h> |
| 27 | #include <linux/spmi.h> |
| 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/of_irq.h> |
| 30 | #include <linux/interrupt.h> |
| 31 | #include <linux/completion.h> |
| 32 | #include <linux/hwmon-sysfs.h> |
| 33 | #include <linux/qpnp/qpnp-adc.h> |
| 34 | #include <linux/platform_device.h> |
| 35 | #include <linux/power_supply.h> |
| 36 | #include <linux/thermal.h> |
Jishnu Prakash | a2d0099 | 2018-11-16 17:09:49 +0530 | [diff] [blame] | 37 | #include <linux/qpnp/qpnp-revid.h> |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 38 | |
| 39 | /* QPNP VADC register definition */ |
| 40 | #define QPNP_VADC_REVISION1 0x0 |
| 41 | #define QPNP_VADC_REVISION2 0x1 |
| 42 | #define QPNP_VADC_REVISION3 0x2 |
| 43 | #define QPNP_VADC_REVISION4 0x3 |
| 44 | #define QPNP_VADC_PERPH_TYPE 0x4 |
| 45 | #define QPNP_VADC_PERH_SUBTYPE 0x5 |
| 46 | |
| 47 | #define QPNP_VADC_SUPPORTED_REVISION2 1 |
| 48 | |
| 49 | #define QPNP_VADC_STATUS1 0x8 |
| 50 | #define QPNP_VADC_STATUS1_OP_MODE 4 |
| 51 | #define QPNP_VADC_STATUS1_MEAS_INTERVAL_EN_STS BIT(2) |
| 52 | #define QPNP_VADC_STATUS1_REQ_STS BIT(1) |
| 53 | #define QPNP_VADC_STATUS1_EOC BIT(0) |
| 54 | #define QPNP_VADC_STATUS1_REQ_STS_EOC_MASK 0x3 |
| 55 | #define QPNP_VADC_STATUS1_OP_MODE_MASK 0x18 |
| 56 | #define QPNP_VADC_MEAS_INT_MODE 0x2 |
| 57 | #define QPNP_VADC_MEAS_INT_MODE_MASK 0x10 |
| 58 | |
| 59 | #define QPNP_VADC_STATUS2 0x9 |
| 60 | #define QPNP_VADC_STATUS2_CONV_SEQ_STATE 6 |
| 61 | #define QPNP_VADC_STATUS2_FIFO_NOT_EMPTY_FLAG BIT(1) |
| 62 | #define QPNP_VADC_STATUS2_CONV_SEQ_TIMEOUT_STS BIT(0) |
| 63 | #define QPNP_VADC_STATUS2_CONV_SEQ_STATE_SHIFT 4 |
| 64 | #define QPNP_VADC_CONV_TIMEOUT_ERR 2 |
| 65 | |
| 66 | #define QPNP_VADC_MODE_CTL 0x40 |
| 67 | #define QPNP_VADC_OP_MODE_SHIFT 3 |
| 68 | #define QPNP_VADC_VREF_XO_THM_FORCE BIT(2) |
| 69 | #define QPNP_VADC_AMUX_TRIM_EN BIT(1) |
| 70 | #define QPNP_VADC_TRIM_EN BIT(0) |
| 71 | #define QPNP_VADC_EN_CTL1 0x46 |
| 72 | #define QPNP_VADC_EN BIT(7) |
| 73 | #define QPNP_VADC_CH_SEL_CTL 0x48 |
| 74 | #define QPNP_VADC_DIG_PARAM 0x50 |
| 75 | #define QPNP_VADC_DIG_DEC_RATIO_SEL_SHIFT 3 |
| 76 | #define QPNP_VADC_HW_SETTLE_DELAY 0x51 |
| 77 | #define QPNP_VADC_CONV_REQ 0x52 |
| 78 | #define QPNP_VADC_CONV_REQ_SET BIT(7) |
| 79 | #define QPNP_VADC_CONV_SEQ_CTL 0x54 |
| 80 | #define QPNP_VADC_CONV_SEQ_HOLDOFF_SHIFT 4 |
| 81 | #define QPNP_VADC_CONV_SEQ_TRIG_CTL 0x55 |
| 82 | #define QPNP_VADC_MEAS_INTERVAL_CTL 0x57 |
| 83 | #define QPNP_VADC_MEAS_INTERVAL_OP_CTL 0x59 |
| 84 | #define QPNP_VADC_MEAS_INTERVAL_OP_SET BIT(7) |
| 85 | |
| 86 | #define QPNP_VADC_CONV_SEQ_FALLING_EDGE 0x0 |
| 87 | #define QPNP_VADC_CONV_SEQ_RISING_EDGE 0x1 |
| 88 | #define QPNP_VADC_CONV_SEQ_EDGE_SHIFT 7 |
| 89 | #define QPNP_VADC_FAST_AVG_CTL 0x5a |
| 90 | |
| 91 | #define QPNP_VADC_LOW_THR_LSB 0x5c |
| 92 | #define QPNP_VADC_LOW_THR_MSB 0x5d |
| 93 | #define QPNP_VADC_HIGH_THR_LSB 0x5e |
| 94 | #define QPNP_VADC_HIGH_THR_MSB 0x5f |
| 95 | #define QPNP_VADC_ACCESS 0xd0 |
| 96 | #define QPNP_VADC_ACCESS_DATA 0xa5 |
| 97 | #define QPNP_VADC_PERH_RESET_CTL3 0xda |
| 98 | #define QPNP_FOLLOW_OTST2_RB BIT(3) |
| 99 | #define QPNP_FOLLOW_WARM_RB BIT(2) |
| 100 | #define QPNP_FOLLOW_SHUTDOWN1_RB BIT(1) |
| 101 | #define QPNP_FOLLOW_SHUTDOWN2_RB BIT(0) |
| 102 | |
| 103 | #define QPNP_INT_TEST_VAL 0xE1 |
| 104 | |
| 105 | #define QPNP_VADC_DATA0 0x60 |
| 106 | #define QPNP_VADC_DATA1 0x61 |
| 107 | #define QPNP_VADC_CONV_TIMEOUT_ERR 2 |
| 108 | #define QPNP_VADC_CONV_TIME_MIN 1000 |
| 109 | #define QPNP_VADC_CONV_TIME_MAX 1100 |
Jishnu Prakash | 32adff7 | 2019-07-08 15:30:21 +0530 | [diff] [blame] | 110 | #define QPNP_ADC_COMPLETION_TIMEOUT msecs_to_jiffies(100) |
| 111 | #define QPNP_VADC_ERR_COUNT 150 |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 112 | #define QPNP_OP_MODE_SHIFT 3 |
| 113 | |
| 114 | #define QPNP_VADC_THR_LSB_MASK(val) (val & 0xff) |
| 115 | #define QPNP_VADC_THR_MSB_MASK(val) ((val & 0xff00) >> 8) |
| 116 | #define QPNP_MIN_TIME 2000 |
| 117 | #define QPNP_MAX_TIME 2000 |
| 118 | #define QPNP_RETRY 100 |
| 119 | #define QPNP_VADC_ABSOLUTE_RECALIB_OFFSET 8 |
| 120 | #define QPNP_VADC_RATIOMETRIC_RECALIB_OFFSET 12 |
| 121 | #define QPNP_VADC_RECALIB_MAXCNT 10 |
| 122 | #define QPNP_VADC_OFFSET_DUMP 8 |
| 123 | #define QPNP_VADC_REG_DUMP 14 |
| 124 | |
| 125 | /* QPNP VADC refreshed register set */ |
| 126 | #define QPNP_VADC_HC1_STATUS1 0x8 |
| 127 | |
| 128 | #define QPNP_VADC_HC1_DATA_HOLD_CTL 0x3f |
| 129 | #define QPNP_VADC_HC1_DATA_HOLD_CTL_FIELD BIT(1) |
| 130 | |
| 131 | #define QPNP_VADC_HC1_ADC_DIG_PARAM 0x42 |
| 132 | #define QPNP_VADC_HC1_CAL_VAL BIT(6) |
| 133 | #define QPNP_VADC_HC1_CAL_VAL_SHIFT 6 |
| 134 | #define QPNP_VADC_HC1_CAL_SEL_MASK 0x30 |
| 135 | #define QPNP_VADC_HC1_CAL_SEL_SHIFT 4 |
| 136 | #define QPNP_VADC_HC1_DEC_RATIO_SEL 0xc |
| 137 | #define QPNP_VADC_HC1_DEC_RATIO_SHIFT 2 |
| 138 | #define QPNP_VADC_HC1_FAST_AVG_CTL 0x43 |
| 139 | #define QPNP_VADC_HC1_FAST_AVG_SAMPLES_MASK 0x7 |
| 140 | #define QPNP_VADC_HC1_ADC_CH_SEL_CTL 0x44 |
| 141 | #define QPNP_VADC_HC1_DELAY_CTL 0x45 |
| 142 | #define QPNP_VADC_HC1_DELAY_CTL_MASK 0xf |
Jishnu Prakash | 35141c3 | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 143 | #define QPNP_VADC_HC1_EN_CTL1 0x46 |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 144 | #define QPNP_VADC_HC1_ADC_EN BIT(7) |
Jishnu Prakash | 35141c3 | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 145 | #define QPNP_VADC_HC1_CONV_REQ 0x47 |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 146 | #define QPNP_VADC_HC1_CONV_REQ_START BIT(7) |
| 147 | |
| 148 | #define QPNP_VADC_HC1_VBAT_MIN_THR0 0x48 |
| 149 | #define QPNP_VADC_HC1_VBAT_MIN_THR1 0x49 |
| 150 | |
| 151 | #define QPNP_VADC_HC1_DATA0 0x50 |
| 152 | #define QPNP_VADC_HC1_DATA1 0x51 |
| 153 | #define QPNP_VADC_HC1_DATA_CHECK_USR 0x8000 |
| 154 | |
| 155 | #define QPNP_VADC_HC1_VBAT_MIN_DATA0 0x52 |
| 156 | #define QPNP_VADC_MC1_VBAT_MIN_DATA1 0x53 |
| 157 | |
| 158 | /* |
| 159 | * Conversion time varies between 213uS to 6827uS based on the decimation, |
| 160 | * clock rate, fast average samples with no measurement in queue. |
| 161 | */ |
| 162 | #define QPNP_VADC_HC1_CONV_TIME_MIN_US 213 |
| 163 | #define QPNP_VADC_HC1_CONV_TIME_MAX_US 214 |
Jishnu Prakash | 32adff7 | 2019-07-08 15:30:21 +0530 | [diff] [blame] | 164 | #define QPNP_VADC_HC1_ERR_COUNT_POLL 705 |
| 165 | #define QPNP_VADC_HC1_ERR_COUNT 235 |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 166 | |
Jishnu Prakash | e213f1b | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 167 | #define QPNP_VADC_CAL_DELAY_CTL_1 0x3744 |
| 168 | #define QPNP_VADC_CAL_DELAY_MEAS_SLOW 0x73 |
| 169 | #define QPNP_VADC_CAL_DELAY_MEAS_DEFAULT 0x3 |
| 170 | |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 171 | struct qpnp_vadc_mode_state { |
| 172 | bool meas_int_mode; |
| 173 | bool meas_int_request_in_queue; |
| 174 | bool vadc_meas_int_enable; |
| 175 | struct qpnp_adc_tm_btm_param *param; |
| 176 | struct qpnp_adc_amux vadc_meas_amux; |
| 177 | }; |
| 178 | |
| 179 | struct qpnp_vadc_thermal_data { |
| 180 | bool thermal_node; |
| 181 | int thermal_chan; |
| 182 | enum qpnp_vadc_channels vadc_channel; |
| 183 | struct thermal_zone_device *tz_dev; |
| 184 | struct qpnp_vadc_chip *vadc_dev; |
| 185 | }; |
| 186 | |
| 187 | struct qpnp_vadc_chip { |
| 188 | struct device *dev; |
| 189 | struct qpnp_adc_drv *adc; |
| 190 | struct list_head list; |
| 191 | struct device *vadc_hwmon; |
| 192 | bool vadc_init_calib; |
| 193 | int max_channels_available; |
| 194 | bool vadc_iadc_sync_lock; |
| 195 | u8 id; |
| 196 | struct work_struct trigger_completion_work; |
| 197 | bool vadc_poll_eoc; |
| 198 | bool vadc_recalib_check; |
| 199 | u8 revision_ana_minor; |
| 200 | u8 revision_dig_major; |
| 201 | struct work_struct trigger_high_thr_work; |
| 202 | struct work_struct trigger_low_thr_work; |
| 203 | struct qpnp_vadc_mode_state *state_copy; |
| 204 | struct qpnp_vadc_thermal_data *vadc_therm_chan; |
| 205 | struct power_supply *vadc_chg_vote; |
| 206 | bool vadc_hc; |
| 207 | int vadc_debug_count; |
Jishnu Prakash | a2d0099 | 2018-11-16 17:09:49 +0530 | [diff] [blame] | 208 | struct pmic_revid_data *pmic_rev_id; |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 209 | struct sensor_device_attribute sens_attr[0]; |
| 210 | }; |
| 211 | |
| 212 | LIST_HEAD(qpnp_vadc_device_list); |
| 213 | |
| 214 | static struct qpnp_vadc_scale_fn vadc_scale_fn[] = { |
| 215 | [SCALE_DEFAULT] = {qpnp_adc_scale_default}, |
| 216 | [SCALE_BATT_THERM] = {qpnp_adc_scale_batt_therm}, |
| 217 | [SCALE_PMIC_THERM] = {qpnp_adc_scale_pmic_therm}, |
| 218 | [SCALE_XOTHERM] = {qpnp_adc_tdkntcg_therm}, |
| 219 | [SCALE_THERM_100K_PULLUP] = {qpnp_adc_scale_therm_pu2}, |
| 220 | [SCALE_THERM_150K_PULLUP] = {qpnp_adc_scale_therm_pu1}, |
| 221 | [SCALE_QRD_BATT_THERM] = {qpnp_adc_scale_qrd_batt_therm}, |
| 222 | [SCALE_QRD_SKUAA_BATT_THERM] = {qpnp_adc_scale_qrd_skuaa_batt_therm}, |
| 223 | [SCALE_SMB_BATT_THERM] = {qpnp_adc_scale_smb_batt_therm}, |
| 224 | [SCALE_QRD_SKUG_BATT_THERM] = {qpnp_adc_scale_qrd_skug_batt_therm}, |
| 225 | [SCALE_QRD_SKUH_BATT_THERM] = {qpnp_adc_scale_qrd_skuh_batt_therm}, |
| 226 | [SCALE_NCP_03WF683_THERM] = {qpnp_adc_scale_therm_ncp03}, |
| 227 | [SCALE_QRD_SKUT1_BATT_THERM] = {qpnp_adc_scale_qrd_skut1_batt_therm}, |
| 228 | [SCALE_PMI_CHG_TEMP] = {qpnp_adc_scale_pmi_chg_temp}, |
Jishnu Prakash | 3b3fe94 | 2018-01-08 12:23:39 +0530 | [diff] [blame] | 229 | [SCALE_BATT_THERM_TEMP] = {qpnp_adc_batt_therm}, |
| 230 | [SCALE_CHRG_TEMP] = {qpnp_adc_scale_chrg_temp}, |
| 231 | [SCALE_DIE_TEMP] = {qpnp_adc_scale_die_temp}, |
| 232 | [SCALE_I_DEFAULT] = {qpnp_iadc_scale_default}, |
| 233 | [SCALE_USBIN_I] = {qpnp_adc_scale_usbin_curr}, |
Jishnu Prakash | 20343d4 | 2018-02-12 14:53:33 +0530 | [diff] [blame] | 234 | [SCALE_BATT_THERM_TEMP_QRD] = {qpnp_adc_batt_therm_qrd}, |
Jishnu Prakash | 62aff11 | 2017-09-15 15:06:59 +0530 | [diff] [blame] | 235 | [SCALE_SMB1390_DIE_TEMP] = {qpnp_adc_scale_die_temp_1390}, |
Jishnu Prakash | 64c9d3f | 2018-04-12 17:01:32 +0530 | [diff] [blame] | 236 | [SCALE_BATT_THERM_TEMP_PU30] = {qpnp_adc_batt_therm_pu30}, |
| 237 | [SCALE_BATT_THERM_TEMP_PU400] = {qpnp_adc_batt_therm_pu400}, |
Jishnu Prakash | 6740de6 | 2018-11-29 14:22:08 +0530 | [diff] [blame] | 238 | [SCALE_BATT_THERM_TEMP_QRD_215] = {qpnp_adc_batt_therm_qrd_215} |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 239 | }; |
| 240 | |
| 241 | static struct qpnp_vadc_rscale_fn adc_vadc_rscale_fn[] = { |
| 242 | [SCALE_RVADC_ABSOLUTE] = {qpnp_vadc_absolute_rthr}, |
| 243 | }; |
| 244 | |
| 245 | static int32_t qpnp_vadc_calib_device(struct qpnp_vadc_chip *vadc); |
| 246 | |
| 247 | static int32_t qpnp_vadc_read_reg(struct qpnp_vadc_chip *vadc, int16_t reg, |
| 248 | u8 *data, int len) |
| 249 | { |
| 250 | int rc; |
| 251 | |
| 252 | rc = regmap_bulk_read(vadc->adc->regmap, |
| 253 | (vadc->adc->offset + reg), data, len); |
| 254 | if (rc < 0) { |
| 255 | pr_err("qpnp adc read reg %d failed with %d\n", reg, rc); |
| 256 | return rc; |
| 257 | } |
| 258 | |
| 259 | return 0; |
| 260 | } |
| 261 | |
| 262 | static int32_t qpnp_vadc_write_reg(struct qpnp_vadc_chip *vadc, int16_t reg, |
| 263 | u8 *buf, int len) |
| 264 | { |
| 265 | int rc; |
| 266 | |
| 267 | rc = regmap_bulk_write(vadc->adc->regmap, |
| 268 | (vadc->adc->offset + reg), buf, len); |
| 269 | if (rc < 0) { |
| 270 | pr_err("qpnp adc write reg %d failed with %d\n", reg, rc); |
| 271 | return rc; |
| 272 | } |
| 273 | |
| 274 | return 0; |
| 275 | } |
| 276 | |
| 277 | static int qpnp_vadc_is_valid(struct qpnp_vadc_chip *vadc) |
| 278 | { |
| 279 | struct qpnp_vadc_chip *vadc_chip = NULL; |
| 280 | |
| 281 | list_for_each_entry(vadc_chip, &qpnp_vadc_device_list, list) |
| 282 | if (vadc == vadc_chip) |
| 283 | return 0; |
| 284 | |
| 285 | return -EINVAL; |
| 286 | } |
| 287 | |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 288 | static int32_t qpnp_vadc_mode_select(struct qpnp_vadc_chip *vadc, u8 mode_ctl) |
| 289 | { |
| 290 | int rc; |
| 291 | |
| 292 | mode_ctl |= (QPNP_VADC_TRIM_EN | QPNP_VADC_AMUX_TRIM_EN); |
| 293 | |
| 294 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_MODE_CTL, &mode_ctl, 1); |
| 295 | if (rc < 0) |
| 296 | pr_err("vadc write mode selection err:%d\n", rc); |
| 297 | |
| 298 | return rc; |
| 299 | } |
| 300 | |
| 301 | static int32_t qpnp_vadc_enable(struct qpnp_vadc_chip *vadc, bool state) |
| 302 | { |
| 303 | int rc = 0; |
| 304 | u8 data = 0; |
| 305 | |
| 306 | data = QPNP_VADC_EN; |
| 307 | if (state) { |
| 308 | if (vadc->adc->hkadc_ldo && vadc->adc->hkadc_ldo_ok) { |
| 309 | rc = qpnp_adc_enable_voltage(vadc->adc); |
| 310 | if (rc) { |
| 311 | pr_err("failed enabling VADC LDO\n"); |
| 312 | return rc; |
| 313 | } |
| 314 | } |
| 315 | |
| 316 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_EN_CTL1, &data, 1); |
| 317 | if (rc < 0) { |
| 318 | pr_err("VADC enable failed\n"); |
| 319 | return rc; |
| 320 | } |
| 321 | } else { |
| 322 | data = (~data & QPNP_VADC_EN); |
| 323 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_EN_CTL1, &data, 1); |
| 324 | if (rc < 0) { |
| 325 | pr_err("VADC disable failed\n"); |
| 326 | return rc; |
| 327 | } |
| 328 | |
| 329 | if (vadc->adc->hkadc_ldo && vadc->adc->hkadc_ldo_ok) |
| 330 | qpnp_adc_disable_voltage(vadc->adc); |
| 331 | } |
| 332 | |
| 333 | return 0; |
| 334 | } |
| 335 | |
| 336 | static int32_t qpnp_vadc_status_debug(struct qpnp_vadc_chip *vadc) |
| 337 | { |
| 338 | int rc = 0, i = 0; |
| 339 | u8 buf[8], offset = 0; |
| 340 | |
| 341 | if (vadc->vadc_debug_count < 3) { |
| 342 | for (i = 0; i < QPNP_VADC_REG_DUMP; i++) { |
| 343 | rc = qpnp_vadc_read_reg(vadc, offset, buf, 8); |
| 344 | if (rc) { |
| 345 | pr_err("debug register dump failed\n"); |
| 346 | return rc; |
| 347 | } |
| 348 | offset += QPNP_VADC_OFFSET_DUMP; |
| 349 | pr_err("row%d: 0%x 0%x 0%x 0%x 0%x 0%x 0%x 0%x\n", |
| 350 | i, buf[0], buf[1], buf[2], buf[3], buf[4], |
| 351 | buf[5], buf[6], buf[7]); |
| 352 | } |
| 353 | } else |
| 354 | pr_debug("VADC peripheral dumps got printed before\n"); |
| 355 | |
| 356 | vadc->vadc_debug_count++; |
| 357 | |
| 358 | rc = qpnp_vadc_enable(vadc, false); |
| 359 | if (rc < 0) { |
| 360 | pr_err("VADC disable failed with %d\n", rc); |
| 361 | return rc; |
| 362 | } |
| 363 | |
| 364 | return 0; |
| 365 | } |
| 366 | |
Jishnu Prakash | 32adff7 | 2019-07-08 15:30:21 +0530 | [diff] [blame] | 367 | static int qpnp_vadc_hc_check_conversion_status(struct qpnp_vadc_chip *vadc, |
| 368 | bool poll) |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 369 | { |
Jishnu Prakash | 32adff7 | 2019-07-08 15:30:21 +0530 | [diff] [blame] | 370 | int rc = 0, count = 0, retry; |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 371 | u8 status1 = 0; |
| 372 | |
Jishnu Prakash | 32adff7 | 2019-07-08 15:30:21 +0530 | [diff] [blame] | 373 | if (poll) |
| 374 | retry = QPNP_VADC_HC1_ERR_COUNT_POLL; |
| 375 | else |
| 376 | retry = QPNP_VADC_HC1_ERR_COUNT; |
| 377 | |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 378 | while (status1 != QPNP_VADC_STATUS1_EOC) { |
| 379 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1, 1); |
| 380 | if (rc < 0) |
| 381 | return rc; |
| 382 | status1 &= QPNP_VADC_STATUS1_REQ_STS_EOC_MASK; |
| 383 | if (status1 == QPNP_VADC_STATUS1_EOC) |
| 384 | break; |
| 385 | usleep_range(QPNP_VADC_HC1_CONV_TIME_MIN_US, |
| 386 | QPNP_VADC_HC1_CONV_TIME_MAX_US); |
| 387 | count++; |
Jishnu Prakash | 32adff7 | 2019-07-08 15:30:21 +0530 | [diff] [blame] | 388 | if (count > retry) { |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 389 | pr_err("retry error exceeded\n"); |
| 390 | rc = qpnp_vadc_status_debug(vadc); |
| 391 | if (rc < 0) |
| 392 | pr_err("VADC disable failed with %d\n", rc); |
| 393 | return -EINVAL; |
| 394 | } |
| 395 | } |
| 396 | |
| 397 | return rc; |
| 398 | } |
| 399 | |
| 400 | static int qpnp_vadc_hc_read_data(struct qpnp_vadc_chip *vadc, int *data) |
| 401 | { |
| 402 | int rc = 0; |
Jishnu Prakash | a53485d | 2018-03-18 17:14:27 +0530 | [diff] [blame] | 403 | u8 rslt_lsb = 0, rslt_msb = 0; |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 404 | |
| 405 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_HC1_DATA0, &rslt_lsb, 1); |
| 406 | if (rc < 0) { |
| 407 | pr_err("qpnp adc result read failed for data0\n"); |
| 408 | return rc; |
| 409 | } |
| 410 | |
| 411 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_HC1_DATA1, &rslt_msb, 1); |
| 412 | if (rc < 0) { |
| 413 | pr_err("qpnp adc result read failed for data1\n"); |
| 414 | return rc; |
| 415 | } |
| 416 | |
| 417 | *data = (rslt_msb << 8) | rslt_lsb; |
| 418 | |
| 419 | if (*data == QPNP_VADC_HC1_DATA_CHECK_USR) { |
| 420 | pr_err("Invalid data :0x%x\n", *data); |
| 421 | return -EINVAL; |
| 422 | } |
| 423 | |
| 424 | rc = qpnp_vadc_enable(vadc, false); |
| 425 | if (rc) { |
| 426 | pr_err("VADC disable failed\n"); |
| 427 | return rc; |
| 428 | } |
| 429 | |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 430 | |
| 431 | return rc; |
| 432 | } |
| 433 | |
Jishnu Prakash | 35141c3 | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 434 | static int qpnp_vadc_wait_for_eoc(struct qpnp_vadc_chip *vadc) |
| 435 | { |
| 436 | int ret; |
| 437 | |
| 438 | if (vadc->vadc_poll_eoc) { |
Jishnu Prakash | 32adff7 | 2019-07-08 15:30:21 +0530 | [diff] [blame] | 439 | ret = qpnp_vadc_hc_check_conversion_status(vadc, true); |
Jishnu Prakash | 35141c3 | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 440 | if (ret < 0) { |
| 441 | pr_err("polling mode conversion failed\n"); |
| 442 | return ret; |
| 443 | } |
| 444 | } else { |
| 445 | ret = wait_for_completion_timeout( |
| 446 | &vadc->adc->adc_rslt_completion, |
| 447 | QPNP_ADC_COMPLETION_TIMEOUT); |
| 448 | if (!ret) { |
Jishnu Prakash | 32adff7 | 2019-07-08 15:30:21 +0530 | [diff] [blame] | 449 | ret = qpnp_vadc_hc_check_conversion_status(vadc, false); |
Jishnu Prakash | 35141c3 | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 450 | if (ret < 0) { |
| 451 | pr_err("interrupt mode conversion failed\n"); |
| 452 | return ret; |
| 453 | } |
| 454 | pr_debug("End of conversion status set\n"); |
| 455 | } |
| 456 | } |
| 457 | return ret; |
| 458 | } |
| 459 | |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 460 | static void qpnp_vadc_hc_update_adc_dig_param(struct qpnp_vadc_chip *vadc, |
| 461 | struct qpnp_adc_amux_properties *amux_prop, u8 *data) |
| 462 | { |
| 463 | /* Update CAL value */ |
| 464 | *data &= ~QPNP_VADC_HC1_CAL_VAL; |
| 465 | *data |= (amux_prop->cal_val << QPNP_VADC_HC1_CAL_VAL_SHIFT); |
| 466 | |
| 467 | /* Update CAL select */ |
| 468 | *data &= ~QPNP_VADC_HC1_CAL_SEL_MASK; |
| 469 | *data |= (amux_prop->calib_type << QPNP_VADC_HC1_CAL_SEL_SHIFT); |
| 470 | |
| 471 | /* Update Decimation ratio select */ |
| 472 | *data &= ~QPNP_VADC_HC1_DEC_RATIO_SEL; |
| 473 | *data |= (amux_prop->decimation << QPNP_VADC_HC1_DEC_RATIO_SHIFT); |
| 474 | |
| 475 | pr_debug("VADC_DIG_PARAM value:0x%x\n", *data); |
| 476 | } |
| 477 | |
Jishnu Prakash | a2d0099 | 2018-11-16 17:09:49 +0530 | [diff] [blame] | 478 | static int qpnp_vadc_channel_check(struct qpnp_vadc_chip *vadc, u8 buf) |
| 479 | { |
| 480 | int rc = 0; |
| 481 | u8 chno = 0; |
| 482 | |
| 483 | rc = qpnp_vadc_read_reg(vadc, |
| 484 | QPNP_VADC_HC1_ADC_CH_SEL_CTL, &chno, 1); |
| 485 | if (rc < 0) { |
| 486 | pr_err("Channel reread failed\n"); |
| 487 | return rc; |
| 488 | } |
| 489 | |
| 490 | if (buf != chno) { |
| 491 | pr_debug("channel write fails once: written:0x%x actual:0x%x\n", |
| 492 | chno, buf); |
| 493 | |
| 494 | rc = qpnp_vadc_write_reg(vadc, |
| 495 | QPNP_VADC_HC1_ADC_CH_SEL_CTL, &buf, 1); |
| 496 | if (rc < 0) { |
| 497 | pr_err("qpnp adc register configure failed\n"); |
| 498 | return rc; |
| 499 | } |
| 500 | |
| 501 | rc = qpnp_vadc_read_reg(vadc, |
| 502 | QPNP_VADC_HC1_ADC_CH_SEL_CTL, &chno, 1); |
| 503 | if (rc < 0) { |
| 504 | pr_err("qpnp adc configure read failed\n"); |
| 505 | return rc; |
| 506 | } |
| 507 | |
| 508 | if (chno != buf) { |
| 509 | pr_err("Write fails twice: written: 0x%x\n", chno); |
| 510 | return -EINVAL; |
| 511 | } |
| 512 | } |
| 513 | return 0; |
| 514 | } |
| 515 | |
Jishnu Prakash | 35141c3 | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 516 | static int qpnp_vadc_hc_pre_configure_usb_in(struct qpnp_vadc_chip *vadc, |
| 517 | int dt_index) |
| 518 | { |
| 519 | int rc = 0; |
| 520 | u8 buf; |
| 521 | u8 dig_param = 0; |
| 522 | struct qpnp_adc_amux_properties conv; |
Jishnu Prakash | a2d0099 | 2018-11-16 17:09:49 +0530 | [diff] [blame] | 523 | bool channel_check = false; |
| 524 | |
| 525 | if (vadc->pmic_rev_id) |
| 526 | if (vadc->pmic_rev_id->pmic_subtype == PMI632_SUBTYPE) |
| 527 | channel_check = true; |
Jishnu Prakash | 35141c3 | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 528 | |
| 529 | /* Setup dig params for USB_IN_V */ |
| 530 | conv.decimation = DECIMATION_TYPE2; |
Jishnu Prakash | a5f6af2 | 2019-03-08 11:00:51 +0530 | [diff] [blame] | 531 | conv.cal_val = (enum qpnp_adc_cal_val)ADC_HC_ABS_CAL; |
Jishnu Prakash | 35141c3 | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 532 | conv.calib_type = vadc->adc->adc_channels[dt_index].calib_type; |
| 533 | |
| 534 | qpnp_vadc_hc_update_adc_dig_param(vadc, &conv, &dig_param); |
| 535 | |
| 536 | /* Increase calib interval and wait for other conversions to complete */ |
| 537 | buf = QPNP_VADC_CAL_DELAY_MEAS_SLOW; |
| 538 | rc = regmap_bulk_write(vadc->adc->regmap, |
| 539 | QPNP_VADC_CAL_DELAY_CTL_1, &buf, 1); |
| 540 | if (rc < 0) { |
| 541 | pr_err("qpnp adc write cal_delay failed with %d\n", rc); |
| 542 | return rc; |
| 543 | } |
| 544 | msleep(20); |
| 545 | |
| 546 | /* Read GND first */ |
| 547 | buf = VADC_VREF_GND; |
| 548 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HC1_ADC_CH_SEL_CTL, &buf, 1); |
| 549 | if (rc < 0) |
| 550 | return rc; |
| 551 | |
Jishnu Prakash | a2d0099 | 2018-11-16 17:09:49 +0530 | [diff] [blame] | 552 | if (channel_check) { |
| 553 | rc = qpnp_vadc_channel_check(vadc, buf); |
| 554 | if (rc) |
| 555 | return rc; |
| 556 | } |
| 557 | |
Jishnu Prakash | 35141c3 | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 558 | buf = QPNP_VADC_HC1_ADC_EN; |
| 559 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HC1_EN_CTL1, &buf, 1); |
| 560 | if (rc < 0) |
| 561 | return rc; |
| 562 | |
| 563 | if (!vadc->vadc_poll_eoc) |
| 564 | reinit_completion(&vadc->adc->adc_rslt_completion); |
| 565 | |
| 566 | buf = QPNP_VADC_HC1_CONV_REQ_START; |
| 567 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HC1_CONV_REQ, &buf, 1); |
| 568 | if (rc < 0) |
| 569 | return rc; |
| 570 | |
| 571 | /* Pre-configure USB_IN_V request */ |
| 572 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HC1_ADC_DIG_PARAM, |
| 573 | &dig_param, 1); |
| 574 | if (rc < 0) |
| 575 | return rc; |
| 576 | |
| 577 | buf = VADC_USB_IN_V_DIV_16_PM5; |
| 578 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HC1_ADC_CH_SEL_CTL, &buf, 1); |
| 579 | if (rc < 0) |
| 580 | return rc; |
| 581 | |
Jishnu Prakash | a2d0099 | 2018-11-16 17:09:49 +0530 | [diff] [blame] | 582 | if (channel_check) { |
| 583 | rc = qpnp_vadc_channel_check(vadc, buf); |
| 584 | if (rc) |
| 585 | return rc; |
| 586 | } |
| 587 | |
Jishnu Prakash | 35141c3 | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 588 | /* Wait for GND read to complete */ |
| 589 | rc = qpnp_vadc_wait_for_eoc(vadc); |
| 590 | if (rc < 0) |
| 591 | return rc; |
| 592 | |
| 593 | if (!vadc->vadc_poll_eoc) |
| 594 | reinit_completion(&vadc->adc->adc_rslt_completion); |
| 595 | |
| 596 | /* Start USB_IN_V read */ |
| 597 | buf = QPNP_VADC_HC1_CONV_REQ_START; |
| 598 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HC1_CONV_REQ, &buf, 1); |
| 599 | if (rc < 0) |
| 600 | return rc; |
| 601 | |
| 602 | return 0; |
| 603 | } |
| 604 | |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 605 | static int qpnp_vadc_hc_configure(struct qpnp_vadc_chip *vadc, |
| 606 | struct qpnp_adc_amux_properties *amux_prop) |
| 607 | { |
| 608 | int rc = 0; |
Jishnu Prakash | a2d0099 | 2018-11-16 17:09:49 +0530 | [diff] [blame] | 609 | u8 buf[5]; |
| 610 | u8 conv_req = 0; |
| 611 | bool channel_check = false; |
| 612 | |
| 613 | if (vadc->pmic_rev_id) |
| 614 | if (vadc->pmic_rev_id->pmic_subtype == PMI632_SUBTYPE) |
| 615 | channel_check = true; |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 616 | |
| 617 | /* Read registers 0x42 through 0x46 */ |
Jishnu Prakash | a2d0099 | 2018-11-16 17:09:49 +0530 | [diff] [blame] | 618 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_HC1_ADC_DIG_PARAM, buf, 5); |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 619 | if (rc < 0) { |
| 620 | pr_err("qpnp adc configure block read failed\n"); |
| 621 | return rc; |
| 622 | } |
| 623 | |
| 624 | /* ADC Digital param selection */ |
| 625 | qpnp_vadc_hc_update_adc_dig_param(vadc, amux_prop, &buf[0]); |
| 626 | |
| 627 | /* Update fast average sample value */ |
| 628 | buf[1] &= (u8) ~QPNP_VADC_HC1_FAST_AVG_SAMPLES_MASK; |
| 629 | buf[1] |= amux_prop->fast_avg_setup; |
| 630 | |
| 631 | /* Select ADC channel */ |
| 632 | buf[2] = amux_prop->amux_channel; |
| 633 | |
| 634 | /* Select hw settle delay for the channel */ |
| 635 | buf[3] &= (u8) ~QPNP_VADC_HC1_DELAY_CTL_MASK; |
| 636 | buf[3] |= amux_prop->hw_settle_time; |
| 637 | |
| 638 | /* Select ADC enable */ |
| 639 | buf[4] |= QPNP_VADC_HC1_ADC_EN; |
| 640 | |
| 641 | /* Select CONV request */ |
Jishnu Prakash | a2d0099 | 2018-11-16 17:09:49 +0530 | [diff] [blame] | 642 | conv_req = QPNP_VADC_HC1_CONV_REQ_START; |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 643 | |
| 644 | if (!vadc->vadc_poll_eoc) |
| 645 | reinit_completion(&vadc->adc->adc_rslt_completion); |
| 646 | |
| 647 | pr_debug("dig:0x%x, fast_avg:0x%x, channel:0x%x, hw_settle:0x%x\n", |
| 648 | buf[0], buf[1], buf[2], buf[3]); |
| 649 | |
| 650 | /* Block register write from 0x42 through 0x46 */ |
Jishnu Prakash | a2d0099 | 2018-11-16 17:09:49 +0530 | [diff] [blame] | 651 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HC1_ADC_DIG_PARAM, buf, 5); |
| 652 | if (rc < 0) { |
| 653 | pr_err("qpnp adc block register configure failed\n"); |
| 654 | return rc; |
| 655 | } |
| 656 | |
| 657 | if (channel_check) { |
| 658 | rc = qpnp_vadc_channel_check(vadc, buf[2]); |
| 659 | if (rc) |
| 660 | return rc; |
| 661 | } |
| 662 | |
| 663 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HC1_CONV_REQ, |
| 664 | &conv_req, 1); |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 665 | if (rc < 0) { |
| 666 | pr_err("qpnp adc block register configure failed\n"); |
| 667 | return rc; |
| 668 | } |
| 669 | |
| 670 | return 0; |
| 671 | } |
| 672 | |
| 673 | int32_t qpnp_vadc_hc_read(struct qpnp_vadc_chip *vadc, |
| 674 | enum qpnp_vadc_channels channel, |
| 675 | struct qpnp_vadc_result *result) |
| 676 | { |
| 677 | int rc = 0, scale_type, amux_prescaling, dt_index = 0, calib_type = 0; |
Jishnu Prakash | e213f1b | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 678 | u8 val = QPNP_VADC_CAL_DELAY_MEAS_SLOW; |
Jishnu Prakash | 35141c3 | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 679 | struct qpnp_adc_amux_properties amux_prop; |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 680 | |
| 681 | if (qpnp_vadc_is_valid(vadc)) |
| 682 | return -EPROBE_DEFER; |
| 683 | |
| 684 | mutex_lock(&vadc->adc->adc_lock); |
| 685 | |
| 686 | while ((vadc->adc->adc_channels[dt_index].channel_num |
| 687 | != channel) && (dt_index < vadc->max_channels_available)) |
| 688 | dt_index++; |
| 689 | |
| 690 | if (dt_index >= vadc->max_channels_available) { |
| 691 | pr_err("not a valid VADC channel:%d\n", channel); |
| 692 | rc = -EINVAL; |
| 693 | goto fail_unlock; |
| 694 | } |
| 695 | |
Jishnu Prakash | d09bc69 | 2018-05-02 10:54:28 +0530 | [diff] [blame] | 696 | if (!vadc->adc->adc_prop->is_pmic_5) { |
Jishnu Prakash | 0af5e3f | 2018-03-02 12:55:42 +0530 | [diff] [blame] | 697 | if (!vadc->vadc_init_calib) { |
| 698 | rc = qpnp_vadc_calib_device(vadc); |
| 699 | if (rc) { |
| 700 | pr_err("Calibration failed\n"); |
| 701 | goto fail_unlock; |
| 702 | } else { |
| 703 | vadc->vadc_init_calib = true; |
| 704 | } |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 705 | } |
| 706 | } |
| 707 | |
| 708 | calib_type = vadc->adc->adc_channels[dt_index].calib_type; |
| 709 | if (calib_type >= ADC_HC_CAL_SEL_NONE) { |
| 710 | pr_err("not a valid calib_type\n"); |
| 711 | rc = -EINVAL; |
| 712 | goto fail_unlock; |
| 713 | } |
| 714 | |
Jishnu Prakash | e213f1b | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 715 | if (channel == VADC_USB_IN_V_DIV_16_PM5 && |
| 716 | vadc->adc->adc_prop->is_pmic_5) { |
Jishnu Prakash | 35141c3 | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 717 | rc = qpnp_vadc_hc_pre_configure_usb_in(vadc, dt_index); |
Jishnu Prakash | e213f1b | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 718 | if (rc < 0) { |
Jishnu Prakash | 35141c3 | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 719 | pr_err("Configuring VADC channel failed with %d\n", rc); |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 720 | goto fail_unlock; |
| 721 | } |
| 722 | } else { |
Jishnu Prakash | 35141c3 | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 723 | amux_prop.decimation = |
| 724 | vadc->adc->adc_channels[dt_index].adc_decimation; |
| 725 | amux_prop.calib_type = |
| 726 | vadc->adc->adc_channels[dt_index].calib_type; |
| 727 | amux_prop.cal_val = vadc->adc->adc_channels[dt_index].cal_val; |
| 728 | amux_prop.fast_avg_setup = |
| 729 | vadc->adc->adc_channels[dt_index].fast_avg_setup; |
| 730 | amux_prop.amux_channel = channel; |
| 731 | amux_prop.hw_settle_time = |
| 732 | vadc->adc->adc_channels[dt_index].hw_settle_time; |
| 733 | |
| 734 | rc = qpnp_vadc_hc_configure(vadc, &amux_prop); |
| 735 | if (rc < 0) { |
| 736 | pr_err("Configuring VADC channel failed with %d\n", rc); |
| 737 | goto fail_unlock; |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 738 | } |
| 739 | } |
| 740 | |
Jishnu Prakash | 35141c3 | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 741 | rc = qpnp_vadc_wait_for_eoc(vadc); |
| 742 | if (rc < 0) |
| 743 | goto fail_unlock; |
Jishnu Prakash | e213f1b | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 744 | |
| 745 | if (channel == VADC_USB_IN_V_DIV_16_PM5 && |
| 746 | vadc->adc->adc_prop->is_pmic_5) { |
Jishnu Prakash | 35141c3 | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 747 | val = QPNP_VADC_CAL_DELAY_MEAS_DEFAULT; |
Jishnu Prakash | e213f1b | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 748 | rc = regmap_bulk_write(vadc->adc->regmap, |
| 749 | QPNP_VADC_CAL_DELAY_CTL_1, &val, 1); |
| 750 | if (rc < 0) { |
| 751 | pr_err("qpnp adc write cal_delay failed with %d\n", rc); |
Jishnu Prakash | 51e6971 | 2019-08-30 12:23:07 +0530 | [diff] [blame] | 752 | goto fail_unlock; |
Jishnu Prakash | e213f1b | 2018-06-28 13:45:40 +0530 | [diff] [blame] | 753 | } |
| 754 | } |
| 755 | |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 756 | rc = qpnp_vadc_hc_read_data(vadc, &result->adc_code); |
| 757 | if (rc) { |
| 758 | pr_err("qpnp vadc read adc code failed with %d\n", rc); |
| 759 | goto fail_unlock; |
| 760 | } |
| 761 | |
| 762 | amux_prescaling = |
| 763 | vadc->adc->adc_channels[dt_index].chan_path_prescaling; |
| 764 | |
| 765 | if (amux_prescaling >= PATH_SCALING_NONE) { |
| 766 | rc = -EINVAL; |
| 767 | goto fail_unlock; |
| 768 | } |
| 769 | |
| 770 | vadc->adc->amux_prop->chan_prop->offset_gain_numerator = |
| 771 | qpnp_vadc_amux_scaling_ratio[amux_prescaling].num; |
| 772 | vadc->adc->amux_prop->chan_prop->offset_gain_denominator = |
| 773 | qpnp_vadc_amux_scaling_ratio[amux_prescaling].den; |
| 774 | |
| 775 | scale_type = vadc->adc->adc_channels[dt_index].adc_scale_fn; |
| 776 | if (scale_type >= SCALE_NONE) { |
| 777 | rc = -EBADF; |
| 778 | goto fail_unlock; |
| 779 | } |
| 780 | |
| 781 | /* Note: Scaling functions for VADC_HC do not need offset/gain */ |
| 782 | vadc_scale_fn[scale_type].chan(vadc, result->adc_code, |
| 783 | vadc->adc->adc_prop, vadc->adc->amux_prop->chan_prop, result); |
| 784 | |
| 785 | pr_debug("channel=0x%x, adc_code=0x%x adc_result=%lld\n", |
| 786 | channel, result->adc_code, result->physical); |
| 787 | |
| 788 | fail_unlock: |
| 789 | mutex_unlock(&vadc->adc->adc_lock); |
| 790 | |
| 791 | return rc; |
| 792 | } |
| 793 | EXPORT_SYMBOL(qpnp_vadc_hc_read); |
| 794 | |
| 795 | static int32_t qpnp_vadc_configure(struct qpnp_vadc_chip *vadc, |
| 796 | struct qpnp_adc_amux_properties *chan_prop) |
| 797 | { |
| 798 | u8 decimation = 0, conv_sequence = 0, conv_sequence_trig = 0; |
| 799 | u8 mode_ctrl = 0, meas_int_op_ctl_data = 0, buf = 0; |
| 800 | int rc = 0; |
| 801 | |
| 802 | /* Mode selection */ |
| 803 | mode_ctrl |= ((chan_prop->mode_sel << QPNP_VADC_OP_MODE_SHIFT) | |
| 804 | (QPNP_VADC_TRIM_EN | QPNP_VADC_AMUX_TRIM_EN)); |
| 805 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_MODE_CTL, &mode_ctrl, 1); |
| 806 | if (rc < 0) { |
| 807 | pr_err("Mode configure write error\n"); |
| 808 | return rc; |
| 809 | } |
| 810 | |
| 811 | /* Channel selection */ |
| 812 | buf = chan_prop->amux_channel; |
| 813 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_CH_SEL_CTL, &buf, 1); |
| 814 | if (rc < 0) { |
| 815 | pr_err("Channel configure error\n"); |
| 816 | return rc; |
| 817 | } |
| 818 | |
| 819 | /* Digital parameter setup */ |
| 820 | decimation = chan_prop->decimation << |
| 821 | QPNP_VADC_DIG_DEC_RATIO_SEL_SHIFT; |
| 822 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_DIG_PARAM, &decimation, 1); |
| 823 | if (rc < 0) { |
| 824 | pr_err("Digital parameter configure write error\n"); |
| 825 | return rc; |
| 826 | } |
| 827 | |
| 828 | /* HW settling time delay */ |
| 829 | buf = chan_prop->hw_settle_time; |
| 830 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HW_SETTLE_DELAY, &buf, 1); |
| 831 | if (rc < 0) { |
| 832 | pr_err("HW settling time setup error\n"); |
| 833 | return rc; |
| 834 | } |
| 835 | |
| 836 | pr_debug("mode:%d, channel:%d, decimation:%d, hw_settle:%d\n", |
| 837 | mode_ctrl, chan_prop->amux_channel, decimation, |
| 838 | chan_prop->hw_settle_time); |
| 839 | |
| 840 | if (chan_prop->mode_sel == (ADC_OP_NORMAL_MODE << |
| 841 | QPNP_VADC_OP_MODE_SHIFT)) { |
| 842 | /* Normal measurement mode */ |
| 843 | buf = chan_prop->fast_avg_setup; |
| 844 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_FAST_AVG_CTL, |
| 845 | &buf, 1); |
| 846 | if (rc < 0) { |
| 847 | pr_err("Fast averaging configure error\n"); |
| 848 | return rc; |
| 849 | } |
| 850 | /* Ensure MEAS_INTERVAL_OP_CTL is set to 0 */ |
| 851 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_MEAS_INTERVAL_OP_CTL, |
| 852 | &meas_int_op_ctl_data, 1); |
| 853 | if (rc < 0) { |
| 854 | pr_err("Measurement interval OP configure error\n"); |
| 855 | return rc; |
| 856 | } |
| 857 | } else if (chan_prop->mode_sel == (ADC_OP_CONVERSION_SEQUENCER << |
| 858 | QPNP_VADC_OP_MODE_SHIFT)) { |
| 859 | /* Conversion sequence mode */ |
| 860 | conv_sequence = ((ADC_SEQ_HOLD_100US << |
| 861 | QPNP_VADC_CONV_SEQ_HOLDOFF_SHIFT) | |
| 862 | ADC_CONV_SEQ_TIMEOUT_5MS); |
| 863 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_CONV_SEQ_CTL, |
| 864 | &conv_sequence, 1); |
| 865 | if (rc < 0) { |
| 866 | pr_err("Conversion sequence error\n"); |
| 867 | return rc; |
| 868 | } |
| 869 | |
| 870 | conv_sequence_trig = ((QPNP_VADC_CONV_SEQ_RISING_EDGE << |
| 871 | QPNP_VADC_CONV_SEQ_EDGE_SHIFT) | |
| 872 | chan_prop->trigger_channel); |
| 873 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_CONV_SEQ_TRIG_CTL, |
| 874 | &conv_sequence_trig, 1); |
| 875 | if (rc < 0) { |
| 876 | pr_err("Conversion trigger error\n"); |
| 877 | return rc; |
| 878 | } |
| 879 | } else if (chan_prop->mode_sel == ADC_OP_MEASUREMENT_INTERVAL) { |
| 880 | buf = QPNP_VADC_MEAS_INTERVAL_OP_SET; |
| 881 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_MEAS_INTERVAL_OP_CTL, |
| 882 | &buf, 1); |
| 883 | if (rc < 0) { |
| 884 | pr_err("Measurement interval OP configure error\n"); |
| 885 | return rc; |
| 886 | } |
| 887 | } |
| 888 | |
| 889 | if (!vadc->vadc_poll_eoc) |
| 890 | reinit_completion(&vadc->adc->adc_rslt_completion); |
| 891 | |
| 892 | rc = qpnp_vadc_enable(vadc, true); |
| 893 | if (rc) |
| 894 | return rc; |
| 895 | |
| 896 | if (!vadc->vadc_iadc_sync_lock) { |
| 897 | /* Request conversion */ |
| 898 | buf = QPNP_VADC_CONV_REQ_SET; |
| 899 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_CONV_REQ, &buf, 1); |
| 900 | if (rc < 0) { |
| 901 | pr_err("Request conversion failed\n"); |
| 902 | return rc; |
| 903 | } |
| 904 | } |
| 905 | |
| 906 | return 0; |
| 907 | } |
| 908 | |
| 909 | static int32_t qpnp_vadc_read_conversion_result(struct qpnp_vadc_chip *vadc, |
| 910 | int32_t *data) |
| 911 | { |
| 912 | uint8_t rslt_lsb, rslt_msb; |
| 913 | int rc = 0, status = 0; |
| 914 | |
| 915 | status = qpnp_vadc_read_reg(vadc, QPNP_VADC_DATA0, &rslt_lsb, 1); |
| 916 | if (status < 0) { |
| 917 | pr_err("qpnp adc result read failed for data0\n"); |
| 918 | goto fail; |
| 919 | } |
| 920 | |
| 921 | status = qpnp_vadc_read_reg(vadc, QPNP_VADC_DATA1, &rslt_msb, 1); |
| 922 | if (status < 0) { |
| 923 | pr_err("qpnp adc result read failed for data1\n"); |
| 924 | goto fail; |
| 925 | } |
| 926 | |
| 927 | *data = (rslt_msb << 8) | rslt_lsb; |
| 928 | |
| 929 | fail: |
| 930 | rc = qpnp_vadc_enable(vadc, false); |
| 931 | if (rc) |
| 932 | return rc; |
| 933 | |
| 934 | return status; |
| 935 | } |
| 936 | |
| 937 | static int32_t qpnp_vadc_read_status(struct qpnp_vadc_chip *vadc, int mode_sel) |
| 938 | { |
| 939 | u8 status1, status2, status2_conv_seq_state; |
| 940 | u8 status_err = QPNP_VADC_CONV_TIMEOUT_ERR; |
| 941 | int rc; |
| 942 | |
| 943 | switch (mode_sel) { |
| 944 | case (ADC_OP_CONVERSION_SEQUENCER << QPNP_VADC_OP_MODE_SHIFT): |
| 945 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1, 1); |
| 946 | if (rc) { |
| 947 | pr_err("qpnp_vadc read mask interrupt failed\n"); |
| 948 | return rc; |
| 949 | } |
| 950 | |
| 951 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS2, &status2, 1); |
| 952 | if (rc) { |
| 953 | pr_err("qpnp_vadc read mask interrupt failed\n"); |
| 954 | return rc; |
| 955 | } |
| 956 | |
| 957 | if (!(status2 & ~QPNP_VADC_STATUS2_CONV_SEQ_TIMEOUT_STS) && |
| 958 | (status1 & (~QPNP_VADC_STATUS1_REQ_STS | |
| 959 | QPNP_VADC_STATUS1_EOC))) { |
| 960 | rc = status_err; |
| 961 | return rc; |
| 962 | } |
| 963 | |
| 964 | status2_conv_seq_state = status2 >> |
| 965 | QPNP_VADC_STATUS2_CONV_SEQ_STATE_SHIFT; |
| 966 | if (status2_conv_seq_state != ADC_CONV_SEQ_IDLE) { |
| 967 | pr_err("qpnp vadc seq error with status %d\n", |
| 968 | status2); |
| 969 | rc = -EINVAL; |
| 970 | return rc; |
| 971 | } |
| 972 | } |
| 973 | |
| 974 | return 0; |
| 975 | } |
| 976 | |
| 977 | static void qpnp_vadc_work(struct work_struct *work) |
| 978 | { |
| 979 | struct qpnp_vadc_chip *vadc = container_of(work, |
| 980 | struct qpnp_vadc_chip, trigger_completion_work); |
| 981 | |
| 982 | if (qpnp_vadc_is_valid(vadc) < 0) |
| 983 | return; |
| 984 | |
| 985 | complete(&vadc->adc->adc_rslt_completion); |
| 986 | } |
| 987 | |
| 988 | static void qpnp_vadc_low_thr_fn(struct work_struct *work) |
| 989 | { |
| 990 | struct qpnp_vadc_chip *vadc = container_of(work, |
| 991 | struct qpnp_vadc_chip, trigger_low_thr_work); |
| 992 | |
| 993 | vadc->state_copy->meas_int_mode = false; |
| 994 | vadc->state_copy->meas_int_request_in_queue = false; |
| 995 | vadc->state_copy->param->threshold_notification( |
| 996 | ADC_TM_LOW_STATE, |
| 997 | vadc->state_copy->param->btm_ctx); |
| 998 | } |
| 999 | |
| 1000 | static void qpnp_vadc_high_thr_fn(struct work_struct *work) |
| 1001 | { |
| 1002 | struct qpnp_vadc_chip *vadc = container_of(work, |
| 1003 | struct qpnp_vadc_chip, trigger_high_thr_work); |
| 1004 | |
| 1005 | vadc->state_copy->meas_int_mode = false; |
| 1006 | vadc->state_copy->meas_int_request_in_queue = false; |
| 1007 | vadc->state_copy->param->threshold_notification( |
| 1008 | ADC_TM_HIGH_STATE, |
| 1009 | vadc->state_copy->param->btm_ctx); |
| 1010 | } |
| 1011 | |
| 1012 | static irqreturn_t qpnp_vadc_isr(int irq, void *dev_id) |
| 1013 | { |
| 1014 | struct qpnp_vadc_chip *vadc = dev_id; |
| 1015 | |
| 1016 | schedule_work(&vadc->trigger_completion_work); |
| 1017 | |
| 1018 | return IRQ_HANDLED; |
| 1019 | } |
| 1020 | |
| 1021 | static irqreturn_t qpnp_vadc_low_thr_isr(int irq, void *data) |
| 1022 | { |
| 1023 | struct qpnp_vadc_chip *vadc = data; |
| 1024 | u8 mode_ctl = 0, mode = 0; |
| 1025 | int rc = 0; |
| 1026 | |
| 1027 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_MODE_CTL, &mode, 1); |
| 1028 | if (rc < 0) { |
| 1029 | pr_err("mode ctl register read failed with %d\n", rc); |
| 1030 | return rc; |
| 1031 | } |
| 1032 | |
| 1033 | if (!(mode & QPNP_VADC_MEAS_INT_MODE_MASK)) { |
| 1034 | pr_debug("Spurious VADC threshold 0x%x\n", mode); |
| 1035 | return IRQ_HANDLED; |
| 1036 | } |
| 1037 | |
| 1038 | mode_ctl = ADC_OP_NORMAL_MODE; |
| 1039 | /* Set measurement in single measurement mode */ |
| 1040 | qpnp_vadc_mode_select(vadc, mode_ctl); |
| 1041 | qpnp_vadc_enable(vadc, false); |
| 1042 | schedule_work(&vadc->trigger_low_thr_work); |
| 1043 | |
| 1044 | return IRQ_HANDLED; |
| 1045 | } |
| 1046 | |
| 1047 | static irqreturn_t qpnp_vadc_high_thr_isr(int irq, void *data) |
| 1048 | { |
| 1049 | struct qpnp_vadc_chip *vadc = data; |
| 1050 | u8 mode_ctl = 0, mode = 0; |
| 1051 | int rc = 0; |
| 1052 | |
| 1053 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_MODE_CTL, &mode, 1); |
| 1054 | if (rc < 0) { |
| 1055 | pr_err("mode ctl register read failed with %d\n", rc); |
| 1056 | return rc; |
| 1057 | } |
| 1058 | |
| 1059 | if (!(mode & QPNP_VADC_MEAS_INT_MODE_MASK)) { |
| 1060 | pr_debug("Spurious VADC threshold 0x%x\n", mode); |
| 1061 | return IRQ_HANDLED; |
| 1062 | } |
| 1063 | |
| 1064 | mode_ctl = ADC_OP_NORMAL_MODE; |
| 1065 | /* Set measurement in single measurement mode */ |
| 1066 | qpnp_vadc_mode_select(vadc, mode_ctl); |
| 1067 | qpnp_vadc_enable(vadc, false); |
| 1068 | schedule_work(&vadc->trigger_high_thr_work); |
| 1069 | |
| 1070 | return IRQ_HANDLED; |
| 1071 | } |
| 1072 | |
| 1073 | static int32_t qpnp_vadc_version_check(struct qpnp_vadc_chip *dev) |
| 1074 | { |
| 1075 | uint8_t revision; |
| 1076 | int rc; |
| 1077 | |
| 1078 | rc = qpnp_vadc_read_reg(dev, QPNP_VADC_REVISION2, &revision, 1); |
| 1079 | if (rc < 0) { |
| 1080 | pr_err("qpnp adc result read failed with %d\n", rc); |
| 1081 | return rc; |
| 1082 | } |
| 1083 | |
| 1084 | if (revision < QPNP_VADC_SUPPORTED_REVISION2) { |
| 1085 | pr_err("VADC Version not supported\n"); |
| 1086 | return -EINVAL; |
| 1087 | } |
| 1088 | |
| 1089 | return 0; |
| 1090 | } |
| 1091 | |
| 1092 | static int32_t |
| 1093 | qpnp_vadc_channel_post_scaling_calib_check(struct qpnp_vadc_chip *vadc, |
| 1094 | int channel) |
| 1095 | { |
| 1096 | int version, rc = 0; |
| 1097 | |
| 1098 | version = qpnp_adc_get_revid_version(vadc->dev); |
| 1099 | |
| 1100 | if (version == QPNP_REV_ID_PM8950_1_0) { |
| 1101 | if ((channel == LR_MUX7_HW_ID) || |
| 1102 | (channel == P_MUX2_1_1) || |
| 1103 | (channel == LR_MUX3_XO_THERM) || |
| 1104 | (channel == LR_MUX3_BUF_XO_THERM_BUF) || |
| 1105 | (channel == P_MUX4_1_1)) { |
| 1106 | vadc->adc->amux_prop->chan_prop->calib_type = |
| 1107 | CALIB_ABSOLUTE; |
| 1108 | return rc; |
| 1109 | } |
| 1110 | } |
| 1111 | |
| 1112 | return -EINVAL; |
| 1113 | } |
| 1114 | |
| 1115 | #define QPNP_VBAT_COEFF_1 3000 |
| 1116 | #define QPNP_VBAT_COEFF_2 45810000 |
| 1117 | #define QPNP_VBAT_COEFF_3 100000 |
| 1118 | #define QPNP_VBAT_COEFF_4 3500 |
| 1119 | #define QPNP_VBAT_COEFF_5 80000000 |
| 1120 | #define QPNP_VBAT_COEFF_6 4400 |
| 1121 | #define QPNP_VBAT_COEFF_7 32200000 |
| 1122 | #define QPNP_VBAT_COEFF_8 3880 |
| 1123 | #define QPNP_VBAT_COEFF_9 5770 |
| 1124 | #define QPNP_VBAT_COEFF_10 3660 |
| 1125 | #define QPNP_VBAT_COEFF_11 5320 |
| 1126 | #define QPNP_VBAT_COEFF_12 8060000 |
| 1127 | #define QPNP_VBAT_COEFF_13 102640000 |
| 1128 | #define QPNP_VBAT_COEFF_14 22220000 |
| 1129 | #define QPNP_VBAT_COEFF_15 83060000 |
| 1130 | #define QPNP_VBAT_COEFF_16 2810 |
| 1131 | #define QPNP_VBAT_COEFF_17 5260 |
| 1132 | #define QPNP_VBAT_COEFF_18 8027 |
| 1133 | #define QPNP_VBAT_COEFF_19 2347 |
| 1134 | #define QPNP_VBAT_COEFF_20 6043 |
| 1135 | #define QPNP_VBAT_COEFF_21 1914 |
| 1136 | #define QPNP_VBAT_OFFSET_SMIC 9446 |
| 1137 | #define QPNP_VBAT_OFFSET_GF 9441 |
| 1138 | #define QPNP_OCV_OFFSET_SMIC 4596 |
| 1139 | #define QPNP_OCV_OFFSET_GF 5896 |
| 1140 | #define QPNP_VBAT_COEFF_22 6800 |
| 1141 | #define QPNP_VBAT_COEFF_23 3500 |
| 1142 | #define QPNP_VBAT_COEFF_24 4360 |
| 1143 | #define QPNP_VBAT_COEFF_25 8060 |
| 1144 | #define QPNP_VBAT_COEFF_26 7895 |
| 1145 | #define QPNP_VBAT_COEFF_27 5658 |
| 1146 | #define QPNP_VBAT_COEFF_28 5760 |
| 1147 | #define QPNP_VBAT_COEFF_29 7900 |
| 1148 | #define QPNP_VBAT_COEFF_30 5660 |
| 1149 | #define QPNP_VBAT_COEFF_31 3620 |
| 1150 | #define QPNP_VBAT_COEFF_32 1230 |
| 1151 | #define QPNP_VBAT_COEFF_33 5760 |
| 1152 | #define QPNP_VBAT_COEFF_34 4080 |
| 1153 | #define QPNP_VBAT_COEFF_35 7000 |
| 1154 | #define QPNP_VBAT_COEFF_36 3040 |
| 1155 | #define QPNP_VBAT_COEFF_37 3850 |
| 1156 | #define QPNP_VBAT_COEFF_38 5000 |
| 1157 | #define QPNP_VBAT_COEFF_39 2610 |
| 1158 | #define QPNP_VBAT_COEFF_40 4190 |
| 1159 | #define QPNP_VBAT_COEFF_41 5800 |
| 1160 | #define QPNP_VBAT_COEFF_42 2620 |
| 1161 | #define QPNP_VBAT_COEFF_43 4030 |
| 1162 | #define QPNP_VBAT_COEFF_44 3230 |
| 1163 | #define QPNP_VBAT_COEFF_45 3450 |
| 1164 | #define QPNP_VBAT_COEFF_46 2120 |
| 1165 | #define QPNP_VBAT_COEFF_47 3560 |
| 1166 | #define QPNP_VBAT_COEFF_48 2190 |
| 1167 | #define QPNP_VBAT_COEFF_49 4180 |
| 1168 | #define QPNP_VBAT_COEFF_50 27800000 |
| 1169 | #define QPNP_VBAT_COEFF_51 5110 |
| 1170 | #define QPNP_VBAT_COEFF_52 34444000 |
| 1171 | |
| 1172 | static int32_t qpnp_ocv_comp(int64_t *result, |
| 1173 | struct qpnp_vadc_chip *vadc, int64_t die_temp) |
| 1174 | { |
| 1175 | int64_t temp_var = 0, offset = 0; |
| 1176 | int64_t old = *result; |
| 1177 | int version; |
| 1178 | |
| 1179 | version = qpnp_adc_get_revid_version(vadc->dev); |
| 1180 | if (version == -EINVAL) |
| 1181 | return 0; |
| 1182 | |
| 1183 | if (version == QPNP_REV_ID_8026_2_2) { |
| 1184 | if (die_temp > 25000) |
| 1185 | return 0; |
| 1186 | } |
| 1187 | |
| 1188 | switch (version) { |
| 1189 | case QPNP_REV_ID_8941_3_1: |
| 1190 | switch (vadc->id) { |
| 1191 | case COMP_ID_TSMC: |
| 1192 | temp_var = ((die_temp - 25000) * |
| 1193 | (-QPNP_VBAT_COEFF_4)); |
| 1194 | break; |
| 1195 | default: |
| 1196 | case COMP_ID_GF: |
| 1197 | temp_var = ((die_temp - 25000) * |
| 1198 | (-QPNP_VBAT_COEFF_1)); |
| 1199 | break; |
| 1200 | } |
| 1201 | break; |
| 1202 | case QPNP_REV_ID_8026_1_0: |
| 1203 | switch (vadc->id) { |
| 1204 | case COMP_ID_TSMC: |
| 1205 | temp_var = (((die_temp * |
| 1206 | (-QPNP_VBAT_COEFF_10)) |
| 1207 | - QPNP_VBAT_COEFF_14)); |
| 1208 | break; |
| 1209 | default: |
| 1210 | case COMP_ID_GF: |
| 1211 | temp_var = (((die_temp * |
| 1212 | (-QPNP_VBAT_COEFF_8)) |
| 1213 | + QPNP_VBAT_COEFF_12)); |
| 1214 | break; |
| 1215 | } |
| 1216 | break; |
| 1217 | case QPNP_REV_ID_8026_2_0: |
| 1218 | case QPNP_REV_ID_8026_2_1: |
| 1219 | switch (vadc->id) { |
| 1220 | case COMP_ID_TSMC: |
| 1221 | temp_var = ((die_temp - 25000) * |
| 1222 | (-QPNP_VBAT_COEFF_10)); |
| 1223 | break; |
| 1224 | default: |
| 1225 | case COMP_ID_GF: |
| 1226 | temp_var = ((die_temp - 25000) * |
| 1227 | (-QPNP_VBAT_COEFF_8)); |
| 1228 | break; |
| 1229 | } |
| 1230 | break; |
| 1231 | case QPNP_REV_ID_8026_2_2: |
| 1232 | switch (vadc->id) { |
| 1233 | case COMP_ID_TSMC: |
| 1234 | *result -= QPNP_VBAT_COEFF_22; |
| 1235 | temp_var = (die_temp - 25000) * |
| 1236 | QPNP_VBAT_COEFF_24; |
| 1237 | break; |
| 1238 | default: |
| 1239 | case COMP_ID_GF: |
| 1240 | *result -= QPNP_VBAT_COEFF_22; |
| 1241 | temp_var = (die_temp - 25000) * |
| 1242 | QPNP_VBAT_COEFF_25; |
| 1243 | break; |
| 1244 | } |
| 1245 | break; |
| 1246 | case QPNP_REV_ID_8110_2_0: |
| 1247 | switch (vadc->id) { |
| 1248 | case COMP_ID_SMIC: |
| 1249 | *result -= QPNP_OCV_OFFSET_SMIC; |
| 1250 | if (die_temp < 25000) |
| 1251 | temp_var = QPNP_VBAT_COEFF_18; |
| 1252 | else |
| 1253 | temp_var = QPNP_VBAT_COEFF_19; |
| 1254 | temp_var = (die_temp - 25000) * temp_var; |
| 1255 | break; |
| 1256 | default: |
| 1257 | case COMP_ID_GF: |
| 1258 | *result -= QPNP_OCV_OFFSET_GF; |
| 1259 | if (die_temp < 25000) |
| 1260 | temp_var = QPNP_VBAT_COEFF_20; |
| 1261 | else |
| 1262 | temp_var = QPNP_VBAT_COEFF_21; |
| 1263 | temp_var = (die_temp - 25000) * temp_var; |
| 1264 | break; |
| 1265 | } |
| 1266 | break; |
| 1267 | case QPNP_REV_ID_8916_1_0: |
| 1268 | switch (vadc->id) { |
| 1269 | case COMP_ID_SMIC: |
| 1270 | if (die_temp < 25000) |
| 1271 | temp_var = QPNP_VBAT_COEFF_26; |
| 1272 | else |
| 1273 | temp_var = QPNP_VBAT_COEFF_27; |
| 1274 | temp_var = (die_temp - 25000) * temp_var; |
| 1275 | break; |
| 1276 | default: |
| 1277 | case COMP_ID_GF: |
| 1278 | offset = QPNP_OCV_OFFSET_GF; |
| 1279 | if (die_temp < 25000) |
| 1280 | temp_var = QPNP_VBAT_COEFF_26; |
| 1281 | else |
| 1282 | temp_var = QPNP_VBAT_COEFF_27; |
| 1283 | temp_var = (die_temp - 25000) * temp_var; |
| 1284 | break; |
| 1285 | } |
| 1286 | break; |
| 1287 | case QPNP_REV_ID_8916_1_1: |
| 1288 | switch (vadc->id) { |
| 1289 | /* FAB_ID is zero */ |
| 1290 | case COMP_ID_GF: |
| 1291 | if (die_temp < 25000) |
| 1292 | temp_var = QPNP_VBAT_COEFF_29; |
| 1293 | else |
| 1294 | temp_var = QPNP_VBAT_COEFF_30; |
| 1295 | temp_var = (die_temp - 25000) * temp_var; |
| 1296 | break; |
| 1297 | /* FAB_ID is non-zero */ |
| 1298 | default: |
| 1299 | if (die_temp < 25000) |
| 1300 | temp_var = QPNP_VBAT_COEFF_31; |
| 1301 | else |
| 1302 | temp_var = (-QPNP_VBAT_COEFF_32); |
| 1303 | temp_var = (die_temp - 25000) * temp_var; |
| 1304 | break; |
| 1305 | } |
| 1306 | break; |
| 1307 | case QPNP_REV_ID_8916_2_0: |
| 1308 | switch (vadc->id) { |
| 1309 | case COMP_ID_SMIC: |
| 1310 | offset = (-QPNP_VBAT_COEFF_38); |
| 1311 | if (die_temp < 0) |
| 1312 | temp_var = die_temp * QPNP_VBAT_COEFF_36; |
| 1313 | else if (die_temp > 40000) |
| 1314 | temp_var = ((die_temp - 40000) * |
| 1315 | (-QPNP_VBAT_COEFF_37)); |
| 1316 | break; |
| 1317 | case COMP_ID_TSMC: |
| 1318 | if (die_temp < 10000) |
| 1319 | temp_var = ((die_temp - 10000) * |
| 1320 | QPNP_VBAT_COEFF_41); |
| 1321 | else if (die_temp > 50000) |
| 1322 | temp_var = ((die_temp - 50000) * |
| 1323 | (-QPNP_VBAT_COEFF_42)); |
| 1324 | break; |
| 1325 | default: |
| 1326 | case COMP_ID_GF: |
| 1327 | if (die_temp < 20000) |
| 1328 | temp_var = ((die_temp - 20000) * |
| 1329 | QPNP_VBAT_COEFF_45); |
| 1330 | else if (die_temp > 40000) |
| 1331 | temp_var = ((die_temp - 40000) * |
| 1332 | (-QPNP_VBAT_COEFF_46)); |
| 1333 | break; |
| 1334 | } |
| 1335 | break; |
| 1336 | case QPNP_REV_ID_8909_1_0: |
| 1337 | switch (vadc->id) { |
| 1338 | case COMP_ID_SMIC: |
| 1339 | temp_var = (-QPNP_VBAT_COEFF_50); |
| 1340 | break; |
| 1341 | } |
| 1342 | break; |
| 1343 | case QPNP_REV_ID_8909_1_1: |
| 1344 | switch (vadc->id) { |
| 1345 | case COMP_ID_SMIC: |
| 1346 | temp_var = (QPNP_VBAT_COEFF_52); |
| 1347 | break; |
| 1348 | } |
| 1349 | break; |
| 1350 | default: |
| 1351 | temp_var = 0; |
| 1352 | break; |
| 1353 | } |
| 1354 | |
| 1355 | temp_var = div64_s64(temp_var, QPNP_VBAT_COEFF_3); |
| 1356 | |
| 1357 | temp_var = 1000000 + temp_var; |
| 1358 | |
| 1359 | *result = *result * temp_var; |
| 1360 | |
| 1361 | if (offset) |
| 1362 | *result -= offset; |
| 1363 | |
| 1364 | *result = div64_s64(*result, 1000000); |
| 1365 | pr_debug("%lld compensated into %lld\n", old, *result); |
| 1366 | |
| 1367 | return 0; |
| 1368 | } |
| 1369 | |
| 1370 | static int32_t qpnp_vbat_sns_comp(int64_t *result, |
| 1371 | struct qpnp_vadc_chip *vadc, int64_t die_temp) |
| 1372 | { |
| 1373 | int64_t temp_var = 0, offset = 0; |
| 1374 | int64_t old = *result; |
| 1375 | int version; |
| 1376 | |
| 1377 | version = qpnp_adc_get_revid_version(vadc->dev); |
| 1378 | if (version == -EINVAL) |
| 1379 | return 0; |
| 1380 | |
| 1381 | if (version != QPNP_REV_ID_8941_3_1) { |
| 1382 | /* min(die_temp_c, 60_degC) */ |
| 1383 | if (die_temp > 60000) |
| 1384 | die_temp = 60000; |
| 1385 | } |
| 1386 | |
| 1387 | switch (version) { |
| 1388 | case QPNP_REV_ID_8941_3_1: |
| 1389 | switch (vadc->id) { |
| 1390 | case COMP_ID_TSMC: |
| 1391 | temp_var = ((die_temp - 25000) * |
| 1392 | (-QPNP_VBAT_COEFF_1)); |
| 1393 | break; |
| 1394 | default: |
| 1395 | case COMP_ID_GF: |
| 1396 | /* min(die_temp_c, 60_degC) */ |
| 1397 | if (die_temp > 60000) |
| 1398 | die_temp = 60000; |
| 1399 | temp_var = ((die_temp - 25000) * |
| 1400 | (-QPNP_VBAT_COEFF_1)); |
| 1401 | break; |
| 1402 | } |
| 1403 | break; |
| 1404 | case QPNP_REV_ID_8026_1_0: |
| 1405 | switch (vadc->id) { |
| 1406 | case COMP_ID_TSMC: |
| 1407 | temp_var = (((die_temp * |
| 1408 | (-QPNP_VBAT_COEFF_11)) |
| 1409 | + QPNP_VBAT_COEFF_15)); |
| 1410 | break; |
| 1411 | default: |
| 1412 | case COMP_ID_GF: |
| 1413 | temp_var = (((die_temp * |
| 1414 | (-QPNP_VBAT_COEFF_9)) |
| 1415 | + QPNP_VBAT_COEFF_13)); |
| 1416 | break; |
| 1417 | } |
| 1418 | break; |
| 1419 | case QPNP_REV_ID_8026_2_0: |
| 1420 | case QPNP_REV_ID_8026_2_1: |
| 1421 | switch (vadc->id) { |
| 1422 | case COMP_ID_TSMC: |
| 1423 | temp_var = ((die_temp - 25000) * |
| 1424 | (-QPNP_VBAT_COEFF_11)); |
| 1425 | break; |
| 1426 | default: |
| 1427 | case COMP_ID_GF: |
| 1428 | temp_var = ((die_temp - 25000) * |
| 1429 | (-QPNP_VBAT_COEFF_9)); |
| 1430 | break; |
| 1431 | } |
| 1432 | break; |
| 1433 | case QPNP_REV_ID_8026_2_2: |
| 1434 | switch (vadc->id) { |
| 1435 | case COMP_ID_TSMC: |
| 1436 | *result -= QPNP_VBAT_COEFF_23; |
| 1437 | temp_var = 0; |
| 1438 | break; |
| 1439 | default: |
| 1440 | case COMP_ID_GF: |
| 1441 | *result -= QPNP_VBAT_COEFF_23; |
| 1442 | temp_var = 0; |
| 1443 | break; |
| 1444 | } |
| 1445 | break; |
| 1446 | case QPNP_REV_ID_8110_2_0: |
| 1447 | switch (vadc->id) { |
| 1448 | case COMP_ID_SMIC: |
| 1449 | *result -= QPNP_VBAT_OFFSET_SMIC; |
| 1450 | temp_var = ((die_temp - 25000) * |
| 1451 | (QPNP_VBAT_COEFF_17)); |
| 1452 | break; |
| 1453 | default: |
| 1454 | case COMP_ID_GF: |
| 1455 | *result -= QPNP_VBAT_OFFSET_GF; |
| 1456 | temp_var = ((die_temp - 25000) * |
| 1457 | (QPNP_VBAT_COEFF_16)); |
| 1458 | break; |
| 1459 | } |
| 1460 | break; |
| 1461 | case QPNP_REV_ID_8916_1_0: |
| 1462 | switch (vadc->id) { |
| 1463 | case COMP_ID_SMIC: |
| 1464 | temp_var = ((die_temp - 25000) * |
| 1465 | (QPNP_VBAT_COEFF_28)); |
| 1466 | break; |
| 1467 | default: |
| 1468 | case COMP_ID_GF: |
| 1469 | temp_var = ((die_temp - 25000) * |
| 1470 | (QPNP_VBAT_COEFF_28)); |
| 1471 | break; |
| 1472 | } |
| 1473 | break; |
| 1474 | case QPNP_REV_ID_8916_1_1: |
| 1475 | switch (vadc->id) { |
| 1476 | /* FAB_ID is zero */ |
| 1477 | case COMP_ID_GF: |
| 1478 | temp_var = ((die_temp - 25000) * |
| 1479 | (QPNP_VBAT_COEFF_33)); |
| 1480 | break; |
| 1481 | /* FAB_ID is non-zero */ |
| 1482 | default: |
| 1483 | offset = QPNP_VBAT_COEFF_35; |
| 1484 | if (die_temp > 50000) { |
| 1485 | temp_var = ((die_temp - 25000) * |
| 1486 | (QPNP_VBAT_COEFF_34)); |
| 1487 | } |
| 1488 | break; |
| 1489 | } |
| 1490 | break; |
| 1491 | case QPNP_REV_ID_8916_2_0: |
| 1492 | switch (vadc->id) { |
| 1493 | case COMP_ID_SMIC: |
| 1494 | if (die_temp < 0) { |
| 1495 | temp_var = (die_temp * |
| 1496 | QPNP_VBAT_COEFF_39); |
| 1497 | } else if (die_temp > 40000) { |
| 1498 | temp_var = ((die_temp - 40000) * |
| 1499 | (-QPNP_VBAT_COEFF_40)); |
| 1500 | } |
| 1501 | break; |
| 1502 | case COMP_ID_TSMC: |
| 1503 | if (die_temp < 10000) |
| 1504 | temp_var = ((die_temp - 10000) * |
| 1505 | QPNP_VBAT_COEFF_43); |
| 1506 | else if (die_temp > 50000) |
| 1507 | temp_var = ((die_temp - 50000) * |
| 1508 | (-QPNP_VBAT_COEFF_44)); |
| 1509 | break; |
| 1510 | default: |
| 1511 | case COMP_ID_GF: |
| 1512 | if (die_temp < 20000) |
| 1513 | temp_var = ((die_temp - 20000) * |
| 1514 | QPNP_VBAT_COEFF_47); |
| 1515 | else if (die_temp > 40000) |
| 1516 | temp_var = ((die_temp - 40000) * |
| 1517 | (-QPNP_VBAT_COEFF_48)); |
| 1518 | break; |
| 1519 | } |
| 1520 | break; |
| 1521 | case QPNP_REV_ID_8909_1_0: |
| 1522 | switch (vadc->id) { |
| 1523 | case COMP_ID_SMIC: |
| 1524 | if (die_temp < 30000) |
| 1525 | temp_var = (-QPNP_VBAT_COEFF_50); |
| 1526 | else if (die_temp > 30000) |
| 1527 | temp_var = (((die_temp - 30000) * |
| 1528 | (-QPNP_VBAT_COEFF_49)) + |
| 1529 | (-QPNP_VBAT_COEFF_50)); |
| 1530 | break; |
| 1531 | } |
| 1532 | break; |
| 1533 | case QPNP_REV_ID_8909_1_1: |
| 1534 | switch (vadc->id) { |
| 1535 | case COMP_ID_SMIC: |
| 1536 | if (die_temp < 30000) |
| 1537 | temp_var = (QPNP_VBAT_COEFF_52); |
| 1538 | else if (die_temp > 30000) |
| 1539 | temp_var = (((die_temp - 30000) * |
| 1540 | (-QPNP_VBAT_COEFF_51)) + |
| 1541 | (QPNP_VBAT_COEFF_52)); |
| 1542 | break; |
| 1543 | } |
| 1544 | break; |
| 1545 | default: |
| 1546 | temp_var = 0; |
| 1547 | break; |
| 1548 | } |
| 1549 | |
| 1550 | temp_var = div64_s64(temp_var, QPNP_VBAT_COEFF_3); |
| 1551 | |
| 1552 | temp_var = 1000000 + temp_var; |
| 1553 | |
| 1554 | *result = *result * temp_var; |
| 1555 | |
| 1556 | if (offset) |
| 1557 | *result -= offset; |
| 1558 | |
| 1559 | *result = div64_s64(*result, 1000000); |
| 1560 | pr_debug("%lld compensated into %lld\n", old, *result); |
| 1561 | |
| 1562 | return 0; |
| 1563 | } |
| 1564 | |
| 1565 | int32_t qpnp_vbat_sns_comp_result(struct qpnp_vadc_chip *vadc, |
| 1566 | int64_t *result, bool is_pon_ocv) |
| 1567 | { |
| 1568 | struct qpnp_vadc_result die_temp_result; |
| 1569 | int rc = 0; |
| 1570 | |
| 1571 | rc = qpnp_vadc_is_valid(vadc); |
| 1572 | if (rc < 0) |
| 1573 | return rc; |
| 1574 | |
| 1575 | rc = qpnp_vadc_conv_seq_request(vadc, ADC_SEQ_NONE, |
| 1576 | DIE_TEMP, &die_temp_result); |
| 1577 | if (rc < 0) { |
| 1578 | pr_err("Error reading die_temp\n"); |
| 1579 | return rc; |
| 1580 | } |
| 1581 | |
| 1582 | pr_debug("die-temp = %lld\n", die_temp_result.physical); |
| 1583 | |
| 1584 | if (is_pon_ocv) |
| 1585 | rc = qpnp_ocv_comp(result, vadc, die_temp_result.physical); |
| 1586 | else |
| 1587 | rc = qpnp_vbat_sns_comp(result, vadc, |
| 1588 | die_temp_result.physical); |
| 1589 | |
| 1590 | if (rc < 0) |
| 1591 | pr_err("Error with vbat compensation\n"); |
| 1592 | |
| 1593 | return rc; |
| 1594 | } |
| 1595 | EXPORT_SYMBOL(qpnp_vbat_sns_comp_result); |
| 1596 | |
| 1597 | static void qpnp_vadc_625mv_channel_sel(struct qpnp_vadc_chip *vadc, |
| 1598 | uint32_t *ref_channel_sel) |
| 1599 | { |
| 1600 | uint32_t dt_index = 0; |
| 1601 | |
| 1602 | /* Check if the buffered 625mV channel exists */ |
| 1603 | while ((vadc->adc->adc_channels[dt_index].channel_num |
| 1604 | != SPARE1) && (dt_index < vadc->max_channels_available)) |
| 1605 | dt_index++; |
| 1606 | |
| 1607 | if (dt_index >= vadc->max_channels_available) { |
| 1608 | pr_debug("Use default 625mV ref channel\n"); |
| 1609 | *ref_channel_sel = REF_625MV; |
| 1610 | } else { |
| 1611 | pr_debug("Use buffered 625mV ref channel\n"); |
| 1612 | *ref_channel_sel = SPARE1; |
| 1613 | } |
| 1614 | } |
| 1615 | |
| 1616 | int32_t qpnp_vadc_calib_vref(struct qpnp_vadc_chip *vadc, |
| 1617 | enum qpnp_adc_calib_type calib_type, |
| 1618 | int *calib_data) |
| 1619 | { |
| 1620 | struct qpnp_adc_amux_properties conv; |
| 1621 | int rc, count = 0, calib_read = 0; |
| 1622 | u8 status1 = 0; |
| 1623 | |
| 1624 | if (vadc->vadc_hc) { |
| 1625 | if (calib_type == ADC_HC_ABS_CAL) |
| 1626 | conv.amux_channel = VADC_CALIB_VREF_1P25; |
| 1627 | else if (calib_type == CALIB_RATIOMETRIC) |
| 1628 | conv.amux_channel = VADC_CALIB_VREF; |
| 1629 | } else { |
| 1630 | if (calib_type == CALIB_ABSOLUTE) |
| 1631 | conv.amux_channel = REF_125V; |
| 1632 | else if (calib_type == CALIB_RATIOMETRIC) |
| 1633 | conv.amux_channel = VDD_VADC; |
| 1634 | } |
| 1635 | |
| 1636 | conv.decimation = DECIMATION_TYPE2; |
| 1637 | conv.mode_sel = ADC_OP_NORMAL_MODE << QPNP_VADC_OP_MODE_SHIFT; |
| 1638 | conv.hw_settle_time = ADC_CHANNEL_HW_SETTLE_DELAY_0US; |
| 1639 | conv.fast_avg_setup = ADC_FAST_AVG_SAMPLE_1; |
Jishnu Prakash | a5f6af2 | 2019-03-08 11:00:51 +0530 | [diff] [blame] | 1640 | conv.cal_val = (enum qpnp_adc_cal_val)calib_type; |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 1641 | |
| 1642 | if (vadc->vadc_hc) { |
| 1643 | rc = qpnp_vadc_hc_configure(vadc, &conv); |
| 1644 | if (rc) { |
| 1645 | pr_err("qpnp_vadc configure failed with %d\n", rc); |
| 1646 | goto calib_fail; |
| 1647 | } |
| 1648 | } else { |
| 1649 | rc = qpnp_vadc_configure(vadc, &conv); |
| 1650 | if (rc) { |
| 1651 | pr_err("qpnp_vadc configure failed with %d\n", rc); |
| 1652 | goto calib_fail; |
| 1653 | } |
| 1654 | } |
| 1655 | |
| 1656 | while (status1 != QPNP_VADC_STATUS1_EOC) { |
| 1657 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1, 1); |
| 1658 | if (rc < 0) |
| 1659 | return rc; |
| 1660 | status1 &= QPNP_VADC_STATUS1_REQ_STS_EOC_MASK; |
| 1661 | usleep_range(QPNP_VADC_CONV_TIME_MIN, |
| 1662 | QPNP_VADC_CONV_TIME_MAX); |
| 1663 | count++; |
| 1664 | if (count > QPNP_VADC_ERR_COUNT) { |
| 1665 | rc = -ENODEV; |
| 1666 | goto calib_fail; |
| 1667 | } |
| 1668 | } |
| 1669 | |
| 1670 | if (vadc->vadc_hc) { |
| 1671 | rc = qpnp_vadc_hc_read_data(vadc, &calib_read); |
| 1672 | if (rc) { |
| 1673 | pr_err("qpnp vadc read adc code failed with %d\n", rc); |
| 1674 | goto calib_fail; |
| 1675 | } |
| 1676 | } else { |
| 1677 | rc = qpnp_vadc_read_conversion_result(vadc, &calib_read); |
| 1678 | if (rc) { |
| 1679 | pr_err("qpnp adc read adc failed with %d\n", rc); |
| 1680 | goto calib_fail; |
| 1681 | } |
| 1682 | } |
| 1683 | |
| 1684 | *calib_data = calib_read; |
| 1685 | calib_fail: |
| 1686 | return rc; |
| 1687 | } |
| 1688 | |
| 1689 | |
| 1690 | int32_t qpnp_vadc_calib_gnd(struct qpnp_vadc_chip *vadc, |
| 1691 | enum qpnp_adc_calib_type calib_type, |
| 1692 | int *calib_data) |
| 1693 | { |
| 1694 | struct qpnp_adc_amux_properties conv; |
| 1695 | int rc, count = 0, calib_read = 0; |
| 1696 | u8 status1 = 0; |
| 1697 | uint32_t ref_channel_sel = 0; |
| 1698 | |
| 1699 | if (vadc->vadc_hc) { |
| 1700 | conv.amux_channel = VADC_VREF_GND; |
| 1701 | } else { |
| 1702 | if (calib_type == CALIB_ABSOLUTE) { |
| 1703 | qpnp_vadc_625mv_channel_sel(vadc, &ref_channel_sel); |
| 1704 | conv.amux_channel = ref_channel_sel; |
| 1705 | } else if (calib_type == CALIB_RATIOMETRIC) |
| 1706 | conv.amux_channel = GND_REF; |
| 1707 | } |
| 1708 | |
| 1709 | conv.decimation = DECIMATION_TYPE2; |
| 1710 | conv.mode_sel = ADC_OP_NORMAL_MODE << QPNP_VADC_OP_MODE_SHIFT; |
| 1711 | conv.hw_settle_time = ADC_CHANNEL_HW_SETTLE_DELAY_0US; |
| 1712 | conv.fast_avg_setup = ADC_FAST_AVG_SAMPLE_1; |
Jishnu Prakash | a5f6af2 | 2019-03-08 11:00:51 +0530 | [diff] [blame] | 1713 | conv.cal_val = (enum qpnp_adc_cal_val)calib_type; |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 1714 | |
| 1715 | if (vadc->vadc_hc) { |
| 1716 | rc = qpnp_vadc_hc_configure(vadc, &conv); |
| 1717 | if (rc) { |
| 1718 | pr_err("qpnp_vadc configure failed with %d\n", rc); |
| 1719 | goto calib_fail; |
| 1720 | } |
| 1721 | } else { |
| 1722 | rc = qpnp_vadc_configure(vadc, &conv); |
| 1723 | if (rc) { |
| 1724 | pr_err("qpnp_vadc configure failed with %d\n", rc); |
| 1725 | goto calib_fail; |
| 1726 | } |
| 1727 | } |
| 1728 | |
| 1729 | while (status1 != QPNP_VADC_STATUS1_EOC) { |
| 1730 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1, 1); |
| 1731 | if (rc < 0) |
| 1732 | return rc; |
| 1733 | status1 &= QPNP_VADC_STATUS1_REQ_STS_EOC_MASK; |
| 1734 | usleep_range(QPNP_VADC_CONV_TIME_MIN, |
| 1735 | QPNP_VADC_CONV_TIME_MAX); |
| 1736 | count++; |
| 1737 | if (count > QPNP_VADC_ERR_COUNT) { |
| 1738 | rc = -ENODEV; |
| 1739 | goto calib_fail; |
| 1740 | } |
| 1741 | } |
| 1742 | |
| 1743 | if (vadc->vadc_hc) { |
| 1744 | rc = qpnp_vadc_hc_read_data(vadc, &calib_read); |
| 1745 | if (rc) { |
| 1746 | pr_err("qpnp vadc read adc code failed with %d\n", rc); |
| 1747 | goto calib_fail; |
| 1748 | } |
| 1749 | } else { |
| 1750 | rc = qpnp_vadc_read_conversion_result(vadc, &calib_read); |
| 1751 | if (rc) { |
| 1752 | pr_err("qpnp adc read adc failed with %d\n", rc); |
| 1753 | goto calib_fail; |
| 1754 | } |
| 1755 | } |
| 1756 | *calib_data = calib_read; |
| 1757 | calib_fail: |
| 1758 | return rc; |
| 1759 | } |
| 1760 | |
| 1761 | static int32_t qpnp_vadc_calib_device(struct qpnp_vadc_chip *vadc) |
| 1762 | { |
| 1763 | int rc, calib_read_1 = 0, calib_read_2 = 0; |
| 1764 | enum qpnp_adc_calib_type calib_type; |
| 1765 | |
| 1766 | if (vadc->vadc_hc) |
| 1767 | calib_type = ADC_HC_ABS_CAL; |
| 1768 | else |
| 1769 | calib_type = CALIB_ABSOLUTE; |
| 1770 | |
| 1771 | rc = qpnp_vadc_calib_vref(vadc, calib_type, &calib_read_1); |
| 1772 | if (rc) { |
| 1773 | pr_err("qpnp adc absolute vref calib failed with %d\n", rc); |
| 1774 | goto calib_fail; |
| 1775 | } |
| 1776 | rc = qpnp_vadc_calib_gnd(vadc, calib_type, &calib_read_2); |
| 1777 | if (rc) { |
| 1778 | pr_err("qpnp adc absolute gnd calib failed with %d\n", rc); |
| 1779 | goto calib_fail; |
| 1780 | } |
| 1781 | pr_debug("absolute reference raw: 1.25V:0x%x, 625mV/GND:0x%x\n", |
| 1782 | calib_read_1, calib_read_2); |
| 1783 | |
| 1784 | if (calib_read_1 == calib_read_2) { |
| 1785 | pr_err("absolute reference raw: 1.25V:0x%x625mV:0x%x\n", |
| 1786 | calib_read_2, calib_read_1); |
| 1787 | rc = -EINVAL; |
| 1788 | goto calib_fail; |
| 1789 | } |
| 1790 | |
| 1791 | vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].dy = |
| 1792 | (calib_read_1 - calib_read_2); |
| 1793 | |
| 1794 | if (calib_type == CALIB_ABSOLUTE) |
| 1795 | vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].dx |
| 1796 | = QPNP_ADC_625_UV; |
| 1797 | else if (calib_type == ADC_HC_ABS_CAL) |
| 1798 | vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].dx |
| 1799 | = QPNP_ADC_1P25_UV; |
| 1800 | vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].adc_vref = |
| 1801 | calib_read_1; |
| 1802 | vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].adc_gnd = |
| 1803 | calib_read_2; |
| 1804 | |
| 1805 | calib_read_1 = 0; |
| 1806 | calib_read_2 = 0; |
| 1807 | rc = qpnp_vadc_calib_vref(vadc, CALIB_RATIOMETRIC, &calib_read_1); |
| 1808 | if (rc) { |
| 1809 | pr_err("qpnp adc ratiometric vref calib failed with %d\n", rc); |
| 1810 | goto calib_fail; |
| 1811 | } |
| 1812 | rc = qpnp_vadc_calib_gnd(vadc, CALIB_RATIOMETRIC, &calib_read_2); |
| 1813 | if (rc) { |
| 1814 | pr_err("qpnp adc ratiometric gnd calib failed with %d\n", rc); |
| 1815 | goto calib_fail; |
| 1816 | } |
| 1817 | pr_debug("ratiometric reference raw: VDD:0x%x GND:0x%x\n", |
| 1818 | calib_read_1, calib_read_2); |
| 1819 | |
| 1820 | if (calib_read_1 == calib_read_2) { |
| 1821 | pr_err("ratiometric reference raw: VDD:0x%x GND:0x%x\n", |
| 1822 | calib_read_1, calib_read_2); |
| 1823 | rc = -EINVAL; |
| 1824 | goto calib_fail; |
| 1825 | } |
| 1826 | |
| 1827 | vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].dy = |
| 1828 | (calib_read_1 - calib_read_2); |
| 1829 | vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].dx = |
| 1830 | vadc->adc->adc_prop->adc_vdd_reference; |
Jishnu Prakash | a5f6af2 | 2019-03-08 11:00:51 +0530 | [diff] [blame] | 1831 | vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].adc_vref = |
| 1832 | calib_read_1; |
| 1833 | vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].adc_gnd = |
| 1834 | calib_read_2; |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 1835 | |
| 1836 | calib_fail: |
| 1837 | return rc; |
| 1838 | } |
| 1839 | |
| 1840 | int32_t qpnp_get_vadc_gain_and_offset(struct qpnp_vadc_chip *vadc, |
| 1841 | struct qpnp_vadc_linear_graph *param, |
| 1842 | enum qpnp_adc_calib_type calib_type) |
| 1843 | { |
| 1844 | int rc = 0; |
| 1845 | struct qpnp_vadc_result result; |
| 1846 | |
| 1847 | rc = qpnp_vadc_is_valid(vadc); |
| 1848 | if (rc < 0) |
| 1849 | return rc; |
| 1850 | |
| 1851 | if (!vadc->vadc_init_calib) { |
| 1852 | if (vadc->vadc_hc) { |
| 1853 | rc = qpnp_vadc_hc_read(vadc, VADC_CALIB_VREF_1P25, |
| 1854 | &result); |
| 1855 | if (rc) { |
| 1856 | pr_debug("vadc read failed with rc = %d\n", rc); |
| 1857 | return rc; |
| 1858 | } |
| 1859 | } else { |
| 1860 | rc = qpnp_vadc_read(vadc, REF_125V, &result); |
| 1861 | if (rc) { |
| 1862 | pr_debug("vadc read failed with rc = %d\n", rc); |
| 1863 | return rc; |
| 1864 | } |
| 1865 | } |
| 1866 | } |
| 1867 | |
| 1868 | switch (calib_type) { |
| 1869 | case CALIB_RATIOMETRIC: |
| 1870 | param->dy = |
| 1871 | vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].dy; |
| 1872 | param->dx = |
| 1873 | vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].dx; |
| 1874 | param->adc_vref = vadc->adc->adc_prop->adc_vdd_reference; |
| 1875 | param->adc_gnd = |
| 1876 | vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].adc_gnd; |
| 1877 | break; |
| 1878 | case CALIB_ABSOLUTE: |
| 1879 | case ADC_HC_ABS_CAL: |
| 1880 | param->dy = |
| 1881 | vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].dy; |
| 1882 | param->dx = |
| 1883 | vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].dx; |
| 1884 | param->adc_vref = vadc->adc->adc_prop->adc_vdd_reference; |
| 1885 | param->adc_gnd = |
| 1886 | vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].adc_gnd; |
| 1887 | break; |
| 1888 | default: |
| 1889 | rc = -EINVAL; |
| 1890 | } |
| 1891 | |
| 1892 | return rc; |
| 1893 | } |
| 1894 | EXPORT_SYMBOL(qpnp_get_vadc_gain_and_offset); |
| 1895 | |
| 1896 | static int32_t qpnp_vadc_wait_for_req_sts_check(struct qpnp_vadc_chip *vadc) |
| 1897 | { |
| 1898 | u8 status1 = 0; |
| 1899 | int rc, count = 0; |
| 1900 | |
| 1901 | /* Re-enable the peripheral */ |
| 1902 | rc = qpnp_vadc_enable(vadc, true); |
| 1903 | if (rc) { |
| 1904 | pr_err("vadc re-enable peripheral failed with %d\n", rc); |
| 1905 | return rc; |
| 1906 | } |
| 1907 | |
| 1908 | /* The VADC_TM bank needs to be disabled for new conversion request */ |
| 1909 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1, 1); |
| 1910 | if (rc) { |
| 1911 | pr_err("vadc read status1 failed with %d\n", rc); |
| 1912 | return rc; |
| 1913 | } |
| 1914 | |
| 1915 | /* Disable the bank if a conversion is occurring */ |
| 1916 | while ((status1 & QPNP_VADC_STATUS1_REQ_STS) && (count < QPNP_RETRY)) { |
| 1917 | /* Wait time is based on the optimum sampling rate |
| 1918 | * and adding enough time buffer to account for ADC conversions |
| 1919 | * occurring on different peripheral banks |
| 1920 | */ |
| 1921 | usleep_range(QPNP_MIN_TIME, QPNP_MAX_TIME); |
| 1922 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1, 1); |
| 1923 | if (rc < 0) { |
| 1924 | pr_err("vadc disable failed with %d\n", rc); |
| 1925 | return rc; |
| 1926 | } |
| 1927 | count++; |
| 1928 | } |
| 1929 | |
| 1930 | if (count >= QPNP_RETRY) |
| 1931 | pr_err("QPNP vadc status req bit did not fall low!!\n"); |
| 1932 | |
| 1933 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1, 1); |
| 1934 | |
| 1935 | /* Disable the peripheral */ |
| 1936 | rc = qpnp_vadc_enable(vadc, false); |
| 1937 | if (rc < 0) |
| 1938 | pr_err("vadc peripheral disable failed with %d\n", rc); |
| 1939 | |
| 1940 | return rc; |
| 1941 | } |
| 1942 | |
| 1943 | static int32_t qpnp_vadc_manage_meas_int_requests(struct qpnp_vadc_chip *chip) |
| 1944 | { |
| 1945 | struct qpnp_vadc_chip *vadc = dev_get_drvdata(chip->dev); |
| 1946 | int rc = 0, dt_index = 0; |
| 1947 | u8 mode_ctl = 0; |
| 1948 | |
| 1949 | pr_debug("meas_int_mode:0x%x, mode_ctl:%0x\n", |
| 1950 | vadc->state_copy->meas_int_mode, mode_ctl); |
| 1951 | |
| 1952 | if (vadc->state_copy->meas_int_mode) { |
| 1953 | pr_debug("meas interval in progress. Procced to disable it\n"); |
| 1954 | /* measurement interval in progress. Proceed to disable it */ |
| 1955 | mode_ctl = ADC_OP_NORMAL_MODE; |
| 1956 | rc = qpnp_vadc_mode_select(vadc, mode_ctl); |
| 1957 | if (rc < 0) { |
| 1958 | pr_err("NORM mode select failed with %d\n", rc); |
| 1959 | return rc; |
| 1960 | } |
| 1961 | |
| 1962 | /* Disable bank */ |
| 1963 | rc = qpnp_vadc_enable(vadc, false); |
| 1964 | if (rc) { |
| 1965 | pr_err("Disable bank failed with %d\n", rc); |
| 1966 | return rc; |
| 1967 | } |
| 1968 | |
| 1969 | /* Check if a conversion is in progress */ |
| 1970 | rc = qpnp_vadc_wait_for_req_sts_check(vadc); |
| 1971 | if (rc < 0) { |
| 1972 | pr_err("req_sts check failed with %d\n", rc); |
| 1973 | return rc; |
| 1974 | } |
| 1975 | |
| 1976 | vadc->state_copy->meas_int_mode = false; |
| 1977 | vadc->state_copy->meas_int_request_in_queue = true; |
| 1978 | } else if (vadc->state_copy->meas_int_request_in_queue) { |
| 1979 | /* put the meas interval back in queue */ |
| 1980 | pr_debug("put meas interval back in queue\n"); |
| 1981 | vadc->adc->amux_prop->amux_channel = |
| 1982 | vadc->state_copy->vadc_meas_amux.channel_num; |
| 1983 | while ((vadc->adc->adc_channels[dt_index].channel_num |
| 1984 | != vadc->adc->amux_prop->amux_channel) && |
| 1985 | (dt_index < vadc->max_channels_available)) |
| 1986 | dt_index++; |
| 1987 | if (dt_index >= vadc->max_channels_available) { |
| 1988 | pr_err("not a valid VADC channel\n"); |
| 1989 | rc = -EINVAL; |
| 1990 | return rc; |
| 1991 | } |
| 1992 | |
| 1993 | vadc->adc->amux_prop->decimation = |
| 1994 | vadc->adc->amux_prop->decimation; |
| 1995 | vadc->adc->amux_prop->hw_settle_time = |
| 1996 | vadc->adc->amux_prop->hw_settle_time; |
| 1997 | vadc->adc->amux_prop->fast_avg_setup = |
| 1998 | vadc->adc->amux_prop->fast_avg_setup; |
| 1999 | vadc->adc->amux_prop->mode_sel = ADC_OP_MEASUREMENT_INTERVAL; |
| 2000 | rc = qpnp_vadc_configure(vadc, vadc->adc->amux_prop); |
| 2001 | if (rc) { |
| 2002 | pr_err("vadc configure failed with %d\n", rc); |
| 2003 | return rc; |
| 2004 | } |
| 2005 | |
| 2006 | vadc->state_copy->meas_int_mode = true; |
| 2007 | vadc->state_copy->meas_int_request_in_queue = false; |
| 2008 | } |
| 2009 | dev_set_drvdata(vadc->dev, vadc); |
| 2010 | |
| 2011 | return 0; |
| 2012 | } |
| 2013 | |
| 2014 | struct qpnp_vadc_chip *qpnp_get_vadc(struct device *dev, const char *name) |
| 2015 | { |
| 2016 | struct qpnp_vadc_chip *vadc; |
| 2017 | struct device_node *node = NULL; |
| 2018 | char prop_name[QPNP_MAX_PROP_NAME_LEN]; |
| 2019 | |
| 2020 | snprintf(prop_name, QPNP_MAX_PROP_NAME_LEN, "qcom,%s-vadc", name); |
| 2021 | |
| 2022 | node = of_parse_phandle(dev->of_node, prop_name, 0); |
| 2023 | if (node == NULL) |
| 2024 | return ERR_PTR(-ENODEV); |
| 2025 | |
| 2026 | list_for_each_entry(vadc, &qpnp_vadc_device_list, list) |
| 2027 | if (vadc->adc->pdev->dev.of_node == node) |
| 2028 | return vadc; |
| 2029 | return ERR_PTR(-EPROBE_DEFER); |
| 2030 | } |
| 2031 | EXPORT_SYMBOL(qpnp_get_vadc); |
| 2032 | |
| 2033 | int32_t qpnp_vadc_conv_seq_request(struct qpnp_vadc_chip *vadc, |
| 2034 | enum qpnp_vadc_trigger trigger_channel, |
| 2035 | enum qpnp_vadc_channels channel, |
| 2036 | struct qpnp_vadc_result *result) |
| 2037 | { |
| 2038 | int rc = 0, scale_type, amux_prescaling, dt_index = 0, calib_type = 0; |
| 2039 | uint32_t ref_channel, count = 0, local_idx = 0; |
| 2040 | int32_t vref_calib = 0, gnd_calib = 0, new_vref_calib = 0, offset = 0; |
| 2041 | int32_t calib_offset = 0; |
| 2042 | u8 status1 = 0; |
| 2043 | |
| 2044 | if (qpnp_vadc_is_valid(vadc)) |
| 2045 | return -EPROBE_DEFER; |
| 2046 | |
| 2047 | mutex_lock(&vadc->adc->adc_lock); |
| 2048 | |
| 2049 | if (vadc->state_copy->vadc_meas_int_enable) |
| 2050 | qpnp_vadc_manage_meas_int_requests(vadc); |
| 2051 | |
| 2052 | if (channel == REF_625MV) { |
| 2053 | qpnp_vadc_625mv_channel_sel(vadc, &ref_channel); |
| 2054 | channel = ref_channel; |
| 2055 | } |
| 2056 | |
| 2057 | vadc->adc->amux_prop->amux_channel = channel; |
| 2058 | |
| 2059 | while ((vadc->adc->adc_channels[dt_index].channel_num |
| 2060 | != channel) && (dt_index < vadc->max_channels_available)) |
| 2061 | dt_index++; |
| 2062 | |
| 2063 | if (dt_index >= vadc->max_channels_available) { |
| 2064 | pr_err("not a valid VADC channel\n"); |
| 2065 | rc = -EINVAL; |
| 2066 | goto fail_unlock; |
| 2067 | } |
| 2068 | |
| 2069 | calib_type = vadc->adc->adc_channels[dt_index].calib_type; |
| 2070 | if (calib_type >= CALIB_NONE) { |
| 2071 | pr_err("not a valid calib_type\n"); |
| 2072 | rc = -EINVAL; |
| 2073 | goto fail_unlock; |
| 2074 | } |
| 2075 | calib_offset = (calib_type == CALIB_ABSOLUTE) ? |
| 2076 | QPNP_VADC_ABSOLUTE_RECALIB_OFFSET : |
| 2077 | QPNP_VADC_RATIOMETRIC_RECALIB_OFFSET; |
| 2078 | rc = qpnp_vadc_version_check(vadc); |
| 2079 | if (rc) |
| 2080 | goto fail_unlock; |
| 2081 | if (vadc->vadc_recalib_check) { |
| 2082 | rc = qpnp_vadc_calib_vref(vadc, calib_type, &vref_calib); |
| 2083 | if (rc) { |
| 2084 | pr_err("Calibration failed\n"); |
| 2085 | goto fail_unlock; |
| 2086 | } |
| 2087 | } else if (!vadc->vadc_init_calib) { |
| 2088 | rc = qpnp_vadc_calib_device(vadc); |
| 2089 | if (rc) { |
| 2090 | pr_err("Calibration failed\n"); |
| 2091 | goto fail_unlock; |
| 2092 | } else { |
| 2093 | vadc->vadc_init_calib = true; |
| 2094 | } |
| 2095 | } |
| 2096 | |
| 2097 | recalibrate: |
| 2098 | status1 = 0; |
| 2099 | vadc->adc->amux_prop->decimation = |
| 2100 | vadc->adc->adc_channels[dt_index].adc_decimation; |
| 2101 | vadc->adc->amux_prop->hw_settle_time = |
| 2102 | vadc->adc->adc_channels[dt_index].hw_settle_time; |
| 2103 | vadc->adc->amux_prop->fast_avg_setup = |
| 2104 | vadc->adc->adc_channels[dt_index].fast_avg_setup; |
| 2105 | |
| 2106 | if (trigger_channel < ADC_SEQ_NONE) |
| 2107 | vadc->adc->amux_prop->mode_sel = (ADC_OP_CONVERSION_SEQUENCER |
| 2108 | << QPNP_VADC_OP_MODE_SHIFT); |
| 2109 | else if (trigger_channel == ADC_SEQ_NONE) |
| 2110 | vadc->adc->amux_prop->mode_sel = (ADC_OP_NORMAL_MODE |
| 2111 | << QPNP_VADC_OP_MODE_SHIFT); |
| 2112 | else { |
| 2113 | pr_err("Invalid trigger channel:%d\n", trigger_channel); |
| 2114 | goto fail_unlock; |
| 2115 | } |
| 2116 | |
| 2117 | vadc->adc->amux_prop->trigger_channel = trigger_channel; |
| 2118 | |
| 2119 | rc = qpnp_vadc_configure(vadc, vadc->adc->amux_prop); |
| 2120 | if (rc) { |
| 2121 | pr_err("qpnp vadc configure failed with %d\n", rc); |
| 2122 | goto fail_unlock; |
| 2123 | } |
| 2124 | |
| 2125 | if (vadc->vadc_poll_eoc) { |
| 2126 | while (status1 != QPNP_VADC_STATUS1_EOC) { |
| 2127 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, |
| 2128 | &status1, 1); |
| 2129 | if (rc < 0) |
| 2130 | goto fail_unlock; |
| 2131 | status1 &= QPNP_VADC_STATUS1_REQ_STS_EOC_MASK; |
| 2132 | if (status1 == QPNP_VADC_STATUS1_EOC) |
| 2133 | break; |
| 2134 | usleep_range(QPNP_VADC_CONV_TIME_MIN, |
| 2135 | QPNP_VADC_CONV_TIME_MAX); |
| 2136 | count++; |
| 2137 | if (count > QPNP_VADC_ERR_COUNT) { |
| 2138 | pr_err("retry error exceeded\n"); |
| 2139 | rc = qpnp_vadc_status_debug(vadc); |
| 2140 | if (rc < 0) |
| 2141 | pr_err("VADC disable failed\n"); |
| 2142 | rc = -EINVAL; |
| 2143 | goto fail_unlock; |
| 2144 | } |
| 2145 | } |
| 2146 | } else { |
| 2147 | rc = wait_for_completion_timeout( |
| 2148 | &vadc->adc->adc_rslt_completion, |
| 2149 | QPNP_ADC_COMPLETION_TIMEOUT); |
| 2150 | if (!rc) { |
| 2151 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, |
| 2152 | &status1, 1); |
| 2153 | if (rc < 0) |
| 2154 | goto fail_unlock; |
| 2155 | status1 &= QPNP_VADC_STATUS1_REQ_STS_EOC_MASK; |
| 2156 | if (status1 == QPNP_VADC_STATUS1_EOC) |
| 2157 | pr_debug("End of conversion status set\n"); |
| 2158 | else { |
| 2159 | rc = qpnp_vadc_status_debug(vadc); |
| 2160 | if (rc < 0) |
| 2161 | pr_err("VADC disable failed\n"); |
| 2162 | rc = -EINVAL; |
| 2163 | goto fail_unlock; |
| 2164 | } |
| 2165 | } |
| 2166 | } |
| 2167 | |
| 2168 | if (trigger_channel < ADC_SEQ_NONE) { |
| 2169 | rc = qpnp_vadc_read_status(vadc, |
| 2170 | vadc->adc->amux_prop->mode_sel); |
| 2171 | if (rc) |
| 2172 | pr_debug("Conversion sequence timed out - %d\n", rc); |
| 2173 | } |
| 2174 | |
| 2175 | rc = qpnp_vadc_read_conversion_result(vadc, &result->adc_code); |
| 2176 | if (rc) { |
| 2177 | pr_err("qpnp vadc read adc code failed with %d\n", rc); |
| 2178 | goto fail_unlock; |
| 2179 | } |
| 2180 | |
| 2181 | if (vadc->vadc_recalib_check) { |
| 2182 | rc = qpnp_vadc_calib_gnd(vadc, calib_type, &gnd_calib); |
| 2183 | if (rc) { |
| 2184 | pr_err("Calibration failed\n"); |
| 2185 | goto fail_unlock; |
| 2186 | } |
| 2187 | rc = qpnp_vadc_calib_vref(vadc, calib_type, &new_vref_calib); |
| 2188 | if (rc < 0) { |
| 2189 | pr_err("qpnp vadc calib read failed with %d\n", rc); |
| 2190 | goto fail_unlock; |
| 2191 | } |
| 2192 | |
| 2193 | if (local_idx >= QPNP_VADC_RECALIB_MAXCNT) { |
| 2194 | pr_err("invalid recalib count=%d\n", local_idx); |
| 2195 | rc = -EINVAL; |
| 2196 | goto fail_unlock; |
| 2197 | } |
| 2198 | pr_debug( |
| 2199 | "chan=%d, calib=%s, vref_calib=0x%x, gnd_calib=0x%x, new_vref_calib=0x%x\n", |
| 2200 | channel, |
| 2201 | ((calib_type == CALIB_ABSOLUTE) ? |
| 2202 | "ABSOLUTE" : "RATIOMETRIC"), |
| 2203 | vref_calib, gnd_calib, new_vref_calib); |
| 2204 | |
| 2205 | offset = (new_vref_calib - vref_calib); |
| 2206 | if (offset < 0) |
| 2207 | offset = -offset; |
| 2208 | if (offset <= calib_offset) { |
| 2209 | pr_debug( |
| 2210 | "qpnp vadc recalibration not required,offset:%d\n", |
| 2211 | offset); |
| 2212 | local_idx = 0; |
| 2213 | vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].dy = |
| 2214 | (vref_calib - gnd_calib); |
| 2215 | vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].dx = |
| 2216 | (calib_type == CALIB_ABSOLUTE) ? QPNP_ADC_625_UV : |
| 2217 | vadc->adc->adc_prop->adc_vdd_reference; |
| 2218 | vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].adc_vref |
| 2219 | = vref_calib; |
| 2220 | vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].adc_gnd |
| 2221 | = gnd_calib; |
| 2222 | } else { |
| 2223 | vref_calib = new_vref_calib; |
| 2224 | local_idx = local_idx + 1; |
| 2225 | if (local_idx >= QPNP_VADC_RECALIB_MAXCNT) { |
| 2226 | pr_err( |
| 2227 | "qpnp_vadc recalibration failed, count=%d", |
| 2228 | local_idx); |
| 2229 | } else { |
| 2230 | pr_debug( |
| 2231 | "qpnp vadc recalibration requested,offset:%d\n", |
| 2232 | offset); |
| 2233 | offset = 0; |
| 2234 | goto recalibrate; |
| 2235 | } |
| 2236 | } |
| 2237 | } |
| 2238 | |
| 2239 | amux_prescaling = |
| 2240 | vadc->adc->adc_channels[dt_index].chan_path_prescaling; |
| 2241 | |
| 2242 | if (amux_prescaling >= PATH_SCALING_NONE) { |
| 2243 | rc = -EINVAL; |
| 2244 | goto fail_unlock; |
| 2245 | } |
| 2246 | |
| 2247 | vadc->adc->amux_prop->chan_prop->offset_gain_numerator = |
| 2248 | qpnp_vadc_amux_scaling_ratio[amux_prescaling].num; |
| 2249 | vadc->adc->amux_prop->chan_prop->offset_gain_denominator = |
| 2250 | qpnp_vadc_amux_scaling_ratio[amux_prescaling].den; |
| 2251 | vadc->adc->amux_prop->chan_prop->calib_type = |
| 2252 | vadc->adc->adc_channels[dt_index].calib_type; |
| 2253 | |
| 2254 | scale_type = vadc->adc->adc_channels[dt_index].adc_scale_fn; |
| 2255 | if (scale_type >= SCALE_NONE) { |
| 2256 | rc = -EBADF; |
| 2257 | goto fail_unlock; |
| 2258 | } |
| 2259 | |
| 2260 | if ((qpnp_vadc_channel_post_scaling_calib_check(vadc, channel)) < 0) |
| 2261 | pr_debug("Post scaling calib type not updated\n"); |
| 2262 | |
| 2263 | vadc_scale_fn[scale_type].chan(vadc, result->adc_code, |
| 2264 | vadc->adc->adc_prop, vadc->adc->amux_prop->chan_prop, result); |
| 2265 | |
| 2266 | pr_debug("channel=%d, adc_code=%d adc_result=%lld\n", |
| 2267 | channel, result->adc_code, result->physical); |
| 2268 | |
| 2269 | fail_unlock: |
| 2270 | if (vadc->state_copy->vadc_meas_int_enable) |
| 2271 | qpnp_vadc_manage_meas_int_requests(vadc); |
| 2272 | |
| 2273 | mutex_unlock(&vadc->adc->adc_lock); |
| 2274 | |
| 2275 | return rc; |
| 2276 | } |
| 2277 | EXPORT_SYMBOL(qpnp_vadc_conv_seq_request); |
| 2278 | |
| 2279 | int32_t qpnp_vadc_read(struct qpnp_vadc_chip *vadc, |
| 2280 | enum qpnp_vadc_channels channel, |
| 2281 | struct qpnp_vadc_result *result) |
| 2282 | { |
| 2283 | struct qpnp_vadc_result die_temp_result; |
| 2284 | int rc = 0; |
| 2285 | enum power_supply_property prop; |
| 2286 | union power_supply_propval ret = {0, }; |
| 2287 | |
| 2288 | if (vadc->vadc_hc) { |
| 2289 | rc = qpnp_vadc_hc_read(vadc, channel, result); |
| 2290 | if (rc < 0) { |
| 2291 | pr_err("Error reading vadc_hc channel %d\n", channel); |
| 2292 | return rc; |
| 2293 | } |
| 2294 | |
| 2295 | return 0; |
| 2296 | } |
| 2297 | |
| 2298 | if (channel == VBAT_SNS) { |
| 2299 | rc = qpnp_vadc_conv_seq_request(vadc, ADC_SEQ_NONE, |
| 2300 | channel, result); |
| 2301 | if (rc < 0) { |
| 2302 | pr_err("Error reading vbatt\n"); |
| 2303 | return rc; |
| 2304 | } |
| 2305 | |
| 2306 | rc = qpnp_vadc_conv_seq_request(vadc, ADC_SEQ_NONE, |
| 2307 | DIE_TEMP, &die_temp_result); |
| 2308 | if (rc < 0) { |
| 2309 | pr_err("Error reading die_temp\n"); |
| 2310 | return rc; |
| 2311 | } |
| 2312 | |
| 2313 | rc = qpnp_vbat_sns_comp(&result->physical, vadc, |
| 2314 | die_temp_result.physical); |
| 2315 | if (rc < 0) |
| 2316 | pr_err("Error with vbat compensation\n"); |
| 2317 | |
| 2318 | return 0; |
| 2319 | } else if (channel == SPARE2) { |
| 2320 | /* chg temp channel */ |
| 2321 | if (!vadc->vadc_chg_vote) { |
| 2322 | vadc->vadc_chg_vote = |
| 2323 | power_supply_get_by_name("battery"); |
| 2324 | if (!vadc->vadc_chg_vote) { |
| 2325 | pr_err("no vadc_chg_vote found\n"); |
| 2326 | return -EINVAL; |
| 2327 | } |
| 2328 | } |
| 2329 | |
| 2330 | prop = POWER_SUPPLY_PROP_FORCE_TLIM; |
| 2331 | ret.intval = 1; |
| 2332 | |
| 2333 | rc = power_supply_set_property(vadc->vadc_chg_vote, |
| 2334 | prop, &ret); |
| 2335 | if (rc) { |
| 2336 | pr_err("error enabling the charger circuitry vote\n"); |
| 2337 | return rc; |
| 2338 | } |
| 2339 | |
| 2340 | rc = qpnp_vadc_conv_seq_request(vadc, ADC_SEQ_NONE, |
| 2341 | channel, result); |
| 2342 | if (rc < 0) |
| 2343 | pr_err("Error reading die_temp\n"); |
| 2344 | |
| 2345 | ret.intval = 0; |
| 2346 | rc = power_supply_set_property(vadc->vadc_chg_vote, |
| 2347 | prop, &ret); |
| 2348 | if (rc) { |
| 2349 | pr_err("error enabling the charger circuitry vote\n"); |
| 2350 | return rc; |
| 2351 | } |
| 2352 | |
| 2353 | return 0; |
| 2354 | } else |
| 2355 | return qpnp_vadc_conv_seq_request(vadc, ADC_SEQ_NONE, |
| 2356 | channel, result); |
| 2357 | } |
| 2358 | EXPORT_SYMBOL(qpnp_vadc_read); |
| 2359 | |
| 2360 | static void qpnp_vadc_lock(struct qpnp_vadc_chip *vadc) |
| 2361 | { |
| 2362 | mutex_lock(&vadc->adc->adc_lock); |
| 2363 | } |
| 2364 | |
| 2365 | static void qpnp_vadc_unlock(struct qpnp_vadc_chip *vadc) |
| 2366 | { |
| 2367 | mutex_unlock(&vadc->adc->adc_lock); |
| 2368 | } |
| 2369 | |
| 2370 | int32_t qpnp_vadc_iadc_sync_request(struct qpnp_vadc_chip *vadc, |
| 2371 | enum qpnp_vadc_channels channel) |
| 2372 | { |
| 2373 | int rc = 0, dt_index = 0, calib_type = 0; |
| 2374 | |
| 2375 | if (qpnp_vadc_is_valid(vadc)) |
| 2376 | return -EPROBE_DEFER; |
| 2377 | |
| 2378 | qpnp_vadc_lock(vadc); |
| 2379 | |
| 2380 | |
| 2381 | vadc->adc->amux_prop->amux_channel = channel; |
| 2382 | |
| 2383 | while ((vadc->adc->adc_channels[dt_index].channel_num |
| 2384 | != channel) && (dt_index < vadc->max_channels_available)) |
| 2385 | dt_index++; |
| 2386 | |
| 2387 | if (dt_index >= vadc->max_channels_available) { |
| 2388 | pr_err("not a valid VADC channel\n"); |
| 2389 | rc = -EINVAL; |
| 2390 | goto fail; |
| 2391 | } |
| 2392 | |
| 2393 | calib_type = vadc->adc->adc_channels[dt_index].calib_type; |
| 2394 | if (!vadc->vadc_init_calib) { |
| 2395 | rc = qpnp_vadc_version_check(vadc); |
| 2396 | if (rc) |
| 2397 | goto fail; |
| 2398 | |
| 2399 | rc = qpnp_vadc_calib_device(vadc); |
| 2400 | if (rc) { |
| 2401 | pr_err("Calibration failed\n"); |
| 2402 | goto fail; |
| 2403 | } else |
| 2404 | vadc->vadc_init_calib = true; |
| 2405 | } |
| 2406 | |
| 2407 | vadc->adc->amux_prop->decimation = |
| 2408 | vadc->adc->adc_channels[dt_index].adc_decimation; |
| 2409 | vadc->adc->amux_prop->hw_settle_time = |
| 2410 | vadc->adc->adc_channels[dt_index].hw_settle_time; |
| 2411 | vadc->adc->amux_prop->fast_avg_setup = |
| 2412 | vadc->adc->adc_channels[dt_index].fast_avg_setup; |
| 2413 | vadc->adc->amux_prop->mode_sel = (ADC_OP_NORMAL_MODE |
| 2414 | << QPNP_VADC_OP_MODE_SHIFT); |
| 2415 | vadc->vadc_iadc_sync_lock = true; |
| 2416 | |
| 2417 | rc = qpnp_vadc_configure(vadc, vadc->adc->amux_prop); |
| 2418 | if (rc) { |
| 2419 | pr_err("qpnp vadc configure failed with %d\n", rc); |
| 2420 | goto fail; |
| 2421 | } |
| 2422 | |
| 2423 | return rc; |
| 2424 | fail: |
| 2425 | vadc->vadc_iadc_sync_lock = false; |
| 2426 | qpnp_vadc_unlock(vadc); |
| 2427 | return rc; |
| 2428 | } |
| 2429 | EXPORT_SYMBOL(qpnp_vadc_iadc_sync_request); |
| 2430 | |
| 2431 | int32_t qpnp_vadc_iadc_sync_complete_request(struct qpnp_vadc_chip *vadc, |
| 2432 | enum qpnp_vadc_channels channel, |
| 2433 | struct qpnp_vadc_result *result) |
| 2434 | { |
| 2435 | int rc = 0, scale_type, amux_prescaling, dt_index = 0; |
| 2436 | |
| 2437 | vadc->adc->amux_prop->amux_channel = channel; |
| 2438 | |
| 2439 | while ((vadc->adc->adc_channels[dt_index].channel_num |
| 2440 | != channel) && (dt_index < vadc->max_channels_available)) |
| 2441 | dt_index++; |
| 2442 | |
| 2443 | rc = qpnp_vadc_read_conversion_result(vadc, &result->adc_code); |
| 2444 | if (rc) { |
| 2445 | pr_err("qpnp vadc read adc code failed with %d\n", rc); |
| 2446 | goto fail; |
| 2447 | } |
| 2448 | |
| 2449 | amux_prescaling = |
| 2450 | vadc->adc->adc_channels[dt_index].chan_path_prescaling; |
| 2451 | |
| 2452 | if (amux_prescaling >= PATH_SCALING_NONE) { |
| 2453 | rc = -EINVAL; |
| 2454 | goto fail; |
| 2455 | } |
| 2456 | |
| 2457 | vadc->adc->amux_prop->chan_prop->offset_gain_numerator = |
| 2458 | qpnp_vadc_amux_scaling_ratio[amux_prescaling].num; |
| 2459 | vadc->adc->amux_prop->chan_prop->offset_gain_denominator = |
| 2460 | qpnp_vadc_amux_scaling_ratio[amux_prescaling].den; |
| 2461 | |
| 2462 | scale_type = vadc->adc->adc_channels[dt_index].adc_scale_fn; |
| 2463 | if (scale_type >= SCALE_NONE) { |
| 2464 | rc = -EBADF; |
| 2465 | goto fail; |
| 2466 | } |
| 2467 | |
| 2468 | vadc_scale_fn[scale_type].chan(vadc, result->adc_code, |
| 2469 | vadc->adc->adc_prop, vadc->adc->amux_prop->chan_prop, result); |
| 2470 | |
| 2471 | fail: |
| 2472 | vadc->vadc_iadc_sync_lock = false; |
| 2473 | qpnp_vadc_unlock(vadc); |
| 2474 | return rc; |
| 2475 | } |
| 2476 | EXPORT_SYMBOL(qpnp_vadc_iadc_sync_complete_request); |
| 2477 | |
| 2478 | static int32_t qpnp_vadc_thr_update(struct qpnp_vadc_chip *vadc, |
| 2479 | int32_t high_thr, int32_t low_thr) |
| 2480 | { |
| 2481 | int rc = 0; |
| 2482 | u8 buf = 0; |
| 2483 | |
| 2484 | pr_debug("client requested high:%d and low:%d\n", |
| 2485 | high_thr, low_thr); |
| 2486 | |
| 2487 | buf = QPNP_VADC_THR_LSB_MASK(low_thr); |
| 2488 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_LOW_THR_LSB, &buf, 1); |
| 2489 | if (rc < 0) { |
| 2490 | pr_err("low threshold lsb setting failed, err:%d\n", rc); |
| 2491 | return rc; |
| 2492 | } |
| 2493 | |
| 2494 | buf = QPNP_VADC_THR_MSB_MASK(low_thr); |
| 2495 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_LOW_THR_MSB, &buf, 1); |
| 2496 | if (rc < 0) { |
| 2497 | pr_err("low threshold msb setting failed, err:%d\n", rc); |
| 2498 | return rc; |
| 2499 | } |
| 2500 | |
| 2501 | buf = QPNP_VADC_THR_LSB_MASK(high_thr); |
| 2502 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HIGH_THR_LSB, &buf, 1); |
| 2503 | if (rc < 0) { |
| 2504 | pr_err("high threshold lsb setting failed, err:%d\n", rc); |
| 2505 | return rc; |
| 2506 | } |
| 2507 | |
| 2508 | buf = QPNP_VADC_THR_MSB_MASK(high_thr); |
| 2509 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HIGH_THR_MSB, &buf, 1); |
| 2510 | if (rc < 0) { |
| 2511 | pr_err("high threshold msb setting failed, err:%d\n", rc); |
| 2512 | return rc; |
| 2513 | } |
| 2514 | |
| 2515 | pr_debug("client requested high:%d and low:%d\n", high_thr, low_thr); |
| 2516 | |
| 2517 | return rc; |
| 2518 | } |
| 2519 | |
| 2520 | int32_t qpnp_vadc_channel_monitor(struct qpnp_vadc_chip *chip, |
| 2521 | struct qpnp_adc_tm_btm_param *param) |
| 2522 | { |
| 2523 | uint32_t channel, scale_type = 0; |
| 2524 | uint32_t low_thr = 0, high_thr = 0; |
| 2525 | int rc = 0, idx = 0, amux_prescaling = 0; |
| 2526 | struct qpnp_vadc_chip *vadc = dev_get_drvdata(chip->dev); |
| 2527 | u8 buf = 0; |
| 2528 | |
| 2529 | if (qpnp_vadc_is_valid(vadc)) |
| 2530 | return -EPROBE_DEFER; |
| 2531 | |
| 2532 | if (!vadc->state_copy->vadc_meas_int_enable) { |
| 2533 | pr_err("Recurring measurement interval not available\n"); |
| 2534 | return -EINVAL; |
| 2535 | } |
| 2536 | |
| 2537 | if (param->threshold_notification == NULL) { |
| 2538 | pr_debug("No notification for high/low temp??\n"); |
| 2539 | return -EINVAL; |
| 2540 | } |
| 2541 | |
| 2542 | mutex_lock(&vadc->adc->adc_lock); |
| 2543 | |
| 2544 | channel = param->channel; |
| 2545 | while (idx < vadc->max_channels_available) { |
| 2546 | if (vadc->adc->adc_channels[idx].channel_num == channel) |
| 2547 | break; |
| 2548 | idx++; |
| 2549 | } |
| 2550 | |
| 2551 | if (idx >= vadc->max_channels_available) { |
| 2552 | pr_err("not a valid VADC channel\n"); |
| 2553 | rc = -EINVAL; |
| 2554 | goto fail_unlock; |
| 2555 | } |
| 2556 | |
| 2557 | scale_type = vadc->adc->adc_channels[idx].adc_scale_fn; |
| 2558 | if (scale_type >= SCALE_RVADC_SCALE_NONE) { |
| 2559 | rc = -EBADF; |
| 2560 | goto fail_unlock; |
| 2561 | } |
| 2562 | |
| 2563 | amux_prescaling = |
| 2564 | vadc->adc->adc_channels[idx].chan_path_prescaling; |
| 2565 | |
| 2566 | if (amux_prescaling >= PATH_SCALING_NONE) { |
| 2567 | rc = -EINVAL; |
| 2568 | goto fail_unlock; |
| 2569 | } |
| 2570 | |
| 2571 | vadc->adc->amux_prop->chan_prop->offset_gain_numerator = |
| 2572 | qpnp_vadc_amux_scaling_ratio[amux_prescaling].num; |
| 2573 | vadc->adc->amux_prop->chan_prop->offset_gain_denominator = |
| 2574 | qpnp_vadc_amux_scaling_ratio[amux_prescaling].den; |
| 2575 | vadc->adc->amux_prop->chan_prop->calib_type = |
| 2576 | vadc->adc->adc_channels[idx].calib_type; |
| 2577 | |
| 2578 | pr_debug("channel:%d, scale_type:%d, dt_idx:%d", |
| 2579 | channel, scale_type, idx); |
| 2580 | vadc->adc->amux_prop->amux_channel = channel; |
| 2581 | vadc->adc->amux_prop->decimation = |
| 2582 | vadc->adc->adc_channels[idx].adc_decimation; |
| 2583 | vadc->adc->amux_prop->hw_settle_time = |
| 2584 | vadc->adc->adc_channels[idx].hw_settle_time; |
| 2585 | vadc->adc->amux_prop->fast_avg_setup = |
| 2586 | vadc->adc->adc_channels[idx].fast_avg_setup; |
| 2587 | vadc->adc->amux_prop->mode_sel = ADC_OP_MEASUREMENT_INTERVAL; |
| 2588 | adc_vadc_rscale_fn[scale_type].chan(vadc, |
| 2589 | vadc->adc->amux_prop->chan_prop, param, |
| 2590 | &low_thr, &high_thr); |
| 2591 | |
| 2592 | if (param->timer_interval >= ADC_MEAS1_INTERVAL_NONE) { |
| 2593 | pr_err("Invalid timer interval :%d\n", param->timer_interval); |
| 2594 | goto fail_unlock; |
| 2595 | } |
| 2596 | |
| 2597 | buf = param->timer_interval; |
| 2598 | rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_MEAS_INTERVAL_CTL, &buf, 1); |
| 2599 | if (rc) { |
| 2600 | pr_err("vadc meas timer failed with %d\n", rc); |
| 2601 | goto fail_unlock; |
| 2602 | } |
| 2603 | |
| 2604 | rc = qpnp_vadc_thr_update(vadc, high_thr, low_thr); |
| 2605 | if (rc) { |
| 2606 | pr_err("vadc thr update failed with %d\n", rc); |
| 2607 | goto fail_unlock; |
| 2608 | } |
| 2609 | |
| 2610 | rc = qpnp_vadc_configure(vadc, vadc->adc->amux_prop); |
| 2611 | if (rc) { |
| 2612 | pr_err("vadc configure failed with %d\n", rc); |
| 2613 | goto fail_unlock; |
| 2614 | } |
| 2615 | |
| 2616 | vadc->state_copy->meas_int_mode = true; |
| 2617 | vadc->state_copy->param = param; |
| 2618 | vadc->state_copy->vadc_meas_amux.channel_num = channel; |
| 2619 | vadc->state_copy->vadc_meas_amux.adc_decimation = |
| 2620 | vadc->adc->amux_prop->decimation; |
| 2621 | vadc->state_copy->vadc_meas_amux.hw_settle_time = |
| 2622 | vadc->adc->amux_prop->hw_settle_time; |
| 2623 | vadc->state_copy->vadc_meas_amux.fast_avg_setup = |
| 2624 | vadc->adc->amux_prop->fast_avg_setup; |
| 2625 | vadc->state_copy->meas_int_request_in_queue = false; |
| 2626 | dev_set_drvdata(vadc->dev, vadc); |
| 2627 | |
| 2628 | fail_unlock: |
| 2629 | mutex_unlock(&vadc->adc->adc_lock); |
| 2630 | |
| 2631 | return rc; |
| 2632 | } |
| 2633 | EXPORT_SYMBOL(qpnp_vadc_channel_monitor); |
| 2634 | |
| 2635 | int32_t qpnp_vadc_end_channel_monitor(struct qpnp_vadc_chip *chip) |
| 2636 | { |
| 2637 | struct qpnp_vadc_chip *vadc = dev_get_drvdata(chip->dev); |
| 2638 | u8 mode_ctl = 0; |
| 2639 | |
| 2640 | if (qpnp_vadc_is_valid(vadc)) |
| 2641 | return -EPROBE_DEFER; |
| 2642 | |
| 2643 | if (!vadc->state_copy->vadc_meas_int_enable) { |
| 2644 | pr_err("Recurring measurement interval not available\n"); |
| 2645 | return -EINVAL; |
| 2646 | } |
| 2647 | |
| 2648 | vadc->state_copy->meas_int_mode = false; |
| 2649 | vadc->state_copy->meas_int_request_in_queue = false; |
| 2650 | dev_set_drvdata(vadc->dev, vadc); |
| 2651 | mode_ctl = ADC_OP_NORMAL_MODE; |
| 2652 | /* Set measurement in single measurement mode */ |
| 2653 | qpnp_vadc_mode_select(vadc, mode_ctl); |
| 2654 | qpnp_vadc_enable(vadc, false); |
| 2655 | |
| 2656 | return 0; |
| 2657 | } |
| 2658 | EXPORT_SYMBOL(qpnp_vadc_end_channel_monitor); |
| 2659 | |
| 2660 | static ssize_t qpnp_adc_show(struct device *dev, |
| 2661 | struct device_attribute *devattr, char *buf) |
| 2662 | { |
| 2663 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); |
| 2664 | struct qpnp_vadc_chip *vadc = dev_get_drvdata(dev); |
| 2665 | struct qpnp_vadc_result result; |
| 2666 | int rc = -1; |
| 2667 | |
| 2668 | rc = qpnp_vadc_read(vadc, attr->index, &result); |
| 2669 | |
| 2670 | if (rc) { |
| 2671 | pr_err("VADC read error with %d\n", rc); |
| 2672 | return 0; |
| 2673 | } |
| 2674 | |
| 2675 | return snprintf(buf, QPNP_ADC_HWMON_NAME_LENGTH, |
| 2676 | "Result:%lld Raw:%x\n", result.physical, result.adc_code); |
| 2677 | } |
| 2678 | |
| 2679 | static struct sensor_device_attribute qpnp_adc_attr = |
| 2680 | SENSOR_ATTR(NULL, 0444, qpnp_adc_show, NULL, 0); |
| 2681 | |
| 2682 | static int32_t qpnp_vadc_init_hwmon(struct qpnp_vadc_chip *vadc, |
| 2683 | struct platform_device *pdev) |
| 2684 | { |
| 2685 | struct device_node *child; |
| 2686 | struct device_node *node = pdev->dev.of_node; |
| 2687 | int rc = 0, i = 0, channel; |
| 2688 | |
| 2689 | for_each_child_of_node(node, child) { |
| 2690 | channel = vadc->adc->adc_channels[i].channel_num; |
| 2691 | qpnp_adc_attr.index = vadc->adc->adc_channels[i].channel_num; |
| 2692 | qpnp_adc_attr.dev_attr.attr.name = |
| 2693 | vadc->adc->adc_channels[i].name; |
| 2694 | memcpy(&vadc->sens_attr[i], &qpnp_adc_attr, |
| 2695 | sizeof(qpnp_adc_attr)); |
| 2696 | sysfs_attr_init(&vadc->sens_attr[i].dev_attr.attr); |
| 2697 | rc = device_create_file(&pdev->dev, |
| 2698 | &vadc->sens_attr[i].dev_attr); |
| 2699 | if (rc) { |
| 2700 | dev_err(&pdev->dev, |
| 2701 | "device_create_file failed for dev %s\n", |
| 2702 | vadc->adc->adc_channels[i].name); |
| 2703 | goto hwmon_err_sens; |
| 2704 | } |
| 2705 | i++; |
| 2706 | } |
| 2707 | |
| 2708 | return 0; |
| 2709 | hwmon_err_sens: |
| 2710 | pr_err("Init HWMON failed for qpnp_adc with %d\n", rc); |
| 2711 | return rc; |
| 2712 | } |
| 2713 | |
Siddartha Mohanadoss | f7c907e | 2017-04-19 16:18:14 -0700 | [diff] [blame] | 2714 | static int qpnp_vadc_get_temp(void *data, int *temp) |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 2715 | { |
Siddartha Mohanadoss | f7c907e | 2017-04-19 16:18:14 -0700 | [diff] [blame] | 2716 | struct qpnp_vadc_thermal_data *vadc_therm = data; |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 2717 | struct qpnp_vadc_chip *vadc = vadc_therm->vadc_dev; |
| 2718 | struct qpnp_vadc_result result; |
| 2719 | int rc = 0; |
| 2720 | |
| 2721 | rc = qpnp_vadc_read(vadc, |
| 2722 | vadc_therm->vadc_channel, &result); |
| 2723 | if (rc) { |
| 2724 | if (rc != -EPROBE_DEFER) |
| 2725 | pr_err("VADC read error with %d\n", rc); |
| 2726 | return rc; |
| 2727 | } |
| 2728 | |
| 2729 | *temp = result.physical; |
| 2730 | |
| 2731 | return rc; |
| 2732 | } |
| 2733 | |
Siddartha Mohanadoss | f7c907e | 2017-04-19 16:18:14 -0700 | [diff] [blame] | 2734 | static struct thermal_zone_of_device_ops qpnp_vadc_thermal_ops = { |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 2735 | .get_temp = qpnp_vadc_get_temp, |
| 2736 | }; |
| 2737 | |
| 2738 | static int32_t qpnp_vadc_init_thermal(struct qpnp_vadc_chip *vadc, |
| 2739 | struct platform_device *pdev) |
| 2740 | { |
| 2741 | struct device_node *child; |
| 2742 | struct device_node *node = pdev->dev.of_node; |
| 2743 | int rc = 0, i = 0; |
| 2744 | bool thermal_node = false; |
| 2745 | |
| 2746 | if (node == NULL) |
| 2747 | goto thermal_err_sens; |
| 2748 | for_each_child_of_node(node, child) { |
| 2749 | char name[QPNP_THERMALNODE_NAME_LENGTH]; |
| 2750 | |
| 2751 | vadc->vadc_therm_chan[i].vadc_channel = |
| 2752 | vadc->adc->adc_channels[i].channel_num; |
| 2753 | vadc->vadc_therm_chan[i].thermal_chan = i; |
| 2754 | thermal_node = of_property_read_bool(child, |
| 2755 | "qcom,vadc-thermal-node"); |
| 2756 | if (thermal_node) { |
| 2757 | /* Register with the thermal zone */ |
| 2758 | vadc->vadc_therm_chan[i].thermal_node = true; |
| 2759 | snprintf(name, sizeof(name), "%s", |
| 2760 | vadc->adc->adc_channels[i].name); |
| 2761 | vadc->vadc_therm_chan[i].vadc_dev = vadc; |
| 2762 | vadc->vadc_therm_chan[i].tz_dev = |
Siddartha Mohanadoss | f7c907e | 2017-04-19 16:18:14 -0700 | [diff] [blame] | 2763 | devm_thermal_zone_of_sensor_register( |
| 2764 | vadc->dev, |
| 2765 | vadc->vadc_therm_chan[i].vadc_channel, |
| 2766 | &vadc->vadc_therm_chan[i], |
| 2767 | &qpnp_vadc_thermal_ops); |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 2768 | if (IS_ERR(vadc->vadc_therm_chan[i].tz_dev)) { |
| 2769 | pr_err("thermal device register failed.\n"); |
Maria Yu | 92ac216 | 2018-01-03 18:32:36 +0800 | [diff] [blame] | 2770 | rc = PTR_ERR(vadc->vadc_therm_chan[i].tz_dev); |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 2771 | goto thermal_err_sens; |
| 2772 | } |
| 2773 | } |
| 2774 | i++; |
| 2775 | thermal_node = false; |
| 2776 | } |
| 2777 | return 0; |
| 2778 | thermal_err_sens: |
| 2779 | pr_err("Init HWMON failed for qpnp_adc with %d\n", rc); |
| 2780 | return rc; |
| 2781 | } |
| 2782 | |
| 2783 | static const struct of_device_id qpnp_vadc_match_table[] = { |
| 2784 | { .compatible = "qcom,qpnp-vadc", |
| 2785 | }, |
| 2786 | { .compatible = "qcom,qpnp-vadc-hc", |
| 2787 | }, |
Jishnu Prakash | d09bc69 | 2018-05-02 10:54:28 +0530 | [diff] [blame] | 2788 | { .compatible = "qcom,qpnp-adc-hc-pm5", |
| 2789 | }, |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 2790 | {} |
| 2791 | }; |
| 2792 | |
| 2793 | static int qpnp_vadc_probe(struct platform_device *pdev) |
| 2794 | { |
| 2795 | struct qpnp_vadc_chip *vadc; |
| 2796 | struct qpnp_adc_drv *adc_qpnp; |
| 2797 | struct qpnp_vadc_thermal_data *adc_thermal; |
Jishnu Prakash | a2d0099 | 2018-11-16 17:09:49 +0530 | [diff] [blame] | 2798 | struct device_node *node = pdev->dev.of_node, *revid_dev_node; |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 2799 | struct device_node *child; |
| 2800 | const struct of_device_id *id; |
| 2801 | int rc, count_adc_channel_list = 0, i = 0; |
| 2802 | u8 fab_id = 0; |
| 2803 | |
| 2804 | for_each_child_of_node(node, child) |
| 2805 | count_adc_channel_list++; |
| 2806 | |
| 2807 | if (!count_adc_channel_list) { |
| 2808 | pr_err("No channel listing\n"); |
| 2809 | return -EINVAL; |
| 2810 | } |
| 2811 | |
| 2812 | id = of_match_node(qpnp_vadc_match_table, node); |
| 2813 | if (id == NULL) { |
| 2814 | pr_err("qpnp_vadc_match of_node prop not present\n"); |
| 2815 | return -ENODEV; |
| 2816 | } |
| 2817 | |
| 2818 | vadc = devm_kzalloc(&pdev->dev, sizeof(struct qpnp_vadc_chip) + |
| 2819 | (sizeof(struct sensor_device_attribute) * |
| 2820 | count_adc_channel_list), GFP_KERNEL); |
| 2821 | if (!vadc) { |
| 2822 | dev_err(&pdev->dev, "Unable to allocate memory\n"); |
| 2823 | return -ENOMEM; |
| 2824 | } |
| 2825 | |
| 2826 | vadc->dev = &(pdev->dev); |
| 2827 | adc_qpnp = devm_kzalloc(&pdev->dev, sizeof(struct qpnp_adc_drv), |
| 2828 | GFP_KERNEL); |
| 2829 | if (!adc_qpnp) |
| 2830 | return -ENOMEM; |
| 2831 | |
| 2832 | adc_qpnp->regmap = dev_get_regmap(pdev->dev.parent, NULL); |
| 2833 | if (!adc_qpnp->regmap) { |
| 2834 | dev_err(&pdev->dev, "Couldn't get parent's regmap\n"); |
| 2835 | return -EINVAL; |
| 2836 | } |
| 2837 | |
| 2838 | vadc->state_copy = devm_kzalloc(&pdev->dev, |
| 2839 | sizeof(struct qpnp_vadc_mode_state), GFP_KERNEL); |
| 2840 | if (!vadc->state_copy) |
| 2841 | return -ENOMEM; |
| 2842 | |
| 2843 | vadc->adc = adc_qpnp; |
| 2844 | adc_thermal = devm_kzalloc(&pdev->dev, |
| 2845 | (sizeof(struct qpnp_vadc_thermal_data) * |
| 2846 | count_adc_channel_list), GFP_KERNEL); |
| 2847 | if (!adc_thermal) { |
| 2848 | dev_err(&pdev->dev, "Unable to allocate memory\n"); |
| 2849 | return -ENOMEM; |
| 2850 | } |
| 2851 | |
Jishnu Prakash | a2d0099 | 2018-11-16 17:09:49 +0530 | [diff] [blame] | 2852 | revid_dev_node = of_parse_phandle(node, "qcom,pmic-revid", 0); |
| 2853 | if (revid_dev_node) { |
| 2854 | vadc->pmic_rev_id = get_revid_data(revid_dev_node); |
| 2855 | if (IS_ERR(vadc->pmic_rev_id)) { |
| 2856 | pr_err("Unable to get revid\n"); |
| 2857 | vadc->pmic_rev_id = NULL; |
| 2858 | } |
| 2859 | of_node_put(revid_dev_node); |
| 2860 | } |
| 2861 | |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 2862 | vadc->vadc_therm_chan = adc_thermal; |
| 2863 | if (!strcmp(id->compatible, "qcom,qpnp-vadc-hc")) { |
| 2864 | vadc->vadc_hc = true; |
| 2865 | vadc->adc->adc_hc = true; |
| 2866 | } |
| 2867 | |
| 2868 | rc = qpnp_adc_get_devicetree_data(pdev, vadc->adc); |
| 2869 | if (rc) { |
| 2870 | dev_err(&pdev->dev, "failed to read device tree\n"); |
| 2871 | return rc; |
| 2872 | } |
| 2873 | mutex_init(&vadc->adc->adc_lock); |
| 2874 | |
| 2875 | rc = qpnp_vadc_init_hwmon(vadc, pdev); |
| 2876 | if (rc) { |
| 2877 | dev_err(&pdev->dev, "failed to initialize qpnp hwmon adc\n"); |
| 2878 | return rc; |
| 2879 | } |
| 2880 | vadc->vadc_hwmon = hwmon_device_register(&vadc->adc->pdev->dev); |
| 2881 | rc = qpnp_vadc_init_thermal(vadc, pdev); |
| 2882 | if (rc) { |
| 2883 | dev_err(&pdev->dev, "failed to initialize qpnp thermal adc\n"); |
| 2884 | return rc; |
| 2885 | } |
| 2886 | vadc->vadc_init_calib = false; |
| 2887 | vadc->max_channels_available = count_adc_channel_list; |
| 2888 | rc = qpnp_vadc_read_reg(vadc, QPNP_INT_TEST_VAL, &fab_id, 1); |
| 2889 | if (rc < 0) { |
| 2890 | pr_err("qpnp adc comp id failed with %d\n", rc); |
| 2891 | goto err_setup; |
| 2892 | } |
| 2893 | vadc->id = fab_id; |
| 2894 | pr_debug("fab_id = %d\n", fab_id); |
| 2895 | |
| 2896 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_REVISION2, |
| 2897 | &vadc->revision_dig_major, 1); |
| 2898 | if (rc < 0) { |
| 2899 | pr_err("qpnp adc dig_major rev read failed with %d\n", rc); |
| 2900 | goto err_setup; |
| 2901 | } |
| 2902 | |
| 2903 | rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_REVISION3, |
| 2904 | &vadc->revision_ana_minor, 1); |
| 2905 | if (rc < 0) { |
| 2906 | pr_err("qpnp adc ana_minor rev read failed with %d\n", rc); |
| 2907 | goto err_setup; |
| 2908 | } |
| 2909 | |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 2910 | INIT_WORK(&vadc->trigger_completion_work, qpnp_vadc_work); |
| 2911 | |
| 2912 | vadc->vadc_recalib_check = of_property_read_bool(node, |
| 2913 | "qcom,vadc-recalib-check"); |
| 2914 | |
| 2915 | vadc->vadc_poll_eoc = of_property_read_bool(node, |
| 2916 | "qcom,vadc-poll-eoc"); |
| 2917 | if (!vadc->vadc_poll_eoc) { |
| 2918 | rc = devm_request_irq(&pdev->dev, vadc->adc->adc_irq_eoc, |
| 2919 | qpnp_vadc_isr, IRQF_TRIGGER_RISING, |
| 2920 | "qpnp_vadc_interrupt", vadc); |
| 2921 | if (rc) { |
| 2922 | dev_err(&pdev->dev, |
| 2923 | "failed to request adc irq with error %d\n", rc); |
| 2924 | goto err_setup; |
| 2925 | } else { |
| 2926 | enable_irq_wake(vadc->adc->adc_irq_eoc); |
| 2927 | } |
| 2928 | } else |
| 2929 | device_init_wakeup(vadc->dev, 1); |
| 2930 | |
| 2931 | vadc->state_copy->vadc_meas_int_enable = of_property_read_bool(node, |
| 2932 | "qcom,vadc-meas-int-mode"); |
| 2933 | if (vadc->state_copy->vadc_meas_int_enable) { |
| 2934 | vadc->adc->adc_high_thr_irq = platform_get_irq_byname(pdev, |
| 2935 | "high-thr-en-set"); |
| 2936 | if (vadc->adc->adc_high_thr_irq < 0) { |
| 2937 | pr_err("Invalid irq\n"); |
| 2938 | rc = -ENXIO; |
| 2939 | goto err_setup; |
| 2940 | } |
| 2941 | |
| 2942 | vadc->adc->adc_low_thr_irq = platform_get_irq_byname(pdev, |
| 2943 | "low-thr-en-set"); |
| 2944 | if (vadc->adc->adc_low_thr_irq < 0) { |
| 2945 | pr_err("Invalid irq\n"); |
| 2946 | rc = -ENXIO; |
| 2947 | goto err_setup; |
| 2948 | } |
| 2949 | |
| 2950 | rc = devm_request_irq(&pdev->dev, vadc->adc->adc_high_thr_irq, |
| 2951 | qpnp_vadc_high_thr_isr, |
| 2952 | IRQF_TRIGGER_RISING, "qpnp_vadc_high_interrupt", vadc); |
| 2953 | if (rc) { |
| 2954 | dev_err(&pdev->dev, "failed to request adc irq\n"); |
| 2955 | goto err_setup; |
| 2956 | } else { |
| 2957 | enable_irq_wake(vadc->adc->adc_high_thr_irq); |
| 2958 | } |
| 2959 | |
| 2960 | rc = devm_request_irq(&pdev->dev, vadc->adc->adc_low_thr_irq, |
| 2961 | qpnp_vadc_low_thr_isr, |
| 2962 | IRQF_TRIGGER_RISING, "qpnp_vadc_low_interrupt", vadc); |
| 2963 | if (rc) { |
| 2964 | dev_err(&pdev->dev, "failed to request adc irq\n"); |
| 2965 | goto err_setup; |
| 2966 | } else { |
| 2967 | enable_irq_wake(vadc->adc->adc_low_thr_irq); |
| 2968 | } |
| 2969 | INIT_WORK(&vadc->trigger_high_thr_work, |
| 2970 | qpnp_vadc_high_thr_fn); |
| 2971 | INIT_WORK(&vadc->trigger_low_thr_work, qpnp_vadc_low_thr_fn); |
| 2972 | } |
| 2973 | |
| 2974 | vadc->vadc_iadc_sync_lock = false; |
| 2975 | dev_set_drvdata(&pdev->dev, vadc); |
| 2976 | list_add(&vadc->list, &qpnp_vadc_device_list); |
| 2977 | |
| 2978 | return 0; |
| 2979 | |
| 2980 | err_setup: |
| 2981 | for_each_child_of_node(node, child) { |
| 2982 | device_remove_file(&pdev->dev, &vadc->sens_attr[i].dev_attr); |
| 2983 | if (vadc->vadc_therm_chan[i].thermal_node) |
| 2984 | thermal_zone_device_unregister( |
| 2985 | vadc->vadc_therm_chan[i].tz_dev); |
| 2986 | i++; |
| 2987 | } |
| 2988 | hwmon_device_unregister(vadc->vadc_hwmon); |
| 2989 | |
| 2990 | return rc; |
| 2991 | } |
| 2992 | |
| 2993 | static int qpnp_vadc_remove(struct platform_device *pdev) |
| 2994 | { |
| 2995 | struct qpnp_vadc_chip *vadc = dev_get_drvdata(&pdev->dev); |
| 2996 | struct device_node *node = pdev->dev.of_node; |
| 2997 | struct device_node *child; |
| 2998 | int i = 0; |
| 2999 | |
| 3000 | for_each_child_of_node(node, child) { |
| 3001 | device_remove_file(&pdev->dev, &vadc->sens_attr[i].dev_attr); |
| 3002 | if (vadc->vadc_therm_chan[i].thermal_node) |
| 3003 | thermal_zone_device_unregister( |
| 3004 | vadc->vadc_therm_chan[i].tz_dev); |
| 3005 | i++; |
| 3006 | } |
| 3007 | hwmon_device_unregister(vadc->vadc_hwmon); |
| 3008 | list_del(&vadc->list); |
| 3009 | if (vadc->adc->hkadc_ldo && vadc->adc->hkadc_ldo_ok) |
| 3010 | qpnp_adc_free_voltage_resource(vadc->adc); |
| 3011 | dev_set_drvdata(&pdev->dev, NULL); |
| 3012 | |
| 3013 | return 0; |
| 3014 | } |
| 3015 | |
| 3016 | static int qpnp_vadc_suspend_noirq(struct device *dev) |
| 3017 | { |
| 3018 | struct qpnp_vadc_chip *vadc = dev_get_drvdata(dev); |
| 3019 | u8 status = 0; |
| 3020 | |
| 3021 | qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status, 1); |
| 3022 | if (((status & QPNP_VADC_STATUS1_OP_MODE_MASK) >> |
| 3023 | QPNP_VADC_OP_MODE_SHIFT) == QPNP_VADC_MEAS_INT_MODE) { |
| 3024 | pr_debug("Meas interval in progress\n"); |
| 3025 | } else if (vadc->vadc_poll_eoc) { |
| 3026 | status &= QPNP_VADC_STATUS1_REQ_STS_EOC_MASK; |
| 3027 | pr_debug("vadc conversion status=%d\n", status); |
| 3028 | if (status != QPNP_VADC_STATUS1_EOC) { |
| 3029 | pr_err( |
| 3030 | "Aborting suspend, adc conversion requested while suspending\n"); |
| 3031 | return -EBUSY; |
| 3032 | } |
| 3033 | } |
| 3034 | |
| 3035 | return 0; |
| 3036 | } |
| 3037 | |
| 3038 | static const struct dev_pm_ops qpnp_vadc_pm_ops = { |
| 3039 | .suspend_noirq = qpnp_vadc_suspend_noirq, |
| 3040 | }; |
| 3041 | |
| 3042 | static struct platform_driver qpnp_vadc_driver = { |
| 3043 | .driver = { |
| 3044 | .name = "qcom,qpnp-vadc", |
| 3045 | .of_match_table = qpnp_vadc_match_table, |
| 3046 | .pm = &qpnp_vadc_pm_ops, |
| 3047 | }, |
| 3048 | .probe = qpnp_vadc_probe, |
| 3049 | .remove = qpnp_vadc_remove, |
| 3050 | }; |
| 3051 | |
| 3052 | static int __init qpnp_vadc_init(void) |
| 3053 | { |
| 3054 | return platform_driver_register(&qpnp_vadc_driver); |
| 3055 | } |
| 3056 | module_init(qpnp_vadc_init); |
| 3057 | |
| 3058 | static void __exit qpnp_vadc_exit(void) |
| 3059 | { |
| 3060 | platform_driver_unregister(&qpnp_vadc_driver); |
| 3061 | } |
| 3062 | module_exit(qpnp_vadc_exit); |
| 3063 | |
| 3064 | MODULE_DESCRIPTION("QPNP PMIC Voltage ADC driver"); |
| 3065 | MODULE_LICENSE("GPL v2"); |