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Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * pata-cs5530.c - CS5530 PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * based upon cs5530.c by Mark Lord.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 * Loosely based on the piix & svwks drivers.
22 *
23 * Documentation:
24 * Available from AMD web site.
25 */
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/blkdev.h>
32#include <linux/delay.h>
33#include <scsi/scsi_host.h>
34#include <linux/libata.h>
35#include <linux/dmi.h>
36
37#define DRV_NAME "pata_cs5530"
Jeff Garzikcb48cab2007-02-26 06:04:24 -050038#define DRV_VERSION "0.7.2"
Jeff Garzik669a5db2006-08-29 18:12:40 -040039
Tejun Heo0d5ff562007-02-01 15:06:36 +090040static void __iomem *cs5530_port_base(struct ata_port *ap)
41{
42 unsigned long bmdma = (unsigned long)ap->ioaddr.bmdma_addr;
43
44 return (void __iomem *)((bmdma & ~0x0F) + 0x20 + 0x10 * ap->port_no);
45}
46
Jeff Garzik669a5db2006-08-29 18:12:40 -040047/**
48 * cs5530_set_piomode - PIO setup
49 * @ap: ATA interface
50 * @adev: device on the interface
51 *
52 * Set our PIO requirements. This is fairly simple on the CS5530
53 * chips.
54 */
55
56static void cs5530_set_piomode(struct ata_port *ap, struct ata_device *adev)
57{
58 static const unsigned int cs5530_pio_timings[2][5] = {
59 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
60 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
61 };
Tejun Heo0d5ff562007-02-01 15:06:36 +090062 void __iomem *base = cs5530_port_base(ap);
Jeff Garzik669a5db2006-08-29 18:12:40 -040063 u32 tuning;
64 int format;
65
66 /* Find out which table to use */
Tejun Heo0d5ff562007-02-01 15:06:36 +090067 tuning = ioread32(base + 0x04);
Jeff Garzik669a5db2006-08-29 18:12:40 -040068 format = (tuning & 0x80000000UL) ? 1 : 0;
69
70 /* Now load the right timing register */
71 if (adev->devno)
72 base += 0x08;
73
Tejun Heo0d5ff562007-02-01 15:06:36 +090074 iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base);
Jeff Garzik669a5db2006-08-29 18:12:40 -040075}
76
77/**
78 * cs5530_set_dmamode - DMA timing setup
79 * @ap: ATA interface
80 * @adev: Device being configured
81 *
82 * We cannot mix MWDMA and UDMA without reloading timings each switch
83 * master to slave. We track the last DMA setup in order to minimise
84 * reloads.
85 */
86
87static void cs5530_set_dmamode(struct ata_port *ap, struct ata_device *adev)
88{
Tejun Heo0d5ff562007-02-01 15:06:36 +090089 void __iomem *base = cs5530_port_base(ap);
Jeff Garzik669a5db2006-08-29 18:12:40 -040090 u32 tuning, timing = 0;
91 u8 reg;
92
93 /* Find out which table to use */
Tejun Heo0d5ff562007-02-01 15:06:36 +090094 tuning = ioread32(base + 0x04);
Jeff Garzik669a5db2006-08-29 18:12:40 -040095
96 switch(adev->dma_mode) {
97 case XFER_UDMA_0:
98 timing = 0x00921250;break;
99 case XFER_UDMA_1:
100 timing = 0x00911140;break;
101 case XFER_UDMA_2:
102 timing = 0x00911030;break;
103 case XFER_MW_DMA_0:
104 timing = 0x00077771;break;
105 case XFER_MW_DMA_1:
106 timing = 0x00012121;break;
107 case XFER_MW_DMA_2:
108 timing = 0x00002020;break;
109 default:
110 BUG();
111 }
112 /* Merge in the PIO format bit */
113 timing |= (tuning & 0x80000000UL);
114 if (adev->devno == 0) /* Master */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900115 iowrite32(timing, base + 0x04);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400116 else {
117 if (timing & 0x00100000)
118 tuning |= 0x00100000; /* UDMA for both */
119 else
120 tuning &= ~0x00100000; /* MWDMA for both */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900121 iowrite32(tuning, base + 0x04);
122 iowrite32(timing, base + 0x0C);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400123 }
124
125 /* Set the DMA capable bit in the BMDMA area */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900126 reg = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400127 reg |= (1 << (5 + adev->devno));
Tejun Heo0d5ff562007-02-01 15:06:36 +0900128 iowrite8(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400129
130 /* Remember the last DMA setup we did */
131
132 ap->private_data = adev;
133}
134
135/**
136 * cs5530_qc_issue_prot - command issue
137 * @qc: command pending
138 *
139 * Called when the libata layer is about to issue a command. We wrap
140 * this interface so that we can load the correct ATA timings if
141 * neccessary. Specifically we have a problem that there is only
142 * one MWDMA/UDMA bit.
143 */
144
145static unsigned int cs5530_qc_issue_prot(struct ata_queued_cmd *qc)
146{
147 struct ata_port *ap = qc->ap;
148 struct ata_device *adev = qc->dev;
149 struct ata_device *prev = ap->private_data;
150
151 /* See if the DMA settings could be wrong */
152 if (adev->dma_mode != 0 && adev != prev && prev != NULL) {
153 /* Maybe, but do the channels match MWDMA/UDMA ? */
154 if ((adev->dma_mode >= XFER_UDMA_0 && prev->dma_mode < XFER_UDMA_0) ||
155 (adev->dma_mode < XFER_UDMA_0 && prev->dma_mode >= XFER_UDMA_0))
156 /* Switch the mode bits */
157 cs5530_set_dmamode(ap, adev);
158 }
159
160 return ata_qc_issue_prot(qc);
161}
162
163static int cs5530_pre_reset(struct ata_port *ap)
164{
165 ap->cbl = ATA_CBL_PATA40;
166 return ata_std_prereset(ap);
167}
168
169static void cs5530_error_handler(struct ata_port *ap)
170{
171 return ata_bmdma_drive_eh(ap, cs5530_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
172}
173
174
175static struct scsi_host_template cs5530_sht = {
176 .module = THIS_MODULE,
177 .name = DRV_NAME,
178 .ioctl = ata_scsi_ioctl,
179 .queuecommand = ata_scsi_queuecmd,
180 .can_queue = ATA_DEF_QUEUE,
181 .this_id = ATA_SHT_THIS_ID,
182 .sg_tablesize = LIBATA_MAX_PRD,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400183 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
184 .emulated = ATA_SHT_EMULATED,
185 .use_clustering = ATA_SHT_USE_CLUSTERING,
186 .proc_name = DRV_NAME,
187 .dma_boundary = ATA_DMA_BOUNDARY,
188 .slave_configure = ata_scsi_slave_config,
Tejun Heoafdfe892006-11-29 11:26:47 +0900189 .slave_destroy = ata_scsi_slave_destroy,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400190 .bios_param = ata_std_bios_param,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900191#ifdef CONFIG_PM
Alanf7e37ba2006-11-22 17:21:03 +0000192 .resume = ata_scsi_device_resume,
193 .suspend = ata_scsi_device_suspend,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900194#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400195};
196
197static struct ata_port_operations cs5530_port_ops = {
198 .port_disable = ata_port_disable,
199 .set_piomode = cs5530_set_piomode,
200 .set_dmamode = cs5530_set_dmamode,
201 .mode_filter = ata_pci_default_filter,
202
203 .tf_load = ata_tf_load,
204 .tf_read = ata_tf_read,
205 .check_status = ata_check_status,
206 .exec_command = ata_exec_command,
207 .dev_select = ata_std_dev_select,
208
209 .bmdma_setup = ata_bmdma_setup,
210 .bmdma_start = ata_bmdma_start,
211 .bmdma_stop = ata_bmdma_stop,
212 .bmdma_status = ata_bmdma_status,
213
214 .freeze = ata_bmdma_freeze,
215 .thaw = ata_bmdma_thaw,
216 .error_handler = cs5530_error_handler,
217 .post_internal_cmd = ata_bmdma_post_internal_cmd,
218
219 .qc_prep = ata_qc_prep,
220 .qc_issue = cs5530_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400221
Tejun Heo0d5ff562007-02-01 15:06:36 +0900222 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400223
224 .irq_handler = ata_interrupt,
225 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900226 .irq_on = ata_irq_on,
227 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400228
229 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400230};
231
232static struct dmi_system_id palmax_dmi_table[] = {
233 {
234 .ident = "Palmax PD1100",
235 .matches = {
236 DMI_MATCH(DMI_SYS_VENDOR, "Cyrix"),
237 DMI_MATCH(DMI_PRODUCT_NAME, "Caddis"),
238 },
239 },
240 { }
241};
242
243static int cs5530_is_palmax(void)
244{
245 if (dmi_check_system(palmax_dmi_table)) {
246 printk(KERN_INFO "Palmax PD1100: Disabling DMA on docking port.\n");
247 return 1;
248 }
249 return 0;
250}
251
Alanf7e37ba2006-11-22 17:21:03 +0000252
Jeff Garzik669a5db2006-08-29 18:12:40 -0400253/**
Alanf7e37ba2006-11-22 17:21:03 +0000254 * cs5530_init_chip - Chipset init
Jeff Garzik669a5db2006-08-29 18:12:40 -0400255 *
Alanf7e37ba2006-11-22 17:21:03 +0000256 * Perform the chip initialisation work that is shared between both
257 * setup and resume paths
Jeff Garzik669a5db2006-08-29 18:12:40 -0400258 */
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500259
Alanf7e37ba2006-11-22 17:21:03 +0000260static int cs5530_init_chip(void)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400261{
Alanf7e37ba2006-11-22 17:21:03 +0000262 struct pci_dev *master_0 = NULL, *cs5530_0 = NULL, *dev = NULL;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400263
Jeff Garzik669a5db2006-08-29 18:12:40 -0400264 while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
265 switch (dev->device) {
266 case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
267 master_0 = pci_dev_get(dev);
268 break;
269 case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
270 cs5530_0 = pci_dev_get(dev);
271 break;
272 }
273 }
274 if (!master_0) {
275 printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
276 goto fail_put;
277 }
278 if (!cs5530_0) {
279 printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
280 goto fail_put;
281 }
282
283 pci_set_master(cs5530_0);
Alanf7e37ba2006-11-22 17:21:03 +0000284 pci_set_mwi(cs5530_0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400285
286 /*
287 * Set PCI CacheLineSize to 16-bytes:
288 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
289 *
290 * Note: This value is constant because the 5530 is only a Geode companion
291 */
292
293 pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
294
295 /*
296 * Disable trapping of UDMA register accesses (Win98 hack):
297 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
298 */
299
300 pci_write_config_word(cs5530_0, 0xd0, 0x5006);
301
302 /*
303 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
304 * The other settings are what is necessary to get the register
305 * into a sane state for IDE DMA operation.
306 */
307
308 pci_write_config_byte(master_0, 0x40, 0x1e);
309
310 /*
311 * Set max PCI burst size (16-bytes seems to work best):
312 * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
313 * all others: clear bit-1 at 0x41, and do:
314 * 128bytes: OR 0x00 at 0x41
315 * 256bytes: OR 0x04 at 0x41
316 * 512bytes: OR 0x08 at 0x41
317 * 1024bytes: OR 0x0c at 0x41
318 */
319
320 pci_write_config_byte(master_0, 0x41, 0x14);
321
322 /*
323 * These settings are necessary to get the chip
324 * into a sane state for IDE DMA operation.
325 */
326
327 pci_write_config_byte(master_0, 0x42, 0x00);
328 pci_write_config_byte(master_0, 0x43, 0xc1);
329
330 pci_dev_put(master_0);
331 pci_dev_put(cs5530_0);
Alanf7e37ba2006-11-22 17:21:03 +0000332 return 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400333fail_put:
334 if (master_0)
335 pci_dev_put(master_0);
336 if (cs5530_0)
337 pci_dev_put(cs5530_0);
338 return -ENODEV;
339}
340
Alanf7e37ba2006-11-22 17:21:03 +0000341/**
342 * cs5530_init_one - Initialise a CS5530
343 * @dev: PCI device
344 * @id: Entry in match table
345 *
346 * Install a driver for the newly found CS5530 companion chip. Most of
347 * this is just housekeeping. We have to set the chip up correctly and
348 * turn off various bits of emulation magic.
349 */
350
351static int cs5530_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
352{
353 static struct ata_port_info info = {
354 .sht = &cs5530_sht,
355 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
356 .pio_mask = 0x1f,
357 .mwdma_mask = 0x07,
358 .udma_mask = 0x07,
359 .port_ops = &cs5530_port_ops
360 };
361 /* The docking connector doesn't do UDMA, and it seems not MWDMA */
362 static struct ata_port_info info_palmax_secondary = {
363 .sht = &cs5530_sht,
364 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
365 .pio_mask = 0x1f,
366 .port_ops = &cs5530_port_ops
367 };
368 static struct ata_port_info *port_info[2] = { &info, &info };
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500369
Alanf7e37ba2006-11-22 17:21:03 +0000370 /* Chip initialisation */
371 if (cs5530_init_chip())
372 return -ENODEV;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500373
Alanf7e37ba2006-11-22 17:21:03 +0000374 if (cs5530_is_palmax())
375 port_info[1] = &info_palmax_secondary;
376
377 /* Now kick off ATA set up */
378 return ata_pci_init_one(pdev, port_info, 2);
379}
380
Tejun Heo438ac6d2007-03-02 17:31:26 +0900381#ifdef CONFIG_PM
Alanf7e37ba2006-11-22 17:21:03 +0000382static int cs5530_reinit_one(struct pci_dev *pdev)
383{
384 /* If we fail on resume we are doomed */
Andrew Morton01532602006-12-20 13:03:11 -0500385 if (cs5530_init_chip())
386 BUG();
Alanf7e37ba2006-11-22 17:21:03 +0000387 return ata_pci_device_resume(pdev);
388}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900389#endif /* CONFIG_PM */
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500390
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400391static const struct pci_device_id cs5530[] = {
392 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), },
393
394 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400395};
396
397static struct pci_driver cs5530_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400398 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400399 .id_table = cs5530,
400 .probe = cs5530_init_one,
Alanf7e37ba2006-11-22 17:21:03 +0000401 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900402#ifdef CONFIG_PM
Alanf7e37ba2006-11-22 17:21:03 +0000403 .suspend = ata_pci_device_suspend,
404 .resume = cs5530_reinit_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900405#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400406};
407
408static int __init cs5530_init(void)
409{
410 return pci_register_driver(&cs5530_pci_driver);
411}
412
Jeff Garzik669a5db2006-08-29 18:12:40 -0400413static void __exit cs5530_exit(void)
414{
415 pci_unregister_driver(&cs5530_pci_driver);
416}
417
Jeff Garzik669a5db2006-08-29 18:12:40 -0400418MODULE_AUTHOR("Alan Cox");
419MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530");
420MODULE_LICENSE("GPL");
421MODULE_DEVICE_TABLE(pci, cs5530);
422MODULE_VERSION(DRV_VERSION);
423
424module_init(cs5530_init);
425module_exit(cs5530_exit);