Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2007 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | */ |
| 26 | |
Jesse Barnes | c1c7af6 | 2009-09-10 15:28:03 -0700 | [diff] [blame] | 27 | #include <linux/module.h> |
| 28 | #include <linux/input.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 29 | #include <linux/i2c.h> |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 30 | #include <linux/kernel.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 31 | #include "drmP.h" |
| 32 | #include "intel_drv.h" |
| 33 | #include "i915_drm.h" |
| 34 | #include "i915_drv.h" |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 35 | #include "intel_dp.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | |
| 37 | #include "drm_crtc_helper.h" |
| 38 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 39 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
| 40 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 41 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 42 | static void intel_update_watermarks(struct drm_device *dev); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 43 | static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 44 | |
| 45 | typedef struct { |
| 46 | /* given values */ |
| 47 | int n; |
| 48 | int m1, m2; |
| 49 | int p1, p2; |
| 50 | /* derived values */ |
| 51 | int dot; |
| 52 | int vco; |
| 53 | int m; |
| 54 | int p; |
| 55 | } intel_clock_t; |
| 56 | |
| 57 | typedef struct { |
| 58 | int min, max; |
| 59 | } intel_range_t; |
| 60 | |
| 61 | typedef struct { |
| 62 | int dot_limit; |
| 63 | int p2_slow, p2_fast; |
| 64 | } intel_p2_t; |
| 65 | |
| 66 | #define INTEL_P2_NUM 2 |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 67 | typedef struct intel_limit intel_limit_t; |
| 68 | struct intel_limit { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 69 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
| 70 | intel_p2_t p2; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 71 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
| 72 | int, int, intel_clock_t *); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 73 | bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *, |
| 74 | int, int, intel_clock_t *); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 75 | }; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 76 | |
| 77 | #define I8XX_DOT_MIN 25000 |
| 78 | #define I8XX_DOT_MAX 350000 |
| 79 | #define I8XX_VCO_MIN 930000 |
| 80 | #define I8XX_VCO_MAX 1400000 |
| 81 | #define I8XX_N_MIN 3 |
| 82 | #define I8XX_N_MAX 16 |
| 83 | #define I8XX_M_MIN 96 |
| 84 | #define I8XX_M_MAX 140 |
| 85 | #define I8XX_M1_MIN 18 |
| 86 | #define I8XX_M1_MAX 26 |
| 87 | #define I8XX_M2_MIN 6 |
| 88 | #define I8XX_M2_MAX 16 |
| 89 | #define I8XX_P_MIN 4 |
| 90 | #define I8XX_P_MAX 128 |
| 91 | #define I8XX_P1_MIN 2 |
| 92 | #define I8XX_P1_MAX 33 |
| 93 | #define I8XX_P1_LVDS_MIN 1 |
| 94 | #define I8XX_P1_LVDS_MAX 6 |
| 95 | #define I8XX_P2_SLOW 4 |
| 96 | #define I8XX_P2_FAST 2 |
| 97 | #define I8XX_P2_LVDS_SLOW 14 |
ling.ma@intel.com | 0c2e395 | 2009-07-17 11:44:30 +0800 | [diff] [blame] | 98 | #define I8XX_P2_LVDS_FAST 7 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 99 | #define I8XX_P2_SLOW_LIMIT 165000 |
| 100 | |
| 101 | #define I9XX_DOT_MIN 20000 |
| 102 | #define I9XX_DOT_MAX 400000 |
| 103 | #define I9XX_VCO_MIN 1400000 |
| 104 | #define I9XX_VCO_MAX 2800000 |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 105 | #define IGD_VCO_MIN 1700000 |
| 106 | #define IGD_VCO_MAX 3500000 |
Kristian Høgsberg | f3cade5 | 2009-02-13 20:56:50 -0500 | [diff] [blame] | 107 | #define I9XX_N_MIN 1 |
| 108 | #define I9XX_N_MAX 6 |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 109 | /* IGD's Ncounter is a ring counter */ |
| 110 | #define IGD_N_MIN 3 |
| 111 | #define IGD_N_MAX 6 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 112 | #define I9XX_M_MIN 70 |
| 113 | #define I9XX_M_MAX 120 |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 114 | #define IGD_M_MIN 2 |
| 115 | #define IGD_M_MAX 256 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 116 | #define I9XX_M1_MIN 10 |
Kristian Høgsberg | f3cade5 | 2009-02-13 20:56:50 -0500 | [diff] [blame] | 117 | #define I9XX_M1_MAX 22 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 118 | #define I9XX_M2_MIN 5 |
| 119 | #define I9XX_M2_MAX 9 |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 120 | /* IGD M1 is reserved, and must be 0 */ |
| 121 | #define IGD_M1_MIN 0 |
| 122 | #define IGD_M1_MAX 0 |
| 123 | #define IGD_M2_MIN 0 |
| 124 | #define IGD_M2_MAX 254 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 125 | #define I9XX_P_SDVO_DAC_MIN 5 |
| 126 | #define I9XX_P_SDVO_DAC_MAX 80 |
| 127 | #define I9XX_P_LVDS_MIN 7 |
| 128 | #define I9XX_P_LVDS_MAX 98 |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 129 | #define IGD_P_LVDS_MIN 7 |
| 130 | #define IGD_P_LVDS_MAX 112 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 131 | #define I9XX_P1_MIN 1 |
| 132 | #define I9XX_P1_MAX 8 |
| 133 | #define I9XX_P2_SDVO_DAC_SLOW 10 |
| 134 | #define I9XX_P2_SDVO_DAC_FAST 5 |
| 135 | #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 |
| 136 | #define I9XX_P2_LVDS_SLOW 14 |
| 137 | #define I9XX_P2_LVDS_FAST 7 |
| 138 | #define I9XX_P2_LVDS_SLOW_LIMIT 112000 |
| 139 | |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 140 | /*The parameter is for SDVO on G4x platform*/ |
| 141 | #define G4X_DOT_SDVO_MIN 25000 |
| 142 | #define G4X_DOT_SDVO_MAX 270000 |
| 143 | #define G4X_VCO_MIN 1750000 |
| 144 | #define G4X_VCO_MAX 3500000 |
| 145 | #define G4X_N_SDVO_MIN 1 |
| 146 | #define G4X_N_SDVO_MAX 4 |
| 147 | #define G4X_M_SDVO_MIN 104 |
| 148 | #define G4X_M_SDVO_MAX 138 |
| 149 | #define G4X_M1_SDVO_MIN 17 |
| 150 | #define G4X_M1_SDVO_MAX 23 |
| 151 | #define G4X_M2_SDVO_MIN 5 |
| 152 | #define G4X_M2_SDVO_MAX 11 |
| 153 | #define G4X_P_SDVO_MIN 10 |
| 154 | #define G4X_P_SDVO_MAX 30 |
| 155 | #define G4X_P1_SDVO_MIN 1 |
| 156 | #define G4X_P1_SDVO_MAX 3 |
| 157 | #define G4X_P2_SDVO_SLOW 10 |
| 158 | #define G4X_P2_SDVO_FAST 10 |
| 159 | #define G4X_P2_SDVO_LIMIT 270000 |
| 160 | |
| 161 | /*The parameter is for HDMI_DAC on G4x platform*/ |
| 162 | #define G4X_DOT_HDMI_DAC_MIN 22000 |
| 163 | #define G4X_DOT_HDMI_DAC_MAX 400000 |
| 164 | #define G4X_N_HDMI_DAC_MIN 1 |
| 165 | #define G4X_N_HDMI_DAC_MAX 4 |
| 166 | #define G4X_M_HDMI_DAC_MIN 104 |
| 167 | #define G4X_M_HDMI_DAC_MAX 138 |
| 168 | #define G4X_M1_HDMI_DAC_MIN 16 |
| 169 | #define G4X_M1_HDMI_DAC_MAX 23 |
| 170 | #define G4X_M2_HDMI_DAC_MIN 5 |
| 171 | #define G4X_M2_HDMI_DAC_MAX 11 |
| 172 | #define G4X_P_HDMI_DAC_MIN 5 |
| 173 | #define G4X_P_HDMI_DAC_MAX 80 |
| 174 | #define G4X_P1_HDMI_DAC_MIN 1 |
| 175 | #define G4X_P1_HDMI_DAC_MAX 8 |
| 176 | #define G4X_P2_HDMI_DAC_SLOW 10 |
| 177 | #define G4X_P2_HDMI_DAC_FAST 5 |
| 178 | #define G4X_P2_HDMI_DAC_LIMIT 165000 |
| 179 | |
| 180 | /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/ |
| 181 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000 |
| 182 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000 |
| 183 | #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1 |
| 184 | #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3 |
| 185 | #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104 |
| 186 | #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138 |
| 187 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17 |
| 188 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23 |
| 189 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5 |
| 190 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11 |
| 191 | #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28 |
| 192 | #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112 |
| 193 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2 |
| 194 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8 |
| 195 | #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14 |
| 196 | #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14 |
| 197 | #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0 |
| 198 | |
| 199 | /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/ |
| 200 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000 |
| 201 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000 |
| 202 | #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1 |
| 203 | #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3 |
| 204 | #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104 |
| 205 | #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138 |
| 206 | #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17 |
| 207 | #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23 |
| 208 | #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5 |
| 209 | #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11 |
| 210 | #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14 |
| 211 | #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42 |
| 212 | #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2 |
| 213 | #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6 |
| 214 | #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7 |
| 215 | #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7 |
| 216 | #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0 |
| 217 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 218 | /*The parameter is for DISPLAY PORT on G4x platform*/ |
| 219 | #define G4X_DOT_DISPLAY_PORT_MIN 161670 |
| 220 | #define G4X_DOT_DISPLAY_PORT_MAX 227000 |
| 221 | #define G4X_N_DISPLAY_PORT_MIN 1 |
| 222 | #define G4X_N_DISPLAY_PORT_MAX 2 |
| 223 | #define G4X_M_DISPLAY_PORT_MIN 97 |
| 224 | #define G4X_M_DISPLAY_PORT_MAX 108 |
| 225 | #define G4X_M1_DISPLAY_PORT_MIN 0x10 |
| 226 | #define G4X_M1_DISPLAY_PORT_MAX 0x12 |
| 227 | #define G4X_M2_DISPLAY_PORT_MIN 0x05 |
| 228 | #define G4X_M2_DISPLAY_PORT_MAX 0x06 |
| 229 | #define G4X_P_DISPLAY_PORT_MIN 10 |
| 230 | #define G4X_P_DISPLAY_PORT_MAX 20 |
| 231 | #define G4X_P1_DISPLAY_PORT_MIN 1 |
| 232 | #define G4X_P1_DISPLAY_PORT_MAX 2 |
| 233 | #define G4X_P2_DISPLAY_PORT_SLOW 10 |
| 234 | #define G4X_P2_DISPLAY_PORT_FAST 10 |
| 235 | #define G4X_P2_DISPLAY_PORT_LIMIT 0 |
| 236 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 237 | /* IGDNG */ |
| 238 | /* as we calculate clock using (register_value + 2) for |
| 239 | N/M1/M2, so here the range value for them is (actual_value-2). |
| 240 | */ |
| 241 | #define IGDNG_DOT_MIN 25000 |
| 242 | #define IGDNG_DOT_MAX 350000 |
| 243 | #define IGDNG_VCO_MIN 1760000 |
| 244 | #define IGDNG_VCO_MAX 3510000 |
| 245 | #define IGDNG_N_MIN 1 |
| 246 | #define IGDNG_N_MAX 5 |
| 247 | #define IGDNG_M_MIN 79 |
| 248 | #define IGDNG_M_MAX 118 |
| 249 | #define IGDNG_M1_MIN 12 |
| 250 | #define IGDNG_M1_MAX 23 |
| 251 | #define IGDNG_M2_MIN 5 |
| 252 | #define IGDNG_M2_MAX 9 |
| 253 | #define IGDNG_P_SDVO_DAC_MIN 5 |
| 254 | #define IGDNG_P_SDVO_DAC_MAX 80 |
| 255 | #define IGDNG_P_LVDS_MIN 28 |
| 256 | #define IGDNG_P_LVDS_MAX 112 |
| 257 | #define IGDNG_P1_MIN 1 |
| 258 | #define IGDNG_P1_MAX 8 |
| 259 | #define IGDNG_P2_SDVO_DAC_SLOW 10 |
| 260 | #define IGDNG_P2_SDVO_DAC_FAST 5 |
| 261 | #define IGDNG_P2_LVDS_SLOW 14 /* single channel */ |
| 262 | #define IGDNG_P2_LVDS_FAST 7 /* double channel */ |
| 263 | #define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */ |
| 264 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 265 | static bool |
| 266 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 267 | int target, int refclk, intel_clock_t *best_clock); |
| 268 | static bool |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 269 | intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 270 | int target, int refclk, intel_clock_t *best_clock); |
| 271 | static bool |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 272 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 273 | int target, int refclk, intel_clock_t *best_clock); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 274 | static bool |
| 275 | intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 276 | int target, int refclk, intel_clock_t *best_clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 277 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 278 | static bool |
| 279 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, |
| 280 | int target, int refclk, intel_clock_t *best_clock); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 281 | static bool |
| 282 | intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc, |
| 283 | int target, int refclk, intel_clock_t *best_clock); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 284 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 285 | static const intel_limit_t intel_limits_i8xx_dvo = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 286 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
| 287 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, |
| 288 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, |
| 289 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, |
| 290 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, |
| 291 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, |
| 292 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, |
| 293 | .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, |
| 294 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, |
| 295 | .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 296 | .find_pll = intel_find_best_PLL, |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 297 | .find_reduced_pll = intel_find_best_reduced_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 298 | }; |
| 299 | |
| 300 | static const intel_limit_t intel_limits_i8xx_lvds = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 301 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
| 302 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, |
| 303 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, |
| 304 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, |
| 305 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, |
| 306 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, |
| 307 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, |
| 308 | .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, |
| 309 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, |
| 310 | .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 311 | .find_pll = intel_find_best_PLL, |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 312 | .find_reduced_pll = intel_find_best_reduced_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 313 | }; |
| 314 | |
| 315 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 316 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
| 317 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, |
| 318 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, |
| 319 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, |
| 320 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, |
| 321 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, |
| 322 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, |
| 323 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
| 324 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, |
| 325 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 326 | .find_pll = intel_find_best_PLL, |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 327 | .find_reduced_pll = intel_find_best_reduced_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 328 | }; |
| 329 | |
| 330 | static const intel_limit_t intel_limits_i9xx_lvds = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 331 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
| 332 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, |
| 333 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, |
| 334 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, |
| 335 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, |
| 336 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, |
| 337 | .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX }, |
| 338 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
| 339 | /* The single-channel range is 25-112Mhz, and dual-channel |
| 340 | * is 80-224Mhz. Prefer single channel as much as possible. |
| 341 | */ |
| 342 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, |
| 343 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 344 | .find_pll = intel_find_best_PLL, |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 345 | .find_reduced_pll = intel_find_best_reduced_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 346 | }; |
| 347 | |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 348 | /* below parameter and function is for G4X Chipset Family*/ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 349 | static const intel_limit_t intel_limits_g4x_sdvo = { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 350 | .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX }, |
| 351 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, |
| 352 | .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX }, |
| 353 | .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX }, |
| 354 | .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX }, |
| 355 | .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX }, |
| 356 | .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX }, |
| 357 | .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX}, |
| 358 | .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT, |
| 359 | .p2_slow = G4X_P2_SDVO_SLOW, |
| 360 | .p2_fast = G4X_P2_SDVO_FAST |
| 361 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 362 | .find_pll = intel_g4x_find_best_PLL, |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 363 | .find_reduced_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 364 | }; |
| 365 | |
| 366 | static const intel_limit_t intel_limits_g4x_hdmi = { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 367 | .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX }, |
| 368 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, |
| 369 | .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX }, |
| 370 | .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX }, |
| 371 | .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX }, |
| 372 | .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX }, |
| 373 | .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX }, |
| 374 | .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX}, |
| 375 | .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT, |
| 376 | .p2_slow = G4X_P2_HDMI_DAC_SLOW, |
| 377 | .p2_fast = G4X_P2_HDMI_DAC_FAST |
| 378 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 379 | .find_pll = intel_g4x_find_best_PLL, |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 380 | .find_reduced_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 381 | }; |
| 382 | |
| 383 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 384 | .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN, |
| 385 | .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX }, |
| 386 | .vco = { .min = G4X_VCO_MIN, |
| 387 | .max = G4X_VCO_MAX }, |
| 388 | .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN, |
| 389 | .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX }, |
| 390 | .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN, |
| 391 | .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX }, |
| 392 | .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN, |
| 393 | .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX }, |
| 394 | .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN, |
| 395 | .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX }, |
| 396 | .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN, |
| 397 | .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX }, |
| 398 | .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN, |
| 399 | .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX }, |
| 400 | .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT, |
| 401 | .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW, |
| 402 | .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST |
| 403 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 404 | .find_pll = intel_g4x_find_best_PLL, |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 405 | .find_reduced_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 406 | }; |
| 407 | |
| 408 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 409 | .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN, |
| 410 | .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX }, |
| 411 | .vco = { .min = G4X_VCO_MIN, |
| 412 | .max = G4X_VCO_MAX }, |
| 413 | .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN, |
| 414 | .max = G4X_N_DUAL_CHANNEL_LVDS_MAX }, |
| 415 | .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN, |
| 416 | .max = G4X_M_DUAL_CHANNEL_LVDS_MAX }, |
| 417 | .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN, |
| 418 | .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX }, |
| 419 | .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN, |
| 420 | .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX }, |
| 421 | .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN, |
| 422 | .max = G4X_P_DUAL_CHANNEL_LVDS_MAX }, |
| 423 | .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN, |
| 424 | .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX }, |
| 425 | .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT, |
| 426 | .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW, |
| 427 | .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST |
| 428 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 429 | .find_pll = intel_g4x_find_best_PLL, |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 430 | .find_reduced_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 431 | }; |
| 432 | |
| 433 | static const intel_limit_t intel_limits_g4x_display_port = { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 434 | .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN, |
| 435 | .max = G4X_DOT_DISPLAY_PORT_MAX }, |
| 436 | .vco = { .min = G4X_VCO_MIN, |
| 437 | .max = G4X_VCO_MAX}, |
| 438 | .n = { .min = G4X_N_DISPLAY_PORT_MIN, |
| 439 | .max = G4X_N_DISPLAY_PORT_MAX }, |
| 440 | .m = { .min = G4X_M_DISPLAY_PORT_MIN, |
| 441 | .max = G4X_M_DISPLAY_PORT_MAX }, |
| 442 | .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN, |
| 443 | .max = G4X_M1_DISPLAY_PORT_MAX }, |
| 444 | .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN, |
| 445 | .max = G4X_M2_DISPLAY_PORT_MAX }, |
| 446 | .p = { .min = G4X_P_DISPLAY_PORT_MIN, |
| 447 | .max = G4X_P_DISPLAY_PORT_MAX }, |
| 448 | .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN, |
| 449 | .max = G4X_P1_DISPLAY_PORT_MAX}, |
| 450 | .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT, |
| 451 | .p2_slow = G4X_P2_DISPLAY_PORT_SLOW, |
| 452 | .p2_fast = G4X_P2_DISPLAY_PORT_FAST }, |
| 453 | .find_pll = intel_find_pll_g4x_dp, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 454 | }; |
| 455 | |
| 456 | static const intel_limit_t intel_limits_igd_sdvo = { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 457 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, |
| 458 | .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, |
| 459 | .n = { .min = IGD_N_MIN, .max = IGD_N_MAX }, |
| 460 | .m = { .min = IGD_M_MIN, .max = IGD_M_MAX }, |
| 461 | .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX }, |
| 462 | .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX }, |
| 463 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, |
| 464 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
| 465 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, |
| 466 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, |
Shaohua Li | 6115707 | 2009-04-03 15:24:43 +0800 | [diff] [blame] | 467 | .find_pll = intel_find_best_PLL, |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 468 | .find_reduced_pll = intel_find_best_reduced_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 469 | }; |
| 470 | |
| 471 | static const intel_limit_t intel_limits_igd_lvds = { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 472 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
| 473 | .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, |
| 474 | .n = { .min = IGD_N_MIN, .max = IGD_N_MAX }, |
| 475 | .m = { .min = IGD_M_MIN, .max = IGD_M_MAX }, |
| 476 | .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX }, |
| 477 | .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX }, |
| 478 | .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX }, |
| 479 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
| 480 | /* IGD only supports single-channel mode. */ |
| 481 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, |
| 482 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, |
Shaohua Li | 6115707 | 2009-04-03 15:24:43 +0800 | [diff] [blame] | 483 | .find_pll = intel_find_best_PLL, |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 484 | .find_reduced_pll = intel_find_best_reduced_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 485 | }; |
| 486 | |
| 487 | static const intel_limit_t intel_limits_igdng_sdvo = { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 488 | .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX }, |
| 489 | .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX }, |
| 490 | .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX }, |
| 491 | .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX }, |
| 492 | .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX }, |
| 493 | .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX }, |
| 494 | .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX }, |
| 495 | .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX }, |
| 496 | .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT, |
| 497 | .p2_slow = IGDNG_P2_SDVO_DAC_SLOW, |
| 498 | .p2_fast = IGDNG_P2_SDVO_DAC_FAST }, |
| 499 | .find_pll = intel_igdng_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 500 | }; |
| 501 | |
| 502 | static const intel_limit_t intel_limits_igdng_lvds = { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 503 | .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX }, |
| 504 | .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX }, |
| 505 | .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX }, |
| 506 | .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX }, |
| 507 | .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX }, |
| 508 | .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX }, |
| 509 | .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX }, |
| 510 | .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX }, |
| 511 | .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT, |
| 512 | .p2_slow = IGDNG_P2_LVDS_SLOW, |
| 513 | .p2_fast = IGDNG_P2_LVDS_FAST }, |
| 514 | .find_pll = intel_igdng_find_best_PLL, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 515 | }; |
| 516 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 517 | static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc) |
| 518 | { |
| 519 | const intel_limit_t *limit; |
| 520 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 521 | limit = &intel_limits_igdng_lvds; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 522 | else |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 523 | limit = &intel_limits_igdng_sdvo; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 524 | |
| 525 | return limit; |
| 526 | } |
| 527 | |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 528 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
| 529 | { |
| 530 | struct drm_device *dev = crtc->dev; |
| 531 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 532 | const intel_limit_t *limit; |
| 533 | |
| 534 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 535 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == |
| 536 | LVDS_CLKB_POWER_UP) |
| 537 | /* LVDS with dual channel */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 538 | limit = &intel_limits_g4x_dual_channel_lvds; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 539 | else |
| 540 | /* LVDS with dual channel */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 541 | limit = &intel_limits_g4x_single_channel_lvds; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 542 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
| 543 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 544 | limit = &intel_limits_g4x_hdmi; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 545 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 546 | limit = &intel_limits_g4x_sdvo; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 547 | } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 548 | limit = &intel_limits_g4x_display_port; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 549 | } else /* The option is for other outputs */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 550 | limit = &intel_limits_i9xx_sdvo; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 551 | |
| 552 | return limit; |
| 553 | } |
| 554 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 555 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc) |
| 556 | { |
| 557 | struct drm_device *dev = crtc->dev; |
| 558 | const intel_limit_t *limit; |
| 559 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 560 | if (IS_IGDNG(dev)) |
| 561 | limit = intel_igdng_limit(crtc); |
| 562 | else if (IS_G4X(dev)) { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 563 | limit = intel_g4x_limit(crtc); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 564 | } else if (IS_I9XX(dev) && !IS_IGD(dev)) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 565 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 566 | limit = &intel_limits_i9xx_lvds; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 567 | else |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 568 | limit = &intel_limits_i9xx_sdvo; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 569 | } else if (IS_IGD(dev)) { |
| 570 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 571 | limit = &intel_limits_igd_lvds; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 572 | else |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 573 | limit = &intel_limits_igd_sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 574 | } else { |
| 575 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 576 | limit = &intel_limits_i8xx_lvds; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 577 | else |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 578 | limit = &intel_limits_i8xx_dvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 579 | } |
| 580 | return limit; |
| 581 | } |
| 582 | |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 583 | /* m1 is reserved as 0 in IGD, n is a ring counter */ |
| 584 | static void igd_clock(int refclk, intel_clock_t *clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 585 | { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 586 | clock->m = clock->m2 + 2; |
| 587 | clock->p = clock->p1 * clock->p2; |
| 588 | clock->vco = refclk * clock->m / clock->n; |
| 589 | clock->dot = clock->vco / clock->p; |
| 590 | } |
| 591 | |
| 592 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) |
| 593 | { |
| 594 | if (IS_IGD(dev)) { |
| 595 | igd_clock(refclk, clock); |
| 596 | return; |
| 597 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 598 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
| 599 | clock->p = clock->p1 * clock->p2; |
| 600 | clock->vco = refclk * clock->m / (clock->n + 2); |
| 601 | clock->dot = clock->vco / clock->p; |
| 602 | } |
| 603 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 604 | /** |
| 605 | * Returns whether any output on the specified pipe is of the specified type |
| 606 | */ |
| 607 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type) |
| 608 | { |
| 609 | struct drm_device *dev = crtc->dev; |
| 610 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 611 | struct drm_connector *l_entry; |
| 612 | |
| 613 | list_for_each_entry(l_entry, &mode_config->connector_list, head) { |
| 614 | if (l_entry->encoder && |
| 615 | l_entry->encoder->crtc == crtc) { |
| 616 | struct intel_output *intel_output = to_intel_output(l_entry); |
| 617 | if (intel_output->type == type) |
| 618 | return true; |
| 619 | } |
| 620 | } |
| 621 | return false; |
| 622 | } |
| 623 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 624 | struct drm_connector * |
| 625 | intel_pipe_get_output (struct drm_crtc *crtc) |
| 626 | { |
| 627 | struct drm_device *dev = crtc->dev; |
| 628 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 629 | struct drm_connector *l_entry, *ret = NULL; |
| 630 | |
| 631 | list_for_each_entry(l_entry, &mode_config->connector_list, head) { |
| 632 | if (l_entry->encoder && |
| 633 | l_entry->encoder->crtc == crtc) { |
| 634 | ret = l_entry; |
| 635 | break; |
| 636 | } |
| 637 | } |
| 638 | return ret; |
| 639 | } |
| 640 | |
Jesse Barnes | 7c04d1d | 2009-02-23 15:36:40 -0800 | [diff] [blame] | 641 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 642 | /** |
| 643 | * Returns whether the given set of divisors are valid for a given refclk with |
| 644 | * the given connectors. |
| 645 | */ |
| 646 | |
| 647 | static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock) |
| 648 | { |
| 649 | const intel_limit_t *limit = intel_limit (crtc); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 650 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 651 | |
| 652 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
| 653 | INTELPllInvalid ("p1 out of range\n"); |
| 654 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
| 655 | INTELPllInvalid ("p out of range\n"); |
| 656 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
| 657 | INTELPllInvalid ("m2 out of range\n"); |
| 658 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
| 659 | INTELPllInvalid ("m1 out of range\n"); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 660 | if (clock->m1 <= clock->m2 && !IS_IGD(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 661 | INTELPllInvalid ("m1 <= m2\n"); |
| 662 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
| 663 | INTELPllInvalid ("m out of range\n"); |
| 664 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
| 665 | INTELPllInvalid ("n out of range\n"); |
| 666 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
| 667 | INTELPllInvalid ("vco out of range\n"); |
| 668 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
| 669 | * connector, etc., rather than just a single range. |
| 670 | */ |
| 671 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
| 672 | INTELPllInvalid ("dot out of range\n"); |
| 673 | |
| 674 | return true; |
| 675 | } |
| 676 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 677 | static bool |
| 678 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 679 | int target, int refclk, intel_clock_t *best_clock) |
| 680 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 681 | { |
| 682 | struct drm_device *dev = crtc->dev; |
| 683 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 684 | intel_clock_t clock; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 685 | int err = target; |
| 686 | |
Bruno Prémont | bc5e571 | 2009-08-08 13:01:17 +0200 | [diff] [blame] | 687 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
Florian Mickler | 832cc28 | 2009-07-13 18:40:32 +0800 | [diff] [blame] | 688 | (I915_READ(LVDS)) != 0) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 689 | /* |
| 690 | * For LVDS, if the panel is on, just rely on its current |
| 691 | * settings for dual-channel. We haven't figured out how to |
| 692 | * reliably set up different single/dual channel state, if we |
| 693 | * even can. |
| 694 | */ |
| 695 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == |
| 696 | LVDS_CLKB_POWER_UP) |
| 697 | clock.p2 = limit->p2.p2_fast; |
| 698 | else |
| 699 | clock.p2 = limit->p2.p2_slow; |
| 700 | } else { |
| 701 | if (target < limit->p2.dot_limit) |
| 702 | clock.p2 = limit->p2.p2_slow; |
| 703 | else |
| 704 | clock.p2 = limit->p2.p2_fast; |
| 705 | } |
| 706 | |
| 707 | memset (best_clock, 0, sizeof (*best_clock)); |
| 708 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 709 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
| 710 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 711 | clock.m1++) { |
| 712 | for (clock.m2 = limit->m2.min; |
| 713 | clock.m2 <= limit->m2.max; clock.m2++) { |
| 714 | /* m1 is always 0 in IGD */ |
| 715 | if (clock.m2 >= clock.m1 && !IS_IGD(dev)) |
| 716 | break; |
| 717 | for (clock.n = limit->n.min; |
| 718 | clock.n <= limit->n.max; clock.n++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 719 | int this_err; |
| 720 | |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 721 | intel_clock(dev, refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 722 | |
| 723 | if (!intel_PLL_is_valid(crtc, &clock)) |
| 724 | continue; |
| 725 | |
| 726 | this_err = abs(clock.dot - target); |
| 727 | if (this_err < err) { |
| 728 | *best_clock = clock; |
| 729 | err = this_err; |
| 730 | } |
| 731 | } |
| 732 | } |
| 733 | } |
| 734 | } |
| 735 | |
| 736 | return (err != target); |
| 737 | } |
| 738 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 739 | |
| 740 | static bool |
| 741 | intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 742 | int target, int refclk, intel_clock_t *best_clock) |
| 743 | |
| 744 | { |
| 745 | struct drm_device *dev = crtc->dev; |
| 746 | intel_clock_t clock; |
| 747 | int err = target; |
| 748 | bool found = false; |
| 749 | |
| 750 | memcpy(&clock, best_clock, sizeof(intel_clock_t)); |
| 751 | |
| 752 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
| 753 | for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) { |
| 754 | /* m1 is always 0 in IGD */ |
| 755 | if (clock.m2 >= clock.m1 && !IS_IGD(dev)) |
| 756 | break; |
| 757 | for (clock.n = limit->n.min; clock.n <= limit->n.max; |
| 758 | clock.n++) { |
| 759 | int this_err; |
| 760 | |
| 761 | intel_clock(dev, refclk, &clock); |
| 762 | |
| 763 | if (!intel_PLL_is_valid(crtc, &clock)) |
| 764 | continue; |
| 765 | |
| 766 | this_err = abs(clock.dot - target); |
| 767 | if (this_err < err) { |
| 768 | *best_clock = clock; |
| 769 | err = this_err; |
| 770 | found = true; |
| 771 | } |
| 772 | } |
| 773 | } |
| 774 | } |
| 775 | |
| 776 | return found; |
| 777 | } |
| 778 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 779 | static bool |
| 780 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 781 | int target, int refclk, intel_clock_t *best_clock) |
| 782 | { |
| 783 | struct drm_device *dev = crtc->dev; |
| 784 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 785 | intel_clock_t clock; |
| 786 | int max_n; |
| 787 | bool found; |
| 788 | /* approximately equals target * 0.00488 */ |
| 789 | int err_most = (target >> 8) + (target >> 10); |
| 790 | found = false; |
| 791 | |
| 792 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 793 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == |
| 794 | LVDS_CLKB_POWER_UP) |
| 795 | clock.p2 = limit->p2.p2_fast; |
| 796 | else |
| 797 | clock.p2 = limit->p2.p2_slow; |
| 798 | } else { |
| 799 | if (target < limit->p2.dot_limit) |
| 800 | clock.p2 = limit->p2.p2_slow; |
| 801 | else |
| 802 | clock.p2 = limit->p2.p2_fast; |
| 803 | } |
| 804 | |
| 805 | memset(best_clock, 0, sizeof(*best_clock)); |
| 806 | max_n = limit->n.max; |
| 807 | /* based on hardware requriment prefer smaller n to precision */ |
| 808 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 809 | /* based on hardware requirment prefere larger m1,m2 */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 810 | for (clock.m1 = limit->m1.max; |
| 811 | clock.m1 >= limit->m1.min; clock.m1--) { |
| 812 | for (clock.m2 = limit->m2.max; |
| 813 | clock.m2 >= limit->m2.min; clock.m2--) { |
| 814 | for (clock.p1 = limit->p1.max; |
| 815 | clock.p1 >= limit->p1.min; clock.p1--) { |
| 816 | int this_err; |
| 817 | |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 818 | intel_clock(dev, refclk, &clock); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 819 | if (!intel_PLL_is_valid(crtc, &clock)) |
| 820 | continue; |
| 821 | this_err = abs(clock.dot - target) ; |
| 822 | if (this_err < err_most) { |
| 823 | *best_clock = clock; |
| 824 | err_most = this_err; |
| 825 | max_n = clock.n; |
| 826 | found = true; |
| 827 | } |
| 828 | } |
| 829 | } |
| 830 | } |
| 831 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 832 | return found; |
| 833 | } |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 834 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 835 | static bool |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 836 | intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 837 | int target, int refclk, intel_clock_t *best_clock) |
| 838 | { |
| 839 | struct drm_device *dev = crtc->dev; |
| 840 | intel_clock_t clock; |
| 841 | if (target < 200000) { |
| 842 | clock.n = 1; |
| 843 | clock.p1 = 2; |
| 844 | clock.p2 = 10; |
| 845 | clock.m1 = 12; |
| 846 | clock.m2 = 9; |
| 847 | } else { |
| 848 | clock.n = 2; |
| 849 | clock.p1 = 1; |
| 850 | clock.p2 = 10; |
| 851 | clock.m1 = 14; |
| 852 | clock.m2 = 8; |
| 853 | } |
| 854 | intel_clock(dev, refclk, &clock); |
| 855 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
| 856 | return true; |
| 857 | } |
| 858 | |
| 859 | static bool |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 860 | intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 861 | int target, int refclk, intel_clock_t *best_clock) |
| 862 | { |
| 863 | struct drm_device *dev = crtc->dev; |
| 864 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 865 | intel_clock_t clock; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 866 | int err_most = 47; |
Zhenyu Wang | 4bfe6b6 | 2009-11-02 07:52:29 +0000 | [diff] [blame] | 867 | int err_min = 10000; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 868 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 869 | /* eDP has only 2 clock choice, no n/m/p setting */ |
| 870 | if (HAS_eDP) |
| 871 | return true; |
| 872 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 873 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) |
| 874 | return intel_find_pll_igdng_dp(limit, crtc, target, |
| 875 | refclk, best_clock); |
| 876 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 877 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
Zhenyu Wang | b09aea7 | 2009-09-19 14:54:06 +0800 | [diff] [blame] | 878 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 879 | LVDS_CLKB_POWER_UP) |
| 880 | clock.p2 = limit->p2.p2_fast; |
| 881 | else |
| 882 | clock.p2 = limit->p2.p2_slow; |
| 883 | } else { |
| 884 | if (target < limit->p2.dot_limit) |
| 885 | clock.p2 = limit->p2.p2_slow; |
| 886 | else |
| 887 | clock.p2 = limit->p2.p2_fast; |
| 888 | } |
| 889 | |
| 890 | memset(best_clock, 0, sizeof(*best_clock)); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 891 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
| 892 | /* based on hardware requriment prefer smaller n to precision */ |
Zhenyu Wang | 4bfe6b6 | 2009-11-02 07:52:29 +0000 | [diff] [blame] | 893 | for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 894 | /* based on hardware requirment prefere larger m1,m2 */ |
| 895 | for (clock.m1 = limit->m1.max; |
| 896 | clock.m1 >= limit->m1.min; clock.m1--) { |
| 897 | for (clock.m2 = limit->m2.max; |
| 898 | clock.m2 >= limit->m2.min; clock.m2--) { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 899 | int this_err; |
| 900 | |
| 901 | intel_clock(dev, refclk, &clock); |
| 902 | if (!intel_PLL_is_valid(crtc, &clock)) |
| 903 | continue; |
| 904 | this_err = abs((10000 - (target*10000/clock.dot))); |
| 905 | if (this_err < err_most) { |
| 906 | *best_clock = clock; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 907 | /* found on first matching */ |
| 908 | goto out; |
Zhenyu Wang | 4bfe6b6 | 2009-11-02 07:52:29 +0000 | [diff] [blame] | 909 | } else if (this_err < err_min) { |
| 910 | *best_clock = clock; |
| 911 | err_min = this_err; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 912 | } |
| 913 | } |
| 914 | } |
| 915 | } |
| 916 | } |
| 917 | out: |
Zhenyu Wang | 4bfe6b6 | 2009-11-02 07:52:29 +0000 | [diff] [blame] | 918 | return true; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 919 | } |
| 920 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 921 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
| 922 | static bool |
| 923 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 924 | int target, int refclk, intel_clock_t *best_clock) |
| 925 | { |
| 926 | intel_clock_t clock; |
| 927 | if (target < 200000) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 928 | clock.p1 = 2; |
| 929 | clock.p2 = 10; |
Keith Packard | b3d2549 | 2009-06-24 23:09:15 -0700 | [diff] [blame] | 930 | clock.n = 2; |
| 931 | clock.m1 = 23; |
| 932 | clock.m2 = 8; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 933 | } else { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 934 | clock.p1 = 1; |
| 935 | clock.p2 = 10; |
Keith Packard | b3d2549 | 2009-06-24 23:09:15 -0700 | [diff] [blame] | 936 | clock.n = 1; |
| 937 | clock.m1 = 14; |
| 938 | clock.m2 = 2; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 939 | } |
Keith Packard | b3d2549 | 2009-06-24 23:09:15 -0700 | [diff] [blame] | 940 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); |
| 941 | clock.p = (clock.p1 * clock.p2); |
| 942 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; |
Jesse Barnes | fe798b9 | 2009-10-20 07:55:28 +0900 | [diff] [blame] | 943 | clock.vco = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 944 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
| 945 | return true; |
| 946 | } |
| 947 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 948 | void |
| 949 | intel_wait_for_vblank(struct drm_device *dev) |
| 950 | { |
| 951 | /* Wait for 20ms, i.e. one cycle at 50hz. */ |
Arjan van de Ven | 580982d | 2009-03-23 13:36:25 -0700 | [diff] [blame] | 952 | mdelay(20); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 953 | } |
| 954 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 955 | /* Parameters have changed, update FBC info */ |
| 956 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
| 957 | { |
| 958 | struct drm_device *dev = crtc->dev; |
| 959 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 960 | struct drm_framebuffer *fb = crtc->fb; |
| 961 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 962 | struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private; |
| 963 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 964 | int plane, i; |
| 965 | u32 fbc_ctl, fbc_ctl2; |
| 966 | |
| 967 | dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
| 968 | |
| 969 | if (fb->pitch < dev_priv->cfb_pitch) |
| 970 | dev_priv->cfb_pitch = fb->pitch; |
| 971 | |
| 972 | /* FBC_CTL wants 64B units */ |
| 973 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
| 974 | dev_priv->cfb_fence = obj_priv->fence_reg; |
| 975 | dev_priv->cfb_plane = intel_crtc->plane; |
| 976 | plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; |
| 977 | |
| 978 | /* Clear old tags */ |
| 979 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) |
| 980 | I915_WRITE(FBC_TAG + (i * 4), 0); |
| 981 | |
| 982 | /* Set it up... */ |
| 983 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane; |
| 984 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 985 | fbc_ctl2 |= FBC_CTL_CPU_FENCE; |
| 986 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
| 987 | I915_WRITE(FBC_FENCE_OFF, crtc->y); |
| 988 | |
| 989 | /* enable it... */ |
| 990 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; |
| 991 | fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
| 992 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; |
| 993 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 994 | fbc_ctl |= dev_priv->cfb_fence; |
| 995 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 996 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 997 | DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ", |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 998 | dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane); |
| 999 | } |
| 1000 | |
| 1001 | void i8xx_disable_fbc(struct drm_device *dev) |
| 1002 | { |
| 1003 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1004 | u32 fbc_ctl; |
| 1005 | |
Jesse Barnes | c1a1cdc | 2009-09-16 15:05:00 -0700 | [diff] [blame] | 1006 | if (!I915_HAS_FBC(dev)) |
| 1007 | return; |
| 1008 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1009 | /* Disable compression */ |
| 1010 | fbc_ctl = I915_READ(FBC_CONTROL); |
| 1011 | fbc_ctl &= ~FBC_CTL_EN; |
| 1012 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 1013 | |
| 1014 | /* Wait for compressing bit to clear */ |
| 1015 | while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) |
| 1016 | ; /* nothing */ |
| 1017 | |
| 1018 | intel_wait_for_vblank(dev); |
| 1019 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1020 | DRM_DEBUG_KMS("disabled FBC\n"); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1021 | } |
| 1022 | |
| 1023 | static bool i8xx_fbc_enabled(struct drm_crtc *crtc) |
| 1024 | { |
| 1025 | struct drm_device *dev = crtc->dev; |
| 1026 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1027 | |
| 1028 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
| 1029 | } |
| 1030 | |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1031 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
| 1032 | { |
| 1033 | struct drm_device *dev = crtc->dev; |
| 1034 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1035 | struct drm_framebuffer *fb = crtc->fb; |
| 1036 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 1037 | struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private; |
| 1038 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1039 | int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : |
| 1040 | DPFC_CTL_PLANEB); |
| 1041 | unsigned long stall_watermark = 200; |
| 1042 | u32 dpfc_ctl; |
| 1043 | |
| 1044 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
| 1045 | dev_priv->cfb_fence = obj_priv->fence_reg; |
| 1046 | dev_priv->cfb_plane = intel_crtc->plane; |
| 1047 | |
| 1048 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; |
| 1049 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
| 1050 | dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence; |
| 1051 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); |
| 1052 | } else { |
| 1053 | I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY); |
| 1054 | } |
| 1055 | |
| 1056 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
| 1057 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
| 1058 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
| 1059 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
| 1060 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
| 1061 | |
| 1062 | /* enable it... */ |
| 1063 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); |
| 1064 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1065 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1066 | } |
| 1067 | |
| 1068 | void g4x_disable_fbc(struct drm_device *dev) |
| 1069 | { |
| 1070 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1071 | u32 dpfc_ctl; |
| 1072 | |
| 1073 | /* Disable compression */ |
| 1074 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
| 1075 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 1076 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
| 1077 | intel_wait_for_vblank(dev); |
| 1078 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1079 | DRM_DEBUG_KMS("disabled FBC\n"); |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1080 | } |
| 1081 | |
| 1082 | static bool g4x_fbc_enabled(struct drm_crtc *crtc) |
| 1083 | { |
| 1084 | struct drm_device *dev = crtc->dev; |
| 1085 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1086 | |
| 1087 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
| 1088 | } |
| 1089 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1090 | /** |
| 1091 | * intel_update_fbc - enable/disable FBC as needed |
| 1092 | * @crtc: CRTC to point the compressor at |
| 1093 | * @mode: mode in use |
| 1094 | * |
| 1095 | * Set up the framebuffer compression hardware at mode set time. We |
| 1096 | * enable it if possible: |
| 1097 | * - plane A only (on pre-965) |
| 1098 | * - no pixel mulitply/line duplication |
| 1099 | * - no alpha buffer discard |
| 1100 | * - no dual wide |
| 1101 | * - framebuffer <= 2048 in width, 1536 in height |
| 1102 | * |
| 1103 | * We can't assume that any compression will take place (worst case), |
| 1104 | * so the compressed buffer has to be the same size as the uncompressed |
| 1105 | * one. It also must reside (along with the line length buffer) in |
| 1106 | * stolen memory. |
| 1107 | * |
| 1108 | * We need to enable/disable FBC on a global basis. |
| 1109 | */ |
| 1110 | static void intel_update_fbc(struct drm_crtc *crtc, |
| 1111 | struct drm_display_mode *mode) |
| 1112 | { |
| 1113 | struct drm_device *dev = crtc->dev; |
| 1114 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1115 | struct drm_framebuffer *fb = crtc->fb; |
| 1116 | struct intel_framebuffer *intel_fb; |
| 1117 | struct drm_i915_gem_object *obj_priv; |
| 1118 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1119 | int plane = intel_crtc->plane; |
| 1120 | |
| 1121 | if (!i915_powersave) |
| 1122 | return; |
| 1123 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 1124 | if (!dev_priv->display.fbc_enabled || |
| 1125 | !dev_priv->display.enable_fbc || |
| 1126 | !dev_priv->display.disable_fbc) |
| 1127 | return; |
| 1128 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1129 | if (!crtc->fb) |
| 1130 | return; |
| 1131 | |
| 1132 | intel_fb = to_intel_framebuffer(fb); |
| 1133 | obj_priv = intel_fb->obj->driver_private; |
| 1134 | |
| 1135 | /* |
| 1136 | * If FBC is already on, we just have to verify that we can |
| 1137 | * keep it that way... |
| 1138 | * Need to disable if: |
| 1139 | * - changing FBC params (stride, fence, mode) |
| 1140 | * - new fb is too large to fit in compressed buffer |
| 1141 | * - going to an unsupported config (interlace, pixel multiply, etc.) |
| 1142 | */ |
| 1143 | if (intel_fb->obj->size > dev_priv->cfb_size) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1144 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
| 1145 | "compression\n"); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1146 | goto out_disable; |
| 1147 | } |
| 1148 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || |
| 1149 | (mode->flags & DRM_MODE_FLAG_DBLSCAN)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1150 | DRM_DEBUG_KMS("mode incompatible with compression, " |
| 1151 | "disabling\n"); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1152 | goto out_disable; |
| 1153 | } |
| 1154 | if ((mode->hdisplay > 2048) || |
| 1155 | (mode->vdisplay > 1536)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1156 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1157 | goto out_disable; |
| 1158 | } |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1159 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1160 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1161 | goto out_disable; |
| 1162 | } |
| 1163 | if (obj_priv->tiling_mode != I915_TILING_X) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1164 | DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n"); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1165 | goto out_disable; |
| 1166 | } |
| 1167 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 1168 | if (dev_priv->display.fbc_enabled(crtc)) { |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1169 | /* We can re-enable it in this case, but need to update pitch */ |
| 1170 | if (fb->pitch > dev_priv->cfb_pitch) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 1171 | dev_priv->display.disable_fbc(dev); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1172 | if (obj_priv->fence_reg != dev_priv->cfb_fence) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 1173 | dev_priv->display.disable_fbc(dev); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1174 | if (plane != dev_priv->cfb_plane) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 1175 | dev_priv->display.disable_fbc(dev); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1176 | } |
| 1177 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 1178 | if (!dev_priv->display.fbc_enabled(crtc)) { |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1179 | /* Now try to turn it back on if possible */ |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 1180 | dev_priv->display.enable_fbc(crtc, 500); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1181 | } |
| 1182 | |
| 1183 | return; |
| 1184 | |
| 1185 | out_disable: |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1186 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1187 | /* Multiple disables should be harmless */ |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 1188 | if (dev_priv->display.fbc_enabled(crtc)) |
| 1189 | dev_priv->display.disable_fbc(dev); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1190 | } |
| 1191 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1192 | static int |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1193 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
| 1194 | struct drm_framebuffer *old_fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1195 | { |
| 1196 | struct drm_device *dev = crtc->dev; |
| 1197 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1198 | struct drm_i915_master_private *master_priv; |
| 1199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1200 | struct intel_framebuffer *intel_fb; |
| 1201 | struct drm_i915_gem_object *obj_priv; |
| 1202 | struct drm_gem_object *obj; |
| 1203 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1204 | int plane = intel_crtc->plane; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1205 | unsigned long Start, Offset; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1206 | int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR); |
| 1207 | int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF); |
| 1208 | int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE; |
| 1209 | int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF); |
| 1210 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1211 | u32 dspcntr, alignment; |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1212 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1213 | |
| 1214 | /* no fb bound */ |
| 1215 | if (!crtc->fb) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1216 | DRM_DEBUG_KMS("No FB bound\n"); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1217 | return 0; |
| 1218 | } |
| 1219 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1220 | switch (plane) { |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1221 | case 0: |
| 1222 | case 1: |
| 1223 | break; |
| 1224 | default: |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1225 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1226 | return -EINVAL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1227 | } |
| 1228 | |
| 1229 | intel_fb = to_intel_framebuffer(crtc->fb); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1230 | obj = intel_fb->obj; |
| 1231 | obj_priv = obj->driver_private; |
| 1232 | |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1233 | switch (obj_priv->tiling_mode) { |
| 1234 | case I915_TILING_NONE: |
| 1235 | alignment = 64 * 1024; |
| 1236 | break; |
| 1237 | case I915_TILING_X: |
Chris Wilson | 2ebed17 | 2009-02-11 14:26:30 +0000 | [diff] [blame] | 1238 | /* pin() will align the object as required by fence */ |
| 1239 | alignment = 0; |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1240 | break; |
| 1241 | case I915_TILING_Y: |
| 1242 | /* FIXME: Is this true? */ |
| 1243 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1244 | return -EINVAL; |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1245 | default: |
| 1246 | BUG(); |
| 1247 | } |
| 1248 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1249 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 1250 | ret = i915_gem_object_pin(obj, alignment); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1251 | if (ret != 0) { |
| 1252 | mutex_unlock(&dev->struct_mutex); |
| 1253 | return ret; |
| 1254 | } |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1255 | |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 1256 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1257 | if (ret != 0) { |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 1258 | i915_gem_object_unpin(obj); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1259 | mutex_unlock(&dev->struct_mutex); |
| 1260 | return ret; |
| 1261 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1262 | |
Chris Wilson | 0d9c778 | 2009-10-14 20:12:46 +0100 | [diff] [blame] | 1263 | /* Install a fence for tiled scan-out. Pre-i965 always needs a fence, |
| 1264 | * whereas 965+ only requires a fence if using framebuffer compression. |
| 1265 | * For simplicity, we always install a fence as the cost is not that onerous. |
| 1266 | */ |
| 1267 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE && |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 1268 | obj_priv->tiling_mode != I915_TILING_NONE) { |
| 1269 | ret = i915_gem_object_get_fence_reg(obj); |
| 1270 | if (ret != 0) { |
| 1271 | i915_gem_object_unpin(obj); |
| 1272 | mutex_unlock(&dev->struct_mutex); |
| 1273 | return ret; |
| 1274 | } |
| 1275 | } |
| 1276 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1277 | dspcntr = I915_READ(dspcntr_reg); |
Jesse Barnes | 712531b | 2009-01-09 13:56:14 -0800 | [diff] [blame] | 1278 | /* Mask out pixel format bits in case we change it */ |
| 1279 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1280 | switch (crtc->fb->bits_per_pixel) { |
| 1281 | case 8: |
| 1282 | dspcntr |= DISPPLANE_8BPP; |
| 1283 | break; |
| 1284 | case 16: |
| 1285 | if (crtc->fb->depth == 15) |
| 1286 | dspcntr |= DISPPLANE_15_16BPP; |
| 1287 | else |
| 1288 | dspcntr |= DISPPLANE_16BPP; |
| 1289 | break; |
| 1290 | case 24: |
| 1291 | case 32: |
Kristian Høgsberg | a4f45cf | 2009-10-19 14:35:30 -0400 | [diff] [blame] | 1292 | if (crtc->fb->depth == 30) |
| 1293 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; |
| 1294 | else |
| 1295 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1296 | break; |
| 1297 | default: |
| 1298 | DRM_ERROR("Unknown color depth\n"); |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 1299 | i915_gem_object_unpin(obj); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1300 | mutex_unlock(&dev->struct_mutex); |
| 1301 | return -EINVAL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1302 | } |
Jesse Barnes | f544847 | 2009-04-14 14:17:47 -0700 | [diff] [blame] | 1303 | if (IS_I965G(dev)) { |
| 1304 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1305 | dspcntr |= DISPPLANE_TILED; |
| 1306 | else |
| 1307 | dspcntr &= ~DISPPLANE_TILED; |
| 1308 | } |
| 1309 | |
Zhenyu Wang | 553bd14 | 2009-09-02 10:57:52 +0800 | [diff] [blame] | 1310 | if (IS_IGDNG(dev)) |
| 1311 | /* must disable */ |
| 1312 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
| 1313 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1314 | I915_WRITE(dspcntr_reg, dspcntr); |
| 1315 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1316 | Start = obj_priv->gtt_offset; |
| 1317 | Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8); |
| 1318 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1319 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1320 | I915_WRITE(dspstride, crtc->fb->pitch); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1321 | if (IS_I965G(dev)) { |
| 1322 | I915_WRITE(dspbase, Offset); |
| 1323 | I915_READ(dspbase); |
| 1324 | I915_WRITE(dspsurf, Start); |
| 1325 | I915_READ(dspsurf); |
Jesse Barnes | f544847 | 2009-04-14 14:17:47 -0700 | [diff] [blame] | 1326 | I915_WRITE(dsptileoff, (y << 16) | x); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1327 | } else { |
| 1328 | I915_WRITE(dspbase, Start + Offset); |
| 1329 | I915_READ(dspbase); |
| 1330 | } |
| 1331 | |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1332 | if ((IS_I965G(dev) || plane == 0)) |
Jesse Barnes | edb8195 | 2009-09-17 17:06:47 -0700 | [diff] [blame] | 1333 | intel_update_fbc(crtc, &crtc->mode); |
| 1334 | |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1335 | intel_wait_for_vblank(dev); |
| 1336 | |
| 1337 | if (old_fb) { |
| 1338 | intel_fb = to_intel_framebuffer(old_fb); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1339 | obj_priv = intel_fb->obj->driver_private; |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1340 | i915_gem_object_unpin(intel_fb->obj); |
| 1341 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1342 | intel_increase_pllclock(crtc, true); |
| 1343 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1344 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1345 | |
| 1346 | if (!dev->primary->master) |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1347 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1348 | |
| 1349 | master_priv = dev->primary->master->driver_priv; |
| 1350 | if (!master_priv->sarea_priv) |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1351 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1352 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1353 | if (pipe) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1354 | master_priv->sarea_priv->pipeB_x = x; |
| 1355 | master_priv->sarea_priv->pipeB_y = y; |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1356 | } else { |
| 1357 | master_priv->sarea_priv->pipeA_x = x; |
| 1358 | master_priv->sarea_priv->pipeA_y = y; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1359 | } |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1360 | |
| 1361 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1362 | } |
| 1363 | |
Zhenyu Wang | 24f119c | 2009-07-24 01:00:28 +0800 | [diff] [blame] | 1364 | /* Disable the VGA plane that we never use */ |
| 1365 | static void i915_disable_vga (struct drm_device *dev) |
| 1366 | { |
| 1367 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1368 | u8 sr1; |
| 1369 | u32 vga_reg; |
| 1370 | |
| 1371 | if (IS_IGDNG(dev)) |
| 1372 | vga_reg = CPU_VGACNTRL; |
| 1373 | else |
| 1374 | vga_reg = VGACNTRL; |
| 1375 | |
| 1376 | if (I915_READ(vga_reg) & VGA_DISP_DISABLE) |
| 1377 | return; |
| 1378 | |
| 1379 | I915_WRITE8(VGA_SR_INDEX, 1); |
| 1380 | sr1 = I915_READ8(VGA_SR_DATA); |
| 1381 | I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5)); |
| 1382 | udelay(100); |
| 1383 | |
| 1384 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
| 1385 | } |
| 1386 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1387 | static void igdng_disable_pll_edp (struct drm_crtc *crtc) |
| 1388 | { |
| 1389 | struct drm_device *dev = crtc->dev; |
| 1390 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1391 | u32 dpa_ctl; |
| 1392 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1393 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1394 | dpa_ctl = I915_READ(DP_A); |
| 1395 | dpa_ctl &= ~DP_PLL_ENABLE; |
| 1396 | I915_WRITE(DP_A, dpa_ctl); |
| 1397 | } |
| 1398 | |
| 1399 | static void igdng_enable_pll_edp (struct drm_crtc *crtc) |
| 1400 | { |
| 1401 | struct drm_device *dev = crtc->dev; |
| 1402 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1403 | u32 dpa_ctl; |
| 1404 | |
| 1405 | dpa_ctl = I915_READ(DP_A); |
| 1406 | dpa_ctl |= DP_PLL_ENABLE; |
| 1407 | I915_WRITE(DP_A, dpa_ctl); |
| 1408 | udelay(200); |
| 1409 | } |
| 1410 | |
| 1411 | |
| 1412 | static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock) |
| 1413 | { |
| 1414 | struct drm_device *dev = crtc->dev; |
| 1415 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1416 | u32 dpa_ctl; |
| 1417 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1418 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1419 | dpa_ctl = I915_READ(DP_A); |
| 1420 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
| 1421 | |
| 1422 | if (clock < 200000) { |
| 1423 | u32 temp; |
| 1424 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
| 1425 | /* workaround for 160Mhz: |
| 1426 | 1) program 0x4600c bits 15:0 = 0x8124 |
| 1427 | 2) program 0x46010 bit 0 = 1 |
| 1428 | 3) program 0x46034 bit 24 = 1 |
| 1429 | 4) program 0x64000 bit 14 = 1 |
| 1430 | */ |
| 1431 | temp = I915_READ(0x4600c); |
| 1432 | temp &= 0xffff0000; |
| 1433 | I915_WRITE(0x4600c, temp | 0x8124); |
| 1434 | |
| 1435 | temp = I915_READ(0x46010); |
| 1436 | I915_WRITE(0x46010, temp | 1); |
| 1437 | |
| 1438 | temp = I915_READ(0x46034); |
| 1439 | I915_WRITE(0x46034, temp | (1 << 24)); |
| 1440 | } else { |
| 1441 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
| 1442 | } |
| 1443 | I915_WRITE(DP_A, dpa_ctl); |
| 1444 | |
| 1445 | udelay(500); |
| 1446 | } |
| 1447 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1448 | static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1449 | { |
| 1450 | struct drm_device *dev = crtc->dev; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1451 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1452 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1453 | int pipe = intel_crtc->pipe; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 1454 | int plane = intel_crtc->plane; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1455 | int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; |
| 1456 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
| 1457 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; |
| 1458 | int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR; |
| 1459 | int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; |
| 1460 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; |
| 1461 | int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR; |
| 1462 | int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR; |
| 1463 | int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; |
| 1464 | int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1; |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 1465 | int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ; |
Zhenyu Wang | 8dd81a3 | 2009-09-19 14:54:09 +0800 | [diff] [blame] | 1466 | int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1467 | int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; |
| 1468 | int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; |
| 1469 | int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; |
| 1470 | int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; |
| 1471 | int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; |
| 1472 | int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; |
| 1473 | int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B; |
| 1474 | int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B; |
| 1475 | int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B; |
| 1476 | int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B; |
| 1477 | int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B; |
| 1478 | int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; |
| 1479 | u32 temp; |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 1480 | int tries = 5, j, n; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1481 | |
| 1482 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
| 1483 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. |
| 1484 | */ |
| 1485 | switch (mode) { |
| 1486 | case DRM_MODE_DPMS_ON: |
| 1487 | case DRM_MODE_DPMS_STANDBY: |
| 1488 | case DRM_MODE_DPMS_SUSPEND: |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1489 | DRM_DEBUG_KMS("crtc %d dpms on\n", pipe); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1490 | if (HAS_eDP) { |
| 1491 | /* enable eDP PLL */ |
| 1492 | igdng_enable_pll_edp(crtc); |
| 1493 | } else { |
| 1494 | /* enable PCH DPLL */ |
| 1495 | temp = I915_READ(pch_dpll_reg); |
| 1496 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
| 1497 | I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE); |
| 1498 | I915_READ(pch_dpll_reg); |
| 1499 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1500 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1501 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
| 1502 | temp = I915_READ(fdi_rx_reg); |
| 1503 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE | |
| 1504 | FDI_SEL_PCDCLK | |
| 1505 | FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */ |
| 1506 | I915_READ(fdi_rx_reg); |
| 1507 | udelay(200); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1508 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1509 | /* Enable CPU FDI TX PLL, always on for IGDNG */ |
| 1510 | temp = I915_READ(fdi_tx_reg); |
| 1511 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
| 1512 | I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE); |
| 1513 | I915_READ(fdi_tx_reg); |
| 1514 | udelay(100); |
| 1515 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1516 | } |
| 1517 | |
Zhenyu Wang | 8dd81a3 | 2009-09-19 14:54:09 +0800 | [diff] [blame] | 1518 | /* Enable panel fitting for LVDS */ |
| 1519 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 1520 | temp = I915_READ(pf_ctl_reg); |
Zhenyu Wang | b1f60b7 | 2009-10-19 15:43:49 +0800 | [diff] [blame] | 1521 | I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3); |
Zhenyu Wang | 8dd81a3 | 2009-09-19 14:54:09 +0800 | [diff] [blame] | 1522 | |
| 1523 | /* currently full aspect */ |
| 1524 | I915_WRITE(pf_win_pos, 0); |
| 1525 | |
| 1526 | I915_WRITE(pf_win_size, |
| 1527 | (dev_priv->panel_fixed_mode->hdisplay << 16) | |
| 1528 | (dev_priv->panel_fixed_mode->vdisplay)); |
| 1529 | } |
| 1530 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1531 | /* Enable CPU pipe */ |
| 1532 | temp = I915_READ(pipeconf_reg); |
| 1533 | if ((temp & PIPEACONF_ENABLE) == 0) { |
| 1534 | I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); |
| 1535 | I915_READ(pipeconf_reg); |
| 1536 | udelay(100); |
| 1537 | } |
| 1538 | |
| 1539 | /* configure and enable CPU plane */ |
| 1540 | temp = I915_READ(dspcntr_reg); |
| 1541 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
| 1542 | I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE); |
| 1543 | /* Flush the plane changes */ |
| 1544 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); |
| 1545 | } |
| 1546 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1547 | if (!HAS_eDP) { |
| 1548 | /* enable CPU FDI TX and PCH FDI RX */ |
| 1549 | temp = I915_READ(fdi_tx_reg); |
| 1550 | temp |= FDI_TX_ENABLE; |
| 1551 | temp |= FDI_DP_PORT_WIDTH_X4; /* default */ |
| 1552 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1553 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 1554 | I915_WRITE(fdi_tx_reg, temp); |
| 1555 | I915_READ(fdi_tx_reg); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1556 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1557 | temp = I915_READ(fdi_rx_reg); |
| 1558 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1559 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 1560 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE); |
| 1561 | I915_READ(fdi_rx_reg); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1562 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1563 | udelay(150); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1564 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1565 | /* Train FDI. */ |
| 1566 | /* umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 1567 | for train result */ |
| 1568 | temp = I915_READ(fdi_rx_imr_reg); |
| 1569 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 1570 | temp &= ~FDI_RX_BIT_LOCK; |
| 1571 | I915_WRITE(fdi_rx_imr_reg, temp); |
| 1572 | I915_READ(fdi_rx_imr_reg); |
| 1573 | udelay(150); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1574 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1575 | temp = I915_READ(fdi_rx_iir_reg); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1576 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1577 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1578 | if ((temp & FDI_RX_BIT_LOCK) == 0) { |
| 1579 | for (j = 0; j < tries; j++) { |
| 1580 | temp = I915_READ(fdi_rx_iir_reg); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1581 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", |
| 1582 | temp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1583 | if (temp & FDI_RX_BIT_LOCK) |
| 1584 | break; |
| 1585 | udelay(200); |
| 1586 | } |
| 1587 | if (j != tries) |
| 1588 | I915_WRITE(fdi_rx_iir_reg, |
| 1589 | temp | FDI_RX_BIT_LOCK); |
| 1590 | else |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1591 | DRM_DEBUG_KMS("train 1 fail\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1592 | } else { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1593 | I915_WRITE(fdi_rx_iir_reg, |
| 1594 | temp | FDI_RX_BIT_LOCK); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1595 | DRM_DEBUG_KMS("train 1 ok 2!\n"); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1596 | } |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1597 | temp = I915_READ(fdi_tx_reg); |
| 1598 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1599 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 1600 | I915_WRITE(fdi_tx_reg, temp); |
| 1601 | |
| 1602 | temp = I915_READ(fdi_rx_reg); |
| 1603 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1604 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 1605 | I915_WRITE(fdi_rx_reg, temp); |
| 1606 | |
| 1607 | udelay(150); |
| 1608 | |
| 1609 | temp = I915_READ(fdi_rx_iir_reg); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1610 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1611 | |
| 1612 | if ((temp & FDI_RX_SYMBOL_LOCK) == 0) { |
| 1613 | for (j = 0; j < tries; j++) { |
| 1614 | temp = I915_READ(fdi_rx_iir_reg); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1615 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", |
| 1616 | temp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1617 | if (temp & FDI_RX_SYMBOL_LOCK) |
| 1618 | break; |
| 1619 | udelay(200); |
| 1620 | } |
| 1621 | if (j != tries) { |
| 1622 | I915_WRITE(fdi_rx_iir_reg, |
| 1623 | temp | FDI_RX_SYMBOL_LOCK); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1624 | DRM_DEBUG_KMS("train 2 ok 1!\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1625 | } else |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1626 | DRM_DEBUG_KMS("train 2 fail\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1627 | } else { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1628 | I915_WRITE(fdi_rx_iir_reg, |
| 1629 | temp | FDI_RX_SYMBOL_LOCK); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1630 | DRM_DEBUG_KMS("train 2 ok 2!\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1631 | } |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1632 | DRM_DEBUG_KMS("train done\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1633 | |
| 1634 | /* set transcoder timing */ |
| 1635 | I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg)); |
| 1636 | I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg)); |
| 1637 | I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg)); |
| 1638 | |
| 1639 | I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg)); |
| 1640 | I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg)); |
| 1641 | I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg)); |
| 1642 | |
| 1643 | /* enable PCH transcoder */ |
| 1644 | temp = I915_READ(transconf_reg); |
| 1645 | I915_WRITE(transconf_reg, temp | TRANS_ENABLE); |
| 1646 | I915_READ(transconf_reg); |
| 1647 | |
| 1648 | while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0) |
| 1649 | ; |
| 1650 | |
| 1651 | /* enable normal */ |
| 1652 | |
| 1653 | temp = I915_READ(fdi_tx_reg); |
| 1654 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1655 | I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE | |
| 1656 | FDI_TX_ENHANCE_FRAME_ENABLE); |
| 1657 | I915_READ(fdi_tx_reg); |
| 1658 | |
| 1659 | temp = I915_READ(fdi_rx_reg); |
| 1660 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1661 | I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE | |
| 1662 | FDI_RX_ENHANCE_FRAME_ENABLE); |
| 1663 | I915_READ(fdi_rx_reg); |
| 1664 | |
| 1665 | /* wait one idle pattern time */ |
| 1666 | udelay(100); |
| 1667 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1668 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1669 | |
| 1670 | intel_crtc_load_lut(crtc); |
| 1671 | |
| 1672 | break; |
| 1673 | case DRM_MODE_DPMS_OFF: |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1674 | DRM_DEBUG_KMS("crtc %d dpms off\n", pipe); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1675 | |
Zhenyu Wang | 24f119c | 2009-07-24 01:00:28 +0800 | [diff] [blame] | 1676 | i915_disable_vga(dev); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1677 | |
| 1678 | /* Disable display plane */ |
| 1679 | temp = I915_READ(dspcntr_reg); |
| 1680 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { |
| 1681 | I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE); |
| 1682 | /* Flush the plane changes */ |
| 1683 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); |
| 1684 | I915_READ(dspbase_reg); |
| 1685 | } |
| 1686 | |
| 1687 | /* disable cpu pipe, disable after all planes disabled */ |
| 1688 | temp = I915_READ(pipeconf_reg); |
| 1689 | if ((temp & PIPEACONF_ENABLE) != 0) { |
| 1690 | I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); |
| 1691 | I915_READ(pipeconf_reg); |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 1692 | n = 0; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1693 | /* wait for cpu pipe off, pipe state */ |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 1694 | while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) { |
| 1695 | n++; |
| 1696 | if (n < 60) { |
| 1697 | udelay(500); |
| 1698 | continue; |
| 1699 | } else { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1700 | DRM_DEBUG_KMS("pipe %d off delay\n", |
| 1701 | pipe); |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 1702 | break; |
| 1703 | } |
| 1704 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1705 | } else |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1706 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1707 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1708 | if (HAS_eDP) { |
| 1709 | igdng_disable_pll_edp(crtc); |
| 1710 | } |
| 1711 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1712 | /* disable CPU FDI tx and PCH FDI rx */ |
| 1713 | temp = I915_READ(fdi_tx_reg); |
| 1714 | I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE); |
| 1715 | I915_READ(fdi_tx_reg); |
| 1716 | |
| 1717 | temp = I915_READ(fdi_rx_reg); |
| 1718 | I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE); |
| 1719 | I915_READ(fdi_rx_reg); |
| 1720 | |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 1721 | udelay(100); |
| 1722 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1723 | /* still set train pattern 1 */ |
| 1724 | temp = I915_READ(fdi_tx_reg); |
| 1725 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1726 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 1727 | I915_WRITE(fdi_tx_reg, temp); |
| 1728 | |
| 1729 | temp = I915_READ(fdi_rx_reg); |
| 1730 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 1731 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 1732 | I915_WRITE(fdi_rx_reg, temp); |
| 1733 | |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 1734 | udelay(100); |
| 1735 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1736 | /* disable PCH transcoder */ |
| 1737 | temp = I915_READ(transconf_reg); |
| 1738 | if ((temp & TRANS_ENABLE) != 0) { |
| 1739 | I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE); |
| 1740 | I915_READ(transconf_reg); |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 1741 | n = 0; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1742 | /* wait for PCH transcoder off, transcoder state */ |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 1743 | while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) { |
| 1744 | n++; |
| 1745 | if (n < 60) { |
| 1746 | udelay(500); |
| 1747 | continue; |
| 1748 | } else { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1749 | DRM_DEBUG_KMS("transcoder %d off " |
| 1750 | "delay\n", pipe); |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 1751 | break; |
| 1752 | } |
| 1753 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1754 | } |
| 1755 | |
| 1756 | /* disable PCH DPLL */ |
| 1757 | temp = I915_READ(pch_dpll_reg); |
| 1758 | if ((temp & DPLL_VCO_ENABLE) != 0) { |
| 1759 | I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE); |
| 1760 | I915_READ(pch_dpll_reg); |
| 1761 | } |
| 1762 | |
| 1763 | temp = I915_READ(fdi_rx_reg); |
| 1764 | if ((temp & FDI_RX_PLL_ENABLE) != 0) { |
| 1765 | temp &= ~FDI_SEL_PCDCLK; |
| 1766 | temp &= ~FDI_RX_PLL_ENABLE; |
| 1767 | I915_WRITE(fdi_rx_reg, temp); |
| 1768 | I915_READ(fdi_rx_reg); |
| 1769 | } |
| 1770 | |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 1771 | /* Disable CPU FDI TX PLL */ |
| 1772 | temp = I915_READ(fdi_tx_reg); |
| 1773 | if ((temp & FDI_TX_PLL_ENABLE) != 0) { |
| 1774 | I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE); |
| 1775 | I915_READ(fdi_tx_reg); |
| 1776 | udelay(100); |
| 1777 | } |
| 1778 | |
| 1779 | /* Disable PF */ |
| 1780 | temp = I915_READ(pf_ctl_reg); |
| 1781 | if ((temp & PF_ENABLE) != 0) { |
| 1782 | I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE); |
| 1783 | I915_READ(pf_ctl_reg); |
| 1784 | } |
| 1785 | I915_WRITE(pf_win_size, 0); |
| 1786 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1787 | /* Wait for the clocks to turn off. */ |
| 1788 | udelay(150); |
| 1789 | break; |
| 1790 | } |
| 1791 | } |
| 1792 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1793 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
| 1794 | { |
| 1795 | struct intel_overlay *overlay; |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 1796 | int ret; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1797 | |
| 1798 | if (!enable && intel_crtc->overlay) { |
| 1799 | overlay = intel_crtc->overlay; |
| 1800 | mutex_lock(&overlay->dev->struct_mutex); |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 1801 | for (;;) { |
| 1802 | ret = intel_overlay_switch_off(overlay); |
| 1803 | if (ret == 0) |
| 1804 | break; |
| 1805 | |
| 1806 | ret = intel_overlay_recover_from_interrupt(overlay, 0); |
| 1807 | if (ret != 0) { |
| 1808 | /* overlay doesn't react anymore. Usually |
| 1809 | * results in a black screen and an unkillable |
| 1810 | * X server. */ |
| 1811 | BUG(); |
| 1812 | overlay->hw_wedged = HW_WEDGED; |
| 1813 | break; |
| 1814 | } |
| 1815 | } |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1816 | mutex_unlock(&overlay->dev->struct_mutex); |
| 1817 | } |
| 1818 | /* Let userspace switch the overlay on again. In most cases userspace |
| 1819 | * has to recompute where to put it anyway. */ |
| 1820 | |
| 1821 | return; |
| 1822 | } |
| 1823 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1824 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 1825 | { |
| 1826 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1827 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1828 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1829 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1830 | int plane = intel_crtc->plane; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1831 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1832 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; |
| 1833 | int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1834 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
| 1835 | u32 temp; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1836 | |
| 1837 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
| 1838 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. |
| 1839 | */ |
| 1840 | switch (mode) { |
| 1841 | case DRM_MODE_DPMS_ON: |
| 1842 | case DRM_MODE_DPMS_STANDBY: |
| 1843 | case DRM_MODE_DPMS_SUSPEND: |
Jesse Barnes | 629598d | 2009-10-20 07:37:32 +0900 | [diff] [blame] | 1844 | intel_update_watermarks(dev); |
| 1845 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1846 | /* Enable the DPLL */ |
| 1847 | temp = I915_READ(dpll_reg); |
| 1848 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
| 1849 | I915_WRITE(dpll_reg, temp); |
| 1850 | I915_READ(dpll_reg); |
| 1851 | /* Wait for the clocks to stabilize. */ |
| 1852 | udelay(150); |
| 1853 | I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); |
| 1854 | I915_READ(dpll_reg); |
| 1855 | /* Wait for the clocks to stabilize. */ |
| 1856 | udelay(150); |
| 1857 | I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); |
| 1858 | I915_READ(dpll_reg); |
| 1859 | /* Wait for the clocks to stabilize. */ |
| 1860 | udelay(150); |
| 1861 | } |
| 1862 | |
| 1863 | /* Enable the pipe */ |
| 1864 | temp = I915_READ(pipeconf_reg); |
| 1865 | if ((temp & PIPEACONF_ENABLE) == 0) |
| 1866 | I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); |
| 1867 | |
| 1868 | /* Enable the plane */ |
| 1869 | temp = I915_READ(dspcntr_reg); |
| 1870 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
| 1871 | I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE); |
| 1872 | /* Flush the plane changes */ |
| 1873 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); |
| 1874 | } |
| 1875 | |
| 1876 | intel_crtc_load_lut(crtc); |
| 1877 | |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1878 | if ((IS_I965G(dev) || plane == 0)) |
| 1879 | intel_update_fbc(crtc, &crtc->mode); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1880 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1881 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1882 | intel_crtc_dpms_overlay(intel_crtc, true); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1883 | break; |
| 1884 | case DRM_MODE_DPMS_OFF: |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 1885 | intel_update_watermarks(dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1886 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1887 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1888 | intel_crtc_dpms_overlay(intel_crtc, false); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1889 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 1890 | if (dev_priv->cfb_plane == plane && |
| 1891 | dev_priv->display.disable_fbc) |
| 1892 | dev_priv->display.disable_fbc(dev); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1893 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1894 | /* Disable the VGA plane that we never use */ |
Zhenyu Wang | 24f119c | 2009-07-24 01:00:28 +0800 | [diff] [blame] | 1895 | i915_disable_vga(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1896 | |
| 1897 | /* Disable display plane */ |
| 1898 | temp = I915_READ(dspcntr_reg); |
| 1899 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { |
| 1900 | I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE); |
| 1901 | /* Flush the plane changes */ |
| 1902 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); |
| 1903 | I915_READ(dspbase_reg); |
| 1904 | } |
| 1905 | |
| 1906 | if (!IS_I9XX(dev)) { |
| 1907 | /* Wait for vblank for the disable to take effect */ |
| 1908 | intel_wait_for_vblank(dev); |
| 1909 | } |
| 1910 | |
| 1911 | /* Next, disable display pipes */ |
| 1912 | temp = I915_READ(pipeconf_reg); |
| 1913 | if ((temp & PIPEACONF_ENABLE) != 0) { |
| 1914 | I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); |
| 1915 | I915_READ(pipeconf_reg); |
| 1916 | } |
| 1917 | |
| 1918 | /* Wait for vblank for the disable to take effect. */ |
| 1919 | intel_wait_for_vblank(dev); |
| 1920 | |
| 1921 | temp = I915_READ(dpll_reg); |
| 1922 | if ((temp & DPLL_VCO_ENABLE) != 0) { |
| 1923 | I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); |
| 1924 | I915_READ(dpll_reg); |
| 1925 | } |
| 1926 | |
| 1927 | /* Wait for the clocks to turn off. */ |
| 1928 | udelay(150); |
| 1929 | break; |
| 1930 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1931 | } |
| 1932 | |
| 1933 | /** |
| 1934 | * Sets the power management mode of the pipe and plane. |
| 1935 | * |
| 1936 | * This code should probably grow support for turning the cursor off and back |
| 1937 | * on appropriately at the same time as we're turning the pipe off/on. |
| 1938 | */ |
| 1939 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 1940 | { |
| 1941 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 1942 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 1943 | struct drm_i915_master_private *master_priv; |
| 1944 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1945 | int pipe = intel_crtc->pipe; |
| 1946 | bool enabled; |
| 1947 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 1948 | dev_priv->display.dpms(crtc, mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1949 | |
Daniel Vetter | 65655d4 | 2009-08-11 16:05:31 +0200 | [diff] [blame] | 1950 | intel_crtc->dpms_mode = mode; |
| 1951 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1952 | if (!dev->primary->master) |
| 1953 | return; |
| 1954 | |
| 1955 | master_priv = dev->primary->master->driver_priv; |
| 1956 | if (!master_priv->sarea_priv) |
| 1957 | return; |
| 1958 | |
| 1959 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; |
| 1960 | |
| 1961 | switch (pipe) { |
| 1962 | case 0: |
| 1963 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
| 1964 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
| 1965 | break; |
| 1966 | case 1: |
| 1967 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
| 1968 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
| 1969 | break; |
| 1970 | default: |
| 1971 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); |
| 1972 | break; |
| 1973 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1974 | } |
| 1975 | |
| 1976 | static void intel_crtc_prepare (struct drm_crtc *crtc) |
| 1977 | { |
| 1978 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 1979 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); |
| 1980 | } |
| 1981 | |
| 1982 | static void intel_crtc_commit (struct drm_crtc *crtc) |
| 1983 | { |
| 1984 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 1985 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); |
| 1986 | } |
| 1987 | |
| 1988 | void intel_encoder_prepare (struct drm_encoder *encoder) |
| 1989 | { |
| 1990 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
| 1991 | /* lvds has its own version of prepare see intel_lvds_prepare */ |
| 1992 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); |
| 1993 | } |
| 1994 | |
| 1995 | void intel_encoder_commit (struct drm_encoder *encoder) |
| 1996 | { |
| 1997 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
| 1998 | /* lvds has its own version of commit see intel_lvds_commit */ |
| 1999 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
| 2000 | } |
| 2001 | |
| 2002 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
| 2003 | struct drm_display_mode *mode, |
| 2004 | struct drm_display_mode *adjusted_mode) |
| 2005 | { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2006 | struct drm_device *dev = crtc->dev; |
| 2007 | if (IS_IGDNG(dev)) { |
| 2008 | /* FDI link clock is fixed at 2.7G */ |
| 2009 | if (mode->clock * 3 > 27000 * 4) |
| 2010 | return MODE_CLOCK_HIGH; |
| 2011 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2012 | return true; |
| 2013 | } |
| 2014 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2015 | static int i945_get_display_clock_speed(struct drm_device *dev) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2016 | { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2017 | return 400000; |
| 2018 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2019 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2020 | static int i915_get_display_clock_speed(struct drm_device *dev) |
| 2021 | { |
| 2022 | return 333000; |
| 2023 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2024 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2025 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
| 2026 | { |
| 2027 | return 200000; |
| 2028 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2029 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2030 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
| 2031 | { |
| 2032 | u16 gcfgc = 0; |
| 2033 | |
| 2034 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 2035 | |
| 2036 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2037 | return 133000; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2038 | else { |
| 2039 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 2040 | case GC_DISPLAY_CLOCK_333_MHZ: |
| 2041 | return 333000; |
| 2042 | default: |
| 2043 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
| 2044 | return 190000; |
| 2045 | } |
| 2046 | } |
| 2047 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2048 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2049 | static int i865_get_display_clock_speed(struct drm_device *dev) |
| 2050 | { |
| 2051 | return 266000; |
| 2052 | } |
| 2053 | |
| 2054 | static int i855_get_display_clock_speed(struct drm_device *dev) |
| 2055 | { |
| 2056 | u16 hpllcc = 0; |
| 2057 | /* Assume that the hardware is in the high speed state. This |
| 2058 | * should be the default. |
| 2059 | */ |
| 2060 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
| 2061 | case GC_CLOCK_133_200: |
| 2062 | case GC_CLOCK_100_200: |
| 2063 | return 200000; |
| 2064 | case GC_CLOCK_166_250: |
| 2065 | return 250000; |
| 2066 | case GC_CLOCK_100_133: |
| 2067 | return 133000; |
| 2068 | } |
| 2069 | |
| 2070 | /* Shouldn't happen */ |
| 2071 | return 0; |
| 2072 | } |
| 2073 | |
| 2074 | static int i830_get_display_clock_speed(struct drm_device *dev) |
| 2075 | { |
| 2076 | return 133000; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2077 | } |
| 2078 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2079 | /** |
| 2080 | * Return the pipe currently connected to the panel fitter, |
| 2081 | * or -1 if the panel fitter is not present or not in use |
| 2082 | */ |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2083 | int intel_panel_fitter_pipe (struct drm_device *dev) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2084 | { |
| 2085 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2086 | u32 pfit_control; |
| 2087 | |
| 2088 | /* i830 doesn't have a panel fitter */ |
| 2089 | if (IS_I830(dev)) |
| 2090 | return -1; |
| 2091 | |
| 2092 | pfit_control = I915_READ(PFIT_CONTROL); |
| 2093 | |
| 2094 | /* See if the panel fitter is in use */ |
| 2095 | if ((pfit_control & PFIT_ENABLE) == 0) |
| 2096 | return -1; |
| 2097 | |
| 2098 | /* 965 can place panel fitter on either pipe */ |
| 2099 | if (IS_I965G(dev)) |
| 2100 | return (pfit_control >> 29) & 0x3; |
| 2101 | |
| 2102 | /* older chips can only use pipe 1 */ |
| 2103 | return 1; |
| 2104 | } |
| 2105 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2106 | struct fdi_m_n { |
| 2107 | u32 tu; |
| 2108 | u32 gmch_m; |
| 2109 | u32 gmch_n; |
| 2110 | u32 link_m; |
| 2111 | u32 link_n; |
| 2112 | }; |
| 2113 | |
| 2114 | static void |
| 2115 | fdi_reduce_ratio(u32 *num, u32 *den) |
| 2116 | { |
| 2117 | while (*num > 0xffffff || *den > 0xffffff) { |
| 2118 | *num >>= 1; |
| 2119 | *den >>= 1; |
| 2120 | } |
| 2121 | } |
| 2122 | |
| 2123 | #define DATA_N 0x800000 |
| 2124 | #define LINK_N 0x80000 |
| 2125 | |
| 2126 | static void |
Zhenyu Wang | 58a2747 | 2009-09-25 08:01:28 +0000 | [diff] [blame] | 2127 | igdng_compute_m_n(int bits_per_pixel, int nlanes, |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2128 | int pixel_clock, int link_clock, |
| 2129 | struct fdi_m_n *m_n) |
| 2130 | { |
| 2131 | u64 temp; |
| 2132 | |
| 2133 | m_n->tu = 64; /* default size */ |
| 2134 | |
| 2135 | temp = (u64) DATA_N * pixel_clock; |
| 2136 | temp = div_u64(temp, link_clock); |
Zhenyu Wang | 58a2747 | 2009-09-25 08:01:28 +0000 | [diff] [blame] | 2137 | m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes); |
| 2138 | m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */ |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2139 | m_n->gmch_n = DATA_N; |
| 2140 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
| 2141 | |
| 2142 | temp = (u64) LINK_N * pixel_clock; |
| 2143 | m_n->link_m = div_u64(temp, link_clock); |
| 2144 | m_n->link_n = LINK_N; |
| 2145 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
| 2146 | } |
| 2147 | |
| 2148 | |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2149 | struct intel_watermark_params { |
| 2150 | unsigned long fifo_size; |
| 2151 | unsigned long max_wm; |
| 2152 | unsigned long default_wm; |
| 2153 | unsigned long guard_size; |
| 2154 | unsigned long cacheline_size; |
| 2155 | }; |
| 2156 | |
| 2157 | /* IGD has different values for various configs */ |
| 2158 | static struct intel_watermark_params igd_display_wm = { |
| 2159 | IGD_DISPLAY_FIFO, |
| 2160 | IGD_MAX_WM, |
| 2161 | IGD_DFT_WM, |
| 2162 | IGD_GUARD_WM, |
| 2163 | IGD_FIFO_LINE_SIZE |
| 2164 | }; |
| 2165 | static struct intel_watermark_params igd_display_hplloff_wm = { |
| 2166 | IGD_DISPLAY_FIFO, |
| 2167 | IGD_MAX_WM, |
| 2168 | IGD_DFT_HPLLOFF_WM, |
| 2169 | IGD_GUARD_WM, |
| 2170 | IGD_FIFO_LINE_SIZE |
| 2171 | }; |
| 2172 | static struct intel_watermark_params igd_cursor_wm = { |
| 2173 | IGD_CURSOR_FIFO, |
| 2174 | IGD_CURSOR_MAX_WM, |
| 2175 | IGD_CURSOR_DFT_WM, |
| 2176 | IGD_CURSOR_GUARD_WM, |
| 2177 | IGD_FIFO_LINE_SIZE, |
| 2178 | }; |
| 2179 | static struct intel_watermark_params igd_cursor_hplloff_wm = { |
| 2180 | IGD_CURSOR_FIFO, |
| 2181 | IGD_CURSOR_MAX_WM, |
| 2182 | IGD_CURSOR_DFT_WM, |
| 2183 | IGD_CURSOR_GUARD_WM, |
| 2184 | IGD_FIFO_LINE_SIZE |
| 2185 | }; |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2186 | static struct intel_watermark_params g4x_wm_info = { |
| 2187 | G4X_FIFO_SIZE, |
| 2188 | G4X_MAX_WM, |
| 2189 | G4X_MAX_WM, |
| 2190 | 2, |
| 2191 | G4X_FIFO_LINE_SIZE, |
| 2192 | }; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2193 | static struct intel_watermark_params i945_wm_info = { |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2194 | I945_FIFO_SIZE, |
| 2195 | I915_MAX_WM, |
| 2196 | 1, |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2197 | 2, |
| 2198 | I915_FIFO_LINE_SIZE |
| 2199 | }; |
| 2200 | static struct intel_watermark_params i915_wm_info = { |
| 2201 | I915_FIFO_SIZE, |
| 2202 | I915_MAX_WM, |
| 2203 | 1, |
| 2204 | 2, |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2205 | I915_FIFO_LINE_SIZE |
| 2206 | }; |
| 2207 | static struct intel_watermark_params i855_wm_info = { |
| 2208 | I855GM_FIFO_SIZE, |
| 2209 | I915_MAX_WM, |
| 2210 | 1, |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2211 | 2, |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2212 | I830_FIFO_LINE_SIZE |
| 2213 | }; |
| 2214 | static struct intel_watermark_params i830_wm_info = { |
| 2215 | I830_FIFO_SIZE, |
| 2216 | I915_MAX_WM, |
| 2217 | 1, |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2218 | 2, |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2219 | I830_FIFO_LINE_SIZE |
| 2220 | }; |
| 2221 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2222 | /** |
| 2223 | * intel_calculate_wm - calculate watermark level |
| 2224 | * @clock_in_khz: pixel clock |
| 2225 | * @wm: chip FIFO params |
| 2226 | * @pixel_size: display pixel size |
| 2227 | * @latency_ns: memory latency for the platform |
| 2228 | * |
| 2229 | * Calculate the watermark level (the level at which the display plane will |
| 2230 | * start fetching from memory again). Each chip has a different display |
| 2231 | * FIFO size and allocation, so the caller needs to figure that out and pass |
| 2232 | * in the correct intel_watermark_params structure. |
| 2233 | * |
| 2234 | * As the pixel clock runs, the FIFO will be drained at a rate that depends |
| 2235 | * on the pixel size. When it reaches the watermark level, it'll start |
| 2236 | * fetching FIFO line sized based chunks from memory until the FIFO fills |
| 2237 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
| 2238 | * will occur, and a display engine hang could result. |
| 2239 | */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2240 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
| 2241 | struct intel_watermark_params *wm, |
| 2242 | int pixel_size, |
| 2243 | unsigned long latency_ns) |
| 2244 | { |
Jesse Barnes | 390c4dd | 2009-07-16 13:01:01 -0700 | [diff] [blame] | 2245 | long entries_required, wm_size; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2246 | |
Jesse Barnes | d660467 | 2009-09-11 12:25:56 -0700 | [diff] [blame] | 2247 | /* |
| 2248 | * Note: we need to make sure we don't overflow for various clock & |
| 2249 | * latency values. |
| 2250 | * clocks go from a few thousand to several hundred thousand. |
| 2251 | * latency is usually a few thousand |
| 2252 | */ |
| 2253 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
| 2254 | 1000; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2255 | entries_required /= wm->cacheline_size; |
| 2256 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2257 | DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2258 | |
| 2259 | wm_size = wm->fifo_size - (entries_required + wm->guard_size); |
| 2260 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2261 | DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2262 | |
Jesse Barnes | 390c4dd | 2009-07-16 13:01:01 -0700 | [diff] [blame] | 2263 | /* Don't promote wm_size to unsigned... */ |
| 2264 | if (wm_size > (long)wm->max_wm) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2265 | wm_size = wm->max_wm; |
Jesse Barnes | 390c4dd | 2009-07-16 13:01:01 -0700 | [diff] [blame] | 2266 | if (wm_size <= 0) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2267 | wm_size = wm->default_wm; |
| 2268 | return wm_size; |
| 2269 | } |
| 2270 | |
| 2271 | struct cxsr_latency { |
| 2272 | int is_desktop; |
| 2273 | unsigned long fsb_freq; |
| 2274 | unsigned long mem_freq; |
| 2275 | unsigned long display_sr; |
| 2276 | unsigned long display_hpll_disable; |
| 2277 | unsigned long cursor_sr; |
| 2278 | unsigned long cursor_hpll_disable; |
| 2279 | }; |
| 2280 | |
| 2281 | static struct cxsr_latency cxsr_latency_table[] = { |
| 2282 | {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
| 2283 | {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
| 2284 | {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ |
| 2285 | |
| 2286 | {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ |
| 2287 | {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ |
| 2288 | {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ |
| 2289 | |
| 2290 | {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ |
| 2291 | {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ |
| 2292 | {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ |
| 2293 | |
| 2294 | {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ |
| 2295 | {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ |
| 2296 | {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ |
| 2297 | |
| 2298 | {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ |
| 2299 | {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ |
| 2300 | {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ |
| 2301 | |
| 2302 | {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ |
| 2303 | {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ |
| 2304 | {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ |
| 2305 | }; |
| 2306 | |
| 2307 | static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb, |
| 2308 | int mem) |
| 2309 | { |
| 2310 | int i; |
| 2311 | struct cxsr_latency *latency; |
| 2312 | |
| 2313 | if (fsb == 0 || mem == 0) |
| 2314 | return NULL; |
| 2315 | |
| 2316 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { |
| 2317 | latency = &cxsr_latency_table[i]; |
| 2318 | if (is_desktop == latency->is_desktop && |
Jaswinder Singh Rajput | decbbcd | 2009-09-12 23:15:07 +0530 | [diff] [blame] | 2319 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
| 2320 | return latency; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2321 | } |
Jaswinder Singh Rajput | decbbcd | 2009-09-12 23:15:07 +0530 | [diff] [blame] | 2322 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2323 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
Jaswinder Singh Rajput | decbbcd | 2009-09-12 23:15:07 +0530 | [diff] [blame] | 2324 | |
| 2325 | return NULL; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2326 | } |
| 2327 | |
| 2328 | static void igd_disable_cxsr(struct drm_device *dev) |
| 2329 | { |
| 2330 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2331 | u32 reg; |
| 2332 | |
| 2333 | /* deactivate cxsr */ |
| 2334 | reg = I915_READ(DSPFW3); |
| 2335 | reg &= ~(IGD_SELF_REFRESH_EN); |
| 2336 | I915_WRITE(DSPFW3, reg); |
| 2337 | DRM_INFO("Big FIFO is disabled\n"); |
| 2338 | } |
| 2339 | |
| 2340 | static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock, |
| 2341 | int pixel_size) |
| 2342 | { |
| 2343 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2344 | u32 reg; |
| 2345 | unsigned long wm; |
| 2346 | struct cxsr_latency *latency; |
| 2347 | |
| 2348 | latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq, |
| 2349 | dev_priv->mem_freq); |
| 2350 | if (!latency) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2351 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2352 | igd_disable_cxsr(dev); |
| 2353 | return; |
| 2354 | } |
| 2355 | |
| 2356 | /* Display SR */ |
| 2357 | wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size, |
| 2358 | latency->display_sr); |
| 2359 | reg = I915_READ(DSPFW1); |
| 2360 | reg &= 0x7fffff; |
| 2361 | reg |= wm << 23; |
| 2362 | I915_WRITE(DSPFW1, reg); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2363 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2364 | |
| 2365 | /* cursor SR */ |
| 2366 | wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size, |
| 2367 | latency->cursor_sr); |
| 2368 | reg = I915_READ(DSPFW3); |
| 2369 | reg &= ~(0x3f << 24); |
| 2370 | reg |= (wm & 0x3f) << 24; |
| 2371 | I915_WRITE(DSPFW3, reg); |
| 2372 | |
| 2373 | /* Display HPLL off SR */ |
| 2374 | wm = intel_calculate_wm(clock, &igd_display_hplloff_wm, |
| 2375 | latency->display_hpll_disable, I915_FIFO_LINE_SIZE); |
| 2376 | reg = I915_READ(DSPFW3); |
| 2377 | reg &= 0xfffffe00; |
| 2378 | reg |= wm & 0x1ff; |
| 2379 | I915_WRITE(DSPFW3, reg); |
| 2380 | |
| 2381 | /* cursor HPLL off SR */ |
| 2382 | wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size, |
| 2383 | latency->cursor_hpll_disable); |
| 2384 | reg = I915_READ(DSPFW3); |
| 2385 | reg &= ~(0x3f << 16); |
| 2386 | reg |= (wm & 0x3f) << 16; |
| 2387 | I915_WRITE(DSPFW3, reg); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2388 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2389 | |
| 2390 | /* activate cxsr */ |
| 2391 | reg = I915_READ(DSPFW3); |
| 2392 | reg |= IGD_SELF_REFRESH_EN; |
| 2393 | I915_WRITE(DSPFW3, reg); |
| 2394 | |
| 2395 | DRM_INFO("Big FIFO is enabled\n"); |
| 2396 | |
| 2397 | return; |
| 2398 | } |
| 2399 | |
Jesse Barnes | bcc24fb | 2009-08-31 10:24:31 -0700 | [diff] [blame] | 2400 | /* |
| 2401 | * Latency for FIFO fetches is dependent on several factors: |
| 2402 | * - memory configuration (speed, channels) |
| 2403 | * - chipset |
| 2404 | * - current MCH state |
| 2405 | * It can be fairly high in some situations, so here we assume a fairly |
| 2406 | * pessimal value. It's a tradeoff between extra memory fetches (if we |
| 2407 | * set this value too high, the FIFO will fetch frequently to stay full) |
| 2408 | * and power consumption (set it too low to save power and we might see |
| 2409 | * FIFO underruns and display "flicker"). |
| 2410 | * |
| 2411 | * A value of 5us seems to be a good balance; safe for very low end |
| 2412 | * platforms but not overly aggressive on lower latency configs. |
| 2413 | */ |
| 2414 | const static int latency_ns = 5000; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2415 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2416 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2417 | { |
| 2418 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2419 | uint32_t dsparb = I915_READ(DSPARB); |
| 2420 | int size; |
| 2421 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2422 | if (plane == 0) |
Jesse Barnes | f360132 | 2009-07-22 12:54:59 -0700 | [diff] [blame] | 2423 | size = dsparb & 0x7f; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2424 | else |
| 2425 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - |
| 2426 | (dsparb & 0x7f); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2427 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2428 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 2429 | plane ? "B" : "A", size); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2430 | |
| 2431 | return size; |
| 2432 | } |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2433 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2434 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
| 2435 | { |
| 2436 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2437 | uint32_t dsparb = I915_READ(DSPARB); |
| 2438 | int size; |
| 2439 | |
| 2440 | if (plane == 0) |
| 2441 | size = dsparb & 0x1ff; |
| 2442 | else |
| 2443 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - |
| 2444 | (dsparb & 0x1ff); |
| 2445 | size >>= 1; /* Convert to cachelines */ |
| 2446 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2447 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 2448 | plane ? "B" : "A", size); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2449 | |
| 2450 | return size; |
| 2451 | } |
| 2452 | |
| 2453 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
| 2454 | { |
| 2455 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2456 | uint32_t dsparb = I915_READ(DSPARB); |
| 2457 | int size; |
| 2458 | |
| 2459 | size = dsparb & 0x7f; |
| 2460 | size >>= 2; /* Convert to cachelines */ |
| 2461 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2462 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 2463 | plane ? "B" : "A", |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2464 | size); |
| 2465 | |
| 2466 | return size; |
| 2467 | } |
| 2468 | |
| 2469 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
| 2470 | { |
| 2471 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2472 | uint32_t dsparb = I915_READ(DSPARB); |
| 2473 | int size; |
| 2474 | |
| 2475 | size = dsparb & 0x7f; |
| 2476 | size >>= 1; /* Convert to cachelines */ |
| 2477 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2478 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 2479 | plane ? "B" : "A", size); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2480 | |
| 2481 | return size; |
| 2482 | } |
| 2483 | |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2484 | static void g4x_update_wm(struct drm_device *dev, int planea_clock, |
| 2485 | int planeb_clock, int sr_hdisplay, int pixel_size) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2486 | { |
| 2487 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2488 | int total_size, cacheline_size; |
| 2489 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr; |
| 2490 | struct intel_watermark_params planea_params, planeb_params; |
| 2491 | unsigned long line_time_us; |
| 2492 | int sr_clock, sr_entries = 0, entries_required; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2493 | |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2494 | /* Create copies of the base settings for each pipe */ |
| 2495 | planea_params = planeb_params = g4x_wm_info; |
| 2496 | |
| 2497 | /* Grab a couple of global values before we overwrite them */ |
| 2498 | total_size = planea_params.fifo_size; |
| 2499 | cacheline_size = planea_params.cacheline_size; |
| 2500 | |
| 2501 | /* |
| 2502 | * Note: we need to make sure we don't overflow for various clock & |
| 2503 | * latency values. |
| 2504 | * clocks go from a few thousand to several hundred thousand. |
| 2505 | * latency is usually a few thousand |
| 2506 | */ |
| 2507 | entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) / |
| 2508 | 1000; |
| 2509 | entries_required /= G4X_FIFO_LINE_SIZE; |
| 2510 | planea_wm = entries_required + planea_params.guard_size; |
| 2511 | |
| 2512 | entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) / |
| 2513 | 1000; |
| 2514 | entries_required /= G4X_FIFO_LINE_SIZE; |
| 2515 | planeb_wm = entries_required + planeb_params.guard_size; |
| 2516 | |
| 2517 | cursora_wm = cursorb_wm = 16; |
| 2518 | cursor_sr = 32; |
| 2519 | |
| 2520 | DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
| 2521 | |
| 2522 | /* Calc sr entries for one plane configs */ |
| 2523 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { |
| 2524 | /* self-refresh has much higher latency */ |
| 2525 | const static int sr_latency_ns = 12000; |
| 2526 | |
| 2527 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
| 2528 | line_time_us = ((sr_hdisplay * 1000) / sr_clock); |
| 2529 | |
| 2530 | /* Use ns/us then divide to preserve precision */ |
| 2531 | sr_entries = (((sr_latency_ns / line_time_us) + 1) * |
| 2532 | pixel_size * sr_hdisplay) / 1000; |
| 2533 | sr_entries = roundup(sr_entries / cacheline_size, 1); |
| 2534 | DRM_DEBUG("self-refresh entries: %d\n", sr_entries); |
| 2535 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
| 2536 | } |
| 2537 | |
| 2538 | DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", |
| 2539 | planea_wm, planeb_wm, sr_entries); |
| 2540 | |
| 2541 | planea_wm &= 0x3f; |
| 2542 | planeb_wm &= 0x3f; |
| 2543 | |
| 2544 | I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) | |
| 2545 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
| 2546 | (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm); |
| 2547 | I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | |
| 2548 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
| 2549 | /* HPLL off in SR has some issues on G4x... disable it */ |
| 2550 | I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | |
| 2551 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2552 | } |
| 2553 | |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 2554 | static void i965_update_wm(struct drm_device *dev, int planea_clock, |
| 2555 | int planeb_clock, int sr_hdisplay, int pixel_size) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2556 | { |
| 2557 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 2558 | unsigned long line_time_us; |
| 2559 | int sr_clock, sr_entries, srwm = 1; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2560 | |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 2561 | /* Calc sr entries for one plane configs */ |
| 2562 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { |
| 2563 | /* self-refresh has much higher latency */ |
| 2564 | const static int sr_latency_ns = 12000; |
| 2565 | |
| 2566 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
| 2567 | line_time_us = ((sr_hdisplay * 1000) / sr_clock); |
| 2568 | |
| 2569 | /* Use ns/us then divide to preserve precision */ |
| 2570 | sr_entries = (((sr_latency_ns / line_time_us) + 1) * |
| 2571 | pixel_size * sr_hdisplay) / 1000; |
| 2572 | sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1); |
| 2573 | DRM_DEBUG("self-refresh entries: %d\n", sr_entries); |
| 2574 | srwm = I945_FIFO_SIZE - sr_entries; |
| 2575 | if (srwm < 0) |
| 2576 | srwm = 1; |
| 2577 | srwm &= 0x3f; |
| 2578 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
| 2579 | } |
| 2580 | |
| 2581 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
| 2582 | srwm); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2583 | |
| 2584 | /* 965 has limitations... */ |
Jesse Barnes | 1dc7546 | 2009-10-19 10:08:17 +0900 | [diff] [blame] | 2585 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) | |
| 2586 | (8 << 0)); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2587 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
| 2588 | } |
| 2589 | |
| 2590 | static void i9xx_update_wm(struct drm_device *dev, int planea_clock, |
| 2591 | int planeb_clock, int sr_hdisplay, int pixel_size) |
| 2592 | { |
| 2593 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2594 | uint32_t fwater_lo; |
| 2595 | uint32_t fwater_hi; |
| 2596 | int total_size, cacheline_size, cwm, srwm = 1; |
| 2597 | int planea_wm, planeb_wm; |
| 2598 | struct intel_watermark_params planea_params, planeb_params; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2599 | unsigned long line_time_us; |
| 2600 | int sr_clock, sr_entries = 0; |
| 2601 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2602 | /* Create copies of the base settings for each pipe */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2603 | if (IS_I965GM(dev) || IS_I945GM(dev)) |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2604 | planea_params = planeb_params = i945_wm_info; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2605 | else if (IS_I9XX(dev)) |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2606 | planea_params = planeb_params = i915_wm_info; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2607 | else |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2608 | planea_params = planeb_params = i855_wm_info; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2609 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2610 | /* Grab a couple of global values before we overwrite them */ |
| 2611 | total_size = planea_params.fifo_size; |
| 2612 | cacheline_size = planea_params.cacheline_size; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2613 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2614 | /* Update per-plane FIFO sizes */ |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2615 | planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
| 2616 | planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2617 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2618 | planea_wm = intel_calculate_wm(planea_clock, &planea_params, |
| 2619 | pixel_size, latency_ns); |
| 2620 | planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params, |
| 2621 | pixel_size, latency_ns); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2622 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2623 | |
| 2624 | /* |
| 2625 | * Overlay gets an aggressive default since video jitter is bad. |
| 2626 | */ |
| 2627 | cwm = 2; |
| 2628 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2629 | /* Calc sr entries for one plane configs */ |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2630 | if (HAS_FW_BLC(dev) && sr_hdisplay && |
| 2631 | (!planea_clock || !planeb_clock)) { |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2632 | /* self-refresh has much higher latency */ |
| 2633 | const static int sr_latency_ns = 6000; |
| 2634 | |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2635 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2636 | line_time_us = ((sr_hdisplay * 1000) / sr_clock); |
| 2637 | |
| 2638 | /* Use ns/us then divide to preserve precision */ |
| 2639 | sr_entries = (((sr_latency_ns / line_time_us) + 1) * |
| 2640 | pixel_size * sr_hdisplay) / 1000; |
| 2641 | sr_entries = roundup(sr_entries / cacheline_size, 1); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2642 | DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries); |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2643 | srwm = total_size - sr_entries; |
| 2644 | if (srwm < 0) |
| 2645 | srwm = 1; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2646 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2647 | } |
| 2648 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2649 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2650 | planea_wm, planeb_wm, cwm, srwm); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2651 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2652 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
| 2653 | fwater_hi = (cwm & 0x1f); |
| 2654 | |
| 2655 | /* Set request length to 8 cachelines per fetch */ |
| 2656 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); |
| 2657 | fwater_hi = fwater_hi | (1 << 8); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2658 | |
| 2659 | I915_WRITE(FW_BLC, fwater_lo); |
| 2660 | I915_WRITE(FW_BLC2, fwater_hi); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2661 | } |
| 2662 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2663 | static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused, |
| 2664 | int unused2, int pixel_size) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2665 | { |
| 2666 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | f360132 | 2009-07-22 12:54:59 -0700 | [diff] [blame] | 2667 | uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2668 | int planea_wm; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2669 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2670 | i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2671 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2672 | planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info, |
| 2673 | pixel_size, latency_ns); |
Jesse Barnes | f360132 | 2009-07-22 12:54:59 -0700 | [diff] [blame] | 2674 | fwater_lo |= (3<<8) | planea_wm; |
| 2675 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2676 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2677 | |
| 2678 | I915_WRITE(FW_BLC, fwater_lo); |
| 2679 | } |
| 2680 | |
| 2681 | /** |
| 2682 | * intel_update_watermarks - update FIFO watermark values based on current modes |
| 2683 | * |
| 2684 | * Calculate watermark values for the various WM regs based on current mode |
| 2685 | * and plane configuration. |
| 2686 | * |
| 2687 | * There are several cases to deal with here: |
| 2688 | * - normal (i.e. non-self-refresh) |
| 2689 | * - self-refresh (SR) mode |
| 2690 | * - lines are large relative to FIFO size (buffer can hold up to 2) |
| 2691 | * - lines are small relative to FIFO size (buffer can hold more than 2 |
| 2692 | * lines), so need to account for TLB latency |
| 2693 | * |
| 2694 | * The normal calculation is: |
| 2695 | * watermark = dotclock * bytes per pixel * latency |
| 2696 | * where latency is platform & configuration dependent (we assume pessimal |
| 2697 | * values here). |
| 2698 | * |
| 2699 | * The SR calculation is: |
| 2700 | * watermark = (trunc(latency/line time)+1) * surface width * |
| 2701 | * bytes per pixel |
| 2702 | * where |
| 2703 | * line time = htotal / dotclock |
| 2704 | * and latency is assumed to be high, as above. |
| 2705 | * |
| 2706 | * The final value programmed to the register should always be rounded up, |
| 2707 | * and include an extra 2 entries to account for clock crossings. |
| 2708 | * |
| 2709 | * We don't use the sprite, so we can ignore that. And on Crestline we have |
| 2710 | * to set the non-SR watermarks to 8. |
| 2711 | */ |
| 2712 | static void intel_update_watermarks(struct drm_device *dev) |
| 2713 | { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2714 | struct drm_i915_private *dev_priv = dev->dev_private; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2715 | struct drm_crtc *crtc; |
| 2716 | struct intel_crtc *intel_crtc; |
| 2717 | int sr_hdisplay = 0; |
| 2718 | unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; |
| 2719 | int enabled = 0, pixel_size = 0; |
| 2720 | |
Zhenyu Wang | c03342f | 2009-09-29 11:01:23 +0800 | [diff] [blame] | 2721 | if (!dev_priv->display.update_wm) |
| 2722 | return; |
| 2723 | |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2724 | /* Get the clock config from both planes */ |
| 2725 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 2726 | intel_crtc = to_intel_crtc(crtc); |
| 2727 | if (crtc->enabled) { |
| 2728 | enabled++; |
| 2729 | if (intel_crtc->plane == 0) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2730 | DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n", |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2731 | intel_crtc->pipe, crtc->mode.clock); |
| 2732 | planea_clock = crtc->mode.clock; |
| 2733 | } else { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2734 | DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n", |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2735 | intel_crtc->pipe, crtc->mode.clock); |
| 2736 | planeb_clock = crtc->mode.clock; |
| 2737 | } |
| 2738 | sr_hdisplay = crtc->mode.hdisplay; |
| 2739 | sr_clock = crtc->mode.clock; |
| 2740 | if (crtc->fb) |
| 2741 | pixel_size = crtc->fb->bits_per_pixel / 8; |
| 2742 | else |
| 2743 | pixel_size = 4; /* by default */ |
| 2744 | } |
| 2745 | } |
| 2746 | |
| 2747 | if (enabled <= 0) |
| 2748 | return; |
| 2749 | |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2750 | /* Single plane configs can enable self refresh */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2751 | if (enabled == 1 && IS_IGD(dev)) |
| 2752 | igd_enable_cxsr(dev, sr_clock, pixel_size); |
| 2753 | else if (IS_IGD(dev)) |
| 2754 | igd_disable_cxsr(dev); |
| 2755 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 2756 | dev_priv->display.update_wm(dev, planea_clock, planeb_clock, |
| 2757 | sr_hdisplay, pixel_size); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2758 | } |
| 2759 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2760 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
| 2761 | struct drm_display_mode *mode, |
| 2762 | struct drm_display_mode *adjusted_mode, |
| 2763 | int x, int y, |
| 2764 | struct drm_framebuffer *old_fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2765 | { |
| 2766 | struct drm_device *dev = crtc->dev; |
| 2767 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2768 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2769 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 2770 | int plane = intel_crtc->plane; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2771 | int fp_reg = (pipe == 0) ? FPA0 : FPB0; |
| 2772 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; |
| 2773 | int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 2774 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2775 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
| 2776 | int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; |
| 2777 | int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; |
| 2778 | int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; |
| 2779 | int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; |
| 2780 | int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; |
| 2781 | int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 2782 | int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE; |
| 2783 | int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2784 | int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 2785 | int refclk, num_outputs = 0; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2786 | intel_clock_t clock, reduced_clock; |
| 2787 | u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf; |
| 2788 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2789 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2790 | bool is_edp = false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2791 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 2792 | struct drm_connector *connector; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 2793 | const intel_limit_t *limit; |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2794 | int ret; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2795 | struct fdi_m_n m_n = {0}; |
| 2796 | int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1; |
| 2797 | int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1; |
| 2798 | int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1; |
| 2799 | int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1; |
| 2800 | int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0; |
| 2801 | int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; |
| 2802 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; |
Zhenyu Wang | 541998a | 2009-06-05 15:38:44 +0800 | [diff] [blame] | 2803 | int lvds_reg = LVDS; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2804 | u32 temp; |
| 2805 | int sdvo_pixel_multiply; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2806 | int target_clock; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2807 | |
| 2808 | drm_vblank_pre_modeset(dev, pipe); |
| 2809 | |
| 2810 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 2811 | struct intel_output *intel_output = to_intel_output(connector); |
| 2812 | |
| 2813 | if (!connector->encoder || connector->encoder->crtc != crtc) |
| 2814 | continue; |
| 2815 | |
| 2816 | switch (intel_output->type) { |
| 2817 | case INTEL_OUTPUT_LVDS: |
| 2818 | is_lvds = true; |
| 2819 | break; |
| 2820 | case INTEL_OUTPUT_SDVO: |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2821 | case INTEL_OUTPUT_HDMI: |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2822 | is_sdvo = true; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2823 | if (intel_output->needs_tv_clock) |
| 2824 | is_tv = true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2825 | break; |
| 2826 | case INTEL_OUTPUT_DVO: |
| 2827 | is_dvo = true; |
| 2828 | break; |
| 2829 | case INTEL_OUTPUT_TVOUT: |
| 2830 | is_tv = true; |
| 2831 | break; |
| 2832 | case INTEL_OUTPUT_ANALOG: |
| 2833 | is_crt = true; |
| 2834 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2835 | case INTEL_OUTPUT_DISPLAYPORT: |
| 2836 | is_dp = true; |
| 2837 | break; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2838 | case INTEL_OUTPUT_EDP: |
| 2839 | is_edp = true; |
| 2840 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2841 | } |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 2842 | |
| 2843 | num_outputs++; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2844 | } |
| 2845 | |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 2846 | if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) { |
| 2847 | refclk = dev_priv->lvds_ssc_freq * 1000; |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2848 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
| 2849 | refclk / 1000); |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 2850 | } else if (IS_I9XX(dev)) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2851 | refclk = 96000; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2852 | if (IS_IGDNG(dev)) |
| 2853 | refclk = 120000; /* 120Mhz refclk */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2854 | } else { |
| 2855 | refclk = 48000; |
| 2856 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2857 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2858 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 2859 | /* |
| 2860 | * Returns a set of divisors for the desired target clock with the given |
| 2861 | * refclk, or FALSE. The returned values represent the clock equation: |
| 2862 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 2863 | */ |
| 2864 | limit = intel_limit(crtc); |
| 2865 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2866 | if (!ok) { |
| 2867 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
Chris Wilson | 1f803ee | 2009-06-06 09:45:59 +0100 | [diff] [blame] | 2868 | drm_vblank_post_modeset(dev, pipe); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2869 | return -EINVAL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2870 | } |
| 2871 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2872 | if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) { |
| 2873 | memcpy(&reduced_clock, &clock, sizeof(intel_clock_t)); |
| 2874 | has_reduced_clock = limit->find_reduced_pll(limit, crtc, |
| 2875 | (adjusted_mode->clock*3/4), |
| 2876 | refclk, |
| 2877 | &reduced_clock); |
| 2878 | } |
| 2879 | |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 2880 | /* SDVO TV has fixed PLL values depend on its clock range, |
| 2881 | this mirrors vbios setting. */ |
| 2882 | if (is_sdvo && is_tv) { |
| 2883 | if (adjusted_mode->clock >= 100000 |
| 2884 | && adjusted_mode->clock < 140500) { |
| 2885 | clock.p1 = 2; |
| 2886 | clock.p2 = 10; |
| 2887 | clock.n = 3; |
| 2888 | clock.m1 = 16; |
| 2889 | clock.m2 = 8; |
| 2890 | } else if (adjusted_mode->clock >= 140500 |
| 2891 | && adjusted_mode->clock <= 200000) { |
| 2892 | clock.p1 = 1; |
| 2893 | clock.p2 = 10; |
| 2894 | clock.n = 6; |
| 2895 | clock.m1 = 12; |
| 2896 | clock.m2 = 8; |
| 2897 | } |
| 2898 | } |
| 2899 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2900 | /* FDI link */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2901 | if (IS_IGDNG(dev)) { |
Zhenyu Wang | 58a2747 | 2009-09-25 08:01:28 +0000 | [diff] [blame] | 2902 | int lane, link_bw, bpp; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2903 | /* eDP doesn't require FDI link, so just set DP M/N |
| 2904 | according to current link config */ |
| 2905 | if (is_edp) { |
| 2906 | struct drm_connector *edp; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2907 | target_clock = mode->clock; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2908 | edp = intel_pipe_get_output(crtc); |
| 2909 | intel_edp_link_config(to_intel_output(edp), |
| 2910 | &lane, &link_bw); |
| 2911 | } else { |
| 2912 | /* DP over FDI requires target mode clock |
| 2913 | instead of link clock */ |
| 2914 | if (is_dp) |
| 2915 | target_clock = mode->clock; |
| 2916 | else |
| 2917 | target_clock = adjusted_mode->clock; |
| 2918 | lane = 4; |
| 2919 | link_bw = 270000; |
| 2920 | } |
Zhenyu Wang | 58a2747 | 2009-09-25 08:01:28 +0000 | [diff] [blame] | 2921 | |
| 2922 | /* determine panel color depth */ |
| 2923 | temp = I915_READ(pipeconf_reg); |
| 2924 | |
| 2925 | switch (temp & PIPE_BPC_MASK) { |
| 2926 | case PIPE_8BPC: |
| 2927 | bpp = 24; |
| 2928 | break; |
| 2929 | case PIPE_10BPC: |
| 2930 | bpp = 30; |
| 2931 | break; |
| 2932 | case PIPE_6BPC: |
| 2933 | bpp = 18; |
| 2934 | break; |
| 2935 | case PIPE_12BPC: |
| 2936 | bpp = 36; |
| 2937 | break; |
| 2938 | default: |
| 2939 | DRM_ERROR("unknown pipe bpc value\n"); |
| 2940 | bpp = 24; |
| 2941 | } |
| 2942 | |
| 2943 | igdng_compute_m_n(bpp, lane, target_clock, |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2944 | link_bw, &m_n); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2945 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2946 | |
Zhenyu Wang | c038e51 | 2009-10-19 15:43:48 +0800 | [diff] [blame] | 2947 | /* Ironlake: try to setup display ref clock before DPLL |
| 2948 | * enabling. This is only under driver's control after |
| 2949 | * PCH B stepping, previous chipset stepping should be |
| 2950 | * ignoring this setting. |
| 2951 | */ |
| 2952 | if (IS_IGDNG(dev)) { |
| 2953 | temp = I915_READ(PCH_DREF_CONTROL); |
| 2954 | /* Always enable nonspread source */ |
| 2955 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; |
| 2956 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; |
| 2957 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 2958 | POSTING_READ(PCH_DREF_CONTROL); |
| 2959 | |
| 2960 | temp &= ~DREF_SSC_SOURCE_MASK; |
| 2961 | temp |= DREF_SSC_SOURCE_ENABLE; |
| 2962 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 2963 | POSTING_READ(PCH_DREF_CONTROL); |
| 2964 | |
| 2965 | udelay(200); |
| 2966 | |
| 2967 | if (is_edp) { |
| 2968 | if (dev_priv->lvds_use_ssc) { |
| 2969 | temp |= DREF_SSC1_ENABLE; |
| 2970 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 2971 | POSTING_READ(PCH_DREF_CONTROL); |
| 2972 | |
| 2973 | udelay(200); |
| 2974 | |
| 2975 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
| 2976 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
| 2977 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 2978 | POSTING_READ(PCH_DREF_CONTROL); |
| 2979 | } else { |
| 2980 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
| 2981 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 2982 | POSTING_READ(PCH_DREF_CONTROL); |
| 2983 | } |
| 2984 | } |
| 2985 | } |
| 2986 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2987 | if (IS_IGD(dev)) { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 2988 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2989 | if (has_reduced_clock) |
| 2990 | fp2 = (1 << reduced_clock.n) << 16 | |
| 2991 | reduced_clock.m1 << 8 | reduced_clock.m2; |
| 2992 | } else { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 2993 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2994 | if (has_reduced_clock) |
| 2995 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | |
| 2996 | reduced_clock.m2; |
| 2997 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2998 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2999 | if (!IS_IGDNG(dev)) |
| 3000 | dpll = DPLL_VGA_MODE_DIS; |
| 3001 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3002 | if (IS_I9XX(dev)) { |
| 3003 | if (is_lvds) |
| 3004 | dpll |= DPLLB_MODE_LVDS; |
| 3005 | else |
| 3006 | dpll |= DPLLB_MODE_DAC_SERIAL; |
| 3007 | if (is_sdvo) { |
| 3008 | dpll |= DPLL_DVO_HIGH_SPEED; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3009 | sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; |
Sean Young | 942642a | 2009-08-06 17:35:50 +0800 | [diff] [blame] | 3010 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3011 | dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3012 | else if (IS_IGDNG(dev)) |
| 3013 | dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3014 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3015 | if (is_dp) |
| 3016 | dpll |= DPLL_DVO_HIGH_SPEED; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3017 | |
| 3018 | /* compute bitmask from p1 value */ |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 3019 | if (IS_IGD(dev)) |
| 3020 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3021 | else { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 3022 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3023 | /* also FPA1 */ |
| 3024 | if (IS_IGDNG(dev)) |
| 3025 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3026 | if (IS_G4X(dev) && has_reduced_clock) |
| 3027 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3028 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3029 | switch (clock.p2) { |
| 3030 | case 5: |
| 3031 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 3032 | break; |
| 3033 | case 7: |
| 3034 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 3035 | break; |
| 3036 | case 10: |
| 3037 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 3038 | break; |
| 3039 | case 14: |
| 3040 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 3041 | break; |
| 3042 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3043 | if (IS_I965G(dev) && !IS_IGDNG(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3044 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
| 3045 | } else { |
| 3046 | if (is_lvds) { |
| 3047 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 3048 | } else { |
| 3049 | if (clock.p1 == 2) |
| 3050 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
| 3051 | else |
| 3052 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 3053 | if (clock.p2 == 4) |
| 3054 | dpll |= PLL_P2_DIVIDE_BY_4; |
| 3055 | } |
| 3056 | } |
| 3057 | |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 3058 | if (is_sdvo && is_tv) |
| 3059 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
| 3060 | else if (is_tv) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3061 | /* XXX: just matching BIOS for now */ |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 3062 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3063 | dpll |= 3; |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 3064 | else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) |
| 3065 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3066 | else |
| 3067 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 3068 | |
| 3069 | /* setup pipeconf */ |
| 3070 | pipeconf = I915_READ(pipeconf_reg); |
| 3071 | |
| 3072 | /* Set up the display plane register */ |
| 3073 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 3074 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3075 | /* IGDNG's plane is forced to pipe, bit 24 is to |
| 3076 | enable color space conversion */ |
| 3077 | if (!IS_IGDNG(dev)) { |
| 3078 | if (pipe == 0) |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 3079 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3080 | else |
| 3081 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
| 3082 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3083 | |
| 3084 | if (pipe == 0 && !IS_I965G(dev)) { |
| 3085 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
| 3086 | * core speed. |
| 3087 | * |
| 3088 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the |
| 3089 | * pipe == 0 check? |
| 3090 | */ |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3091 | if (mode->clock > |
| 3092 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3093 | pipeconf |= PIPEACONF_DOUBLE_WIDE; |
| 3094 | else |
| 3095 | pipeconf &= ~PIPEACONF_DOUBLE_WIDE; |
| 3096 | } |
| 3097 | |
| 3098 | dspcntr |= DISPLAY_PLANE_ENABLE; |
| 3099 | pipeconf |= PIPEACONF_ENABLE; |
| 3100 | dpll |= DPLL_VCO_ENABLE; |
| 3101 | |
| 3102 | |
| 3103 | /* Disable the panel fitter if it was on our pipe */ |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3104 | if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3105 | I915_WRITE(PFIT_CONTROL, 0); |
| 3106 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3107 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3108 | drm_mode_debug_printmodeline(mode); |
| 3109 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3110 | /* assign to IGDNG registers */ |
| 3111 | if (IS_IGDNG(dev)) { |
| 3112 | fp_reg = pch_fp_reg; |
| 3113 | dpll_reg = pch_dpll_reg; |
| 3114 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3115 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3116 | if (is_edp) { |
| 3117 | igdng_disable_pll_edp(crtc); |
| 3118 | } else if ((dpll & DPLL_VCO_ENABLE)) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3119 | I915_WRITE(fp_reg, fp); |
| 3120 | I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); |
| 3121 | I915_READ(dpll_reg); |
| 3122 | udelay(150); |
| 3123 | } |
| 3124 | |
| 3125 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
| 3126 | * This is an exception to the general rule that mode_set doesn't turn |
| 3127 | * things on. |
| 3128 | */ |
| 3129 | if (is_lvds) { |
Zhenyu Wang | 541998a | 2009-06-05 15:38:44 +0800 | [diff] [blame] | 3130 | u32 lvds; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3131 | |
Zhenyu Wang | 541998a | 2009-06-05 15:38:44 +0800 | [diff] [blame] | 3132 | if (IS_IGDNG(dev)) |
| 3133 | lvds_reg = PCH_LVDS; |
| 3134 | |
| 3135 | lvds = I915_READ(lvds_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3136 | lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT; |
Zhao Yakui | a3e17eb | 2009-10-10 10:42:37 +0800 | [diff] [blame] | 3137 | /* set the corresponsding LVDS_BORDER bit */ |
| 3138 | lvds |= dev_priv->lvds_border_bits; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3139 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
| 3140 | * set the DPLLs for dual-channel mode or not. |
| 3141 | */ |
| 3142 | if (clock.p2 == 7) |
| 3143 | lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
| 3144 | else |
| 3145 | lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
| 3146 | |
| 3147 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
| 3148 | * appropriately here, but we need to look more thoroughly into how |
| 3149 | * panels behave in the two modes. |
| 3150 | */ |
| 3151 | |
Zhenyu Wang | 541998a | 2009-06-05 15:38:44 +0800 | [diff] [blame] | 3152 | I915_WRITE(lvds_reg, lvds); |
| 3153 | I915_READ(lvds_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3154 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3155 | if (is_dp) |
| 3156 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3157 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3158 | if (!is_edp) { |
| 3159 | I915_WRITE(fp_reg, fp); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3160 | I915_WRITE(dpll_reg, dpll); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3161 | I915_READ(dpll_reg); |
| 3162 | /* Wait for the clocks to stabilize. */ |
| 3163 | udelay(150); |
| 3164 | |
| 3165 | if (IS_I965G(dev) && !IS_IGDNG(dev)) { |
Zhao Yakui | bb66c51 | 2009-09-10 15:45:49 +0800 | [diff] [blame] | 3166 | if (is_sdvo) { |
| 3167 | sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; |
| 3168 | I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3169 | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); |
Zhao Yakui | bb66c51 | 2009-09-10 15:45:49 +0800 | [diff] [blame] | 3170 | } else |
| 3171 | I915_WRITE(dpll_md_reg, 0); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3172 | } else { |
| 3173 | /* write it again -- the BIOS does, after all */ |
| 3174 | I915_WRITE(dpll_reg, dpll); |
| 3175 | } |
| 3176 | I915_READ(dpll_reg); |
| 3177 | /* Wait for the clocks to stabilize. */ |
| 3178 | udelay(150); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3179 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3180 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3181 | if (is_lvds && has_reduced_clock && i915_powersave) { |
| 3182 | I915_WRITE(fp_reg + 4, fp2); |
| 3183 | intel_crtc->lowfreq_avail = true; |
| 3184 | if (HAS_PIPE_CXSR(dev)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3185 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3186 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
| 3187 | } |
| 3188 | } else { |
| 3189 | I915_WRITE(fp_reg + 4, fp); |
| 3190 | intel_crtc->lowfreq_avail = false; |
| 3191 | if (HAS_PIPE_CXSR(dev)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3192 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3193 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
| 3194 | } |
| 3195 | } |
| 3196 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3197 | I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | |
| 3198 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
| 3199 | I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | |
| 3200 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
| 3201 | I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | |
| 3202 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
| 3203 | I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | |
| 3204 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
| 3205 | I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | |
| 3206 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
| 3207 | I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | |
| 3208 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
| 3209 | /* pipesrc and dspsize control the size that is scaled from, which should |
| 3210 | * always be the user's requested size. |
| 3211 | */ |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3212 | if (!IS_IGDNG(dev)) { |
| 3213 | I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | |
| 3214 | (mode->hdisplay - 1)); |
| 3215 | I915_WRITE(dsppos_reg, 0); |
| 3216 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3217 | I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3218 | |
| 3219 | if (IS_IGDNG(dev)) { |
| 3220 | I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m); |
| 3221 | I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n); |
| 3222 | I915_WRITE(link_m1_reg, m_n.link_m); |
| 3223 | I915_WRITE(link_n1_reg, m_n.link_n); |
| 3224 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3225 | if (is_edp) { |
| 3226 | igdng_set_pll_edp(crtc, adjusted_mode->clock); |
| 3227 | } else { |
| 3228 | /* enable FDI RX PLL too */ |
| 3229 | temp = I915_READ(fdi_rx_reg); |
| 3230 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE); |
| 3231 | udelay(200); |
| 3232 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3233 | } |
| 3234 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3235 | I915_WRITE(pipeconf_reg, pipeconf); |
| 3236 | I915_READ(pipeconf_reg); |
| 3237 | |
| 3238 | intel_wait_for_vblank(dev); |
| 3239 | |
Zhenyu Wang | 553bd14 | 2009-09-02 10:57:52 +0800 | [diff] [blame] | 3240 | if (IS_IGDNG(dev)) { |
| 3241 | /* enable address swizzle for tiling buffer */ |
| 3242 | temp = I915_READ(DISP_ARB_CTL); |
| 3243 | I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); |
| 3244 | } |
| 3245 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3246 | I915_WRITE(dspcntr_reg, dspcntr); |
| 3247 | |
| 3248 | /* Flush the plane changes */ |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 3249 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3250 | |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 3251 | if ((IS_I965G(dev) || plane == 0)) |
| 3252 | intel_update_fbc(crtc, &crtc->mode); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3253 | |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 3254 | intel_update_watermarks(dev); |
| 3255 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3256 | drm_vblank_post_modeset(dev, pipe); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 3257 | |
Chris Wilson | 1f803ee | 2009-06-06 09:45:59 +0100 | [diff] [blame] | 3258 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3259 | } |
| 3260 | |
| 3261 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
| 3262 | void intel_crtc_load_lut(struct drm_crtc *crtc) |
| 3263 | { |
| 3264 | struct drm_device *dev = crtc->dev; |
| 3265 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3266 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3267 | int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; |
| 3268 | int i; |
| 3269 | |
| 3270 | /* The clocks have to be on to load the palette. */ |
| 3271 | if (!crtc->enabled) |
| 3272 | return; |
| 3273 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3274 | /* use legacy palette for IGDNG */ |
| 3275 | if (IS_IGDNG(dev)) |
| 3276 | palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : |
| 3277 | LGC_PALETTE_B; |
| 3278 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3279 | for (i = 0; i < 256; i++) { |
| 3280 | I915_WRITE(palreg + 4 * i, |
| 3281 | (intel_crtc->lut_r[i] << 16) | |
| 3282 | (intel_crtc->lut_g[i] << 8) | |
| 3283 | intel_crtc->lut_b[i]); |
| 3284 | } |
| 3285 | } |
| 3286 | |
| 3287 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
| 3288 | struct drm_file *file_priv, |
| 3289 | uint32_t handle, |
| 3290 | uint32_t width, uint32_t height) |
| 3291 | { |
| 3292 | struct drm_device *dev = crtc->dev; |
| 3293 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3294 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3295 | struct drm_gem_object *bo; |
| 3296 | struct drm_i915_gem_object *obj_priv; |
| 3297 | int pipe = intel_crtc->pipe; |
| 3298 | uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; |
| 3299 | uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 3300 | uint32_t temp = I915_READ(control); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3301 | size_t addr; |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 3302 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3303 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3304 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3305 | |
| 3306 | /* if we want to turn off the cursor ignore width and height */ |
| 3307 | if (!handle) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3308 | DRM_DEBUG_KMS("cursor off\n"); |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 3309 | if (IS_MOBILE(dev) || IS_I9XX(dev)) { |
| 3310 | temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
| 3311 | temp |= CURSOR_MODE_DISABLE; |
| 3312 | } else { |
| 3313 | temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
| 3314 | } |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 3315 | addr = 0; |
| 3316 | bo = NULL; |
Pierre Willenbrock | 5004417 | 2009-02-23 10:12:15 +1000 | [diff] [blame] | 3317 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 3318 | goto finish; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3319 | } |
| 3320 | |
| 3321 | /* Currently we only support 64x64 cursors */ |
| 3322 | if (width != 64 || height != 64) { |
| 3323 | DRM_ERROR("we currently only support 64x64 cursors\n"); |
| 3324 | return -EINVAL; |
| 3325 | } |
| 3326 | |
| 3327 | bo = drm_gem_object_lookup(dev, file_priv, handle); |
| 3328 | if (!bo) |
| 3329 | return -ENOENT; |
| 3330 | |
| 3331 | obj_priv = bo->driver_private; |
| 3332 | |
| 3333 | if (bo->size < width * height * 4) { |
| 3334 | DRM_ERROR("buffer is to small\n"); |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 3335 | ret = -ENOMEM; |
| 3336 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3337 | } |
| 3338 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3339 | /* we only need to pin inside GTT if cursor is non-phy */ |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 3340 | mutex_lock(&dev->struct_mutex); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3341 | if (!dev_priv->cursor_needs_physical) { |
| 3342 | ret = i915_gem_object_pin(bo, PAGE_SIZE); |
| 3343 | if (ret) { |
| 3344 | DRM_ERROR("failed to pin cursor bo\n"); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 3345 | goto fail_locked; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3346 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3347 | addr = obj_priv->gtt_offset; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3348 | } else { |
| 3349 | ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1); |
| 3350 | if (ret) { |
| 3351 | DRM_ERROR("failed to attach phys object\n"); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 3352 | goto fail_locked; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3353 | } |
| 3354 | addr = obj_priv->phys_obj->handle->busaddr; |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 3355 | } |
| 3356 | |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 3357 | if (!IS_I9XX(dev)) |
| 3358 | I915_WRITE(CURSIZE, (height << 12) | width); |
| 3359 | |
| 3360 | /* Hooray for CUR*CNTR differences */ |
| 3361 | if (IS_MOBILE(dev) || IS_I9XX(dev)) { |
| 3362 | temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
| 3363 | temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
| 3364 | temp |= (pipe << 28); /* Connect to correct pipe */ |
| 3365 | } else { |
| 3366 | temp &= ~(CURSOR_FORMAT_MASK); |
| 3367 | temp |= CURSOR_ENABLE; |
| 3368 | temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE; |
| 3369 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3370 | |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 3371 | finish: |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3372 | I915_WRITE(control, temp); |
| 3373 | I915_WRITE(base, addr); |
| 3374 | |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 3375 | if (intel_crtc->cursor_bo) { |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3376 | if (dev_priv->cursor_needs_physical) { |
| 3377 | if (intel_crtc->cursor_bo != bo) |
| 3378 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
| 3379 | } else |
| 3380 | i915_gem_object_unpin(intel_crtc->cursor_bo); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 3381 | drm_gem_object_unreference(intel_crtc->cursor_bo); |
| 3382 | } |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 3383 | |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 3384 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 3385 | |
| 3386 | intel_crtc->cursor_addr = addr; |
| 3387 | intel_crtc->cursor_bo = bo; |
| 3388 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3389 | return 0; |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 3390 | fail: |
| 3391 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 3392 | fail_locked: |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 3393 | drm_gem_object_unreference(bo); |
| 3394 | mutex_unlock(&dev->struct_mutex); |
| 3395 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3396 | } |
| 3397 | |
| 3398 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
| 3399 | { |
| 3400 | struct drm_device *dev = crtc->dev; |
| 3401 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3402 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3403 | struct intel_framebuffer *intel_fb; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3404 | int pipe = intel_crtc->pipe; |
| 3405 | uint32_t temp = 0; |
| 3406 | uint32_t adder; |
| 3407 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3408 | if (crtc->fb) { |
| 3409 | intel_fb = to_intel_framebuffer(crtc->fb); |
| 3410 | intel_mark_busy(dev, intel_fb->obj); |
| 3411 | } |
| 3412 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3413 | if (x < 0) { |
Keith Packard | 2245fda | 2009-05-30 20:42:29 -0700 | [diff] [blame] | 3414 | temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3415 | x = -x; |
| 3416 | } |
| 3417 | if (y < 0) { |
Keith Packard | 2245fda | 2009-05-30 20:42:29 -0700 | [diff] [blame] | 3418 | temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3419 | y = -y; |
| 3420 | } |
| 3421 | |
Keith Packard | 2245fda | 2009-05-30 20:42:29 -0700 | [diff] [blame] | 3422 | temp |= x << CURSOR_X_SHIFT; |
| 3423 | temp |= y << CURSOR_Y_SHIFT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3424 | |
| 3425 | adder = intel_crtc->cursor_addr; |
| 3426 | I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); |
| 3427 | I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder); |
| 3428 | |
| 3429 | return 0; |
| 3430 | } |
| 3431 | |
| 3432 | /** Sets the color ramps on behalf of RandR */ |
| 3433 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
| 3434 | u16 blue, int regno) |
| 3435 | { |
| 3436 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3437 | |
| 3438 | intel_crtc->lut_r[regno] = red >> 8; |
| 3439 | intel_crtc->lut_g[regno] = green >> 8; |
| 3440 | intel_crtc->lut_b[regno] = blue >> 8; |
| 3441 | } |
| 3442 | |
Dave Airlie | b8c00ac | 2009-10-06 13:54:01 +1000 | [diff] [blame] | 3443 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
| 3444 | u16 *blue, int regno) |
| 3445 | { |
| 3446 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3447 | |
| 3448 | *red = intel_crtc->lut_r[regno] << 8; |
| 3449 | *green = intel_crtc->lut_g[regno] << 8; |
| 3450 | *blue = intel_crtc->lut_b[regno] << 8; |
| 3451 | } |
| 3452 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3453 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
| 3454 | u16 *blue, uint32_t size) |
| 3455 | { |
| 3456 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3457 | int i; |
| 3458 | |
| 3459 | if (size != 256) |
| 3460 | return; |
| 3461 | |
| 3462 | for (i = 0; i < 256; i++) { |
| 3463 | intel_crtc->lut_r[i] = red[i] >> 8; |
| 3464 | intel_crtc->lut_g[i] = green[i] >> 8; |
| 3465 | intel_crtc->lut_b[i] = blue[i] >> 8; |
| 3466 | } |
| 3467 | |
| 3468 | intel_crtc_load_lut(crtc); |
| 3469 | } |
| 3470 | |
| 3471 | /** |
| 3472 | * Get a pipe with a simple mode set on it for doing load-based monitor |
| 3473 | * detection. |
| 3474 | * |
| 3475 | * It will be up to the load-detect code to adjust the pipe as appropriate for |
| 3476 | * its requirements. The pipe will be connected to no other outputs. |
| 3477 | * |
| 3478 | * Currently this code will only succeed if there is a pipe with no outputs |
| 3479 | * configured for it. In the future, it could choose to temporarily disable |
| 3480 | * some outputs to free up a pipe for its use. |
| 3481 | * |
| 3482 | * \return crtc, or NULL if no pipes are available. |
| 3483 | */ |
| 3484 | |
| 3485 | /* VESA 640x480x72Hz mode to set on the pipe */ |
| 3486 | static struct drm_display_mode load_detect_mode = { |
| 3487 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
| 3488 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
| 3489 | }; |
| 3490 | |
| 3491 | struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output, |
| 3492 | struct drm_display_mode *mode, |
| 3493 | int *dpms_mode) |
| 3494 | { |
| 3495 | struct intel_crtc *intel_crtc; |
| 3496 | struct drm_crtc *possible_crtc; |
| 3497 | struct drm_crtc *supported_crtc =NULL; |
| 3498 | struct drm_encoder *encoder = &intel_output->enc; |
| 3499 | struct drm_crtc *crtc = NULL; |
| 3500 | struct drm_device *dev = encoder->dev; |
| 3501 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
| 3502 | struct drm_crtc_helper_funcs *crtc_funcs; |
| 3503 | int i = -1; |
| 3504 | |
| 3505 | /* |
| 3506 | * Algorithm gets a little messy: |
| 3507 | * - if the connector already has an assigned crtc, use it (but make |
| 3508 | * sure it's on first) |
| 3509 | * - try to find the first unused crtc that can drive this connector, |
| 3510 | * and use that if we find one |
| 3511 | * - if there are no unused crtcs available, try to use the first |
| 3512 | * one we found that supports the connector |
| 3513 | */ |
| 3514 | |
| 3515 | /* See if we already have a CRTC for this connector */ |
| 3516 | if (encoder->crtc) { |
| 3517 | crtc = encoder->crtc; |
| 3518 | /* Make sure the crtc and connector are running */ |
| 3519 | intel_crtc = to_intel_crtc(crtc); |
| 3520 | *dpms_mode = intel_crtc->dpms_mode; |
| 3521 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
| 3522 | crtc_funcs = crtc->helper_private; |
| 3523 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); |
| 3524 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
| 3525 | } |
| 3526 | return crtc; |
| 3527 | } |
| 3528 | |
| 3529 | /* Find an unused one (if possible) */ |
| 3530 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
| 3531 | i++; |
| 3532 | if (!(encoder->possible_crtcs & (1 << i))) |
| 3533 | continue; |
| 3534 | if (!possible_crtc->enabled) { |
| 3535 | crtc = possible_crtc; |
| 3536 | break; |
| 3537 | } |
| 3538 | if (!supported_crtc) |
| 3539 | supported_crtc = possible_crtc; |
| 3540 | } |
| 3541 | |
| 3542 | /* |
| 3543 | * If we didn't find an unused CRTC, don't use any. |
| 3544 | */ |
| 3545 | if (!crtc) { |
| 3546 | return NULL; |
| 3547 | } |
| 3548 | |
| 3549 | encoder->crtc = crtc; |
Keith Packard | 03d6069 | 2009-06-05 18:19:56 -0700 | [diff] [blame] | 3550 | intel_output->base.encoder = encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3551 | intel_output->load_detect_temp = true; |
| 3552 | |
| 3553 | intel_crtc = to_intel_crtc(crtc); |
| 3554 | *dpms_mode = intel_crtc->dpms_mode; |
| 3555 | |
| 3556 | if (!crtc->enabled) { |
| 3557 | if (!mode) |
| 3558 | mode = &load_detect_mode; |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 3559 | drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3560 | } else { |
| 3561 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
| 3562 | crtc_funcs = crtc->helper_private; |
| 3563 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); |
| 3564 | } |
| 3565 | |
| 3566 | /* Add this connector to the crtc */ |
| 3567 | encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode); |
| 3568 | encoder_funcs->commit(encoder); |
| 3569 | } |
| 3570 | /* let the connector get through one full cycle before testing */ |
| 3571 | intel_wait_for_vblank(dev); |
| 3572 | |
| 3573 | return crtc; |
| 3574 | } |
| 3575 | |
| 3576 | void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode) |
| 3577 | { |
| 3578 | struct drm_encoder *encoder = &intel_output->enc; |
| 3579 | struct drm_device *dev = encoder->dev; |
| 3580 | struct drm_crtc *crtc = encoder->crtc; |
| 3581 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
| 3582 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 3583 | |
| 3584 | if (intel_output->load_detect_temp) { |
| 3585 | encoder->crtc = NULL; |
Keith Packard | 03d6069 | 2009-06-05 18:19:56 -0700 | [diff] [blame] | 3586 | intel_output->base.encoder = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3587 | intel_output->load_detect_temp = false; |
| 3588 | crtc->enabled = drm_helper_crtc_in_use(crtc); |
| 3589 | drm_helper_disable_unused_functions(dev); |
| 3590 | } |
| 3591 | |
| 3592 | /* Switch crtc and output back off if necessary */ |
| 3593 | if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { |
| 3594 | if (encoder->crtc == crtc) |
| 3595 | encoder_funcs->dpms(encoder, dpms_mode); |
| 3596 | crtc_funcs->dpms(crtc, dpms_mode); |
| 3597 | } |
| 3598 | } |
| 3599 | |
| 3600 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
| 3601 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) |
| 3602 | { |
| 3603 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3604 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3605 | int pipe = intel_crtc->pipe; |
| 3606 | u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B); |
| 3607 | u32 fp; |
| 3608 | intel_clock_t clock; |
| 3609 | |
| 3610 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
| 3611 | fp = I915_READ((pipe == 0) ? FPA0 : FPB0); |
| 3612 | else |
| 3613 | fp = I915_READ((pipe == 0) ? FPA1 : FPB1); |
| 3614 | |
| 3615 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 3616 | if (IS_IGD(dev)) { |
| 3617 | clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
| 3618 | clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT; |
| 3619 | } else { |
| 3620 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
| 3621 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
| 3622 | } |
| 3623 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3624 | if (IS_I9XX(dev)) { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 3625 | if (IS_IGD(dev)) |
| 3626 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >> |
| 3627 | DPLL_FPA01_P1_POST_DIV_SHIFT_IGD); |
| 3628 | else |
| 3629 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3630 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 3631 | |
| 3632 | switch (dpll & DPLL_MODE_MASK) { |
| 3633 | case DPLLB_MODE_DAC_SERIAL: |
| 3634 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
| 3635 | 5 : 10; |
| 3636 | break; |
| 3637 | case DPLLB_MODE_LVDS: |
| 3638 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
| 3639 | 7 : 14; |
| 3640 | break; |
| 3641 | default: |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3642 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3643 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
| 3644 | return 0; |
| 3645 | } |
| 3646 | |
| 3647 | /* XXX: Handle the 100Mhz refclk */ |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 3648 | intel_clock(dev, 96000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3649 | } else { |
| 3650 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); |
| 3651 | |
| 3652 | if (is_lvds) { |
| 3653 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
| 3654 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 3655 | clock.p2 = 14; |
| 3656 | |
| 3657 | if ((dpll & PLL_REF_INPUT_MASK) == |
| 3658 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
| 3659 | /* XXX: might not be 66MHz */ |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 3660 | intel_clock(dev, 66000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3661 | } else |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 3662 | intel_clock(dev, 48000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3663 | } else { |
| 3664 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
| 3665 | clock.p1 = 2; |
| 3666 | else { |
| 3667 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
| 3668 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
| 3669 | } |
| 3670 | if (dpll & PLL_P2_DIVIDE_BY_4) |
| 3671 | clock.p2 = 4; |
| 3672 | else |
| 3673 | clock.p2 = 2; |
| 3674 | |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 3675 | intel_clock(dev, 48000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3676 | } |
| 3677 | } |
| 3678 | |
| 3679 | /* XXX: It would be nice to validate the clocks, but we can't reuse |
| 3680 | * i830PllIsValid() because it relies on the xf86_config connector |
| 3681 | * configuration being accurate, which it isn't necessarily. |
| 3682 | */ |
| 3683 | |
| 3684 | return clock.dot; |
| 3685 | } |
| 3686 | |
| 3687 | /** Returns the currently programmed mode of the given pipe. */ |
| 3688 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| 3689 | struct drm_crtc *crtc) |
| 3690 | { |
| 3691 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3692 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3693 | int pipe = intel_crtc->pipe; |
| 3694 | struct drm_display_mode *mode; |
| 3695 | int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); |
| 3696 | int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B); |
| 3697 | int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); |
| 3698 | int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B); |
| 3699 | |
| 3700 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
| 3701 | if (!mode) |
| 3702 | return NULL; |
| 3703 | |
| 3704 | mode->clock = intel_crtc_clock_get(dev, crtc); |
| 3705 | mode->hdisplay = (htot & 0xffff) + 1; |
| 3706 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
| 3707 | mode->hsync_start = (hsync & 0xffff) + 1; |
| 3708 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
| 3709 | mode->vdisplay = (vtot & 0xffff) + 1; |
| 3710 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
| 3711 | mode->vsync_start = (vsync & 0xffff) + 1; |
| 3712 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
| 3713 | |
| 3714 | drm_mode_set_name(mode); |
| 3715 | drm_mode_set_crtcinfo(mode, 0); |
| 3716 | |
| 3717 | return mode; |
| 3718 | } |
| 3719 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3720 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
| 3721 | |
| 3722 | /* When this timer fires, we've been idle for awhile */ |
| 3723 | static void intel_gpu_idle_timer(unsigned long arg) |
| 3724 | { |
| 3725 | struct drm_device *dev = (struct drm_device *)arg; |
| 3726 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3727 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 3728 | DRM_DEBUG_DRIVER("idle timer fired, downclocking\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3729 | |
| 3730 | dev_priv->busy = false; |
| 3731 | |
Eric Anholt | 01dfba9 | 2009-09-06 15:18:53 -0700 | [diff] [blame] | 3732 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3733 | } |
| 3734 | |
| 3735 | void intel_increase_renderclock(struct drm_device *dev, bool schedule) |
| 3736 | { |
| 3737 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3738 | |
| 3739 | if (IS_IGDNG(dev)) |
| 3740 | return; |
| 3741 | |
| 3742 | if (!dev_priv->render_reclock_avail) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 3743 | DRM_DEBUG_DRIVER("not reclocking render clock\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3744 | return; |
| 3745 | } |
| 3746 | |
| 3747 | /* Restore render clock frequency to original value */ |
| 3748 | if (IS_G4X(dev) || IS_I9XX(dev)) |
| 3749 | pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock); |
| 3750 | else if (IS_I85X(dev)) |
| 3751 | pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock); |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 3752 | DRM_DEBUG_DRIVER("increasing render clock frequency\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3753 | |
| 3754 | /* Schedule downclock */ |
| 3755 | if (schedule) |
| 3756 | mod_timer(&dev_priv->idle_timer, jiffies + |
| 3757 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); |
| 3758 | } |
| 3759 | |
| 3760 | void intel_decrease_renderclock(struct drm_device *dev) |
| 3761 | { |
| 3762 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3763 | |
| 3764 | if (IS_IGDNG(dev)) |
| 3765 | return; |
| 3766 | |
| 3767 | if (!dev_priv->render_reclock_avail) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 3768 | DRM_DEBUG_DRIVER("not reclocking render clock\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3769 | return; |
| 3770 | } |
| 3771 | |
| 3772 | if (IS_G4X(dev)) { |
| 3773 | u16 gcfgc; |
| 3774 | |
| 3775 | /* Adjust render clock... */ |
| 3776 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 3777 | |
| 3778 | /* Down to minimum... */ |
| 3779 | gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK; |
| 3780 | gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ; |
| 3781 | |
| 3782 | pci_write_config_word(dev->pdev, GCFGC, gcfgc); |
| 3783 | } else if (IS_I965G(dev)) { |
| 3784 | u16 gcfgc; |
| 3785 | |
| 3786 | /* Adjust render clock... */ |
| 3787 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 3788 | |
| 3789 | /* Down to minimum... */ |
| 3790 | gcfgc &= ~I965_GC_RENDER_CLOCK_MASK; |
| 3791 | gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ; |
| 3792 | |
| 3793 | pci_write_config_word(dev->pdev, GCFGC, gcfgc); |
| 3794 | } else if (IS_I945G(dev) || IS_I945GM(dev)) { |
| 3795 | u16 gcfgc; |
| 3796 | |
| 3797 | /* Adjust render clock... */ |
| 3798 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 3799 | |
| 3800 | /* Down to minimum... */ |
| 3801 | gcfgc &= ~I945_GC_RENDER_CLOCK_MASK; |
| 3802 | gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ; |
| 3803 | |
| 3804 | pci_write_config_word(dev->pdev, GCFGC, gcfgc); |
| 3805 | } else if (IS_I915G(dev)) { |
| 3806 | u16 gcfgc; |
| 3807 | |
| 3808 | /* Adjust render clock... */ |
| 3809 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 3810 | |
| 3811 | /* Down to minimum... */ |
| 3812 | gcfgc &= ~I915_GC_RENDER_CLOCK_MASK; |
| 3813 | gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ; |
| 3814 | |
| 3815 | pci_write_config_word(dev->pdev, GCFGC, gcfgc); |
| 3816 | } else if (IS_I85X(dev)) { |
| 3817 | u16 hpllcc; |
| 3818 | |
| 3819 | /* Adjust render clock... */ |
| 3820 | pci_read_config_word(dev->pdev, HPLLCC, &hpllcc); |
| 3821 | |
| 3822 | /* Up to maximum... */ |
| 3823 | hpllcc &= ~GC_CLOCK_CONTROL_MASK; |
| 3824 | hpllcc |= GC_CLOCK_133_200; |
| 3825 | |
| 3826 | pci_write_config_word(dev->pdev, HPLLCC, hpllcc); |
| 3827 | } |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 3828 | DRM_DEBUG_DRIVER("decreasing render clock frequency\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3829 | } |
| 3830 | |
| 3831 | /* Note that no increase function is needed for this - increase_renderclock() |
| 3832 | * will also rewrite these bits |
| 3833 | */ |
| 3834 | void intel_decrease_displayclock(struct drm_device *dev) |
| 3835 | { |
| 3836 | if (IS_IGDNG(dev)) |
| 3837 | return; |
| 3838 | |
| 3839 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) || |
| 3840 | IS_I915GM(dev)) { |
| 3841 | u16 gcfgc; |
| 3842 | |
| 3843 | /* Adjust render clock... */ |
| 3844 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 3845 | |
| 3846 | /* Down to minimum... */ |
| 3847 | gcfgc &= ~0xf0; |
| 3848 | gcfgc |= 0x80; |
| 3849 | |
| 3850 | pci_write_config_word(dev->pdev, GCFGC, gcfgc); |
| 3851 | } |
| 3852 | } |
| 3853 | |
| 3854 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
| 3855 | |
| 3856 | static void intel_crtc_idle_timer(unsigned long arg) |
| 3857 | { |
| 3858 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; |
| 3859 | struct drm_crtc *crtc = &intel_crtc->base; |
| 3860 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; |
| 3861 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 3862 | DRM_DEBUG_DRIVER("idle timer fired, downclocking\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3863 | |
| 3864 | intel_crtc->busy = false; |
| 3865 | |
Eric Anholt | 01dfba9 | 2009-09-06 15:18:53 -0700 | [diff] [blame] | 3866 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3867 | } |
| 3868 | |
| 3869 | static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule) |
| 3870 | { |
| 3871 | struct drm_device *dev = crtc->dev; |
| 3872 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3873 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3874 | int pipe = intel_crtc->pipe; |
| 3875 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; |
| 3876 | int dpll = I915_READ(dpll_reg); |
| 3877 | |
| 3878 | if (IS_IGDNG(dev)) |
| 3879 | return; |
| 3880 | |
| 3881 | if (!dev_priv->lvds_downclock_avail) |
| 3882 | return; |
| 3883 | |
| 3884 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 3885 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3886 | |
| 3887 | /* Unlock panel regs */ |
| 3888 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); |
| 3889 | |
| 3890 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
| 3891 | I915_WRITE(dpll_reg, dpll); |
| 3892 | dpll = I915_READ(dpll_reg); |
| 3893 | intel_wait_for_vblank(dev); |
| 3894 | dpll = I915_READ(dpll_reg); |
| 3895 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 3896 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3897 | |
| 3898 | /* ...and lock them again */ |
| 3899 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); |
| 3900 | } |
| 3901 | |
| 3902 | /* Schedule downclock */ |
| 3903 | if (schedule) |
| 3904 | mod_timer(&intel_crtc->idle_timer, jiffies + |
| 3905 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); |
| 3906 | } |
| 3907 | |
| 3908 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
| 3909 | { |
| 3910 | struct drm_device *dev = crtc->dev; |
| 3911 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3912 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3913 | int pipe = intel_crtc->pipe; |
| 3914 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; |
| 3915 | int dpll = I915_READ(dpll_reg); |
| 3916 | |
| 3917 | if (IS_IGDNG(dev)) |
| 3918 | return; |
| 3919 | |
| 3920 | if (!dev_priv->lvds_downclock_avail) |
| 3921 | return; |
| 3922 | |
| 3923 | /* |
| 3924 | * Since this is called by a timer, we should never get here in |
| 3925 | * the manual case. |
| 3926 | */ |
| 3927 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 3928 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3929 | |
| 3930 | /* Unlock panel regs */ |
| 3931 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); |
| 3932 | |
| 3933 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
| 3934 | I915_WRITE(dpll_reg, dpll); |
| 3935 | dpll = I915_READ(dpll_reg); |
| 3936 | intel_wait_for_vblank(dev); |
| 3937 | dpll = I915_READ(dpll_reg); |
| 3938 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 3939 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3940 | |
| 3941 | /* ...and lock them again */ |
| 3942 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); |
| 3943 | } |
| 3944 | |
| 3945 | } |
| 3946 | |
| 3947 | /** |
| 3948 | * intel_idle_update - adjust clocks for idleness |
| 3949 | * @work: work struct |
| 3950 | * |
| 3951 | * Either the GPU or display (or both) went idle. Check the busy status |
| 3952 | * here and adjust the CRTC and GPU clocks as necessary. |
| 3953 | */ |
| 3954 | static void intel_idle_update(struct work_struct *work) |
| 3955 | { |
| 3956 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 3957 | idle_work); |
| 3958 | struct drm_device *dev = dev_priv->dev; |
| 3959 | struct drm_crtc *crtc; |
| 3960 | struct intel_crtc *intel_crtc; |
| 3961 | |
| 3962 | if (!i915_powersave) |
| 3963 | return; |
| 3964 | |
| 3965 | mutex_lock(&dev->struct_mutex); |
| 3966 | |
| 3967 | /* GPU isn't processing, downclock it. */ |
| 3968 | if (!dev_priv->busy) { |
| 3969 | intel_decrease_renderclock(dev); |
| 3970 | intel_decrease_displayclock(dev); |
| 3971 | } |
| 3972 | |
| 3973 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 3974 | /* Skip inactive CRTCs */ |
| 3975 | if (!crtc->fb) |
| 3976 | continue; |
| 3977 | |
| 3978 | intel_crtc = to_intel_crtc(crtc); |
| 3979 | if (!intel_crtc->busy) |
| 3980 | intel_decrease_pllclock(crtc); |
| 3981 | } |
| 3982 | |
| 3983 | mutex_unlock(&dev->struct_mutex); |
| 3984 | } |
| 3985 | |
| 3986 | /** |
| 3987 | * intel_mark_busy - mark the GPU and possibly the display busy |
| 3988 | * @dev: drm device |
| 3989 | * @obj: object we're operating on |
| 3990 | * |
| 3991 | * Callers can use this function to indicate that the GPU is busy processing |
| 3992 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout |
| 3993 | * buffer), we'll also mark the display as busy, so we know to increase its |
| 3994 | * clock frequency. |
| 3995 | */ |
| 3996 | void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) |
| 3997 | { |
| 3998 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3999 | struct drm_crtc *crtc = NULL; |
| 4000 | struct intel_framebuffer *intel_fb; |
| 4001 | struct intel_crtc *intel_crtc; |
| 4002 | |
Zhenyu Wang | 5e17ee7 | 2009-09-03 09:30:06 +0800 | [diff] [blame] | 4003 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4004 | return; |
| 4005 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4006 | dev_priv->busy = true; |
| 4007 | intel_increase_renderclock(dev, true); |
| 4008 | |
| 4009 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 4010 | if (!crtc->fb) |
| 4011 | continue; |
| 4012 | |
| 4013 | intel_crtc = to_intel_crtc(crtc); |
| 4014 | intel_fb = to_intel_framebuffer(crtc->fb); |
| 4015 | if (intel_fb->obj == obj) { |
| 4016 | if (!intel_crtc->busy) { |
| 4017 | /* Non-busy -> busy, upclock */ |
| 4018 | intel_increase_pllclock(crtc, true); |
| 4019 | intel_crtc->busy = true; |
| 4020 | } else { |
| 4021 | /* Busy -> busy, put off timer */ |
| 4022 | mod_timer(&intel_crtc->idle_timer, jiffies + |
| 4023 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); |
| 4024 | } |
| 4025 | } |
| 4026 | } |
| 4027 | } |
| 4028 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4029 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
| 4030 | { |
| 4031 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4032 | |
| 4033 | drm_crtc_cleanup(crtc); |
| 4034 | kfree(intel_crtc); |
| 4035 | } |
| 4036 | |
| 4037 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
| 4038 | .dpms = intel_crtc_dpms, |
| 4039 | .mode_fixup = intel_crtc_mode_fixup, |
| 4040 | .mode_set = intel_crtc_mode_set, |
| 4041 | .mode_set_base = intel_pipe_set_base, |
| 4042 | .prepare = intel_crtc_prepare, |
| 4043 | .commit = intel_crtc_commit, |
Dave Airlie | 068143d | 2009-10-05 09:58:02 +1000 | [diff] [blame] | 4044 | .load_lut = intel_crtc_load_lut, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4045 | }; |
| 4046 | |
| 4047 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
| 4048 | .cursor_set = intel_crtc_cursor_set, |
| 4049 | .cursor_move = intel_crtc_cursor_move, |
| 4050 | .gamma_set = intel_crtc_gamma_set, |
| 4051 | .set_config = drm_crtc_helper_set_config, |
| 4052 | .destroy = intel_crtc_destroy, |
| 4053 | }; |
| 4054 | |
| 4055 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 4056 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4057 | { |
| 4058 | struct intel_crtc *intel_crtc; |
| 4059 | int i; |
| 4060 | |
| 4061 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
| 4062 | if (intel_crtc == NULL) |
| 4063 | return; |
| 4064 | |
| 4065 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
| 4066 | |
| 4067 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
| 4068 | intel_crtc->pipe = pipe; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4069 | intel_crtc->plane = pipe; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4070 | for (i = 0; i < 256; i++) { |
| 4071 | intel_crtc->lut_r[i] = i; |
| 4072 | intel_crtc->lut_g[i] = i; |
| 4073 | intel_crtc->lut_b[i] = i; |
| 4074 | } |
| 4075 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 4076 | /* Swap pipes & planes for FBC on pre-965 */ |
| 4077 | intel_crtc->pipe = pipe; |
| 4078 | intel_crtc->plane = pipe; |
| 4079 | if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 4080 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 4081 | intel_crtc->plane = ((pipe == 0) ? 1 : 0); |
| 4082 | } |
| 4083 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4084 | intel_crtc->cursor_addr = 0; |
| 4085 | intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; |
| 4086 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
| 4087 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4088 | intel_crtc->busy = false; |
| 4089 | |
| 4090 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, |
| 4091 | (unsigned long)intel_crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4092 | } |
| 4093 | |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 4094 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
| 4095 | struct drm_file *file_priv) |
| 4096 | { |
| 4097 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4098 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 4099 | struct drm_mode_object *drmmode_obj; |
| 4100 | struct intel_crtc *crtc; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 4101 | |
| 4102 | if (!dev_priv) { |
| 4103 | DRM_ERROR("called with no initialization\n"); |
| 4104 | return -EINVAL; |
| 4105 | } |
| 4106 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 4107 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
| 4108 | DRM_MODE_OBJECT_CRTC); |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 4109 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 4110 | if (!drmmode_obj) { |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 4111 | DRM_ERROR("no such CRTC id\n"); |
| 4112 | return -EINVAL; |
| 4113 | } |
| 4114 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 4115 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
| 4116 | pipe_from_crtc_id->pipe = crtc->pipe; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 4117 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 4118 | return 0; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 4119 | } |
| 4120 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4121 | struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) |
| 4122 | { |
| 4123 | struct drm_crtc *crtc = NULL; |
| 4124 | |
| 4125 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 4126 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4127 | if (intel_crtc->pipe == pipe) |
| 4128 | break; |
| 4129 | } |
| 4130 | return crtc; |
| 4131 | } |
| 4132 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 4133 | static int intel_connector_clones(struct drm_device *dev, int type_mask) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4134 | { |
| 4135 | int index_mask = 0; |
| 4136 | struct drm_connector *connector; |
| 4137 | int entry = 0; |
| 4138 | |
| 4139 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 4140 | struct intel_output *intel_output = to_intel_output(connector); |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 4141 | if (type_mask & intel_output->clone_mask) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4142 | index_mask |= (1 << entry); |
| 4143 | entry++; |
| 4144 | } |
| 4145 | return index_mask; |
| 4146 | } |
| 4147 | |
| 4148 | |
| 4149 | static void intel_setup_outputs(struct drm_device *dev) |
| 4150 | { |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 4151 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4152 | struct drm_connector *connector; |
| 4153 | |
| 4154 | intel_crt_init(dev); |
| 4155 | |
| 4156 | /* Set up integrated LVDS */ |
Zhenyu Wang | 541998a | 2009-06-05 15:38:44 +0800 | [diff] [blame] | 4157 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4158 | intel_lvds_init(dev); |
| 4159 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4160 | if (IS_IGDNG(dev)) { |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 4161 | int found; |
| 4162 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4163 | if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED)) |
| 4164 | intel_dp_init(dev, DP_A); |
| 4165 | |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 4166 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
| 4167 | /* check SDVOB */ |
| 4168 | /* found = intel_sdvo_init(dev, HDMIB); */ |
| 4169 | found = 0; |
| 4170 | if (!found) |
| 4171 | intel_hdmi_init(dev, HDMIB); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4172 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
| 4173 | intel_dp_init(dev, PCH_DP_B); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 4174 | } |
| 4175 | |
| 4176 | if (I915_READ(HDMIC) & PORT_DETECTED) |
| 4177 | intel_hdmi_init(dev, HDMIC); |
| 4178 | |
| 4179 | if (I915_READ(HDMID) & PORT_DETECTED) |
| 4180 | intel_hdmi_init(dev, HDMID); |
| 4181 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4182 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
| 4183 | intel_dp_init(dev, PCH_DP_C); |
| 4184 | |
| 4185 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
| 4186 | intel_dp_init(dev, PCH_DP_D); |
| 4187 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4188 | } else if (IS_I9XX(dev)) { |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 4189 | bool found = false; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 4190 | |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 4191 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
| 4192 | found = intel_sdvo_init(dev, SDVOB); |
| 4193 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) |
| 4194 | intel_hdmi_init(dev, SDVOB); |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 4195 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4196 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
| 4197 | intel_dp_init(dev, DP_B); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 4198 | } |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 4199 | |
| 4200 | /* Before G4X SDVOC doesn't have its own detect register */ |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 4201 | |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 4202 | if (I915_READ(SDVOB) & SDVO_DETECTED) |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 4203 | found = intel_sdvo_init(dev, SDVOC); |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 4204 | |
| 4205 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { |
| 4206 | |
| 4207 | if (SUPPORTS_INTEGRATED_HDMI(dev)) |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 4208 | intel_hdmi_init(dev, SDVOC); |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 4209 | if (SUPPORTS_INTEGRATED_DP(dev)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4210 | intel_dp_init(dev, DP_C); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 4211 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 4212 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4213 | if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED)) |
| 4214 | intel_dp_init(dev, DP_D); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4215 | } else |
| 4216 | intel_dvo_init(dev); |
| 4217 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4218 | if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4219 | intel_tv_init(dev); |
| 4220 | |
| 4221 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 4222 | struct intel_output *intel_output = to_intel_output(connector); |
| 4223 | struct drm_encoder *encoder = &intel_output->enc; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4224 | |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 4225 | encoder->possible_crtcs = intel_output->crtc_mask; |
| 4226 | encoder->possible_clones = intel_connector_clones(dev, |
| 4227 | intel_output->clone_mask); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4228 | } |
| 4229 | } |
| 4230 | |
| 4231 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
| 4232 | { |
| 4233 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 4234 | struct drm_device *dev = fb->dev; |
| 4235 | |
| 4236 | if (fb->fbdev) |
| 4237 | intelfb_remove(dev, fb); |
| 4238 | |
| 4239 | drm_framebuffer_cleanup(fb); |
| 4240 | mutex_lock(&dev->struct_mutex); |
| 4241 | drm_gem_object_unreference(intel_fb->obj); |
| 4242 | mutex_unlock(&dev->struct_mutex); |
| 4243 | |
| 4244 | kfree(intel_fb); |
| 4245 | } |
| 4246 | |
| 4247 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
| 4248 | struct drm_file *file_priv, |
| 4249 | unsigned int *handle) |
| 4250 | { |
| 4251 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 4252 | struct drm_gem_object *object = intel_fb->obj; |
| 4253 | |
| 4254 | return drm_gem_handle_create(file_priv, object, handle); |
| 4255 | } |
| 4256 | |
| 4257 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
| 4258 | .destroy = intel_user_framebuffer_destroy, |
| 4259 | .create_handle = intel_user_framebuffer_create_handle, |
| 4260 | }; |
| 4261 | |
| 4262 | int intel_framebuffer_create(struct drm_device *dev, |
| 4263 | struct drm_mode_fb_cmd *mode_cmd, |
| 4264 | struct drm_framebuffer **fb, |
| 4265 | struct drm_gem_object *obj) |
| 4266 | { |
| 4267 | struct intel_framebuffer *intel_fb; |
| 4268 | int ret; |
| 4269 | |
| 4270 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
| 4271 | if (!intel_fb) |
| 4272 | return -ENOMEM; |
| 4273 | |
| 4274 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
| 4275 | if (ret) { |
| 4276 | DRM_ERROR("framebuffer init failed %d\n", ret); |
| 4277 | return ret; |
| 4278 | } |
| 4279 | |
| 4280 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
| 4281 | |
| 4282 | intel_fb->obj = obj; |
| 4283 | |
| 4284 | *fb = &intel_fb->base; |
| 4285 | |
| 4286 | return 0; |
| 4287 | } |
| 4288 | |
| 4289 | |
| 4290 | static struct drm_framebuffer * |
| 4291 | intel_user_framebuffer_create(struct drm_device *dev, |
| 4292 | struct drm_file *filp, |
| 4293 | struct drm_mode_fb_cmd *mode_cmd) |
| 4294 | { |
| 4295 | struct drm_gem_object *obj; |
| 4296 | struct drm_framebuffer *fb; |
| 4297 | int ret; |
| 4298 | |
| 4299 | obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle); |
| 4300 | if (!obj) |
| 4301 | return NULL; |
| 4302 | |
| 4303 | ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj); |
| 4304 | if (ret) { |
Jesse Barnes | 496818f | 2009-02-11 13:28:14 -0800 | [diff] [blame] | 4305 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4306 | drm_gem_object_unreference(obj); |
Jesse Barnes | 496818f | 2009-02-11 13:28:14 -0800 | [diff] [blame] | 4307 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4308 | return NULL; |
| 4309 | } |
| 4310 | |
| 4311 | return fb; |
| 4312 | } |
| 4313 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4314 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4315 | .fb_create = intel_user_framebuffer_create, |
| 4316 | .fb_changed = intelfb_probe, |
| 4317 | }; |
| 4318 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4319 | void intel_init_clock_gating(struct drm_device *dev) |
| 4320 | { |
| 4321 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4322 | |
| 4323 | /* |
| 4324 | * Disable clock gating reported to work incorrectly according to the |
| 4325 | * specs, but enable as much else as we can. |
| 4326 | */ |
Zhenyu Wang | c03342f | 2009-09-29 11:01:23 +0800 | [diff] [blame] | 4327 | if (IS_IGDNG(dev)) { |
| 4328 | return; |
| 4329 | } else if (IS_G4X(dev)) { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4330 | uint32_t dspclk_gate; |
| 4331 | I915_WRITE(RENCLK_GATE_D1, 0); |
| 4332 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
| 4333 | GS_UNIT_CLOCK_GATE_DISABLE | |
| 4334 | CL_UNIT_CLOCK_GATE_DISABLE); |
| 4335 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 4336 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
| 4337 | OVRUNIT_CLOCK_GATE_DISABLE | |
| 4338 | OVCUNIT_CLOCK_GATE_DISABLE; |
| 4339 | if (IS_GM45(dev)) |
| 4340 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
| 4341 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); |
| 4342 | } else if (IS_I965GM(dev)) { |
| 4343 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
| 4344 | I915_WRITE(RENCLK_GATE_D2, 0); |
| 4345 | I915_WRITE(DSPCLK_GATE_D, 0); |
| 4346 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 4347 | I915_WRITE16(DEUC, 0); |
| 4348 | } else if (IS_I965G(dev)) { |
| 4349 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
| 4350 | I965_RCC_CLOCK_GATE_DISABLE | |
| 4351 | I965_RCPB_CLOCK_GATE_DISABLE | |
| 4352 | I965_ISC_CLOCK_GATE_DISABLE | |
| 4353 | I965_FBC_CLOCK_GATE_DISABLE); |
| 4354 | I915_WRITE(RENCLK_GATE_D2, 0); |
| 4355 | } else if (IS_I9XX(dev)) { |
| 4356 | u32 dstate = I915_READ(D_STATE); |
| 4357 | |
| 4358 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | |
| 4359 | DSTATE_DOT_CLOCK_GATING; |
| 4360 | I915_WRITE(D_STATE, dstate); |
Daniel Vetter | f0f8a9c | 2009-09-15 22:57:33 +0200 | [diff] [blame] | 4361 | } else if (IS_I85X(dev) || IS_I865G(dev)) { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4362 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
| 4363 | } else if (IS_I830(dev)) { |
| 4364 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); |
| 4365 | } |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 4366 | |
| 4367 | /* |
| 4368 | * GPU can automatically power down the render unit if given a page |
| 4369 | * to save state. |
| 4370 | */ |
| 4371 | if (I915_HAS_RC6(dev)) { |
| 4372 | struct drm_gem_object *pwrctx; |
| 4373 | struct drm_i915_gem_object *obj_priv; |
| 4374 | int ret; |
| 4375 | |
| 4376 | pwrctx = drm_gem_object_alloc(dev, 4096); |
| 4377 | if (!pwrctx) { |
| 4378 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
| 4379 | goto out; |
| 4380 | } |
| 4381 | |
| 4382 | ret = i915_gem_object_pin(pwrctx, 4096); |
| 4383 | if (ret) { |
| 4384 | DRM_ERROR("failed to pin power context: %d\n", ret); |
| 4385 | drm_gem_object_unreference(pwrctx); |
| 4386 | goto out; |
| 4387 | } |
| 4388 | |
| 4389 | i915_gem_object_set_to_gtt_domain(pwrctx, 1); |
| 4390 | |
| 4391 | obj_priv = pwrctx->driver_private; |
| 4392 | |
| 4393 | I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN); |
| 4394 | I915_WRITE(MCHBAR_RENDER_STANDBY, |
| 4395 | I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT); |
| 4396 | |
| 4397 | dev_priv->pwrctx = pwrctx; |
| 4398 | } |
| 4399 | |
| 4400 | out: |
| 4401 | return; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4402 | } |
| 4403 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 4404 | /* Set up chip specific display functions */ |
| 4405 | static void intel_init_display(struct drm_device *dev) |
| 4406 | { |
| 4407 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4408 | |
| 4409 | /* We always want a DPMS function */ |
| 4410 | if (IS_IGDNG(dev)) |
| 4411 | dev_priv->display.dpms = igdng_crtc_dpms; |
| 4412 | else |
| 4413 | dev_priv->display.dpms = i9xx_crtc_dpms; |
| 4414 | |
| 4415 | /* Only mobile has FBC, leave pointers NULL for other chips */ |
| 4416 | if (IS_MOBILE(dev)) { |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 4417 | if (IS_GM45(dev)) { |
| 4418 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
| 4419 | dev_priv->display.enable_fbc = g4x_enable_fbc; |
| 4420 | dev_priv->display.disable_fbc = g4x_disable_fbc; |
| 4421 | } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 4422 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
| 4423 | dev_priv->display.enable_fbc = i8xx_enable_fbc; |
| 4424 | dev_priv->display.disable_fbc = i8xx_disable_fbc; |
| 4425 | } |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 4426 | /* 855GM needs testing */ |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 4427 | } |
| 4428 | |
| 4429 | /* Returns the core display clock speed */ |
| 4430 | if (IS_I945G(dev)) |
| 4431 | dev_priv->display.get_display_clock_speed = |
| 4432 | i945_get_display_clock_speed; |
| 4433 | else if (IS_I915G(dev)) |
| 4434 | dev_priv->display.get_display_clock_speed = |
| 4435 | i915_get_display_clock_speed; |
| 4436 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev)) |
| 4437 | dev_priv->display.get_display_clock_speed = |
| 4438 | i9xx_misc_get_display_clock_speed; |
| 4439 | else if (IS_I915GM(dev)) |
| 4440 | dev_priv->display.get_display_clock_speed = |
| 4441 | i915gm_get_display_clock_speed; |
| 4442 | else if (IS_I865G(dev)) |
| 4443 | dev_priv->display.get_display_clock_speed = |
| 4444 | i865_get_display_clock_speed; |
Daniel Vetter | f0f8a9c | 2009-09-15 22:57:33 +0200 | [diff] [blame] | 4445 | else if (IS_I85X(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 4446 | dev_priv->display.get_display_clock_speed = |
| 4447 | i855_get_display_clock_speed; |
| 4448 | else /* 852, 830 */ |
| 4449 | dev_priv->display.get_display_clock_speed = |
| 4450 | i830_get_display_clock_speed; |
| 4451 | |
| 4452 | /* For FIFO watermark updates */ |
Zhenyu Wang | c03342f | 2009-09-29 11:01:23 +0800 | [diff] [blame] | 4453 | if (IS_IGDNG(dev)) |
| 4454 | dev_priv->display.update_wm = NULL; |
| 4455 | else if (IS_G4X(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 4456 | dev_priv->display.update_wm = g4x_update_wm; |
| 4457 | else if (IS_I965G(dev)) |
| 4458 | dev_priv->display.update_wm = i965_update_wm; |
| 4459 | else if (IS_I9XX(dev) || IS_MOBILE(dev)) { |
| 4460 | dev_priv->display.update_wm = i9xx_update_wm; |
| 4461 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; |
| 4462 | } else { |
| 4463 | if (IS_I85X(dev)) |
| 4464 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; |
| 4465 | else if (IS_845G(dev)) |
| 4466 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
| 4467 | else |
| 4468 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
| 4469 | dev_priv->display.update_wm = i830_update_wm; |
| 4470 | } |
| 4471 | } |
| 4472 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4473 | void intel_modeset_init(struct drm_device *dev) |
| 4474 | { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4475 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4476 | int num_pipe; |
| 4477 | int i; |
| 4478 | |
| 4479 | drm_mode_config_init(dev); |
| 4480 | |
| 4481 | dev->mode_config.min_width = 0; |
| 4482 | dev->mode_config.min_height = 0; |
| 4483 | |
| 4484 | dev->mode_config.funcs = (void *)&intel_mode_funcs; |
| 4485 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 4486 | intel_init_display(dev); |
| 4487 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4488 | if (IS_I965G(dev)) { |
| 4489 | dev->mode_config.max_width = 8192; |
| 4490 | dev->mode_config.max_height = 8192; |
Keith Packard | 5e4d6fa | 2009-07-12 23:53:17 -0700 | [diff] [blame] | 4491 | } else if (IS_I9XX(dev)) { |
| 4492 | dev->mode_config.max_width = 4096; |
| 4493 | dev->mode_config.max_height = 4096; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4494 | } else { |
| 4495 | dev->mode_config.max_width = 2048; |
| 4496 | dev->mode_config.max_height = 2048; |
| 4497 | } |
| 4498 | |
| 4499 | /* set memory base */ |
| 4500 | if (IS_I9XX(dev)) |
| 4501 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2); |
| 4502 | else |
| 4503 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0); |
| 4504 | |
| 4505 | if (IS_MOBILE(dev) || IS_I9XX(dev)) |
| 4506 | num_pipe = 2; |
| 4507 | else |
| 4508 | num_pipe = 1; |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 4509 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4510 | num_pipe, num_pipe > 1 ? "s" : ""); |
| 4511 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4512 | if (IS_I85X(dev)) |
| 4513 | pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock); |
| 4514 | else if (IS_I9XX(dev) || IS_G4X(dev)) |
| 4515 | pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock); |
| 4516 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4517 | for (i = 0; i < num_pipe; i++) { |
| 4518 | intel_crtc_init(dev, i); |
| 4519 | } |
| 4520 | |
| 4521 | intel_setup_outputs(dev); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4522 | |
| 4523 | intel_init_clock_gating(dev); |
| 4524 | |
| 4525 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
| 4526 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, |
| 4527 | (unsigned long)dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 4528 | |
| 4529 | intel_setup_overlay(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4530 | } |
| 4531 | |
| 4532 | void intel_modeset_cleanup(struct drm_device *dev) |
| 4533 | { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4534 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4535 | struct drm_crtc *crtc; |
| 4536 | struct intel_crtc *intel_crtc; |
| 4537 | |
| 4538 | mutex_lock(&dev->struct_mutex); |
| 4539 | |
| 4540 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 4541 | /* Skip inactive CRTCs */ |
| 4542 | if (!crtc->fb) |
| 4543 | continue; |
| 4544 | |
| 4545 | intel_crtc = to_intel_crtc(crtc); |
| 4546 | intel_increase_pllclock(crtc, false); |
| 4547 | del_timer_sync(&intel_crtc->idle_timer); |
| 4548 | } |
| 4549 | |
| 4550 | intel_increase_renderclock(dev, false); |
| 4551 | del_timer_sync(&dev_priv->idle_timer); |
| 4552 | |
| 4553 | mutex_unlock(&dev->struct_mutex); |
| 4554 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 4555 | if (dev_priv->display.disable_fbc) |
| 4556 | dev_priv->display.disable_fbc(dev); |
| 4557 | |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 4558 | if (dev_priv->pwrctx) { |
| 4559 | i915_gem_object_unpin(dev_priv->pwrctx); |
| 4560 | drm_gem_object_unreference(dev_priv->pwrctx); |
| 4561 | } |
| 4562 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4563 | drm_mode_config_cleanup(dev); |
| 4564 | } |
| 4565 | |
| 4566 | |
| 4567 | /* current intel driver doesn't take advantage of encoders |
| 4568 | always give back the encoder for the connector |
| 4569 | */ |
| 4570 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
| 4571 | { |
| 4572 | struct intel_output *intel_output = to_intel_output(connector); |
| 4573 | |
| 4574 | return &intel_output->enc; |
| 4575 | } |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 4576 | |
| 4577 | /* |
| 4578 | * set vga decode state - true == enable VGA decode |
| 4579 | */ |
| 4580 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
| 4581 | { |
| 4582 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4583 | u16 gmch_ctrl; |
| 4584 | |
| 4585 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); |
| 4586 | if (state) |
| 4587 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
| 4588 | else |
| 4589 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
| 4590 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); |
| 4591 | return 0; |
| 4592 | } |