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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
David Brownell075c1772007-04-26 00:12:06 -070014#include <linux/pm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <linux/module.h>
16#include <linux/spinlock.h>
Tim Schmielau4e57b682005-10-30 15:03:48 -080017#include <linux/string.h>
vignesh babu229f5af2007-08-13 18:23:14 +053018#include <linux/log2.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080019#include <linux/pci-aspm.h>
Stephen Rothwellc300bd2fb2008-07-10 02:16:44 +020020#include <linux/pm_wakeup.h>
Sheng Yang8dd7f802008-10-21 17:38:25 +080021#include <linux/interrupt.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <asm/dma.h> /* isa_dma_bridge_buggy */
Yuji Shimada32a9a6822009-03-16 17:13:39 +090023#include <linux/device.h>
24#include <asm/setup.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090025#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Rafael J. Wysockiaa8c6c92009-01-16 21:54:43 +010027unsigned int pci_pm_d3_delay = PCI_PM_D3_WAIT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Jeff Garzik32a2eea2007-10-11 16:57:27 -040029#ifdef CONFIG_PCI_DOMAINS
30int pci_domains_supported = 1;
31#endif
32
Atsushi Nemoto4516a612007-02-05 16:36:06 -080033#define DEFAULT_CARDBUS_IO_SIZE (256)
34#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
35/* pci=cbmemsize=nnM,cbiosize=nn can override this */
36unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
37unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
38
Linus Torvalds1da177e2005-04-16 15:20:36 -070039/**
40 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
41 * @bus: pointer to PCI bus structure to search
42 *
43 * Given a PCI bus, returns the highest PCI bus number present in the set
44 * including the given PCI bus and its list of child PCI buses.
45 */
Sam Ravnborg96bde062007-03-26 21:53:30 -080046unsigned char pci_bus_max_busnr(struct pci_bus* bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -070047{
48 struct list_head *tmp;
49 unsigned char max, n;
50
Kristen Accardib82db5c2006-01-17 16:56:56 -080051 max = bus->subordinate;
Linus Torvalds1da177e2005-04-16 15:20:36 -070052 list_for_each(tmp, &bus->children) {
53 n = pci_bus_max_busnr(pci_bus_b(tmp));
54 if(n > max)
55 max = n;
56 }
57 return max;
58}
Kristen Accardib82db5c2006-01-17 16:56:56 -080059EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -070060
Andrew Morton1684f5d2008-12-01 14:30:30 -080061#ifdef CONFIG_HAS_IOMEM
62void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
63{
64 /*
65 * Make sure the BAR is actually a memory resource, not an IO resource
66 */
67 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
68 WARN_ON(1);
69 return NULL;
70 }
71 return ioremap_nocache(pci_resource_start(pdev, bar),
72 pci_resource_len(pdev, bar));
73}
74EXPORT_SYMBOL_GPL(pci_ioremap_bar);
75#endif
76
Kristen Accardib82db5c2006-01-17 16:56:56 -080077#if 0
Linus Torvalds1da177e2005-04-16 15:20:36 -070078/**
79 * pci_max_busnr - returns maximum PCI bus number
80 *
81 * Returns the highest PCI bus number present in the system global list of
82 * PCI buses.
83 */
84unsigned char __devinit
85pci_max_busnr(void)
86{
87 struct pci_bus *bus = NULL;
88 unsigned char max, n;
89
90 max = 0;
91 while ((bus = pci_find_next_bus(bus)) != NULL) {
92 n = pci_bus_max_busnr(bus);
93 if(n > max)
94 max = n;
95 }
96 return max;
97}
98
Adrian Bunk54c762f2005-12-22 01:08:52 +010099#endif /* 0 */
100
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100101#define PCI_FIND_CAP_TTL 48
102
103static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
104 u8 pos, int cap, int *ttl)
Roland Dreier24a4e372005-10-28 17:35:34 -0700105{
106 u8 id;
Roland Dreier24a4e372005-10-28 17:35:34 -0700107
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100108 while ((*ttl)--) {
Roland Dreier24a4e372005-10-28 17:35:34 -0700109 pci_bus_read_config_byte(bus, devfn, pos, &pos);
110 if (pos < 0x40)
111 break;
112 pos &= ~3;
113 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
114 &id);
115 if (id == 0xff)
116 break;
117 if (id == cap)
118 return pos;
119 pos += PCI_CAP_LIST_NEXT;
120 }
121 return 0;
122}
123
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100124static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
125 u8 pos, int cap)
126{
127 int ttl = PCI_FIND_CAP_TTL;
128
129 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
130}
131
Roland Dreier24a4e372005-10-28 17:35:34 -0700132int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
133{
134 return __pci_find_next_cap(dev->bus, dev->devfn,
135 pos + PCI_CAP_LIST_NEXT, cap);
136}
137EXPORT_SYMBOL_GPL(pci_find_next_capability);
138
Michael Ellermand3bac112006-11-22 18:26:16 +1100139static int __pci_bus_find_cap_start(struct pci_bus *bus,
140 unsigned int devfn, u8 hdr_type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141{
142 u16 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143
144 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
145 if (!(status & PCI_STATUS_CAP_LIST))
146 return 0;
147
148 switch (hdr_type) {
149 case PCI_HEADER_TYPE_NORMAL:
150 case PCI_HEADER_TYPE_BRIDGE:
Michael Ellermand3bac112006-11-22 18:26:16 +1100151 return PCI_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152 case PCI_HEADER_TYPE_CARDBUS:
Michael Ellermand3bac112006-11-22 18:26:16 +1100153 return PCI_CB_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154 default:
155 return 0;
156 }
Michael Ellermand3bac112006-11-22 18:26:16 +1100157
158 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159}
160
161/**
162 * pci_find_capability - query for devices' capabilities
163 * @dev: PCI device to query
164 * @cap: capability code
165 *
166 * Tell if a device supports a given PCI capability.
167 * Returns the address of the requested capability structure within the
168 * device's PCI configuration space or 0 in case the device does not
169 * support it. Possible values for @cap:
170 *
171 * %PCI_CAP_ID_PM Power Management
172 * %PCI_CAP_ID_AGP Accelerated Graphics Port
173 * %PCI_CAP_ID_VPD Vital Product Data
174 * %PCI_CAP_ID_SLOTID Slot Identification
175 * %PCI_CAP_ID_MSI Message Signalled Interrupts
176 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
177 * %PCI_CAP_ID_PCIX PCI-X
178 * %PCI_CAP_ID_EXP PCI Express
179 */
180int pci_find_capability(struct pci_dev *dev, int cap)
181{
Michael Ellermand3bac112006-11-22 18:26:16 +1100182 int pos;
183
184 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
185 if (pos)
186 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
187
188 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189}
190
191/**
192 * pci_bus_find_capability - query for devices' capabilities
193 * @bus: the PCI bus to query
194 * @devfn: PCI device to query
195 * @cap: capability code
196 *
197 * Like pci_find_capability() but works for pci devices that do not have a
198 * pci_dev structure set up yet.
199 *
200 * Returns the address of the requested capability structure within the
201 * device's PCI configuration space or 0 in case the device does not
202 * support it.
203 */
204int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
205{
Michael Ellermand3bac112006-11-22 18:26:16 +1100206 int pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207 u8 hdr_type;
208
209 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
210
Michael Ellermand3bac112006-11-22 18:26:16 +1100211 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
212 if (pos)
213 pos = __pci_find_next_cap(bus, devfn, pos, cap);
214
215 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216}
217
218/**
219 * pci_find_ext_capability - Find an extended capability
220 * @dev: PCI device to query
221 * @cap: capability code
222 *
223 * Returns the address of the requested extended capability structure
224 * within the device's PCI configuration space or 0 if the device does
225 * not support it. Possible values for @cap:
226 *
227 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
228 * %PCI_EXT_CAP_ID_VC Virtual Channel
229 * %PCI_EXT_CAP_ID_DSN Device Serial Number
230 * %PCI_EXT_CAP_ID_PWR Power Budgeting
231 */
232int pci_find_ext_capability(struct pci_dev *dev, int cap)
233{
234 u32 header;
Zhao, Yu557848c2008-10-13 19:18:07 +0800235 int ttl;
236 int pos = PCI_CFG_SPACE_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237
Zhao, Yu557848c2008-10-13 19:18:07 +0800238 /* minimum 8 bytes per capability */
239 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
240
241 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242 return 0;
243
244 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
245 return 0;
246
247 /*
248 * If we have no capabilities, this is indicated by cap ID,
249 * cap version and next pointer all being 0.
250 */
251 if (header == 0)
252 return 0;
253
254 while (ttl-- > 0) {
255 if (PCI_EXT_CAP_ID(header) == cap)
256 return pos;
257
258 pos = PCI_EXT_CAP_NEXT(header);
Zhao, Yu557848c2008-10-13 19:18:07 +0800259 if (pos < PCI_CFG_SPACE_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260 break;
261
262 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
263 break;
264 }
265
266 return 0;
267}
Brice Goglin3a720d72006-05-23 06:10:01 -0400268EXPORT_SYMBOL_GPL(pci_find_ext_capability);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100270static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
271{
272 int rc, ttl = PCI_FIND_CAP_TTL;
273 u8 cap, mask;
274
275 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
276 mask = HT_3BIT_CAP_MASK;
277 else
278 mask = HT_5BIT_CAP_MASK;
279
280 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
281 PCI_CAP_ID_HT, &ttl);
282 while (pos) {
283 rc = pci_read_config_byte(dev, pos + 3, &cap);
284 if (rc != PCIBIOS_SUCCESSFUL)
285 return 0;
286
287 if ((cap & mask) == ht_cap)
288 return pos;
289
Brice Goglin47a4d5b2007-01-10 23:15:29 -0800290 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
291 pos + PCI_CAP_LIST_NEXT,
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100292 PCI_CAP_ID_HT, &ttl);
293 }
294
295 return 0;
296}
297/**
298 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
299 * @dev: PCI device to query
300 * @pos: Position from which to continue searching
301 * @ht_cap: Hypertransport capability code
302 *
303 * To be used in conjunction with pci_find_ht_capability() to search for
304 * all capabilities matching @ht_cap. @pos should always be a value returned
305 * from pci_find_ht_capability().
306 *
307 * NB. To be 100% safe against broken PCI devices, the caller should take
308 * steps to avoid an infinite loop.
309 */
310int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
311{
312 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
313}
314EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
315
316/**
317 * pci_find_ht_capability - query a device's Hypertransport capabilities
318 * @dev: PCI device to query
319 * @ht_cap: Hypertransport capability code
320 *
321 * Tell if a device supports a given Hypertransport capability.
322 * Returns an address within the device's PCI configuration space
323 * or 0 in case the device does not support the request capability.
324 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
325 * which has a Hypertransport capability matching @ht_cap.
326 */
327int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
328{
329 int pos;
330
331 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
332 if (pos)
333 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
334
335 return pos;
336}
337EXPORT_SYMBOL_GPL(pci_find_ht_capability);
338
Linus Torvalds1da177e2005-04-16 15:20:36 -0700339/**
340 * pci_find_parent_resource - return resource region of parent bus of given region
341 * @dev: PCI device structure contains resources to be searched
342 * @res: child resource record for which parent is sought
343 *
344 * For given resource region of given device, return the resource
345 * region of parent bus the given region is contained in or where
346 * it should be allocated from.
347 */
348struct resource *
349pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
350{
351 const struct pci_bus *bus = dev->bus;
352 int i;
353 struct resource *best = NULL;
354
355 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
356 struct resource *r = bus->resource[i];
357 if (!r)
358 continue;
359 if (res->start && !(res->start >= r->start && res->end <= r->end))
360 continue; /* Not contained */
361 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
362 continue; /* Wrong type */
363 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
364 return r; /* Exact match */
365 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
366 best = r; /* Approximating prefetchable by non-prefetchable */
367 }
368 return best;
369}
370
371/**
John W. Linville064b53db2005-07-27 10:19:44 -0400372 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
373 * @dev: PCI device to have its BARs restored
374 *
375 * Restore the BAR values for a given device, so as to make it
376 * accessible by its driver.
377 */
Adrian Bunkad6685992007-10-27 03:06:22 +0200378static void
John W. Linville064b53db2005-07-27 10:19:44 -0400379pci_restore_bars(struct pci_dev *dev)
380{
Yu Zhaobc5f5a82008-11-22 02:40:00 +0800381 int i;
John W. Linville064b53db2005-07-27 10:19:44 -0400382
Yu Zhaobc5f5a82008-11-22 02:40:00 +0800383 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
Yu Zhao14add802008-11-22 02:38:52 +0800384 pci_update_resource(dev, i);
John W. Linville064b53db2005-07-27 10:19:44 -0400385}
386
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200387static struct pci_platform_pm_ops *pci_platform_pm;
388
389int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
390{
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +0200391 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
392 || !ops->sleep_wake || !ops->can_wakeup)
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200393 return -EINVAL;
394 pci_platform_pm = ops;
395 return 0;
396}
397
398static inline bool platform_pci_power_manageable(struct pci_dev *dev)
399{
400 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
401}
402
403static inline int platform_pci_set_power_state(struct pci_dev *dev,
404 pci_power_t t)
405{
406 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
407}
408
409static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
410{
411 return pci_platform_pm ?
412 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
413}
Randy Dunlap8f7020d2005-10-23 11:57:38 -0700414
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +0200415static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
416{
417 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
418}
419
420static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
421{
422 return pci_platform_pm ?
423 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
424}
425
John W. Linville064b53db2005-07-27 10:19:44 -0400426/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200427 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
428 * given PCI device
429 * @dev: PCI device to handle.
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200430 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431 *
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200432 * RETURN VALUE:
433 * -EINVAL if the requested state is invalid.
434 * -EIO if device does not support PCI PM or its PM capabilities register has a
435 * wrong version, or device doesn't support the requested state.
436 * 0 if device already is in the requested state.
437 * 0 if device's power state has been successfully changed.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438 */
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100439static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200441 u16 pmcsr;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200442 bool need_restore = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443
Rafael J. Wysocki4a865902009-03-16 22:40:36 +0100444 /* Check if we're already there */
445 if (dev->current_state == state)
446 return 0;
447
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200448 if (!dev->pm_cap)
Andrew Lunncca03de2007-07-09 11:55:58 -0700449 return -EIO;
450
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200451 if (state < PCI_D0 || state > PCI_D3hot)
452 return -EINVAL;
453
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454 /* Validate current state:
455 * Can enter D0 from any state, but if we can only go deeper
456 * to sleep if we're already in a low power state
457 */
Rafael J. Wysocki4a865902009-03-16 22:40:36 +0100458 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200459 && dev->current_state > state) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600460 dev_err(&dev->dev, "invalid power transition "
461 "(from state %d to %d)\n", dev->current_state, state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462 return -EINVAL;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200463 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465 /* check if this device supports the desired state */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200466 if ((state == PCI_D1 && !dev->d1_support)
467 || (state == PCI_D2 && !dev->d2_support))
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700468 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200470 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
John W. Linville064b53db2005-07-27 10:19:44 -0400471
John W. Linville32a36582005-09-14 09:52:42 -0400472 /* If we're (effectively) in D3, force entire word to 0.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473 * This doesn't affect PME_Status, disables PME_En, and
474 * sets PowerState to 0.
475 */
John W. Linville32a36582005-09-14 09:52:42 -0400476 switch (dev->current_state) {
John W. Linvilled3535fb2005-09-28 17:50:51 -0400477 case PCI_D0:
478 case PCI_D1:
479 case PCI_D2:
480 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
481 pmcsr |= state;
482 break;
Rafael J. Wysockif62795f2009-05-18 22:51:12 +0200483 case PCI_D3hot:
484 case PCI_D3cold:
John W. Linville32a36582005-09-14 09:52:42 -0400485 case PCI_UNKNOWN: /* Boot-up */
486 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100487 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200488 need_restore = true;
John W. Linville32a36582005-09-14 09:52:42 -0400489 /* Fall-through: force to D0 */
John W. Linville32a36582005-09-14 09:52:42 -0400490 default:
John W. Linvilled3535fb2005-09-28 17:50:51 -0400491 pmcsr = 0;
John W. Linville32a36582005-09-14 09:52:42 -0400492 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493 }
494
495 /* enter specified state */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200496 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497
498 /* Mandatory power management transition delays */
499 /* see PCI PM 1.1 5.6.1 table 18 */
500 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -0700501 msleep(pci_pm_d3_delay);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502 else if (state == PCI_D2 || dev->current_state == PCI_D2)
Rafael J. Wysockiaa8c6c92009-01-16 21:54:43 +0100503 udelay(PCI_PM_D2_DELAY);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504
David Shaohua Lib9131002005-03-19 00:16:18 -0500505 dev->current_state = state;
John W. Linville064b53db2005-07-27 10:19:44 -0400506
507 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
508 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
509 * from D3hot to D0 _may_ perform an internal reset, thereby
510 * going to "D0 Uninitialized" rather than "D0 Initialized".
511 * For example, at least some versions of the 3c905B and the
512 * 3c556B exhibit this behaviour.
513 *
514 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
515 * devices in a D3hot state at boot. Consequently, we need to
516 * restore at least the BARs so that the device will be
517 * accessible to its driver.
518 */
519 if (need_restore)
520 pci_restore_bars(dev);
521
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100522 if (dev->bus->self)
Shaohua Li7d715a62008-02-25 09:46:41 +0800523 pcie_aspm_pm_state_change(dev->bus->self);
524
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525 return 0;
526}
527
528/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200529 * pci_update_current_state - Read PCI power state of given device from its
530 * PCI PM registers and cache it
531 * @dev: PCI device to handle.
Rafael J. Wysockif06fc0b2008-12-27 16:30:52 +0100532 * @state: State to cache in case the device doesn't have the PM capability
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200533 */
Rafael J. Wysocki734104292009-01-07 13:07:15 +0100534void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200535{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200536 if (dev->pm_cap) {
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200537 u16 pmcsr;
538
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200539 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200540 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
Rafael J. Wysockif06fc0b2008-12-27 16:30:52 +0100541 } else {
542 dev->current_state = state;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200543 }
544}
545
546/**
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100547 * pci_platform_power_transition - Use platform to change device power state
548 * @dev: PCI device to handle.
549 * @state: State to put the device into.
550 */
551static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
552{
553 int error;
554
555 if (platform_pci_power_manageable(dev)) {
556 error = platform_pci_set_power_state(dev, state);
557 if (!error)
558 pci_update_current_state(dev, state);
559 } else {
560 error = -ENODEV;
561 /* Fall back to PCI_D0 if native PM is not supported */
Rafael J. Wysockib3bad722009-05-17 20:17:06 +0200562 if (!dev->pm_cap)
563 dev->current_state = PCI_D0;
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100564 }
565
566 return error;
567}
568
569/**
570 * __pci_start_power_transition - Start power transition of a PCI device
571 * @dev: PCI device to handle.
572 * @state: State to put the device into.
573 */
574static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
575{
576 if (state == PCI_D0)
577 pci_platform_power_transition(dev, PCI_D0);
578}
579
580/**
581 * __pci_complete_power_transition - Complete power transition of a PCI device
582 * @dev: PCI device to handle.
583 * @state: State to put the device into.
584 *
585 * This function should not be called directly by device drivers.
586 */
587int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
588{
589 return state > PCI_D0 ?
590 pci_platform_power_transition(dev, state) : -EINVAL;
591}
592EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
593
594/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200595 * pci_set_power_state - Set the power state of a PCI device
596 * @dev: PCI device to handle.
597 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
598 *
Nick Andrew877d0312009-01-26 11:06:57 +0100599 * Transition a device to a new power state, using the platform firmware and/or
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200600 * the device's PCI PM registers.
601 *
602 * RETURN VALUE:
603 * -EINVAL if the requested state is invalid.
604 * -EIO if device does not support PCI PM or its PM capabilities register has a
605 * wrong version, or device doesn't support the requested state.
606 * 0 if device already is in the requested state.
607 * 0 if device's power state has been successfully changed.
608 */
609int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
610{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200611 int error;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200612
613 /* bound the state we're entering */
614 if (state > PCI_D3hot)
615 state = PCI_D3hot;
616 else if (state < PCI_D0)
617 state = PCI_D0;
618 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
619 /*
620 * If the device or the parent bridge do not support PCI PM,
621 * ignore the request if we're doing anything other than putting
622 * it into D0 (which would only happen on boot).
623 */
624 return 0;
625
Rafael J. Wysocki4a865902009-03-16 22:40:36 +0100626 /* Check if we're already there */
627 if (dev->current_state == state)
628 return 0;
629
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100630 __pci_start_power_transition(dev, state);
631
Alan Cox979b1792008-07-24 17:18:38 +0100632 /* This device is quirked not to be put into D3, so
633 don't put it in D3 */
634 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
635 return 0;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200636
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100637 error = pci_raw_set_power_state(dev, state);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200638
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100639 if (!__pci_complete_power_transition(dev, state))
640 error = 0;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200641
642 return error;
643}
644
645/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646 * pci_choose_state - Choose the power state of a PCI device
647 * @dev: PCI device to be suspended
648 * @state: target sleep state for the whole system. This is the value
649 * that is passed to suspend() function.
650 *
651 * Returns PCI power state suitable for given device and given system
652 * message.
653 */
654
655pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
656{
Shaohua Liab826ca2007-07-20 10:03:22 +0800657 pci_power_t ret;
David Shaohua Li0f644742005-03-19 00:15:48 -0500658
Linus Torvalds1da177e2005-04-16 15:20:36 -0700659 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
660 return PCI_D0;
661
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200662 ret = platform_pci_choose_state(dev);
663 if (ret != PCI_POWER_ERROR)
664 return ret;
Pavel Machekca078ba2005-09-03 15:56:57 -0700665
666 switch (state.event) {
667 case PM_EVENT_ON:
668 return PCI_D0;
669 case PM_EVENT_FREEZE:
David Brownellb887d2e2006-08-14 23:11:05 -0700670 case PM_EVENT_PRETHAW:
671 /* REVISIT both freeze and pre-thaw "should" use D0 */
Pavel Machekca078ba2005-09-03 15:56:57 -0700672 case PM_EVENT_SUSPEND:
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +0100673 case PM_EVENT_HIBERNATE:
Pavel Machekca078ba2005-09-03 15:56:57 -0700674 return PCI_D3hot;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675 default:
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600676 dev_info(&dev->dev, "unrecognized suspend event %d\n",
677 state.event);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678 BUG();
679 }
680 return PCI_D0;
681}
682
683EXPORT_SYMBOL(pci_choose_state);
684
Yu Zhao89858512009-02-16 02:55:47 +0800685#define PCI_EXP_SAVE_REGS 7
686
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800687#define pcie_cap_has_devctl(type, flags) 1
688#define pcie_cap_has_lnkctl(type, flags) \
689 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
690 (type == PCI_EXP_TYPE_ROOT_PORT || \
691 type == PCI_EXP_TYPE_ENDPOINT || \
692 type == PCI_EXP_TYPE_LEG_END))
693#define pcie_cap_has_sltctl(type, flags) \
694 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
695 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
696 (type == PCI_EXP_TYPE_DOWNSTREAM && \
697 (flags & PCI_EXP_FLAGS_SLOT))))
698#define pcie_cap_has_rtctl(type, flags) \
699 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
700 (type == PCI_EXP_TYPE_ROOT_PORT || \
701 type == PCI_EXP_TYPE_RC_EC))
702#define pcie_cap_has_devctl2(type, flags) \
703 ((flags & PCI_EXP_FLAGS_VERS) > 1)
704#define pcie_cap_has_lnkctl2(type, flags) \
705 ((flags & PCI_EXP_FLAGS_VERS) > 1)
706#define pcie_cap_has_sltctl2(type, flags) \
707 ((flags & PCI_EXP_FLAGS_VERS) > 1)
708
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300709static int pci_save_pcie_state(struct pci_dev *dev)
710{
711 int pos, i = 0;
712 struct pci_cap_saved_state *save_state;
713 u16 *cap;
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800714 u16 flags;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300715
716 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
717 if (pos <= 0)
718 return 0;
719
Eric W. Biederman9f355752007-03-08 13:06:13 -0700720 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300721 if (!save_state) {
Harvey Harrisone496b612009-01-07 16:22:37 -0800722 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300723 return -ENOMEM;
724 }
725 cap = (u16 *)&save_state->data[0];
726
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800727 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
728
729 if (pcie_cap_has_devctl(dev->pcie_type, flags))
730 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
731 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
732 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
733 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
734 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
735 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
736 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
737 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
738 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
739 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
740 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
741 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
742 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
Rafael J. Wysocki63f48982008-12-07 22:02:58 +0100743
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300744 return 0;
745}
746
747static void pci_restore_pcie_state(struct pci_dev *dev)
748{
749 int i = 0, pos;
750 struct pci_cap_saved_state *save_state;
751 u16 *cap;
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800752 u16 flags;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300753
754 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
755 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
756 if (!save_state || pos <= 0)
757 return;
758 cap = (u16 *)&save_state->data[0];
759
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800760 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
761
762 if (pcie_cap_has_devctl(dev->pcie_type, flags))
763 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
764 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
765 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
766 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
767 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
768 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
769 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
770 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
771 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
772 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
773 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
774 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
775 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300776}
777
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800778
779static int pci_save_pcix_state(struct pci_dev *dev)
780{
Rafael J. Wysocki63f48982008-12-07 22:02:58 +0100781 int pos;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800782 struct pci_cap_saved_state *save_state;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800783
784 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
785 if (pos <= 0)
786 return 0;
787
Shaohua Lif34303d2007-12-18 09:56:47 +0800788 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800789 if (!save_state) {
Harvey Harrisone496b612009-01-07 16:22:37 -0800790 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800791 return -ENOMEM;
792 }
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800793
Rafael J. Wysocki63f48982008-12-07 22:02:58 +0100794 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
795
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800796 return 0;
797}
798
799static void pci_restore_pcix_state(struct pci_dev *dev)
800{
801 int i = 0, pos;
802 struct pci_cap_saved_state *save_state;
803 u16 *cap;
804
805 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
806 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
807 if (!save_state || pos <= 0)
808 return;
809 cap = (u16 *)&save_state->data[0];
810
811 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800812}
813
814
Linus Torvalds1da177e2005-04-16 15:20:36 -0700815/**
816 * pci_save_state - save the PCI configuration space of a device before suspending
817 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818 */
819int
820pci_save_state(struct pci_dev *dev)
821{
822 int i;
823 /* XXX: 100% dword access ok here? */
824 for (i = 0; i < 16; i++)
825 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
Rafael J. Wysockiaa8c6c92009-01-16 21:54:43 +0100826 dev->state_saved = true;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300827 if ((i = pci_save_pcie_state(dev)) != 0)
828 return i;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800829 if ((i = pci_save_pcix_state(dev)) != 0)
830 return i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700831 return 0;
832}
833
834/**
835 * pci_restore_state - Restore the saved state of a PCI device
836 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837 */
838int
839pci_restore_state(struct pci_dev *dev)
840{
841 int i;
Al Virob4482a42007-10-14 19:35:40 +0100842 u32 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700843
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300844 /* PCI Express register must be restored first */
845 pci_restore_pcie_state(dev);
846
Yu, Luming8b8c8d22006-04-25 00:00:34 -0700847 /*
848 * The Base Address register should be programmed before the command
849 * register(s)
850 */
851 for (i = 15; i >= 0; i--) {
Dave Jones04d9c1a2006-04-18 21:06:51 -0700852 pci_read_config_dword(dev, i * 4, &val);
853 if (val != dev->saved_config_space[i]) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600854 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
855 "space at offset %#x (was %#x, writing %#x)\n",
856 i, val, (int)dev->saved_config_space[i]);
Dave Jones04d9c1a2006-04-18 21:06:51 -0700857 pci_write_config_dword(dev,i * 4,
858 dev->saved_config_space[i]);
859 }
860 }
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800861 pci_restore_pcix_state(dev);
Shaohua Li41017f02006-02-08 17:11:38 +0800862 pci_restore_msi_state(dev);
Yu Zhao8c5cdb62009-03-20 11:25:12 +0800863 pci_restore_iov_state(dev);
Michael Ellerman8fed4b62007-01-25 19:34:08 +1100864
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865 return 0;
866}
867
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900868static int do_pci_enable_device(struct pci_dev *dev, int bars)
869{
870 int err;
871
872 err = pci_set_power_state(dev, PCI_D0);
873 if (err < 0 && err != -EIO)
874 return err;
875 err = pcibios_enable_device(dev, bars);
876 if (err < 0)
877 return err;
878 pci_fixup_device(pci_fixup_enable, dev);
879
880 return 0;
881}
882
883/**
Tejun Heo0b62e132007-07-27 14:43:35 +0900884 * pci_reenable_device - Resume abandoned device
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900885 * @dev: PCI device to be resumed
886 *
887 * Note this function is a backend of pci_default_resume and is not supposed
888 * to be called by normal code, write proper resume handler and use it instead.
889 */
Tejun Heo0b62e132007-07-27 14:43:35 +0900890int pci_reenable_device(struct pci_dev *dev)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900891{
Yuji Shimada296ccb02009-04-03 16:41:46 +0900892 if (pci_is_enabled(dev))
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900893 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
894 return 0;
895}
896
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100897static int __pci_enable_device_flags(struct pci_dev *dev,
898 resource_size_t flags)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700899{
900 int err;
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100901 int i, bars = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700902
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900903 if (atomic_add_return(1, &dev->enable_cnt) > 1)
904 return 0; /* already enabled */
905
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100906 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
907 if (dev->resource[i].flags & flags)
908 bars |= (1 << i);
909
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900910 err = do_pci_enable_device(dev, bars);
Greg Kroah-Hartman95a62962005-07-28 11:37:33 -0700911 if (err < 0)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900912 atomic_dec(&dev->enable_cnt);
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900913 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914}
915
916/**
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100917 * pci_enable_device_io - Initialize a device for use with IO space
918 * @dev: PCI device to be initialized
919 *
920 * Initialize device before it's used by a driver. Ask low-level code
921 * to enable I/O resources. Wake up the device if it was suspended.
922 * Beware, this function can fail.
923 */
924int pci_enable_device_io(struct pci_dev *dev)
925{
926 return __pci_enable_device_flags(dev, IORESOURCE_IO);
927}
928
929/**
930 * pci_enable_device_mem - Initialize a device for use with Memory space
931 * @dev: PCI device to be initialized
932 *
933 * Initialize device before it's used by a driver. Ask low-level code
934 * to enable Memory resources. Wake up the device if it was suspended.
935 * Beware, this function can fail.
936 */
937int pci_enable_device_mem(struct pci_dev *dev)
938{
939 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
940}
941
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942/**
943 * pci_enable_device - Initialize device before it's used by a driver.
944 * @dev: PCI device to be initialized
945 *
946 * Initialize device before it's used by a driver. Ask low-level code
947 * to enable I/O and memory. Wake up the device if it was suspended.
948 * Beware, this function can fail.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800949 *
950 * Note we don't actually enable the device many times if we call
951 * this function repeatedly (we just increment the count).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700952 */
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800953int pci_enable_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700954{
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100955 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956}
957
Tejun Heo9ac78492007-01-20 16:00:26 +0900958/*
959 * Managed PCI resources. This manages device on/off, intx/msi/msix
960 * on/off and BAR regions. pci_dev itself records msi/msix status, so
961 * there's no need to track it separately. pci_devres is initialized
962 * when a device is enabled using managed PCI device enable interface.
963 */
964struct pci_devres {
Tejun Heo7f375f32007-02-25 04:36:01 -0800965 unsigned int enabled:1;
966 unsigned int pinned:1;
Tejun Heo9ac78492007-01-20 16:00:26 +0900967 unsigned int orig_intx:1;
968 unsigned int restore_intx:1;
969 u32 region_mask;
970};
971
972static void pcim_release(struct device *gendev, void *res)
973{
974 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
975 struct pci_devres *this = res;
976 int i;
977
978 if (dev->msi_enabled)
979 pci_disable_msi(dev);
980 if (dev->msix_enabled)
981 pci_disable_msix(dev);
982
983 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
984 if (this->region_mask & (1 << i))
985 pci_release_region(dev, i);
986
987 if (this->restore_intx)
988 pci_intx(dev, this->orig_intx);
989
Tejun Heo7f375f32007-02-25 04:36:01 -0800990 if (this->enabled && !this->pinned)
Tejun Heo9ac78492007-01-20 16:00:26 +0900991 pci_disable_device(dev);
992}
993
994static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
995{
996 struct pci_devres *dr, *new_dr;
997
998 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
999 if (dr)
1000 return dr;
1001
1002 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1003 if (!new_dr)
1004 return NULL;
1005 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1006}
1007
1008static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1009{
1010 if (pci_is_managed(pdev))
1011 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1012 return NULL;
1013}
1014
1015/**
1016 * pcim_enable_device - Managed pci_enable_device()
1017 * @pdev: PCI device to be initialized
1018 *
1019 * Managed pci_enable_device().
1020 */
1021int pcim_enable_device(struct pci_dev *pdev)
1022{
1023 struct pci_devres *dr;
1024 int rc;
1025
1026 dr = get_pci_dr(pdev);
1027 if (unlikely(!dr))
1028 return -ENOMEM;
Tejun Heob95d58e2008-01-30 18:20:04 +09001029 if (dr->enabled)
1030 return 0;
Tejun Heo9ac78492007-01-20 16:00:26 +09001031
1032 rc = pci_enable_device(pdev);
1033 if (!rc) {
1034 pdev->is_managed = 1;
Tejun Heo7f375f32007-02-25 04:36:01 -08001035 dr->enabled = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +09001036 }
1037 return rc;
1038}
1039
1040/**
1041 * pcim_pin_device - Pin managed PCI device
1042 * @pdev: PCI device to pin
1043 *
1044 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1045 * driver detach. @pdev must have been enabled with
1046 * pcim_enable_device().
1047 */
1048void pcim_pin_device(struct pci_dev *pdev)
1049{
1050 struct pci_devres *dr;
1051
1052 dr = find_pci_dr(pdev);
Tejun Heo7f375f32007-02-25 04:36:01 -08001053 WARN_ON(!dr || !dr->enabled);
Tejun Heo9ac78492007-01-20 16:00:26 +09001054 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -08001055 dr->pinned = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +09001056}
1057
Linus Torvalds1da177e2005-04-16 15:20:36 -07001058/**
1059 * pcibios_disable_device - disable arch specific PCI resources for device dev
1060 * @dev: the PCI device to disable
1061 *
1062 * Disables architecture specific PCI resources for the device. This
1063 * is the default implementation. Architecture implementations can
1064 * override this.
1065 */
1066void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1067
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001068static void do_pci_disable_device(struct pci_dev *dev)
1069{
1070 u16 pci_command;
1071
1072 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1073 if (pci_command & PCI_COMMAND_MASTER) {
1074 pci_command &= ~PCI_COMMAND_MASTER;
1075 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1076 }
1077
1078 pcibios_disable_device(dev);
1079}
1080
1081/**
1082 * pci_disable_enabled_device - Disable device without updating enable_cnt
1083 * @dev: PCI device to disable
1084 *
1085 * NOTE: This function is a backend of PCI power management routines and is
1086 * not supposed to be called drivers.
1087 */
1088void pci_disable_enabled_device(struct pci_dev *dev)
1089{
Yuji Shimada296ccb02009-04-03 16:41:46 +09001090 if (pci_is_enabled(dev))
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001091 do_pci_disable_device(dev);
1092}
1093
Linus Torvalds1da177e2005-04-16 15:20:36 -07001094/**
1095 * pci_disable_device - Disable PCI device after use
1096 * @dev: PCI device to be disabled
1097 *
1098 * Signal to the system that the PCI device is not in use by the system
1099 * anymore. This only involves disabling PCI bus-mastering, if active.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -08001100 *
1101 * Note we don't actually disable the device until all callers of
1102 * pci_device_enable() have called pci_device_disable().
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103 */
1104void
1105pci_disable_device(struct pci_dev *dev)
1106{
Tejun Heo9ac78492007-01-20 16:00:26 +09001107 struct pci_devres *dr;
Shaohua Li99dc8042006-05-26 10:58:27 +08001108
Tejun Heo9ac78492007-01-20 16:00:26 +09001109 dr = find_pci_dr(dev);
1110 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -08001111 dr->enabled = 0;
Tejun Heo9ac78492007-01-20 16:00:26 +09001112
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -08001113 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1114 return;
1115
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001116 do_pci_disable_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001117
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001118 dev->is_busmaster = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001119}
1120
1121/**
Brian Kingf7bdd122007-04-06 16:39:36 -05001122 * pcibios_set_pcie_reset_state - set reset state for device dev
1123 * @dev: the PCI-E device reset
1124 * @state: Reset state to enter into
1125 *
1126 *
1127 * Sets the PCI-E reset state for the device. This is the default
1128 * implementation. Architecture implementations can override this.
1129 */
1130int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1131 enum pcie_reset_state state)
1132{
1133 return -EINVAL;
1134}
1135
1136/**
1137 * pci_set_pcie_reset_state - set reset state for device dev
1138 * @dev: the PCI-E device reset
1139 * @state: Reset state to enter into
1140 *
1141 *
1142 * Sets the PCI reset state for the device.
1143 */
1144int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1145{
1146 return pcibios_set_pcie_reset_state(dev, state);
1147}
1148
1149/**
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001150 * pci_pme_capable - check the capability of PCI device to generate PME#
1151 * @dev: PCI device to handle.
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001152 * @state: PCI state from which device will issue PME#.
1153 */
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02001154bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001155{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001156 if (!dev->pm_cap)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001157 return false;
1158
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001159 return !!(dev->pme_support & (1 << state));
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001160}
1161
1162/**
1163 * pci_pme_active - enable or disable PCI device's PME# function
1164 * @dev: PCI device to handle.
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001165 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1166 *
1167 * The caller must verify that the device is capable of generating PME# before
1168 * calling this function with @enable equal to 'true'.
1169 */
Rafael J. Wysocki5a6c9b62008-08-08 00:14:24 +02001170void pci_pme_active(struct pci_dev *dev, bool enable)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001171{
1172 u16 pmcsr;
1173
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001174 if (!dev->pm_cap)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001175 return;
1176
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001177 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001178 /* Clear PME_Status by writing 1 to it and enable PME# */
1179 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1180 if (!enable)
1181 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1182
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001183 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001184
1185 dev_printk(KERN_INFO, &dev->dev, "PME# %s\n",
1186 enable ? "enabled" : "disabled");
1187}
1188
1189/**
David Brownell075c1772007-04-26 00:12:06 -07001190 * pci_enable_wake - enable PCI device as wakeup event source
1191 * @dev: PCI device affected
1192 * @state: PCI state from which device will issue wakeup events
1193 * @enable: True to enable event generation; false to disable
Linus Torvalds1da177e2005-04-16 15:20:36 -07001194 *
David Brownell075c1772007-04-26 00:12:06 -07001195 * This enables the device as a wakeup event source, or disables it.
1196 * When such events involves platform-specific hooks, those hooks are
1197 * called automatically by this routine.
1198 *
1199 * Devices with legacy power management (no standard PCI PM capabilities)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001200 * always require such platform hooks.
David Brownell075c1772007-04-26 00:12:06 -07001201 *
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001202 * RETURN VALUE:
1203 * 0 is returned on success
1204 * -EINVAL is returned if device is not supposed to wake up the system
1205 * Error code depending on the platform is returned if both the platform and
1206 * the native mechanism fail to enable the generation of wake-up events
Linus Torvalds1da177e2005-04-16 15:20:36 -07001207 */
1208int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
1209{
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001210 int error = 0;
1211 bool pme_done = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001212
Alan Sternbebd5902008-12-16 14:06:58 -05001213 if (enable && !device_may_wakeup(&dev->dev))
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001214 return -EINVAL;
1215
1216 /*
1217 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1218 * Anderson we should be doing PME# wake enable followed by ACPI wake
1219 * enable. To disable wake-up we call the platform first, for symmetry.
David Brownell075c1772007-04-26 00:12:06 -07001220 */
1221
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001222 if (!enable && platform_pci_can_wakeup(dev))
1223 error = platform_pci_sleep_wake(dev, false);
1224
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001225 if (!enable || pci_pme_capable(dev, state)) {
1226 pci_pme_active(dev, enable);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001227 pme_done = true;
1228 }
1229
1230 if (enable && platform_pci_can_wakeup(dev))
1231 error = platform_pci_sleep_wake(dev, true);
1232
1233 return pme_done ? 0 : error;
1234}
1235
1236/**
Rafael J. Wysocki0235c4f2008-08-18 21:38:00 +02001237 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1238 * @dev: PCI device to prepare
1239 * @enable: True to enable wake-up event generation; false to disable
1240 *
1241 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1242 * and this function allows them to set that up cleanly - pci_enable_wake()
1243 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1244 * ordering constraints.
1245 *
1246 * This function only returns error code if the device is not capable of
1247 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1248 * enable wake-up power for it.
1249 */
1250int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1251{
1252 return pci_pme_capable(dev, PCI_D3cold) ?
1253 pci_enable_wake(dev, PCI_D3cold, enable) :
1254 pci_enable_wake(dev, PCI_D3hot, enable);
1255}
1256
1257/**
Jesse Barnes37139072008-07-28 11:49:26 -07001258 * pci_target_state - find an appropriate low power state for a given PCI dev
1259 * @dev: PCI device
1260 *
1261 * Use underlying platform code to find a supported low power state for @dev.
1262 * If the platform can't manage @dev, return the deepest state from which it
1263 * can generate wake events, based on any available PME info.
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001264 */
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02001265pci_power_t pci_target_state(struct pci_dev *dev)
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001266{
1267 pci_power_t target_state = PCI_D3hot;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001268
1269 if (platform_pci_power_manageable(dev)) {
1270 /*
1271 * Call the platform to choose the target state of the device
1272 * and enable wake-up from this state if supported.
1273 */
1274 pci_power_t state = platform_pci_choose_state(dev);
1275
1276 switch (state) {
1277 case PCI_POWER_ERROR:
1278 case PCI_UNKNOWN:
1279 break;
1280 case PCI_D1:
1281 case PCI_D2:
1282 if (pci_no_d1d2(dev))
1283 break;
1284 default:
1285 target_state = state;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001286 }
1287 } else if (device_may_wakeup(&dev->dev)) {
1288 /*
1289 * Find the deepest state from which the device can generate
1290 * wake-up events, make it the target state and enable device
1291 * to generate PME#.
1292 */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001293 if (!dev->pm_cap)
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02001294 return PCI_POWER_ERROR;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001295
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001296 if (dev->pme_support) {
1297 while (target_state
1298 && !(dev->pme_support & (1 << target_state)))
1299 target_state--;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001300 }
1301 }
1302
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02001303 return target_state;
1304}
1305
1306/**
1307 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1308 * @dev: Device to handle.
1309 *
1310 * Choose the power state appropriate for the device depending on whether
1311 * it can wake up the system and/or is power manageable by the platform
1312 * (PCI_D3hot is the default) and put the device into that state.
1313 */
1314int pci_prepare_to_sleep(struct pci_dev *dev)
1315{
1316 pci_power_t target_state = pci_target_state(dev);
1317 int error;
1318
1319 if (target_state == PCI_POWER_ERROR)
1320 return -EIO;
1321
Rafael J. Wysocki8efb8c72009-03-30 21:46:27 +02001322 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
Rafael J. Wysockic157dfa2008-07-13 22:45:06 +02001323
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001324 error = pci_set_power_state(dev, target_state);
1325
1326 if (error)
1327 pci_enable_wake(dev, target_state, false);
1328
1329 return error;
1330}
1331
1332/**
Randy Dunlap443bd1c2008-07-21 09:27:18 -07001333 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001334 * @dev: Device to handle.
1335 *
1336 * Disable device's sytem wake-up capability and put it into D0.
1337 */
1338int pci_back_from_sleep(struct pci_dev *dev)
1339{
1340 pci_enable_wake(dev, PCI_D0, false);
1341 return pci_set_power_state(dev, PCI_D0);
1342}
1343
1344/**
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001345 * pci_pm_init - Initialize PM functions of given PCI device
1346 * @dev: PCI device to handle.
1347 */
1348void pci_pm_init(struct pci_dev *dev)
1349{
1350 int pm;
1351 u16 pmc;
David Brownell075c1772007-04-26 00:12:06 -07001352
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001353 dev->pm_cap = 0;
1354
Linus Torvalds1da177e2005-04-16 15:20:36 -07001355 /* find PCI PM capability in list */
1356 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
David Brownell075c1772007-04-26 00:12:06 -07001357 if (!pm)
Linus Torvalds50246dd2009-01-16 08:14:51 -08001358 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001359 /* Check device's ability to generate PME# */
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001360 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001361
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001362 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1363 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1364 pmc & PCI_PM_CAP_VER_MASK);
Linus Torvalds50246dd2009-01-16 08:14:51 -08001365 return;
David Brownell075c1772007-04-26 00:12:06 -07001366 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001367
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001368 dev->pm_cap = pm;
1369
1370 dev->d1_support = false;
1371 dev->d2_support = false;
1372 if (!pci_no_d1d2(dev)) {
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06001373 if (pmc & PCI_PM_CAP_D1)
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001374 dev->d1_support = true;
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06001375 if (pmc & PCI_PM_CAP_D2)
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001376 dev->d2_support = true;
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06001377
1378 if (dev->d1_support || dev->d2_support)
1379 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
Jesse Barnesec84f122008-09-23 11:43:34 -07001380 dev->d1_support ? " D1" : "",
1381 dev->d2_support ? " D2" : "");
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001382 }
1383
1384 pmc &= PCI_PM_CAP_PME_MASK;
1385 if (pmc) {
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06001386 dev_info(&dev->dev, "PME# supported from%s%s%s%s%s\n",
1387 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1388 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1389 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1390 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1391 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001392 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001393 /*
1394 * Make device's PM flags reflect the wake-up capability, but
1395 * let the user space enable it to wake up the system as needed.
1396 */
1397 device_set_wakeup_capable(&dev->dev, true);
1398 device_set_wakeup_enable(&dev->dev, false);
1399 /* Disable the PME# generation functionality */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001400 pci_pme_active(dev, false);
1401 } else {
1402 dev->pme_support = 0;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001403 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001404}
1405
Yu Zhao58c3a722008-10-14 14:02:53 +08001406/**
Jesse Barneseb9c39d2008-12-17 12:10:05 -08001407 * platform_pci_wakeup_init - init platform wakeup if present
1408 * @dev: PCI device
1409 *
1410 * Some devices don't have PCI PM caps but can still generate wakeup
1411 * events through platform methods (like ACPI events). If @dev supports
1412 * platform wakeup events, set the device flag to indicate as much. This
1413 * may be redundant if the device also supports PCI PM caps, but double
1414 * initialization should be safe in that case.
1415 */
1416void platform_pci_wakeup_init(struct pci_dev *dev)
1417{
1418 if (!platform_pci_can_wakeup(dev))
1419 return;
1420
1421 device_set_wakeup_capable(&dev->dev, true);
1422 device_set_wakeup_enable(&dev->dev, false);
1423 platform_pci_sleep_wake(dev, false);
1424}
1425
1426/**
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001427 * pci_add_save_buffer - allocate buffer for saving given capability registers
1428 * @dev: the PCI device
1429 * @cap: the capability to allocate the buffer for
1430 * @size: requested size of the buffer
1431 */
1432static int pci_add_cap_save_buffer(
1433 struct pci_dev *dev, char cap, unsigned int size)
1434{
1435 int pos;
1436 struct pci_cap_saved_state *save_state;
1437
1438 pos = pci_find_capability(dev, cap);
1439 if (pos <= 0)
1440 return 0;
1441
1442 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1443 if (!save_state)
1444 return -ENOMEM;
1445
1446 save_state->cap_nr = cap;
1447 pci_add_saved_cap(dev, save_state);
1448
1449 return 0;
1450}
1451
1452/**
1453 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1454 * @dev: the PCI device
1455 */
1456void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1457{
1458 int error;
1459
Yu Zhao89858512009-02-16 02:55:47 +08001460 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1461 PCI_EXP_SAVE_REGS * sizeof(u16));
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001462 if (error)
1463 dev_err(&dev->dev,
1464 "unable to preallocate PCI Express save buffer\n");
1465
1466 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1467 if (error)
1468 dev_err(&dev->dev,
1469 "unable to preallocate PCI-X save buffer\n");
1470}
1471
1472/**
Yu Zhao58c3a722008-10-14 14:02:53 +08001473 * pci_enable_ari - enable ARI forwarding if hardware support it
1474 * @dev: the PCI device
1475 */
1476void pci_enable_ari(struct pci_dev *dev)
1477{
1478 int pos;
1479 u32 cap;
1480 u16 ctrl;
Zhao, Yu81135872008-10-23 13:15:39 +08001481 struct pci_dev *bridge;
Yu Zhao58c3a722008-10-14 14:02:53 +08001482
Zhao, Yu81135872008-10-23 13:15:39 +08001483 if (!dev->is_pcie || dev->devfn)
Yu Zhao58c3a722008-10-14 14:02:53 +08001484 return;
1485
Zhao, Yu81135872008-10-23 13:15:39 +08001486 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
Yu Zhao58c3a722008-10-14 14:02:53 +08001487 if (!pos)
1488 return;
1489
Zhao, Yu81135872008-10-23 13:15:39 +08001490 bridge = dev->bus->self;
1491 if (!bridge || !bridge->is_pcie)
1492 return;
1493
1494 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
1495 if (!pos)
1496 return;
1497
1498 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
Yu Zhao58c3a722008-10-14 14:02:53 +08001499 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1500 return;
1501
Zhao, Yu81135872008-10-23 13:15:39 +08001502 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
Yu Zhao58c3a722008-10-14 14:02:53 +08001503 ctrl |= PCI_EXP_DEVCTL2_ARI;
Zhao, Yu81135872008-10-23 13:15:39 +08001504 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
Yu Zhao58c3a722008-10-14 14:02:53 +08001505
Zhao, Yu81135872008-10-23 13:15:39 +08001506 bridge->ari_enabled = 1;
Yu Zhao58c3a722008-10-14 14:02:53 +08001507}
1508
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07001509/**
1510 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1511 * @dev: the PCI device
1512 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1513 *
1514 * Perform INTx swizzling for a device behind one level of bridge. This is
1515 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1516 * behind bridges on add-in cards.
1517 */
1518u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1519{
1520 return (((pin - 1) + PCI_SLOT(dev->devfn)) % 4) + 1;
1521}
1522
Linus Torvalds1da177e2005-04-16 15:20:36 -07001523int
1524pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1525{
1526 u8 pin;
1527
Kristen Accardi514d2072005-11-02 16:24:39 -08001528 pin = dev->pin;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001529 if (!pin)
1530 return -1;
Bjorn Helgaas878f2e52008-12-09 16:11:46 -07001531
Kenji Kaneshigec2a30722009-02-17 14:15:45 +09001532 while (dev->bus->parent) {
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07001533 pin = pci_swizzle_interrupt_pin(dev, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001534 dev = dev->bus->self;
1535 }
1536 *bridge = dev;
1537 return pin;
1538}
1539
1540/**
Bjorn Helgaas68feac82008-12-16 21:36:55 -07001541 * pci_common_swizzle - swizzle INTx all the way to root bridge
1542 * @dev: the PCI device
1543 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1544 *
1545 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1546 * bridges all the way up to a PCI root bus.
1547 */
1548u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1549{
1550 u8 pin = *pinp;
1551
Kenji Kaneshigec74d7242009-02-17 14:16:13 +09001552 while (dev->bus->parent) {
Bjorn Helgaas68feac82008-12-16 21:36:55 -07001553 pin = pci_swizzle_interrupt_pin(dev, pin);
1554 dev = dev->bus->self;
1555 }
1556 *pinp = pin;
1557 return PCI_SLOT(dev->devfn);
1558}
1559
1560/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001561 * pci_release_region - Release a PCI bar
1562 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1563 * @bar: BAR to release
1564 *
1565 * Releases the PCI I/O and memory resources previously reserved by a
1566 * successful call to pci_request_region. Call this function only
1567 * after all use of the PCI regions has ceased.
1568 */
1569void pci_release_region(struct pci_dev *pdev, int bar)
1570{
Tejun Heo9ac78492007-01-20 16:00:26 +09001571 struct pci_devres *dr;
1572
Linus Torvalds1da177e2005-04-16 15:20:36 -07001573 if (pci_resource_len(pdev, bar) == 0)
1574 return;
1575 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1576 release_region(pci_resource_start(pdev, bar),
1577 pci_resource_len(pdev, bar));
1578 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1579 release_mem_region(pci_resource_start(pdev, bar),
1580 pci_resource_len(pdev, bar));
Tejun Heo9ac78492007-01-20 16:00:26 +09001581
1582 dr = find_pci_dr(pdev);
1583 if (dr)
1584 dr->region_mask &= ~(1 << bar);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001585}
1586
1587/**
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08001588 * __pci_request_region - Reserved PCI I/O and memory resource
Linus Torvalds1da177e2005-04-16 15:20:36 -07001589 * @pdev: PCI device whose resources are to be reserved
1590 * @bar: BAR to be reserved
1591 * @res_name: Name to be associated with resource.
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08001592 * @exclusive: whether the region access is exclusive or not
Linus Torvalds1da177e2005-04-16 15:20:36 -07001593 *
1594 * Mark the PCI region associated with PCI device @pdev BR @bar as
1595 * being reserved by owner @res_name. Do not access any
1596 * address inside the PCI regions unless this call returns
1597 * successfully.
1598 *
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08001599 * If @exclusive is set, then the region is marked so that userspace
1600 * is explicitly not allowed to map the resource via /dev/mem or
1601 * sysfs MMIO access.
1602 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603 * Returns 0 on success, or %EBUSY on error. A warning
1604 * message is also printed on failure.
1605 */
Arjan van de Vene8de1482008-10-22 19:55:31 -07001606static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
1607 int exclusive)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001608{
Tejun Heo9ac78492007-01-20 16:00:26 +09001609 struct pci_devres *dr;
1610
Linus Torvalds1da177e2005-04-16 15:20:36 -07001611 if (pci_resource_len(pdev, bar) == 0)
1612 return 0;
1613
1614 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1615 if (!request_region(pci_resource_start(pdev, bar),
1616 pci_resource_len(pdev, bar), res_name))
1617 goto err_out;
1618 }
1619 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
Arjan van de Vene8de1482008-10-22 19:55:31 -07001620 if (!__request_mem_region(pci_resource_start(pdev, bar),
1621 pci_resource_len(pdev, bar), res_name,
1622 exclusive))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001623 goto err_out;
1624 }
Tejun Heo9ac78492007-01-20 16:00:26 +09001625
1626 dr = find_pci_dr(pdev);
1627 if (dr)
1628 dr->region_mask |= 1 << bar;
1629
Linus Torvalds1da177e2005-04-16 15:20:36 -07001630 return 0;
1631
1632err_out:
Benjamin Herrenschmidt096e6f62008-10-20 15:07:37 +11001633 dev_warn(&pdev->dev, "BAR %d: can't reserve %s region %pR\n",
Jesse Barnese4ec7a02008-06-25 16:12:25 -07001634 bar,
1635 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
Benjamin Herrenschmidt096e6f62008-10-20 15:07:37 +11001636 &pdev->resource[bar]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001637 return -EBUSY;
1638}
1639
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001640/**
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08001641 * pci_request_region - Reserve PCI I/O and memory resource
Arjan van de Vene8de1482008-10-22 19:55:31 -07001642 * @pdev: PCI device whose resources are to be reserved
1643 * @bar: BAR to be reserved
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08001644 * @res_name: Name to be associated with resource
Arjan van de Vene8de1482008-10-22 19:55:31 -07001645 *
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08001646 * Mark the PCI region associated with PCI device @pdev BAR @bar as
Arjan van de Vene8de1482008-10-22 19:55:31 -07001647 * being reserved by owner @res_name. Do not access any
1648 * address inside the PCI regions unless this call returns
1649 * successfully.
1650 *
1651 * Returns 0 on success, or %EBUSY on error. A warning
1652 * message is also printed on failure.
1653 */
1654int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1655{
1656 return __pci_request_region(pdev, bar, res_name, 0);
1657}
1658
1659/**
1660 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1661 * @pdev: PCI device whose resources are to be reserved
1662 * @bar: BAR to be reserved
1663 * @res_name: Name to be associated with resource.
1664 *
1665 * Mark the PCI region associated with PCI device @pdev BR @bar as
1666 * being reserved by owner @res_name. Do not access any
1667 * address inside the PCI regions unless this call returns
1668 * successfully.
1669 *
1670 * Returns 0 on success, or %EBUSY on error. A warning
1671 * message is also printed on failure.
1672 *
1673 * The key difference that _exclusive makes it that userspace is
1674 * explicitly not allowed to map the resource via /dev/mem or
1675 * sysfs.
1676 */
1677int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
1678{
1679 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
1680}
1681/**
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001682 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1683 * @pdev: PCI device whose resources were previously reserved
1684 * @bars: Bitmask of BARs to be released
1685 *
1686 * Release selected PCI I/O and memory resources previously reserved.
1687 * Call this function only after all use of the PCI regions has ceased.
1688 */
1689void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1690{
1691 int i;
1692
1693 for (i = 0; i < 6; i++)
1694 if (bars & (1 << i))
1695 pci_release_region(pdev, i);
1696}
1697
Arjan van de Vene8de1482008-10-22 19:55:31 -07001698int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
1699 const char *res_name, int excl)
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001700{
1701 int i;
1702
1703 for (i = 0; i < 6; i++)
1704 if (bars & (1 << i))
Arjan van de Vene8de1482008-10-22 19:55:31 -07001705 if (__pci_request_region(pdev, i, res_name, excl))
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001706 goto err_out;
1707 return 0;
1708
1709err_out:
1710 while(--i >= 0)
1711 if (bars & (1 << i))
1712 pci_release_region(pdev, i);
1713
1714 return -EBUSY;
1715}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001716
Arjan van de Vene8de1482008-10-22 19:55:31 -07001717
1718/**
1719 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1720 * @pdev: PCI device whose resources are to be reserved
1721 * @bars: Bitmask of BARs to be requested
1722 * @res_name: Name to be associated with resource
1723 */
1724int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1725 const char *res_name)
1726{
1727 return __pci_request_selected_regions(pdev, bars, res_name, 0);
1728}
1729
1730int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
1731 int bars, const char *res_name)
1732{
1733 return __pci_request_selected_regions(pdev, bars, res_name,
1734 IORESOURCE_EXCLUSIVE);
1735}
1736
Linus Torvalds1da177e2005-04-16 15:20:36 -07001737/**
1738 * pci_release_regions - Release reserved PCI I/O and memory resources
1739 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1740 *
1741 * Releases all PCI I/O and memory resources previously reserved by a
1742 * successful call to pci_request_regions. Call this function only
1743 * after all use of the PCI regions has ceased.
1744 */
1745
1746void pci_release_regions(struct pci_dev *pdev)
1747{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001748 pci_release_selected_regions(pdev, (1 << 6) - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001749}
1750
1751/**
1752 * pci_request_regions - Reserved PCI I/O and memory resources
1753 * @pdev: PCI device whose resources are to be reserved
1754 * @res_name: Name to be associated with resource.
1755 *
1756 * Mark all PCI regions associated with PCI device @pdev as
1757 * being reserved by owner @res_name. Do not access any
1758 * address inside the PCI regions unless this call returns
1759 * successfully.
1760 *
1761 * Returns 0 on success, or %EBUSY on error. A warning
1762 * message is also printed on failure.
1763 */
Jeff Garzik3c990e92006-03-04 21:52:42 -05001764int pci_request_regions(struct pci_dev *pdev, const char *res_name)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001765{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001766 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001767}
1768
1769/**
Arjan van de Vene8de1482008-10-22 19:55:31 -07001770 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1771 * @pdev: PCI device whose resources are to be reserved
1772 * @res_name: Name to be associated with resource.
1773 *
1774 * Mark all PCI regions associated with PCI device @pdev as
1775 * being reserved by owner @res_name. Do not access any
1776 * address inside the PCI regions unless this call returns
1777 * successfully.
1778 *
1779 * pci_request_regions_exclusive() will mark the region so that
1780 * /dev/mem and the sysfs MMIO access will not be allowed.
1781 *
1782 * Returns 0 on success, or %EBUSY on error. A warning
1783 * message is also printed on failure.
1784 */
1785int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
1786{
1787 return pci_request_selected_regions_exclusive(pdev,
1788 ((1 << 6) - 1), res_name);
1789}
1790
Ben Hutchings6a479072008-12-23 03:08:29 +00001791static void __pci_set_master(struct pci_dev *dev, bool enable)
1792{
1793 u16 old_cmd, cmd;
1794
1795 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
1796 if (enable)
1797 cmd = old_cmd | PCI_COMMAND_MASTER;
1798 else
1799 cmd = old_cmd & ~PCI_COMMAND_MASTER;
1800 if (cmd != old_cmd) {
1801 dev_dbg(&dev->dev, "%s bus mastering\n",
1802 enable ? "enabling" : "disabling");
1803 pci_write_config_word(dev, PCI_COMMAND, cmd);
1804 }
1805 dev->is_busmaster = enable;
1806}
Arjan van de Vene8de1482008-10-22 19:55:31 -07001807
1808/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001809 * pci_set_master - enables bus-mastering for device dev
1810 * @dev: the PCI device to enable
1811 *
1812 * Enables bus-mastering on the device and calls pcibios_set_master()
1813 * to do the needed arch specific settings.
1814 */
Ben Hutchings6a479072008-12-23 03:08:29 +00001815void pci_set_master(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001816{
Ben Hutchings6a479072008-12-23 03:08:29 +00001817 __pci_set_master(dev, true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001818 pcibios_set_master(dev);
1819}
1820
Ben Hutchings6a479072008-12-23 03:08:29 +00001821/**
1822 * pci_clear_master - disables bus-mastering for device dev
1823 * @dev: the PCI device to disable
1824 */
1825void pci_clear_master(struct pci_dev *dev)
1826{
1827 __pci_set_master(dev, false);
1828}
1829
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001830#ifdef PCI_DISABLE_MWI
1831int pci_set_mwi(struct pci_dev *dev)
1832{
1833 return 0;
1834}
1835
Randy Dunlap694625c2007-07-09 11:55:54 -07001836int pci_try_set_mwi(struct pci_dev *dev)
1837{
1838 return 0;
1839}
1840
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001841void pci_clear_mwi(struct pci_dev *dev)
1842{
1843}
1844
1845#else
Matthew Wilcoxebf5a242006-10-10 08:01:20 -06001846
1847#ifndef PCI_CACHE_LINE_BYTES
1848#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1849#endif
1850
Linus Torvalds1da177e2005-04-16 15:20:36 -07001851/* This can be overridden by arch code. */
Matthew Wilcoxebf5a242006-10-10 08:01:20 -06001852/* Don't forget this is measured in 32-bit words, not bytes */
1853u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001854
1855/**
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001856 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1857 * @dev: the PCI device for which MWI is to be enabled
Linus Torvalds1da177e2005-04-16 15:20:36 -07001858 *
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001859 * Helper function for pci_set_mwi.
1860 * Originally copied from drivers/net/acenic.c.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001861 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1862 *
1863 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1864 */
1865static int
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001866pci_set_cacheline_size(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001867{
1868 u8 cacheline_size;
1869
1870 if (!pci_cache_line_size)
1871 return -EINVAL; /* The system doesn't support MWI. */
1872
1873 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1874 equal to or multiple of the right value. */
1875 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1876 if (cacheline_size >= pci_cache_line_size &&
1877 (cacheline_size % pci_cache_line_size) == 0)
1878 return 0;
1879
1880 /* Write the correct value. */
1881 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1882 /* Read it back. */
1883 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1884 if (cacheline_size == pci_cache_line_size)
1885 return 0;
1886
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001887 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
1888 "supported\n", pci_cache_line_size << 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001889
1890 return -EINVAL;
1891}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001892
1893/**
1894 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1895 * @dev: the PCI device for which MWI is enabled
1896 *
Randy Dunlap694625c2007-07-09 11:55:54 -07001897 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001898 *
1899 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1900 */
1901int
1902pci_set_mwi(struct pci_dev *dev)
1903{
1904 int rc;
1905 u16 cmd;
1906
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001907 rc = pci_set_cacheline_size(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001908 if (rc)
1909 return rc;
1910
1911 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1912 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001913 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001914 cmd |= PCI_COMMAND_INVALIDATE;
1915 pci_write_config_word(dev, PCI_COMMAND, cmd);
1916 }
1917
1918 return 0;
1919}
1920
1921/**
Randy Dunlap694625c2007-07-09 11:55:54 -07001922 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1923 * @dev: the PCI device for which MWI is enabled
1924 *
1925 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1926 * Callers are not required to check the return value.
1927 *
1928 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1929 */
1930int pci_try_set_mwi(struct pci_dev *dev)
1931{
1932 int rc = pci_set_mwi(dev);
1933 return rc;
1934}
1935
1936/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001937 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1938 * @dev: the PCI device to disable
1939 *
1940 * Disables PCI Memory-Write-Invalidate transaction on the device
1941 */
1942void
1943pci_clear_mwi(struct pci_dev *dev)
1944{
1945 u16 cmd;
1946
1947 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1948 if (cmd & PCI_COMMAND_INVALIDATE) {
1949 cmd &= ~PCI_COMMAND_INVALIDATE;
1950 pci_write_config_word(dev, PCI_COMMAND, cmd);
1951 }
1952}
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001953#endif /* ! PCI_DISABLE_MWI */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001954
Brett M Russa04ce0f2005-08-15 15:23:41 -04001955/**
1956 * pci_intx - enables/disables PCI INTx for device dev
Randy Dunlap8f7020d2005-10-23 11:57:38 -07001957 * @pdev: the PCI device to operate on
1958 * @enable: boolean: whether to enable or disable PCI INTx
Brett M Russa04ce0f2005-08-15 15:23:41 -04001959 *
1960 * Enables/disables PCI INTx for device dev
1961 */
1962void
1963pci_intx(struct pci_dev *pdev, int enable)
1964{
1965 u16 pci_command, new;
1966
1967 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1968
1969 if (enable) {
1970 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1971 } else {
1972 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1973 }
1974
1975 if (new != pci_command) {
Tejun Heo9ac78492007-01-20 16:00:26 +09001976 struct pci_devres *dr;
1977
Brett M Russ2fd9d742005-09-09 10:02:22 -07001978 pci_write_config_word(pdev, PCI_COMMAND, new);
Tejun Heo9ac78492007-01-20 16:00:26 +09001979
1980 dr = find_pci_dr(pdev);
1981 if (dr && !dr->restore_intx) {
1982 dr->restore_intx = 1;
1983 dr->orig_intx = !enable;
1984 }
Brett M Russa04ce0f2005-08-15 15:23:41 -04001985 }
1986}
1987
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08001988/**
1989 * pci_msi_off - disables any msi or msix capabilities
Randy Dunlap8d7d86e2007-03-16 19:55:52 -07001990 * @dev: the PCI device to operate on
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08001991 *
1992 * If you want to use msi see pci_enable_msi and friends.
1993 * This is a lower level primitive that allows us to disable
1994 * msi operation at the device level.
1995 */
1996void pci_msi_off(struct pci_dev *dev)
1997{
1998 int pos;
1999 u16 control;
2000
2001 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2002 if (pos) {
2003 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2004 control &= ~PCI_MSI_FLAGS_ENABLE;
2005 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2006 }
2007 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2008 if (pos) {
2009 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2010 control &= ~PCI_MSIX_FLAGS_ENABLE;
2011 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2012 }
2013}
2014
Linus Torvalds1da177e2005-04-16 15:20:36 -07002015#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
2016/*
2017 * These can be overridden by arch-specific implementations
2018 */
2019int
2020pci_set_dma_mask(struct pci_dev *dev, u64 mask)
2021{
2022 if (!pci_dma_supported(dev, mask))
2023 return -EIO;
2024
2025 dev->dma_mask = mask;
2026
2027 return 0;
2028}
2029
2030int
Linus Torvalds1da177e2005-04-16 15:20:36 -07002031pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
2032{
2033 if (!pci_dma_supported(dev, mask))
2034 return -EIO;
2035
2036 dev->dev.coherent_dma_mask = mask;
2037
2038 return 0;
2039}
2040#endif
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002041
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08002042#ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2043int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2044{
2045 return dma_set_max_seg_size(&dev->dev, size);
2046}
2047EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2048#endif
2049
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -08002050#ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2051int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2052{
2053 return dma_set_seg_boundary(&dev->dev, mask);
2054}
2055EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2056#endif
2057
Sheng Yangd91cdc72008-11-11 17:17:47 +08002058static int __pcie_flr(struct pci_dev *dev, int probe)
Sheng Yang8dd7f802008-10-21 17:38:25 +08002059{
2060 u16 status;
2061 u32 cap;
2062 int exppos = pci_find_capability(dev, PCI_CAP_ID_EXP);
2063
2064 if (!exppos)
2065 return -ENOTTY;
2066 pci_read_config_dword(dev, exppos + PCI_EXP_DEVCAP, &cap);
2067 if (!(cap & PCI_EXP_DEVCAP_FLR))
2068 return -ENOTTY;
2069
Sheng Yangd91cdc72008-11-11 17:17:47 +08002070 if (probe)
2071 return 0;
2072
Sheng Yang8dd7f802008-10-21 17:38:25 +08002073 pci_block_user_cfg_access(dev);
2074
2075 /* Wait for Transaction Pending bit clean */
Sheng Yang5fe5db02009-02-09 14:53:47 +08002076 pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status);
2077 if (!(status & PCI_EXP_DEVSTA_TRPND))
2078 goto transaction_done;
2079
Sheng Yang8dd7f802008-10-21 17:38:25 +08002080 msleep(100);
2081 pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status);
Sheng Yang5fe5db02009-02-09 14:53:47 +08002082 if (!(status & PCI_EXP_DEVSTA_TRPND))
2083 goto transaction_done;
Sheng Yang8dd7f802008-10-21 17:38:25 +08002084
Sheng Yang5fe5db02009-02-09 14:53:47 +08002085 dev_info(&dev->dev, "Busy after 100ms while trying to reset; "
2086 "sleeping for 1 second\n");
2087 ssleep(1);
2088 pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status);
2089 if (status & PCI_EXP_DEVSTA_TRPND)
2090 dev_info(&dev->dev, "Still busy after 1s; "
2091 "proceeding with reset anyway\n");
2092
2093transaction_done:
Sheng Yang8dd7f802008-10-21 17:38:25 +08002094 pci_write_config_word(dev, exppos + PCI_EXP_DEVCTL,
2095 PCI_EXP_DEVCTL_BCR_FLR);
2096 mdelay(100);
2097
2098 pci_unblock_user_cfg_access(dev);
2099 return 0;
2100}
Sheng Yangd91cdc72008-11-11 17:17:47 +08002101
Sheng Yang1ca88792008-11-11 17:17:48 +08002102static int __pci_af_flr(struct pci_dev *dev, int probe)
2103{
2104 int cappos = pci_find_capability(dev, PCI_CAP_ID_AF);
2105 u8 status;
2106 u8 cap;
2107
2108 if (!cappos)
2109 return -ENOTTY;
2110 pci_read_config_byte(dev, cappos + PCI_AF_CAP, &cap);
2111 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2112 return -ENOTTY;
2113
2114 if (probe)
2115 return 0;
2116
2117 pci_block_user_cfg_access(dev);
2118
2119 /* Wait for Transaction Pending bit clean */
Sheng Yang5fe5db02009-02-09 14:53:47 +08002120 pci_read_config_byte(dev, cappos + PCI_AF_STATUS, &status);
2121 if (!(status & PCI_AF_STATUS_TP))
2122 goto transaction_done;
2123
Sheng Yang1ca88792008-11-11 17:17:48 +08002124 msleep(100);
2125 pci_read_config_byte(dev, cappos + PCI_AF_STATUS, &status);
Sheng Yang5fe5db02009-02-09 14:53:47 +08002126 if (!(status & PCI_AF_STATUS_TP))
2127 goto transaction_done;
2128
2129 dev_info(&dev->dev, "Busy after 100ms while trying to"
2130 " reset; sleeping for 1 second\n");
2131 ssleep(1);
2132 pci_read_config_byte(dev, cappos + PCI_AF_STATUS, &status);
2133 if (status & PCI_AF_STATUS_TP)
2134 dev_info(&dev->dev, "Still busy after 1s; "
2135 "proceeding with reset anyway\n");
2136
2137transaction_done:
Sheng Yang1ca88792008-11-11 17:17:48 +08002138 pci_write_config_byte(dev, cappos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2139 mdelay(100);
2140
2141 pci_unblock_user_cfg_access(dev);
2142 return 0;
2143}
2144
Sheng Yangd91cdc72008-11-11 17:17:47 +08002145static int __pci_reset_function(struct pci_dev *pdev, int probe)
2146{
2147 int res;
2148
2149 res = __pcie_flr(pdev, probe);
2150 if (res != -ENOTTY)
2151 return res;
2152
Sheng Yang1ca88792008-11-11 17:17:48 +08002153 res = __pci_af_flr(pdev, probe);
2154 if (res != -ENOTTY)
2155 return res;
2156
Sheng Yangd91cdc72008-11-11 17:17:47 +08002157 return res;
2158}
2159
2160/**
2161 * pci_execute_reset_function() - Reset a PCI device function
2162 * @dev: Device function to reset
2163 *
2164 * Some devices allow an individual function to be reset without affecting
2165 * other functions in the same device. The PCI device must be responsive
2166 * to PCI config space in order to use this function.
2167 *
2168 * The device function is presumed to be unused when this function is called.
2169 * Resetting the device will make the contents of PCI configuration space
2170 * random, so any caller of this must be prepared to reinitialise the
2171 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2172 * etc.
2173 *
2174 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2175 * device doesn't support resetting a single function.
2176 */
2177int pci_execute_reset_function(struct pci_dev *dev)
2178{
2179 return __pci_reset_function(dev, 0);
2180}
Sheng Yang8dd7f802008-10-21 17:38:25 +08002181EXPORT_SYMBOL_GPL(pci_execute_reset_function);
2182
2183/**
2184 * pci_reset_function() - quiesce and reset a PCI device function
2185 * @dev: Device function to reset
2186 *
2187 * Some devices allow an individual function to be reset without affecting
2188 * other functions in the same device. The PCI device must be responsive
2189 * to PCI config space in order to use this function.
2190 *
2191 * This function does not just reset the PCI portion of a device, but
2192 * clears all the state associated with the device. This function differs
2193 * from pci_execute_reset_function in that it saves and restores device state
2194 * over the reset.
2195 *
2196 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2197 * device doesn't support resetting a single function.
2198 */
2199int pci_reset_function(struct pci_dev *dev)
2200{
Sheng Yangd91cdc72008-11-11 17:17:47 +08002201 int r = __pci_reset_function(dev, 1);
Sheng Yang8dd7f802008-10-21 17:38:25 +08002202
Sheng Yangd91cdc72008-11-11 17:17:47 +08002203 if (r < 0)
2204 return r;
Sheng Yang8dd7f802008-10-21 17:38:25 +08002205
Sheng Yang1df8fb32008-11-11 17:17:45 +08002206 if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0)
Sheng Yang8dd7f802008-10-21 17:38:25 +08002207 disable_irq(dev->irq);
2208 pci_save_state(dev);
2209
2210 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2211
2212 r = pci_execute_reset_function(dev);
2213
2214 pci_restore_state(dev);
Sheng Yang1df8fb32008-11-11 17:17:45 +08002215 if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0)
Sheng Yang8dd7f802008-10-21 17:38:25 +08002216 enable_irq(dev->irq);
2217
2218 return r;
2219}
2220EXPORT_SYMBOL_GPL(pci_reset_function);
2221
2222/**
Peter Orubad556ad42007-05-15 13:59:13 +02002223 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2224 * @dev: PCI device to query
2225 *
2226 * Returns mmrbc: maximum designed memory read count in bytes
2227 * or appropriate error value.
2228 */
2229int pcix_get_max_mmrbc(struct pci_dev *dev)
2230{
Andrew Mortonb7b095c2007-07-09 11:55:50 -07002231 int err, cap;
Peter Orubad556ad42007-05-15 13:59:13 +02002232 u32 stat;
2233
2234 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2235 if (!cap)
2236 return -EINVAL;
2237
2238 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2239 if (err)
2240 return -EINVAL;
2241
Andrew Mortonb7b095c2007-07-09 11:55:50 -07002242 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
Peter Orubad556ad42007-05-15 13:59:13 +02002243}
2244EXPORT_SYMBOL(pcix_get_max_mmrbc);
2245
2246/**
2247 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2248 * @dev: PCI device to query
2249 *
2250 * Returns mmrbc: maximum memory read count in bytes
2251 * or appropriate error value.
2252 */
2253int pcix_get_mmrbc(struct pci_dev *dev)
2254{
2255 int ret, cap;
2256 u32 cmd;
2257
2258 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2259 if (!cap)
2260 return -EINVAL;
2261
2262 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2263 if (!ret)
2264 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2265
2266 return ret;
2267}
2268EXPORT_SYMBOL(pcix_get_mmrbc);
2269
2270/**
2271 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2272 * @dev: PCI device to query
2273 * @mmrbc: maximum memory read count in bytes
2274 * valid values are 512, 1024, 2048, 4096
2275 *
2276 * If possible sets maximum memory read byte count, some bridges have erratas
2277 * that prevent this.
2278 */
2279int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2280{
2281 int cap, err = -EINVAL;
2282 u32 stat, cmd, v, o;
2283
vignesh babu229f5af2007-08-13 18:23:14 +05302284 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
Peter Orubad556ad42007-05-15 13:59:13 +02002285 goto out;
2286
2287 v = ffs(mmrbc) - 10;
2288
2289 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2290 if (!cap)
2291 goto out;
2292
2293 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2294 if (err)
2295 goto out;
2296
2297 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2298 return -E2BIG;
2299
2300 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2301 if (err)
2302 goto out;
2303
2304 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2305 if (o != v) {
2306 if (v > o && dev->bus &&
2307 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2308 return -EIO;
2309
2310 cmd &= ~PCI_X_CMD_MAX_READ;
2311 cmd |= v << 2;
2312 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
2313 }
2314out:
2315 return err;
2316}
2317EXPORT_SYMBOL(pcix_set_mmrbc);
2318
2319/**
2320 * pcie_get_readrq - get PCI Express read request size
2321 * @dev: PCI device to query
2322 *
2323 * Returns maximum memory read request in bytes
2324 * or appropriate error value.
2325 */
2326int pcie_get_readrq(struct pci_dev *dev)
2327{
2328 int ret, cap;
2329 u16 ctl;
2330
2331 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
2332 if (!cap)
2333 return -EINVAL;
2334
2335 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2336 if (!ret)
2337 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2338
2339 return ret;
2340}
2341EXPORT_SYMBOL(pcie_get_readrq);
2342
2343/**
2344 * pcie_set_readrq - set PCI Express maximum memory read request
2345 * @dev: PCI device to query
Randy Dunlap42e61f42007-07-23 21:42:11 -07002346 * @rq: maximum memory read count in bytes
Peter Orubad556ad42007-05-15 13:59:13 +02002347 * valid values are 128, 256, 512, 1024, 2048, 4096
2348 *
2349 * If possible sets maximum read byte count
2350 */
2351int pcie_set_readrq(struct pci_dev *dev, int rq)
2352{
2353 int cap, err = -EINVAL;
2354 u16 ctl, v;
2355
vignesh babu229f5af2007-08-13 18:23:14 +05302356 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
Peter Orubad556ad42007-05-15 13:59:13 +02002357 goto out;
2358
2359 v = (ffs(rq) - 8) << 12;
2360
2361 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
2362 if (!cap)
2363 goto out;
2364
2365 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2366 if (err)
2367 goto out;
2368
2369 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2370 ctl &= ~PCI_EXP_DEVCTL_READRQ;
2371 ctl |= v;
2372 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2373 }
2374
2375out:
2376 return err;
2377}
2378EXPORT_SYMBOL(pcie_set_readrq);
2379
2380/**
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002381 * pci_select_bars - Make BAR mask from the type of resource
Randy Dunlapf95d8822007-02-10 14:41:56 -08002382 * @dev: the PCI device for which BAR mask is made
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002383 * @flags: resource type mask to be selected
2384 *
2385 * This helper routine makes bar mask from the type of resource.
2386 */
2387int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2388{
2389 int i, bars = 0;
2390 for (i = 0; i < PCI_NUM_RESOURCES; i++)
2391 if (pci_resource_flags(dev, i) & flags)
2392 bars |= (1 << i);
2393 return bars;
2394}
2395
Yu Zhao613e7ed2008-11-22 02:41:27 +08002396/**
2397 * pci_resource_bar - get position of the BAR associated with a resource
2398 * @dev: the PCI device
2399 * @resno: the resource number
2400 * @type: the BAR type to be filled in
2401 *
2402 * Returns BAR position in config space, or 0 if the BAR is invalid.
2403 */
2404int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2405{
Yu Zhaod1b054d2009-03-20 11:25:11 +08002406 int reg;
2407
Yu Zhao613e7ed2008-11-22 02:41:27 +08002408 if (resno < PCI_ROM_RESOURCE) {
2409 *type = pci_bar_unknown;
2410 return PCI_BASE_ADDRESS_0 + 4 * resno;
2411 } else if (resno == PCI_ROM_RESOURCE) {
2412 *type = pci_bar_mem32;
2413 return dev->rom_base_reg;
Yu Zhaod1b054d2009-03-20 11:25:11 +08002414 } else if (resno < PCI_BRIDGE_RESOURCES) {
2415 /* device specific resource */
2416 reg = pci_iov_resource_bar(dev, resno, type);
2417 if (reg)
2418 return reg;
Yu Zhao613e7ed2008-11-22 02:41:27 +08002419 }
2420
2421 dev_err(&dev->dev, "BAR: invalid resource #%d\n", resno);
2422 return 0;
2423}
2424
Yuji Shimada32a9a6822009-03-16 17:13:39 +09002425#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2426static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
2427spinlock_t resource_alignment_lock = SPIN_LOCK_UNLOCKED;
2428
2429/**
2430 * pci_specified_resource_alignment - get resource alignment specified by user.
2431 * @dev: the PCI device to get
2432 *
2433 * RETURNS: Resource alignment if it is specified.
2434 * Zero if it is not specified.
2435 */
2436resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
2437{
2438 int seg, bus, slot, func, align_order, count;
2439 resource_size_t align = 0;
2440 char *p;
2441
2442 spin_lock(&resource_alignment_lock);
2443 p = resource_alignment_param;
2444 while (*p) {
2445 count = 0;
2446 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
2447 p[count] == '@') {
2448 p += count + 1;
2449 } else {
2450 align_order = -1;
2451 }
2452 if (sscanf(p, "%x:%x:%x.%x%n",
2453 &seg, &bus, &slot, &func, &count) != 4) {
2454 seg = 0;
2455 if (sscanf(p, "%x:%x.%x%n",
2456 &bus, &slot, &func, &count) != 3) {
2457 /* Invalid format */
2458 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
2459 p);
2460 break;
2461 }
2462 }
2463 p += count;
2464 if (seg == pci_domain_nr(dev->bus) &&
2465 bus == dev->bus->number &&
2466 slot == PCI_SLOT(dev->devfn) &&
2467 func == PCI_FUNC(dev->devfn)) {
2468 if (align_order == -1) {
2469 align = PAGE_SIZE;
2470 } else {
2471 align = 1 << align_order;
2472 }
2473 /* Found */
2474 break;
2475 }
2476 if (*p != ';' && *p != ',') {
2477 /* End of param or invalid format */
2478 break;
2479 }
2480 p++;
2481 }
2482 spin_unlock(&resource_alignment_lock);
2483 return align;
2484}
2485
2486/**
2487 * pci_is_reassigndev - check if specified PCI is target device to reassign
2488 * @dev: the PCI device to check
2489 *
2490 * RETURNS: non-zero for PCI device is a target device to reassign,
2491 * or zero is not.
2492 */
2493int pci_is_reassigndev(struct pci_dev *dev)
2494{
2495 return (pci_specified_resource_alignment(dev) != 0);
2496}
2497
2498ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
2499{
2500 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
2501 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
2502 spin_lock(&resource_alignment_lock);
2503 strncpy(resource_alignment_param, buf, count);
2504 resource_alignment_param[count] = '\0';
2505 spin_unlock(&resource_alignment_lock);
2506 return count;
2507}
2508
2509ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
2510{
2511 size_t count;
2512 spin_lock(&resource_alignment_lock);
2513 count = snprintf(buf, size, "%s", resource_alignment_param);
2514 spin_unlock(&resource_alignment_lock);
2515 return count;
2516}
2517
2518static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
2519{
2520 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
2521}
2522
2523static ssize_t pci_resource_alignment_store(struct bus_type *bus,
2524 const char *buf, size_t count)
2525{
2526 return pci_set_resource_alignment_param(buf, count);
2527}
2528
2529BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
2530 pci_resource_alignment_store);
2531
2532static int __init pci_resource_alignment_sysfs_init(void)
2533{
2534 return bus_create_file(&pci_bus_type,
2535 &bus_attr_resource_alignment);
2536}
2537
2538late_initcall(pci_resource_alignment_sysfs_init);
2539
Jeff Garzik32a2eea2007-10-11 16:57:27 -04002540static void __devinit pci_no_domains(void)
2541{
2542#ifdef CONFIG_PCI_DOMAINS
2543 pci_domains_supported = 0;
2544#endif
2545}
2546
Andrew Patterson0ef5f8f2008-11-10 15:30:50 -07002547/**
2548 * pci_ext_cfg_enabled - can we access extended PCI config space?
2549 * @dev: The PCI device of the root bridge.
2550 *
2551 * Returns 1 if we can access PCI extended config space (offsets
2552 * greater than 0xff). This is the default implementation. Architecture
2553 * implementations can override this.
2554 */
2555int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
2556{
2557 return 1;
2558}
2559
Linus Torvalds1da177e2005-04-16 15:20:36 -07002560static int __devinit pci_init(void)
2561{
2562 struct pci_dev *dev = NULL;
2563
2564 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2565 pci_fixup_device(pci_fixup_final, dev);
2566 }
Taku Izumid389fec2008-10-17 13:52:51 +09002567
Linus Torvalds1da177e2005-04-16 15:20:36 -07002568 return 0;
2569}
2570
Al Viroad04d312008-11-22 17:37:14 +00002571static int __init pci_setup(char *str)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002572{
2573 while (str) {
2574 char *k = strchr(str, ',');
2575 if (k)
2576 *k++ = 0;
2577 if (*str && (str = pcibios_setup(str)) && *str) {
Matthew Wilcox309e57d2006-03-05 22:33:34 -07002578 if (!strcmp(str, "nomsi")) {
2579 pci_no_msi();
Randy Dunlap7f785762007-10-05 13:17:58 -07002580 } else if (!strcmp(str, "noaer")) {
2581 pci_no_aer();
Jeff Garzik32a2eea2007-10-11 16:57:27 -04002582 } else if (!strcmp(str, "nodomains")) {
2583 pci_no_domains();
Atsushi Nemoto4516a612007-02-05 16:36:06 -08002584 } else if (!strncmp(str, "cbiosize=", 9)) {
2585 pci_cardbus_io_size = memparse(str + 9, &str);
2586 } else if (!strncmp(str, "cbmemsize=", 10)) {
2587 pci_cardbus_mem_size = memparse(str + 10, &str);
Yuji Shimada32a9a6822009-03-16 17:13:39 +09002588 } else if (!strncmp(str, "resource_alignment=", 19)) {
2589 pci_set_resource_alignment_param(str + 19,
2590 strlen(str + 19));
Andrew Patterson43c16402009-04-22 16:52:09 -06002591 } else if (!strncmp(str, "ecrc=", 5)) {
2592 pcie_ecrc_get_policy(str + 5);
Matthew Wilcox309e57d2006-03-05 22:33:34 -07002593 } else {
2594 printk(KERN_ERR "PCI: Unknown option `%s'\n",
2595 str);
2596 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002597 }
2598 str = k;
2599 }
Andi Kleen0637a702006-09-26 10:52:41 +02002600 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002601}
Andi Kleen0637a702006-09-26 10:52:41 +02002602early_param("pci", pci_setup);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002603
2604device_initcall(pci_init);
2605
Tejun Heo0b62e132007-07-27 14:43:35 +09002606EXPORT_SYMBOL(pci_reenable_device);
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11002607EXPORT_SYMBOL(pci_enable_device_io);
2608EXPORT_SYMBOL(pci_enable_device_mem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002609EXPORT_SYMBOL(pci_enable_device);
Tejun Heo9ac78492007-01-20 16:00:26 +09002610EXPORT_SYMBOL(pcim_enable_device);
2611EXPORT_SYMBOL(pcim_pin_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002612EXPORT_SYMBOL(pci_disable_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002613EXPORT_SYMBOL(pci_find_capability);
2614EXPORT_SYMBOL(pci_bus_find_capability);
2615EXPORT_SYMBOL(pci_release_regions);
2616EXPORT_SYMBOL(pci_request_regions);
Arjan van de Vene8de1482008-10-22 19:55:31 -07002617EXPORT_SYMBOL(pci_request_regions_exclusive);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002618EXPORT_SYMBOL(pci_release_region);
2619EXPORT_SYMBOL(pci_request_region);
Arjan van de Vene8de1482008-10-22 19:55:31 -07002620EXPORT_SYMBOL(pci_request_region_exclusive);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002621EXPORT_SYMBOL(pci_release_selected_regions);
2622EXPORT_SYMBOL(pci_request_selected_regions);
Arjan van de Vene8de1482008-10-22 19:55:31 -07002623EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002624EXPORT_SYMBOL(pci_set_master);
Ben Hutchings6a479072008-12-23 03:08:29 +00002625EXPORT_SYMBOL(pci_clear_master);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002626EXPORT_SYMBOL(pci_set_mwi);
Randy Dunlap694625c2007-07-09 11:55:54 -07002627EXPORT_SYMBOL(pci_try_set_mwi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002628EXPORT_SYMBOL(pci_clear_mwi);
Brett M Russa04ce0f2005-08-15 15:23:41 -04002629EXPORT_SYMBOL_GPL(pci_intx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002630EXPORT_SYMBOL(pci_set_dma_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002631EXPORT_SYMBOL(pci_set_consistent_dma_mask);
2632EXPORT_SYMBOL(pci_assign_resource);
2633EXPORT_SYMBOL(pci_find_parent_resource);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002634EXPORT_SYMBOL(pci_select_bars);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002635
2636EXPORT_SYMBOL(pci_set_power_state);
2637EXPORT_SYMBOL(pci_save_state);
2638EXPORT_SYMBOL(pci_restore_state);
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02002639EXPORT_SYMBOL(pci_pme_capable);
Rafael J. Wysocki5a6c9b62008-08-08 00:14:24 +02002640EXPORT_SYMBOL(pci_pme_active);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002641EXPORT_SYMBOL(pci_enable_wake);
Rafael J. Wysocki0235c4f2008-08-18 21:38:00 +02002642EXPORT_SYMBOL(pci_wake_from_d3);
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02002643EXPORT_SYMBOL(pci_target_state);
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02002644EXPORT_SYMBOL(pci_prepare_to_sleep);
2645EXPORT_SYMBOL(pci_back_from_sleep);
Brian Kingf7bdd122007-04-06 16:39:36 -05002646EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002647