| Murali Karicheri | 0c4ffcf | 2014-09-02 17:26:19 -0600 | [diff] [blame] | 1 | TI Keystone PCIe interface |
| 2 | |
| 3 | Keystone PCI host Controller is based on Designware PCI h/w version 3.65. |
| 4 | It shares common functions with PCIe Designware core driver and inherit |
| 5 | common properties defined in |
| 6 | Documentation/devicetree/bindings/pci/designware-pci.txt |
| 7 | |
| 8 | Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt |
| 9 | for the details of Designware DT bindings. Additional properties are |
| 10 | described here as well as properties that are not applicable. |
| 11 | |
| 12 | Required Properties:- |
| 13 | |
| 14 | compatibility: "ti,keystone-pcie" |
| 15 | reg: index 1 is the base address and length of DW application registers. |
| 16 | index 2 is the base address and length of PCI mode configuration |
| 17 | register. |
| 18 | index 3 is the base address and length of PCI device ID register. |
| 19 | |
| 20 | pcie_msi_intc : Interrupt controller device node for MSI IRQ chip |
| 21 | interrupt-cells: should be set to 1 |
| 22 | interrupt-parent: Parent interrupt controller phandle |
| 23 | interrupts: GIC interrupt lines connected to PCI MSI interrupt lines |
| 24 | |
| 25 | Example: |
| 26 | pcie_msi_intc: msi-interrupt-controller { |
| 27 | interrupt-controller; |
| 28 | #interrupt-cells = <1>; |
| 29 | interrupt-parent = <&gic>; |
| 30 | interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, |
| 31 | <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, |
| 32 | <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, |
| 33 | <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, |
| 34 | <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, |
| 35 | <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, |
| 36 | <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, |
| 37 | <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>; |
| 38 | }; |
| 39 | |
| 40 | pcie_intc: Interrupt controller device node for Legacy IRQ chip |
| 41 | interrupt-cells: should be set to 1 |
| 42 | interrupt-parent: Parent interrupt controller phandle |
| 43 | interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines |
| 44 | |
| 45 | Example: |
| 46 | pcie_intc: legacy-interrupt-controller { |
| 47 | interrupt-controller; |
| 48 | #interrupt-cells = <1>; |
| 49 | interrupt-parent = <&gic>; |
| 50 | interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, |
| 51 | <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, |
| 52 | <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, |
| 53 | <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>; |
| 54 | }; |
| 55 | |
| 56 | Optional properties:- |
| 57 | phys: phandle to Generic Keystone SerDes phy for PCI |
| 58 | phy-names: name of the Generic Keystine SerDes phy for PCI |
| 59 | - If boot loader already does PCI link establishment, then phys and |
| 60 | phy-names shouldn't be present. |
| 61 | |
| 62 | Designware DT Properties not applicable for Keystone PCI |
| 63 | |
| 64 | 1. pcie_bus clock-names not used. Instead, a phandle to phys is used. |
| 65 | |