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Dinh Nguyencfda5902012-07-11 15:13:16 -05001/*
2 * Copyright (C) 2012 Altera Corporation
3 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
4 *
5 * Modified from mach-picoxcell/time.c
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
Jisheng Zhang9115df82015-11-05 10:32:06 +080019#include <linux/delay.h>
Dinh Nguyencfda5902012-07-11 15:13:16 -050020#include <linux/dw_apb_timer.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
Heiko Stuebnera8b447f2013-06-04 11:37:36 +020024#include <linux/clk.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070025#include <linux/sched_clock.h>
Dinh Nguyencfda5902012-07-11 15:13:16 -050026
Uwe Kleine-König1cf02032013-10-01 10:38:12 +020027static void __init timer_get_base_and_rate(struct device_node *np,
Dinh Nguyencfda5902012-07-11 15:13:16 -050028 void __iomem **base, u32 *rate)
29{
Heiko Stuebnera8b447f2013-06-04 11:37:36 +020030 struct clk *timer_clk;
31 struct clk *pclk;
32
Dinh Nguyencfda5902012-07-11 15:13:16 -050033 *base = of_iomap(np, 0);
34
35 if (!*base)
36 panic("Unable to map regs for %s", np->name);
37
Heiko Stuebnera8b447f2013-06-04 11:37:36 +020038 /*
39 * Not all implementations use a periphal clock, so don't panic
40 * if it's not present
41 */
42 pclk = of_clk_get_by_name(np, "pclk");
43 if (!IS_ERR(pclk))
44 if (clk_prepare_enable(pclk))
45 pr_warn("pclk for %s is present, but could not be activated\n",
46 np->name);
47
48 timer_clk = of_clk_get_by_name(np, "timer");
49 if (IS_ERR(timer_clk))
50 goto try_clock_freq;
51
52 if (!clk_prepare_enable(timer_clk)) {
53 *rate = clk_get_rate(timer_clk);
54 return;
55 }
56
57try_clock_freq:
Dinh Nguyencfda5902012-07-11 15:13:16 -050058 if (of_property_read_u32(np, "clock-freq", rate) &&
Uwe Kleine-König1cf02032013-10-01 10:38:12 +020059 of_property_read_u32(np, "clock-frequency", rate))
Heiko Stuebnera8b447f2013-06-04 11:37:36 +020060 panic("No clock nor clock-frequency property for %s", np->name);
Dinh Nguyencfda5902012-07-11 15:13:16 -050061}
62
Uwe Kleine-König1cf02032013-10-01 10:38:12 +020063static void __init add_clockevent(struct device_node *event_timer)
Dinh Nguyencfda5902012-07-11 15:13:16 -050064{
65 void __iomem *iobase;
66 struct dw_apb_clock_event_device *ced;
67 u32 irq, rate;
68
69 irq = irq_of_parse_and_map(event_timer, 0);
Baruch Siach1a33bd22013-05-29 10:11:17 +020070 if (irq == 0)
Dinh Nguyencfda5902012-07-11 15:13:16 -050071 panic("No IRQ for clock event timer");
72
73 timer_get_base_and_rate(event_timer, &iobase, &rate);
74
75 ced = dw_apb_clockevent_init(0, event_timer->name, 300, iobase, irq,
76 rate);
77 if (!ced)
78 panic("Unable to initialise clockevent device");
79
80 dw_apb_clockevent_register(ced);
81}
82
Heiko Stuebnera1198f82013-06-04 11:37:02 +020083static void __iomem *sched_io_base;
84static u32 sched_rate;
85
Uwe Kleine-König1cf02032013-10-01 10:38:12 +020086static void __init add_clocksource(struct device_node *source_timer)
Dinh Nguyencfda5902012-07-11 15:13:16 -050087{
88 void __iomem *iobase;
89 struct dw_apb_clocksource *cs;
90 u32 rate;
91
92 timer_get_base_and_rate(source_timer, &iobase, &rate);
93
94 cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);
95 if (!cs)
96 panic("Unable to initialise clocksource device");
97
98 dw_apb_clocksource_start(cs);
99 dw_apb_clocksource_register(cs);
Dinh Nguyencfda5902012-07-11 15:13:16 -0500100
Heiko Stuebnera1198f82013-06-04 11:37:02 +0200101 /*
102 * Fallback to use the clocksource as sched_clock if no separate
103 * timer is found. sched_io_base then points to the current_value
104 * register of the clocksource timer.
105 */
106 sched_io_base = iobase + 0x04;
107 sched_rate = rate;
108}
Dinh Nguyencfda5902012-07-11 15:13:16 -0500109
Yang Wei0d24d1f2014-05-13 11:10:08 +0800110static u64 notrace read_sched_clock(void)
Dinh Nguyencfda5902012-07-11 15:13:16 -0500111{
Ben Dooks3a100132015-03-30 22:17:12 +0200112 return ~readl_relaxed(sched_io_base);
Dinh Nguyencfda5902012-07-11 15:13:16 -0500113}
114
115static const struct of_device_id sptimer_ids[] __initconst = {
116 { .compatible = "picochip,pc3x2-rtc" },
Dinh Nguyencfda5902012-07-11 15:13:16 -0500117 { /* Sentinel */ },
118};
119
Uwe Kleine-König1cf02032013-10-01 10:38:12 +0200120static void __init init_sched_clock(void)
Dinh Nguyencfda5902012-07-11 15:13:16 -0500121{
122 struct device_node *sched_timer;
Dinh Nguyencfda5902012-07-11 15:13:16 -0500123
124 sched_timer = of_find_matching_node(NULL, sptimer_ids);
Heiko Stuebnera1198f82013-06-04 11:37:02 +0200125 if (sched_timer) {
126 timer_get_base_and_rate(sched_timer, &sched_io_base,
127 &sched_rate);
128 of_node_put(sched_timer);
129 }
Dinh Nguyencfda5902012-07-11 15:13:16 -0500130
Stephen Boydfa8296a2013-07-18 16:21:22 -0700131 sched_clock_register(read_sched_clock, 32, sched_rate);
Dinh Nguyencfda5902012-07-11 15:13:16 -0500132}
133
Jisheng Zhang9115df82015-11-05 10:32:06 +0800134#ifdef CONFIG_ARM
135static unsigned long dw_apb_delay_timer_read(void)
136{
137 return ~readl_relaxed(sched_io_base);
138}
139
140static struct delay_timer dw_apb_delay_timer = {
141 .read_current_timer = dw_apb_delay_timer_read,
142};
143#endif
144
Heiko Stuebner10021482013-06-04 11:38:42 +0200145static int num_called;
146static void __init dw_apb_timer_init(struct device_node *timer)
Dinh Nguyencfda5902012-07-11 15:13:16 -0500147{
Heiko Stuebner10021482013-06-04 11:38:42 +0200148 switch (num_called) {
149 case 0:
150 pr_debug("%s: found clockevent timer\n", __func__);
151 add_clockevent(timer);
Heiko Stuebner10021482013-06-04 11:38:42 +0200152 break;
153 case 1:
154 pr_debug("%s: found clocksource timer\n", __func__);
155 add_clocksource(timer);
Heiko Stuebner10021482013-06-04 11:38:42 +0200156 init_sched_clock();
Jisheng Zhang9115df82015-11-05 10:32:06 +0800157#ifdef CONFIG_ARM
158 dw_apb_delay_timer.freq = sched_rate;
159 register_current_timer_delay(&dw_apb_delay_timer);
160#endif
Heiko Stuebner10021482013-06-04 11:38:42 +0200161 break;
162 default:
163 break;
164 }
Dinh Nguyencfda5902012-07-11 15:13:16 -0500165
Heiko Stuebner10021482013-06-04 11:38:42 +0200166 num_called++;
Dinh Nguyencfda5902012-07-11 15:13:16 -0500167}
Heiko Stuebner10021482013-06-04 11:38:42 +0200168CLOCKSOURCE_OF_DECLARE(pc3x2_timer, "picochip,pc3x2-timer", dw_apb_timer_init);
Dinh Nguyen9ab47272013-12-10 19:49:18 +0100169CLOCKSOURCE_OF_DECLARE(apb_timer_osc, "snps,dw-apb-timer-osc", dw_apb_timer_init);
170CLOCKSOURCE_OF_DECLARE(apb_timer_sp, "snps,dw-apb-timer-sp", dw_apb_timer_init);
171CLOCKSOURCE_OF_DECLARE(apb_timer, "snps,dw-apb-timer", dw_apb_timer_init);