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Ryan Mallonb6850042008-04-16 02:56:35 +01001/*
Ryan Mallonb6850042008-04-16 02:56:35 +01002 * Generic EP93xx GPIO handling
3 *
Ryan Mallon1c5454e2011-06-15 14:45:36 +10004 * Copyright (c) 2008 Ryan Mallon
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -07005 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
Ryan Mallonb6850042008-04-16 02:56:35 +01006 *
7 * Based on code originally from:
8 * linux/arch/arm/mach-ep93xx/core.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
Paul Gortmakerbb207ef2011-07-03 13:38:09 -040016#include <linux/module.h>
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -070017#include <linux/platform_device.h>
Russell Kingfced80c2008-09-06 12:10:45 +010018#include <linux/io.h>
Ryan Mallon595c0502009-07-15 21:31:46 +010019#include <linux/irq.h>
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -070020#include <linux/slab.h>
Linus Walleij0f4630f2015-12-04 14:02:58 +010021#include <linux/gpio/driver.h>
22/* FIXME: this is here for gpio_to_irq() - get rid of this! */
23#include <linux/gpio.h>
Ryan Mallonb6850042008-04-16 02:56:35 +010024
Hartley Sweetenddf4f3d2009-06-26 21:39:27 +010025#include <mach/hardware.h>
Linus Walleijbd5f12a2011-09-22 08:07:00 +010026#include <mach/gpio-ep93xx.h>
27
28#define irq_to_gpio(irq) ((irq) - gpio_to_irq(0))
Ryan Mallonb6850042008-04-16 02:56:35 +010029
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -070030struct ep93xx_gpio {
31 void __iomem *mmio_base;
Linus Walleij0f4630f2015-12-04 14:02:58 +010032 struct gpio_chip gc[8];
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -070033};
34
Hartley Sweetend056ab72010-02-23 21:41:17 +010035/*************************************************************************
Hartley Sweeten47427232010-04-06 22:46:16 +010036 * Interrupt handling for EP93xx on-chip GPIOs
Hartley Sweetend056ab72010-02-23 21:41:17 +010037 *************************************************************************/
38static unsigned char gpio_int_unmasked[3];
39static unsigned char gpio_int_enabled[3];
40static unsigned char gpio_int_type1[3];
41static unsigned char gpio_int_type2[3];
42static unsigned char gpio_int_debounce[3];
43
44/* Port ordering is: A B F */
45static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
46static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
47static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
48static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
49static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
50
Hartley Sweeten47427232010-04-06 22:46:16 +010051static void ep93xx_gpio_update_int_params(unsigned port)
Hartley Sweetend056ab72010-02-23 21:41:17 +010052{
53 BUG_ON(port > 2);
54
Linus Walleijd27e06a2013-10-14 10:07:08 +020055 writeb_relaxed(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
Hartley Sweetend056ab72010-02-23 21:41:17 +010056
Linus Walleijd27e06a2013-10-14 10:07:08 +020057 writeb_relaxed(gpio_int_type2[port],
Hartley Sweetend056ab72010-02-23 21:41:17 +010058 EP93XX_GPIO_REG(int_type2_register_offset[port]));
59
Linus Walleijd27e06a2013-10-14 10:07:08 +020060 writeb_relaxed(gpio_int_type1[port],
Hartley Sweetend056ab72010-02-23 21:41:17 +010061 EP93XX_GPIO_REG(int_type1_register_offset[port]));
62
Linus Walleijd27e06a2013-10-14 10:07:08 +020063 writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
Hartley Sweetend056ab72010-02-23 21:41:17 +010064 EP93XX_GPIO_REG(int_en_register_offset[port]));
65}
66
Hartley Sweeten5d046af2011-01-27 17:29:29 +010067static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
Hartley Sweetend056ab72010-02-23 21:41:17 +010068{
69 int line = irq_to_gpio(irq);
70 int port = line >> 3;
71 int port_mask = 1 << (line & 7);
72
73 if (enable)
74 gpio_int_debounce[port] |= port_mask;
75 else
76 gpio_int_debounce[port] &= ~port_mask;
77
Linus Walleijd27e06a2013-10-14 10:07:08 +020078 writeb(gpio_int_debounce[port],
Hartley Sweetend056ab72010-02-23 21:41:17 +010079 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
80}
Hartley Sweetend056ab72010-02-23 21:41:17 +010081
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +020082static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
Hartley Sweetend056ab72010-02-23 21:41:17 +010083{
84 unsigned char status;
85 int i;
86
Linus Walleijd27e06a2013-10-14 10:07:08 +020087 status = readb(EP93XX_GPIO_A_INT_STATUS);
Hartley Sweetend056ab72010-02-23 21:41:17 +010088 for (i = 0; i < 8; i++) {
89 if (status & (1 << i)) {
90 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
91 generic_handle_irq(gpio_irq);
92 }
93 }
94
Linus Walleijd27e06a2013-10-14 10:07:08 +020095 status = readb(EP93XX_GPIO_B_INT_STATUS);
Hartley Sweetend056ab72010-02-23 21:41:17 +010096 for (i = 0; i < 8; i++) {
97 if (status & (1 << i)) {
98 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
99 generic_handle_irq(gpio_irq);
100 }
101 }
102}
103
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200104static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
Hartley Sweetend056ab72010-02-23 21:41:17 +0100105{
106 /*
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300107 * map discontiguous hw irq range to continuous sw irq range:
Hartley Sweetend056ab72010-02-23 21:41:17 +0100108 *
109 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
110 */
Thomas Gleixnere43ea7a2015-07-13 00:06:41 +0200111 unsigned int irq = irq_desc_get_irq(desc);
Hartley Sweetend056ab72010-02-23 21:41:17 +0100112 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
113 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
114
115 generic_handle_irq(gpio_irq);
116}
117
Lennert Buytenhekc0afc912010-11-29 10:29:50 +0100118static void ep93xx_gpio_irq_ack(struct irq_data *d)
Hartley Sweetend056ab72010-02-23 21:41:17 +0100119{
Lennert Buytenhekc0afc912010-11-29 10:29:50 +0100120 int line = irq_to_gpio(d->irq);
Hartley Sweetend056ab72010-02-23 21:41:17 +0100121 int port = line >> 3;
122 int port_mask = 1 << (line & 7);
123
Thomas Gleixnerd1735a22011-03-24 12:45:56 +0100124 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
Hartley Sweetend056ab72010-02-23 21:41:17 +0100125 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
126 ep93xx_gpio_update_int_params(port);
127 }
128
Linus Walleijd27e06a2013-10-14 10:07:08 +0200129 writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
Hartley Sweetend056ab72010-02-23 21:41:17 +0100130}
131
Lennert Buytenhekc0afc912010-11-29 10:29:50 +0100132static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
Hartley Sweetend056ab72010-02-23 21:41:17 +0100133{
Lennert Buytenhekc0afc912010-11-29 10:29:50 +0100134 int line = irq_to_gpio(d->irq);
Hartley Sweetend056ab72010-02-23 21:41:17 +0100135 int port = line >> 3;
136 int port_mask = 1 << (line & 7);
137
Thomas Gleixnerd1735a22011-03-24 12:45:56 +0100138 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
Hartley Sweetend056ab72010-02-23 21:41:17 +0100139 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
140
141 gpio_int_unmasked[port] &= ~port_mask;
142 ep93xx_gpio_update_int_params(port);
143
Linus Walleijd27e06a2013-10-14 10:07:08 +0200144 writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
Hartley Sweetend056ab72010-02-23 21:41:17 +0100145}
146
Lennert Buytenhekc0afc912010-11-29 10:29:50 +0100147static void ep93xx_gpio_irq_mask(struct irq_data *d)
Hartley Sweetend056ab72010-02-23 21:41:17 +0100148{
Lennert Buytenhekc0afc912010-11-29 10:29:50 +0100149 int line = irq_to_gpio(d->irq);
Hartley Sweetend056ab72010-02-23 21:41:17 +0100150 int port = line >> 3;
151
152 gpio_int_unmasked[port] &= ~(1 << (line & 7));
153 ep93xx_gpio_update_int_params(port);
154}
155
Lennert Buytenhekc0afc912010-11-29 10:29:50 +0100156static void ep93xx_gpio_irq_unmask(struct irq_data *d)
Hartley Sweetend056ab72010-02-23 21:41:17 +0100157{
Lennert Buytenhekc0afc912010-11-29 10:29:50 +0100158 int line = irq_to_gpio(d->irq);
Hartley Sweetend056ab72010-02-23 21:41:17 +0100159 int port = line >> 3;
160
161 gpio_int_unmasked[port] |= 1 << (line & 7);
162 ep93xx_gpio_update_int_params(port);
163}
164
165/*
166 * gpio_int_type1 controls whether the interrupt is level (0) or
167 * edge (1) triggered, while gpio_int_type2 controls whether it
168 * triggers on low/falling (0) or high/rising (1).
169 */
Lennert Buytenhekc0afc912010-11-29 10:29:50 +0100170static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
Hartley Sweetend056ab72010-02-23 21:41:17 +0100171{
Lennert Buytenhekc0afc912010-11-29 10:29:50 +0100172 const int gpio = irq_to_gpio(d->irq);
Hartley Sweetend056ab72010-02-23 21:41:17 +0100173 const int port = gpio >> 3;
174 const int port_mask = 1 << (gpio & 7);
Thomas Gleixnerd1735a22011-03-24 12:45:56 +0100175 irq_flow_handler_t handler;
Hartley Sweetend056ab72010-02-23 21:41:17 +0100176
177 gpio_direction_input(gpio);
178
179 switch (type) {
180 case IRQ_TYPE_EDGE_RISING:
181 gpio_int_type1[port] |= port_mask;
182 gpio_int_type2[port] |= port_mask;
Thomas Gleixnerd1735a22011-03-24 12:45:56 +0100183 handler = handle_edge_irq;
Hartley Sweetend056ab72010-02-23 21:41:17 +0100184 break;
185 case IRQ_TYPE_EDGE_FALLING:
186 gpio_int_type1[port] |= port_mask;
187 gpio_int_type2[port] &= ~port_mask;
Thomas Gleixnerd1735a22011-03-24 12:45:56 +0100188 handler = handle_edge_irq;
Hartley Sweetend056ab72010-02-23 21:41:17 +0100189 break;
190 case IRQ_TYPE_LEVEL_HIGH:
191 gpio_int_type1[port] &= ~port_mask;
192 gpio_int_type2[port] |= port_mask;
Thomas Gleixnerd1735a22011-03-24 12:45:56 +0100193 handler = handle_level_irq;
Hartley Sweetend056ab72010-02-23 21:41:17 +0100194 break;
195 case IRQ_TYPE_LEVEL_LOW:
196 gpio_int_type1[port] &= ~port_mask;
197 gpio_int_type2[port] &= ~port_mask;
Thomas Gleixnerd1735a22011-03-24 12:45:56 +0100198 handler = handle_level_irq;
Hartley Sweetend056ab72010-02-23 21:41:17 +0100199 break;
200 case IRQ_TYPE_EDGE_BOTH:
201 gpio_int_type1[port] |= port_mask;
202 /* set initial polarity based on current input level */
203 if (gpio_get_value(gpio))
204 gpio_int_type2[port] &= ~port_mask; /* falling */
205 else
206 gpio_int_type2[port] |= port_mask; /* rising */
Thomas Gleixnerd1735a22011-03-24 12:45:56 +0100207 handler = handle_edge_irq;
Hartley Sweetend056ab72010-02-23 21:41:17 +0100208 break;
209 default:
Hartley Sweetend056ab72010-02-23 21:41:17 +0100210 return -EINVAL;
211 }
212
Thomas Gleixner72b2a9e2015-06-23 15:52:38 +0200213 irq_set_handler_locked(d, handler);
Hartley Sweetend056ab72010-02-23 21:41:17 +0100214
Thomas Gleixnerd1735a22011-03-24 12:45:56 +0100215 gpio_int_enabled[port] |= port_mask;
Hartley Sweetend056ab72010-02-23 21:41:17 +0100216
217 ep93xx_gpio_update_int_params(port);
218
219 return 0;
220}
221
222static struct irq_chip ep93xx_gpio_irq_chip = {
223 .name = "GPIO",
Lennert Buytenhekc0afc912010-11-29 10:29:50 +0100224 .irq_ack = ep93xx_gpio_irq_ack,
225 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
226 .irq_mask = ep93xx_gpio_irq_mask,
227 .irq_unmask = ep93xx_gpio_irq_unmask,
228 .irq_set_type = ep93xx_gpio_irq_type,
Hartley Sweetend056ab72010-02-23 21:41:17 +0100229};
230
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700231static void ep93xx_gpio_init_irq(void)
Hartley Sweetend056ab72010-02-23 21:41:17 +0100232{
233 int gpio_irq;
234
235 for (gpio_irq = gpio_to_irq(0);
236 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
Thomas Gleixnerf38c02f2011-03-24 13:35:09 +0100237 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
238 handle_level_irq);
Rob Herring23393d42015-07-27 15:55:16 -0500239 irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
Hartley Sweetend056ab72010-02-23 21:41:17 +0100240 }
241
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100242 irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
243 ep93xx_gpio_ab_irq_handler);
244 irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
245 ep93xx_gpio_f_irq_handler);
246 irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
247 ep93xx_gpio_f_irq_handler);
248 irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
249 ep93xx_gpio_f_irq_handler);
250 irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
251 ep93xx_gpio_f_irq_handler);
252 irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
253 ep93xx_gpio_f_irq_handler);
254 irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
255 ep93xx_gpio_f_irq_handler);
256 irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
257 ep93xx_gpio_f_irq_handler);
258 irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
259 ep93xx_gpio_f_irq_handler);
Hartley Sweetend056ab72010-02-23 21:41:17 +0100260}
261
262
263/*************************************************************************
264 * gpiolib interface for EP93xx on-chip GPIOs
265 *************************************************************************/
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700266struct ep93xx_gpio_bank {
267 const char *label;
268 int data;
269 int dir;
270 int base;
271 bool has_debounce;
Ryan Mallonb6850042008-04-16 02:56:35 +0100272};
273
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700274#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \
275 { \
276 .label = _label, \
277 .data = _data, \
278 .dir = _dir, \
279 .base = _base, \
280 .has_debounce = _debounce, \
Ryan Mallonb6850042008-04-16 02:56:35 +0100281 }
282
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700283static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
284 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
285 EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
286 EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
287 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
288 EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
289 EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
290 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
291 EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
292};
Ryan Mallonb6850042008-04-16 02:56:35 +0100293
Hartley Sweeten5d046af2011-01-27 17:29:29 +0100294static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
295 unsigned offset, unsigned debounce)
296{
297 int gpio = chip->base + offset;
298 int irq = gpio_to_irq(gpio);
299
300 if (irq < 0)
301 return -EINVAL;
302
303 ep93xx_gpio_int_debounce(irq, debounce ? true : false);
304
305 return 0;
306}
307
Linus Walleij257af9f2011-08-22 08:43:04 +0100308/*
309 * Map GPIO A0..A7 (0..7) to irq 64..71,
310 * B0..B7 (7..15) to irq 72..79, and
311 * F0..F7 (16..24) to irq 80..87.
312 */
313static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
314{
315 int gpio = chip->base + offset;
316
317 if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
318 return -EINVAL;
319
320 return 64 + gpio;
321}
322
Linus Walleij0f4630f2015-12-04 14:02:58 +0100323static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev,
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700324 void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
325{
326 void __iomem *data = mmio_base + bank->data;
327 void __iomem *dir = mmio_base + bank->dir;
328 int err;
329
Linus Walleij0f4630f2015-12-04 14:02:58 +0100330 err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700331 if (err)
332 return err;
333
Linus Walleij0f4630f2015-12-04 14:02:58 +0100334 gc->label = bank->label;
335 gc->base = bank->base;
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700336
Linus Walleij257af9f2011-08-22 08:43:04 +0100337 if (bank->has_debounce) {
Linus Walleij0f4630f2015-12-04 14:02:58 +0100338 gc->set_debounce = ep93xx_gpio_set_debounce;
339 gc->to_irq = ep93xx_gpio_to_irq;
Linus Walleij257af9f2011-08-22 08:43:04 +0100340 }
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700341
Linus Walleij0f4630f2015-12-04 14:02:58 +0100342 return gpiochip_add_data(gc, NULL);
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700343}
344
Bill Pemberton38363092012-11-19 13:22:34 -0500345static int ep93xx_gpio_probe(struct platform_device *pdev)
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700346{
347 struct ep93xx_gpio *ep93xx_gpio;
348 struct resource *res;
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700349 int i;
abdoulaye berthe1aeede02014-05-14 00:36:54 +0200350 struct device *dev = &pdev->dev;
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700351
abdoulaye berthe1aeede02014-05-14 00:36:54 +0200352 ep93xx_gpio = devm_kzalloc(dev, sizeof(struct ep93xx_gpio), GFP_KERNEL);
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700353 if (!ep93xx_gpio)
354 return -ENOMEM;
355
356 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Jingoo Hanc829f952014-05-27 15:25:51 +0900357 ep93xx_gpio->mmio_base = devm_ioremap_resource(dev, res);
abdoulaye berthe1aeede02014-05-14 00:36:54 +0200358 if (IS_ERR(ep93xx_gpio->mmio_base))
359 return PTR_ERR(ep93xx_gpio->mmio_base);
Ryan Mallonb6850042008-04-16 02:56:35 +0100360
Hartley Sweeten5d046af2011-01-27 17:29:29 +0100361 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
Linus Walleij0f4630f2015-12-04 14:02:58 +0100362 struct gpio_chip *gc = &ep93xx_gpio->gc[i];
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700363 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
Hartley Sweeten5d046af2011-01-27 17:29:29 +0100364
Linus Walleij0f4630f2015-12-04 14:02:58 +0100365 if (ep93xx_gpio_add_bank(gc, &pdev->dev,
abdoulaye berthe1aeede02014-05-14 00:36:54 +0200366 ep93xx_gpio->mmio_base, bank))
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700367 dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
368 bank->label);
Hartley Sweeten5d046af2011-01-27 17:29:29 +0100369 }
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700370
371 ep93xx_gpio_init_irq();
372
373 return 0;
Ryan Mallonb6850042008-04-16 02:56:35 +0100374}
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700375
376static struct platform_driver ep93xx_gpio_driver = {
377 .driver = {
378 .name = "gpio-ep93xx",
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700379 },
380 .probe = ep93xx_gpio_probe,
381};
382
383static int __init ep93xx_gpio_init(void)
384{
H Hartley Sweeten1e4c8842011-06-08 14:35:33 -0700385 return platform_driver_register(&ep93xx_gpio_driver);
386}
387postcore_initcall(ep93xx_gpio_init);
388
389MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
390 "H Hartley Sweeten <hsweeten@visionengravers.com>");
391MODULE_DESCRIPTION("EP93XX GPIO driver");
392MODULE_LICENSE("GPL");