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Philipp Zabel1c44f5f2008-02-04 22:28:22 -08001/*
Eric Miao38f539a2009-01-20 12:09:06 +08002 * linux/arch/arm/plat-pxa/gpio.c
Philipp Zabel1c44f5f2008-02-04 22:28:22 -08003 *
4 * Generic PXA GPIO handling
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
Haojian Zhuang7a4d5072012-04-13 15:15:45 +080014#include <linux/module.h>
Haojian Zhuang389eda12011-10-17 21:26:55 +080015#include <linux/clk.h>
16#include <linux/err.h>
Russell King2f8163b2011-07-26 10:53:52 +010017#include <linux/gpio.h>
Haojian Zhuang157d2642011-10-17 20:37:52 +080018#include <linux/gpio-pxa.h>
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080019#include <linux/init.h>
Rob Herringae4f4cf2015-01-26 22:46:04 -060020#include <linux/interrupt.h>
eric miaoe3630db2008-03-04 11:42:26 +080021#include <linux/irq.h>
Haojian Zhuang7a4d5072012-04-13 15:15:45 +080022#include <linux/irqdomain.h>
Catalin Marinasde88cbb2013-01-18 15:31:37 +000023#include <linux/irqchip/chained_irq.h>
Russell Kingfced80c2008-09-06 12:10:45 +010024#include <linux/io.h>
Haojian Zhuang7a4d5072012-04-13 15:15:45 +080025#include <linux/of.h>
26#include <linux/of_device.h>
Robert Jarzmika770d942015-12-12 23:55:21 +010027#include <linux/pinctrl/consumer.h>
Haojian Zhuang157d2642011-10-17 20:37:52 +080028#include <linux/platform_device.h>
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020029#include <linux/syscore_ops.h>
Daniel Mack4aa78262009-06-19 22:56:09 +020030#include <linux/slab.h>
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080031
Haojian Zhuang157d2642011-10-17 20:37:52 +080032/*
33 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
34 * one set of registers. The register offsets are organized below:
35 *
36 * GPLR GPDR GPSR GPCR GRER GFER GEDR
37 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
38 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
39 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
40 *
41 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
42 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
43 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
44 *
Rob Herring684bba22015-01-26 22:46:06 -060045 * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248
46 *
Haojian Zhuang157d2642011-10-17 20:37:52 +080047 * NOTE:
48 * BANK 3 is only available on PXA27x and later processors.
Rob Herring684bba22015-01-26 22:46:06 -060049 * BANK 4 and 5 are only available on PXA935, PXA1928
50 * BANK 6 is only available on PXA1928
Haojian Zhuang157d2642011-10-17 20:37:52 +080051 */
52
53#define GPLR_OFFSET 0x00
54#define GPDR_OFFSET 0x0C
55#define GPSR_OFFSET 0x18
56#define GPCR_OFFSET 0x24
57#define GRER_OFFSET 0x30
58#define GFER_OFFSET 0x3C
59#define GEDR_OFFSET 0x48
60#define GAFR_OFFSET 0x54
Haojian Zhuangbe241682011-10-17 21:07:15 +080061#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
Haojian Zhuang157d2642011-10-17 20:37:52 +080062
Rob Herring1e970b72015-03-02 15:30:58 -060063#define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2)
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080064
Eric Miao3b8e2852009-01-07 11:30:49 +080065int pxa_last_gpio;
Daniel Mack9450be72012-07-22 16:55:44 +020066static int irq_base;
Eric Miao3b8e2852009-01-07 11:30:49 +080067
Robert Jarzmikfc0589c2015-11-28 22:37:42 +010068struct pxa_gpio_bank {
Eric Miao0807da52009-01-07 18:01:51 +080069 void __iomem *regbase;
Eric Miao0807da52009-01-07 18:01:51 +080070 unsigned long irq_mask;
71 unsigned long irq_edge_rise;
72 unsigned long irq_edge_fall;
73
74#ifdef CONFIG_PM
75 unsigned long saved_gplr;
76 unsigned long saved_gpdr;
77 unsigned long saved_grer;
78 unsigned long saved_gfer;
79#endif
Philipp Zabel1c44f5f2008-02-04 22:28:22 -080080};
81
Robert Jarzmikfc0589c2015-11-28 22:37:42 +010082struct pxa_gpio_chip {
83 struct device *dev;
84 struct gpio_chip chip;
85 struct pxa_gpio_bank *banks;
Robert Jarzmik384ca3c2015-11-28 22:37:44 +010086 struct irq_domain *irqdomain;
Robert Jarzmikfc0589c2015-11-28 22:37:42 +010087
88 int irq0;
89 int irq1;
90 int (*set_wake)(unsigned int gpio, unsigned int on);
91};
92
Haojian Zhuang2cab0292013-04-07 16:44:33 +080093enum pxa_gpio_type {
Haojian Zhuang4929f5a2011-10-10 16:03:51 +080094 PXA25X_GPIO = 0,
95 PXA26X_GPIO,
96 PXA27X_GPIO,
97 PXA3XX_GPIO,
98 PXA93X_GPIO,
99 MMP_GPIO = 0x10,
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800100 MMP2_GPIO,
Rob Herring684bba22015-01-26 22:46:06 -0600101 PXA1928_GPIO,
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800102};
103
104struct pxa_gpio_id {
105 enum pxa_gpio_type type;
106 int gpio_nums;
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800107};
108
Eric Miao0807da52009-01-07 18:01:51 +0800109static DEFINE_SPINLOCK(gpio_lock);
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100110static struct pxa_gpio_chip *pxa_gpio_chip;
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800111static enum pxa_gpio_type gpio_type;
Eric Miao0807da52009-01-07 18:01:51 +0800112
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800113static struct pxa_gpio_id pxa25x_id = {
114 .type = PXA25X_GPIO,
115 .gpio_nums = 85,
116};
117
118static struct pxa_gpio_id pxa26x_id = {
119 .type = PXA26X_GPIO,
120 .gpio_nums = 90,
121};
122
123static struct pxa_gpio_id pxa27x_id = {
124 .type = PXA27X_GPIO,
125 .gpio_nums = 121,
126};
127
128static struct pxa_gpio_id pxa3xx_id = {
129 .type = PXA3XX_GPIO,
130 .gpio_nums = 128,
131};
132
133static struct pxa_gpio_id pxa93x_id = {
134 .type = PXA93X_GPIO,
135 .gpio_nums = 192,
136};
137
138static struct pxa_gpio_id mmp_id = {
139 .type = MMP_GPIO,
140 .gpio_nums = 128,
141};
142
143static struct pxa_gpio_id mmp2_id = {
144 .type = MMP2_GPIO,
145 .gpio_nums = 192,
146};
147
Rob Herring684bba22015-01-26 22:46:06 -0600148static struct pxa_gpio_id pxa1928_id = {
149 .type = PXA1928_GPIO,
150 .gpio_nums = 224,
151};
152
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100153#define for_each_gpio_bank(i, b, pc) \
154 for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++)
Eric Miao0807da52009-01-07 18:01:51 +0800155
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100156static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c)
Eric Miao0807da52009-01-07 18:01:51 +0800157{
Linus Walleij81d0c312015-12-07 11:42:22 +0100158 struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c);
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100159
160 return pxa_chip;
161}
Linus Walleij81d0c312015-12-07 11:42:22 +0100162
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100163static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio)
164{
Linus Walleij81d0c312015-12-07 11:42:22 +0100165 struct pxa_gpio_chip *p = gpiochip_get_data(c);
166 struct pxa_gpio_bank *bank = p->banks + (gpio / 32);
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100167
168 return bank->regbase;
Eric Miao0807da52009-01-07 18:01:51 +0800169}
170
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100171static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c,
172 unsigned gpio)
Eric Miao0807da52009-01-07 18:01:51 +0800173{
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100174 return chip_to_pxachip(c)->banks + gpio / 32;
Eric Miao0807da52009-01-07 18:01:51 +0800175}
176
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800177static inline int gpio_is_pxa_type(int type)
178{
179 return (type & MMP_GPIO) == 0;
180}
181
182static inline int gpio_is_mmp_type(int type)
183{
184 return (type & MMP_GPIO) != 0;
185}
186
Haojian Zhuang157d2642011-10-17 20:37:52 +0800187/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
188 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
189 */
190static inline int __gpio_is_inverted(int gpio)
191{
192 if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
193 return 1;
194 return 0;
195}
196
197/*
198 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
199 * function of a GPIO, and GPDRx cannot be altered once configured. It
200 * is attributed as "occupied" here (I know this terminology isn't
201 * accurate, you are welcome to propose a better one :-)
202 */
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100203static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio)
Haojian Zhuang157d2642011-10-17 20:37:52 +0800204{
Haojian Zhuang157d2642011-10-17 20:37:52 +0800205 void __iomem *base;
206 unsigned long gafr = 0, gpdr = 0;
207 int ret, af = 0, dir = 0;
208
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100209 base = gpio_bank_base(&pchip->chip, gpio);
Haojian Zhuang157d2642011-10-17 20:37:52 +0800210 gpdr = readl_relaxed(base + GPDR_OFFSET);
211
212 switch (gpio_type) {
213 case PXA25X_GPIO:
214 case PXA26X_GPIO:
215 case PXA27X_GPIO:
216 gafr = readl_relaxed(base + GAFR_OFFSET);
217 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
218 dir = gpdr & GPIO_bit(gpio);
219
220 if (__gpio_is_inverted(gpio))
221 ret = (af != 1) || (dir == 0);
222 else
223 ret = (af != 0) || (dir != 0);
224 break;
225 default:
226 ret = gpdr & GPIO_bit(gpio);
227 break;
228 }
229 return ret;
230}
231
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800232int pxa_irq_to_gpio(int irq)
233{
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100234 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
235 int irq_gpio0;
236
237 irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0);
238 if (irq_gpio0 > 0)
239 return irq - irq_gpio0;
240
241 return irq_gpio0;
242}
243
244static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
245{
246 struct pxa_gpio_chip *pchip = chip_to_pxachip(chip);
247
248 return irq_find_mapping(pchip->irqdomain, offset);
Haojian Zhuang4929f5a2011-10-10 16:03:51 +0800249}
250
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800251static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
252{
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100253 void __iomem *base = gpio_bank_base(chip, offset);
254 uint32_t value, mask = GPIO_bit(offset);
Eric Miao0807da52009-01-07 18:01:51 +0800255 unsigned long flags;
Robert Jarzmika770d942015-12-12 23:55:21 +0100256 int ret;
257
258 ret = pinctrl_gpio_direction_input(chip->base + offset);
259 if (!ret)
260 return 0;
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800261
Eric Miao0807da52009-01-07 18:01:51 +0800262 spin_lock_irqsave(&gpio_lock, flags);
263
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800264 value = readl_relaxed(base + GPDR_OFFSET);
Eric Miao067455a2008-11-26 18:12:04 +0800265 if (__gpio_is_inverted(chip->base + offset))
266 value |= mask;
267 else
268 value &= ~mask;
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800269 writel_relaxed(value, base + GPDR_OFFSET);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800270
Eric Miao0807da52009-01-07 18:01:51 +0800271 spin_unlock_irqrestore(&gpio_lock, flags);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800272 return 0;
273}
274
275static int pxa_gpio_direction_output(struct gpio_chip *chip,
Eric Miao0807da52009-01-07 18:01:51 +0800276 unsigned offset, int value)
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800277{
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100278 void __iomem *base = gpio_bank_base(chip, offset);
279 uint32_t tmp, mask = GPIO_bit(offset);
Eric Miao0807da52009-01-07 18:01:51 +0800280 unsigned long flags;
Robert Jarzmika770d942015-12-12 23:55:21 +0100281 int ret;
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800282
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800283 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
Eric Miao0807da52009-01-07 18:01:51 +0800284
Robert Jarzmika770d942015-12-12 23:55:21 +0100285 ret = pinctrl_gpio_direction_output(chip->base + offset);
286 if (!ret)
287 return 0;
288
Eric Miao0807da52009-01-07 18:01:51 +0800289 spin_lock_irqsave(&gpio_lock, flags);
290
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800291 tmp = readl_relaxed(base + GPDR_OFFSET);
Eric Miao067455a2008-11-26 18:12:04 +0800292 if (__gpio_is_inverted(chip->base + offset))
293 tmp &= ~mask;
294 else
295 tmp |= mask;
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800296 writel_relaxed(tmp, base + GPDR_OFFSET);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800297
Eric Miao0807da52009-01-07 18:01:51 +0800298 spin_unlock_irqrestore(&gpio_lock, flags);
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800299 return 0;
300}
301
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800302static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
303{
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100304 void __iomem *base = gpio_bank_base(chip, offset);
305 u32 gplr = readl_relaxed(base + GPLR_OFFSET);
306
307 return !!(gplr & GPIO_bit(offset));
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800308}
309
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800310static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
311{
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100312 void __iomem *base = gpio_bank_base(chip, offset);
313
314 writel_relaxed(GPIO_bit(offset),
315 base + (value ? GPSR_OFFSET : GPCR_OFFSET));
Philipp Zabel1c44f5f2008-02-04 22:28:22 -0800316}
317
Daniel Mack72121572012-07-25 17:35:39 +0200318#ifdef CONFIG_OF_GPIO
319static int pxa_gpio_of_xlate(struct gpio_chip *gc,
320 const struct of_phandle_args *gpiospec,
321 u32 *flags)
322{
323 if (gpiospec->args[0] > pxa_last_gpio)
324 return -EINVAL;
325
Daniel Mack72121572012-07-25 17:35:39 +0200326 if (flags)
327 *flags = gpiospec->args[1];
328
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100329 return gpiospec->args[0];
Daniel Mack72121572012-07-25 17:35:39 +0200330}
331#endif
332
Robert Jarzmika770d942015-12-12 23:55:21 +0100333static int pxa_gpio_request(struct gpio_chip *chip, unsigned int offset)
334{
335 return pinctrl_request_gpio(chip->base + offset);
336}
337
338static void pxa_gpio_free(struct gpio_chip *chip, unsigned int offset)
339{
340 pinctrl_free_gpio(chip->base + offset);
341}
342
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100343static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio,
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100344 struct device_node *np, void __iomem *regbase)
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800345{
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100346 int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32);
347 struct pxa_gpio_bank *bank;
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800348
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100349 pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks),
350 GFP_KERNEL);
351 if (!pchip->banks)
Eric Miao0807da52009-01-07 18:01:51 +0800352 return -ENOMEM;
Eric Miao0807da52009-01-07 18:01:51 +0800353
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100354 pchip->chip.label = "gpio-pxa";
355 pchip->chip.direction_input = pxa_gpio_direction_input;
356 pchip->chip.direction_output = pxa_gpio_direction_output;
357 pchip->chip.get = pxa_gpio_get;
358 pchip->chip.set = pxa_gpio_set;
359 pchip->chip.to_irq = pxa_gpio_to_irq;
360 pchip->chip.ngpio = ngpio;
Robert Jarzmika770d942015-12-12 23:55:21 +0100361 pchip->chip.request = pxa_gpio_request;
362 pchip->chip.free = pxa_gpio_free;
Daniel Mack72121572012-07-25 17:35:39 +0200363#ifdef CONFIG_OF_GPIO
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100364 pchip->chip.of_node = np;
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100365 pchip->chip.of_xlate = pxa_gpio_of_xlate;
366 pchip->chip.of_gpio_n_cells = 2;
Daniel Mack72121572012-07-25 17:35:39 +0200367#endif
Eric Miao0807da52009-01-07 18:01:51 +0800368
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100369 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
370 bank = pchip->banks + i;
371 bank->regbase = regbase + BANK_OFF(i);
Eric Miao0807da52009-01-07 18:01:51 +0800372 }
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100373
Linus Walleij81d0c312015-12-07 11:42:22 +0100374 return gpiochip_add_data(&pchip->chip, pchip);
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800375}
376
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800377/* Update only those GRERx and GFERx edge detection register bits if those
378 * bits are set in c->irq_mask
379 */
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100380static inline void update_edge_detect(struct pxa_gpio_bank *c)
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800381{
382 uint32_t grer, gfer;
383
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800384 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
385 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800386 grer |= c->irq_edge_rise & c->irq_mask;
387 gfer |= c->irq_edge_fall & c->irq_mask;
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800388 writel_relaxed(grer, c->regbase + GRER_OFFSET);
389 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800390}
391
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100392static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
eric miaoe3630db2008-03-04 11:42:26 +0800393{
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100394 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
395 unsigned int gpio = irqd_to_hwirq(d);
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100396 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
Eric Miao0807da52009-01-07 18:01:51 +0800397 unsigned long gpdr, mask = GPIO_bit(gpio);
eric miaoe3630db2008-03-04 11:42:26 +0800398
eric miaoe3630db2008-03-04 11:42:26 +0800399 if (type == IRQ_TYPE_PROBE) {
400 /* Don't mess with enabled GPIOs using preconfigured edges or
401 * GPIOs set to alternate function or to output during probe
402 */
Eric Miao0807da52009-01-07 18:01:51 +0800403 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
eric miaoe3630db2008-03-04 11:42:26 +0800404 return 0;
eric miao689c04a2008-03-04 17:18:38 +0800405
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100406 if (__gpio_is_occupied(pchip, gpio))
eric miaoe3630db2008-03-04 11:42:26 +0800407 return 0;
eric miao689c04a2008-03-04 17:18:38 +0800408
eric miaoe3630db2008-03-04 11:42:26 +0800409 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
410 }
411
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800412 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
Eric Miao0807da52009-01-07 18:01:51 +0800413
Eric Miao067455a2008-11-26 18:12:04 +0800414 if (__gpio_is_inverted(gpio))
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800415 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
Eric Miao067455a2008-11-26 18:12:04 +0800416 else
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800417 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800418
419 if (type & IRQ_TYPE_EDGE_RISING)
Eric Miao0807da52009-01-07 18:01:51 +0800420 c->irq_edge_rise |= mask;
eric miaoe3630db2008-03-04 11:42:26 +0800421 else
Eric Miao0807da52009-01-07 18:01:51 +0800422 c->irq_edge_rise &= ~mask;
eric miaoe3630db2008-03-04 11:42:26 +0800423
424 if (type & IRQ_TYPE_EDGE_FALLING)
Eric Miao0807da52009-01-07 18:01:51 +0800425 c->irq_edge_fall |= mask;
eric miaoe3630db2008-03-04 11:42:26 +0800426 else
Eric Miao0807da52009-01-07 18:01:51 +0800427 c->irq_edge_fall &= ~mask;
eric miaoe3630db2008-03-04 11:42:26 +0800428
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800429 update_edge_detect(c);
eric miaoe3630db2008-03-04 11:42:26 +0800430
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100431 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
eric miaoe3630db2008-03-04 11:42:26 +0800432 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
433 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
434 return 0;
435}
436
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100437static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d)
eric miaoe3630db2008-03-04 11:42:26 +0800438{
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100439 int loop, gpio, n, handled = 0;
Eric Miao0807da52009-01-07 18:01:51 +0800440 unsigned long gedr;
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100441 struct pxa_gpio_chip *pchip = d;
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100442 struct pxa_gpio_bank *c;
Chao Xie0d2ee5d2012-07-31 14:13:09 +0800443
eric miaoe3630db2008-03-04 11:42:26 +0800444 do {
eric miaoe3630db2008-03-04 11:42:26 +0800445 loop = 0;
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100446 for_each_gpio_bank(gpio, c, pchip) {
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800447 gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
Eric Miao0807da52009-01-07 18:01:51 +0800448 gedr = gedr & c->irq_mask;
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800449 writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800450
Wei Yongjund724f1c2012-09-14 10:36:59 +0800451 for_each_set_bit(n, &gedr, BITS_PER_LONG) {
Eric Miao0807da52009-01-07 18:01:51 +0800452 loop = 1;
453
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100454 generic_handle_irq(gpio_to_irq(gpio + n));
Eric Miao0807da52009-01-07 18:01:51 +0800455 }
eric miaoe3630db2008-03-04 11:42:26 +0800456 }
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100457 handled += loop;
eric miaoe3630db2008-03-04 11:42:26 +0800458 } while (loop);
Chao Xie0d2ee5d2012-07-31 14:13:09 +0800459
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100460 return handled ? IRQ_HANDLED : IRQ_NONE;
461}
462
463static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d)
464{
465 struct pxa_gpio_chip *pchip = d;
466
467 if (in_irq == pchip->irq0) {
468 generic_handle_irq(gpio_to_irq(0));
469 } else if (in_irq == pchip->irq1) {
470 generic_handle_irq(gpio_to_irq(1));
471 } else {
472 pr_err("%s() unknown irq %d\n", __func__, in_irq);
473 return IRQ_NONE;
474 }
475 return IRQ_HANDLED;
eric miaoe3630db2008-03-04 11:42:26 +0800476}
477
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100478static void pxa_ack_muxed_gpio(struct irq_data *d)
eric miaoe3630db2008-03-04 11:42:26 +0800479{
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100480 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
481 unsigned int gpio = irqd_to_hwirq(d);
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100482 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
Eric Miao0807da52009-01-07 18:01:51 +0800483
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100484 writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800485}
486
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100487static void pxa_mask_muxed_gpio(struct irq_data *d)
eric miaoe3630db2008-03-04 11:42:26 +0800488{
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100489 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
490 unsigned int gpio = irqd_to_hwirq(d);
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100491 struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio);
492 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
Eric Miao0807da52009-01-07 18:01:51 +0800493 uint32_t grer, gfer;
494
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100495 b->irq_mask &= ~GPIO_bit(gpio);
Eric Miao0807da52009-01-07 18:01:51 +0800496
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100497 grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio);
498 gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio);
499 writel_relaxed(grer, base + GRER_OFFSET);
500 writel_relaxed(gfer, base + GFER_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800501}
502
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200503static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
504{
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100505 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
506 unsigned int gpio = irqd_to_hwirq(d);
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200507
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100508 if (pchip->set_wake)
509 return pchip->set_wake(gpio, on);
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200510 else
511 return 0;
512}
513
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100514static void pxa_unmask_muxed_gpio(struct irq_data *d)
eric miaoe3630db2008-03-04 11:42:26 +0800515{
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100516 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
517 unsigned int gpio = irqd_to_hwirq(d);
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100518 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
Eric Miao0807da52009-01-07 18:01:51 +0800519
520 c->irq_mask |= GPIO_bit(gpio);
Eric Miaoa8f6fae2009-04-21 14:39:07 +0800521 update_edge_detect(c);
eric miaoe3630db2008-03-04 11:42:26 +0800522}
523
524static struct irq_chip pxa_muxed_gpio_chip = {
525 .name = "GPIO",
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100526 .irq_ack = pxa_ack_muxed_gpio,
527 .irq_mask = pxa_mask_muxed_gpio,
528 .irq_unmask = pxa_unmask_muxed_gpio,
529 .irq_set_type = pxa_gpio_irq_type,
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200530 .irq_set_wake = pxa_gpio_set_wake,
eric miaoe3630db2008-03-04 11:42:26 +0800531};
532
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800533static int pxa_gpio_nums(struct platform_device *pdev)
Haojian Zhuang478e2232011-10-14 16:44:07 +0800534{
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800535 const struct platform_device_id *id = platform_get_device_id(pdev);
536 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
Haojian Zhuang478e2232011-10-14 16:44:07 +0800537 int count = 0;
538
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800539 switch (pxa_id->type) {
540 case PXA25X_GPIO:
541 case PXA26X_GPIO:
542 case PXA27X_GPIO:
543 case PXA3XX_GPIO:
544 case PXA93X_GPIO:
545 case MMP_GPIO:
546 case MMP2_GPIO:
Rob Herring684bba22015-01-26 22:46:06 -0600547 case PXA1928_GPIO:
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800548 gpio_type = pxa_id->type;
549 count = pxa_id->gpio_nums - 1;
550 break;
551 default:
552 count = -EINVAL;
553 break;
Haojian Zhuang478e2232011-10-14 16:44:07 +0800554 }
Haojian Zhuang478e2232011-10-14 16:44:07 +0800555 return count;
556}
557
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800558static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
559 irq_hw_number_t hw)
560{
561 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
562 handle_edge_irq);
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100563 irq_set_chip_data(irq, d->host_data);
Rob Herring23393d42015-07-27 15:55:16 -0500564 irq_set_noprobe(irq);
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800565 return 0;
566}
567
568const struct irq_domain_ops pxa_irq_domain_ops = {
569 .map = pxa_irq_domain_map,
Daniel Mack72121572012-07-25 17:35:39 +0200570 .xlate = irq_domain_xlate_twocell,
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800571};
572
Robert Jarzmik04400912015-12-18 21:40:40 +0100573#ifdef CONFIG_OF
574static const struct of_device_id pxa_gpio_dt_ids[] = {
575 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, },
576 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, },
577 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, },
578 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, },
579 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, },
580 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, },
581 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, },
582 { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, },
583 {}
584};
585
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100586static int pxa_gpio_probe_dt(struct platform_device *pdev,
587 struct pxa_gpio_chip *pchip)
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800588{
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100589 int nr_gpios;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800590 const struct of_device_id *of_id =
591 of_match_device(pxa_gpio_dt_ids, &pdev->dev);
Haojian Zhuangf8731172013-04-09 22:27:50 +0800592 const struct pxa_gpio_id *gpio_id;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800593
Haojian Zhuangf8731172013-04-09 22:27:50 +0800594 if (!of_id || !of_id->data) {
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800595 dev_err(&pdev->dev, "Failed to find gpio controller\n");
596 return -EFAULT;
597 }
Haojian Zhuangf8731172013-04-09 22:27:50 +0800598 gpio_id = of_id->data;
599 gpio_type = gpio_id->type;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800600
Haojian Zhuangf8731172013-04-09 22:27:50 +0800601 nr_gpios = gpio_id->gpio_nums;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800602 pxa_last_gpio = nr_gpios - 1;
603
604 irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
605 if (irq_base < 0) {
606 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100607 return irq_base;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800608 }
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100609 return irq_base;
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800610}
611#else
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100612#define pxa_gpio_probe_dt(pdev, pchip) (-1)
Haojian Zhuang7a4d5072012-04-13 15:15:45 +0800613#endif
614
Bill Pemberton38363092012-11-19 13:22:34 -0500615static int pxa_gpio_probe(struct platform_device *pdev)
eric miaoe3630db2008-03-04 11:42:26 +0800616{
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100617 struct pxa_gpio_chip *pchip;
618 struct pxa_gpio_bank *c;
Haojian Zhuang157d2642011-10-17 20:37:52 +0800619 struct resource *res;
Haojian Zhuang389eda12011-10-17 21:26:55 +0800620 struct clk *clk;
Robert Jarzmikb95ace52012-04-22 13:37:24 +0200621 struct pxa_gpio_platform_data *info;
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100622 void __iomem *gpio_reg_base;
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100623 int gpio, ret;
Haojian Zhuang157d2642011-10-17 20:37:52 +0800624 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
eric miaoe3630db2008-03-04 11:42:26 +0800625
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100626 pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL);
627 if (!pchip)
628 return -ENOMEM;
629 pchip->dev = &pdev->dev;
630
Haojian Zhuangb8f649f2013-04-09 18:12:04 +0800631 info = dev_get_platdata(&pdev->dev);
632 if (info) {
633 irq_base = info->irq_base;
634 if (irq_base <= 0)
635 return -EINVAL;
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800636 pxa_last_gpio = pxa_gpio_nums(pdev);
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100637 pchip->set_wake = info->gpio_set_wake;
Daniel Mack9450be72012-07-22 16:55:44 +0200638 } else {
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100639 irq_base = pxa_gpio_probe_dt(pdev, pchip);
640 if (irq_base < 0)
Haojian Zhuangb8f649f2013-04-09 18:12:04 +0800641 return -EINVAL;
Daniel Mack9450be72012-07-22 16:55:44 +0200642 }
643
Haojian Zhuang478e2232011-10-14 16:44:07 +0800644 if (!pxa_last_gpio)
Haojian Zhuang157d2642011-10-17 20:37:52 +0800645 return -EINVAL;
646
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100647 pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
648 pxa_last_gpio + 1, irq_base,
649 0, &pxa_irq_domain_ops, pchip);
Dan Carpenter41d107a2016-01-05 12:56:37 +0300650 if (!pchip->irqdomain)
651 return -ENOMEM;
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100652
Haojian Zhuang157d2642011-10-17 20:37:52 +0800653 irq0 = platform_get_irq_byname(pdev, "gpio0");
654 irq1 = platform_get_irq_byname(pdev, "gpio1");
655 irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
656 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
657 || (irq_mux <= 0))
658 return -EINVAL;
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100659
660 pchip->irq0 = irq0;
661 pchip->irq1 = irq1;
Haojian Zhuang157d2642011-10-17 20:37:52 +0800662 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Robert Jarzmik8852b2f2015-11-28 22:37:43 +0100663 gpio_reg_base = devm_ioremap(&pdev->dev, res->start,
664 resource_size(res));
Haojian Zhuang157d2642011-10-17 20:37:52 +0800665 if (!gpio_reg_base)
666 return -EINVAL;
667
668 if (irq0 > 0)
669 gpio_offset = 2;
eric miaoe3630db2008-03-04 11:42:26 +0800670
Haojian Zhuang389eda12011-10-17 21:26:55 +0800671 clk = clk_get(&pdev->dev, NULL);
672 if (IS_ERR(clk)) {
673 dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
674 PTR_ERR(clk));
Haojian Zhuang389eda12011-10-17 21:26:55 +0800675 return PTR_ERR(clk);
676 }
Julia Lawall6ab49f42012-08-26 18:00:55 +0200677 ret = clk_prepare_enable(clk);
Haojian Zhuang389eda12011-10-17 21:26:55 +0800678 if (ret) {
679 clk_put(clk);
Haojian Zhuang389eda12011-10-17 21:26:55 +0800680 return ret;
681 }
Haojian Zhuang389eda12011-10-17 21:26:55 +0800682
Eric Miao0807da52009-01-07 18:01:51 +0800683 /* Initialize GPIO chips */
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100684 ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, pdev->dev.of_node,
685 gpio_reg_base);
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100686 if (ret) {
687 clk_put(clk);
688 return ret;
689 }
Eric Miao0807da52009-01-07 18:01:51 +0800690
eric miaoe3630db2008-03-04 11:42:26 +0800691 /* clear all GPIO edge detects */
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100692 for_each_gpio_bank(gpio, c, pchip) {
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800693 writel_relaxed(0, c->regbase + GFER_OFFSET);
694 writel_relaxed(0, c->regbase + GRER_OFFSET);
Laurent Navete37f4af2013-03-20 13:15:59 +0100695 writel_relaxed(~0, c->regbase + GEDR_OFFSET);
Haojian Zhuangbe241682011-10-17 21:07:15 +0800696 /* unmask GPIO edge detect for AP side */
697 if (gpio_is_mmp_type(gpio_type))
698 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
eric miaoe3630db2008-03-04 11:42:26 +0800699 }
700
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100701 if (irq0 > 0) {
702 ret = devm_request_irq(&pdev->dev,
703 irq0, pxa_gpio_direct_handler, 0,
704 "gpio-0", pchip);
705 if (ret)
706 dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n",
707 ret);
eric miaoe3630db2008-03-04 11:42:26 +0800708 }
Robert Jarzmik384ca3c2015-11-28 22:37:44 +0100709 if (irq1 > 0) {
710 ret = devm_request_irq(&pdev->dev,
711 irq1, pxa_gpio_direct_handler, 0,
712 "gpio-1", pchip);
713 if (ret)
714 dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n",
715 ret);
716 }
717 ret = devm_request_irq(&pdev->dev,
718 irq_mux, pxa_gpio_demux_handler, 0,
719 "gpio-mux", pchip);
720 if (ret)
721 dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n",
722 ret);
eric miaoe3630db2008-03-04 11:42:26 +0800723
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100724 pxa_gpio_chip = pchip;
Rob Herringae4f4cf2015-01-26 22:46:04 -0600725
Haojian Zhuang157d2642011-10-17 20:37:52 +0800726 return 0;
eric miaoe3630db2008-03-04 11:42:26 +0800727}
eric miao663707c2008-03-04 16:13:58 +0800728
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800729static const struct platform_device_id gpio_id_table[] = {
730 { "pxa25x-gpio", (unsigned long)&pxa25x_id },
731 { "pxa26x-gpio", (unsigned long)&pxa26x_id },
732 { "pxa27x-gpio", (unsigned long)&pxa27x_id },
733 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id },
734 { "pxa93x-gpio", (unsigned long)&pxa93x_id },
735 { "mmp-gpio", (unsigned long)&mmp_id },
736 { "mmp2-gpio", (unsigned long)&mmp2_id },
Rob Herring684bba22015-01-26 22:46:06 -0600737 { "pxa1928-gpio", (unsigned long)&pxa1928_id },
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800738 { },
739};
740
Haojian Zhuang157d2642011-10-17 20:37:52 +0800741static struct platform_driver pxa_gpio_driver = {
742 .probe = pxa_gpio_probe,
743 .driver = {
744 .name = "pxa-gpio",
Arnd Bergmannf43e04e2012-08-13 14:36:10 +0000745 .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
Haojian Zhuang157d2642011-10-17 20:37:52 +0800746 },
Haojian Zhuang2cab0292013-04-07 16:44:33 +0800747 .id_table = gpio_id_table,
Haojian Zhuang157d2642011-10-17 20:37:52 +0800748};
Linus Walleijcf3fa172013-04-24 21:41:20 +0200749
Robert Jarzmikeae122b2015-11-13 21:22:38 +0100750static int __init pxa_gpio_legacy_init(void)
Linus Walleijcf3fa172013-04-24 21:41:20 +0200751{
Robert Jarzmikeae122b2015-11-13 21:22:38 +0100752 if (of_have_populated_dt())
753 return 0;
754
Linus Walleijcf3fa172013-04-24 21:41:20 +0200755 return platform_driver_register(&pxa_gpio_driver);
756}
Robert Jarzmikeae122b2015-11-13 21:22:38 +0100757postcore_initcall(pxa_gpio_legacy_init);
758
759static int __init pxa_gpio_dt_init(void)
760{
761 if (of_have_populated_dt())
762 return platform_driver_register(&pxa_gpio_driver);
763
764 return 0;
765}
766device_initcall(pxa_gpio_dt_init);
Haojian Zhuang157d2642011-10-17 20:37:52 +0800767
eric miao663707c2008-03-04 16:13:58 +0800768#ifdef CONFIG_PM
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200769static int pxa_gpio_suspend(void)
eric miao663707c2008-03-04 16:13:58 +0800770{
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100771 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
772 struct pxa_gpio_bank *c;
Eric Miao0807da52009-01-07 18:01:51 +0800773 int gpio;
eric miao663707c2008-03-04 16:13:58 +0800774
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100775 for_each_gpio_bank(gpio, c, pchip) {
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800776 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
777 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
778 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
779 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
eric miao663707c2008-03-04 16:13:58 +0800780
781 /* Clear GPIO transition detect bits */
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800782 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
eric miao663707c2008-03-04 16:13:58 +0800783 }
784 return 0;
785}
786
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200787static void pxa_gpio_resume(void)
eric miao663707c2008-03-04 16:13:58 +0800788{
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100789 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
790 struct pxa_gpio_bank *c;
Eric Miao0807da52009-01-07 18:01:51 +0800791 int gpio;
eric miao663707c2008-03-04 16:13:58 +0800792
Robert Jarzmikfc0589c2015-11-28 22:37:42 +0100793 for_each_gpio_bank(gpio, c, pchip) {
eric miao663707c2008-03-04 16:13:58 +0800794 /* restore level with set/clear */
Laurent Navete37f4af2013-03-20 13:15:59 +0100795 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800796 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
eric miao663707c2008-03-04 16:13:58 +0800797
Haojian Zhuangdf664d22011-10-14 17:24:03 +0800798 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
799 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
800 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
eric miao663707c2008-03-04 16:13:58 +0800801 }
eric miao663707c2008-03-04 16:13:58 +0800802}
803#else
804#define pxa_gpio_suspend NULL
805#define pxa_gpio_resume NULL
806#endif
807
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200808struct syscore_ops pxa_gpio_syscore_ops = {
eric miao663707c2008-03-04 16:13:58 +0800809 .suspend = pxa_gpio_suspend,
810 .resume = pxa_gpio_resume,
811};
Haojian Zhuang157d2642011-10-17 20:37:52 +0800812
813static int __init pxa_gpio_sysinit(void)
814{
815 register_syscore_ops(&pxa_gpio_syscore_ops);
816 return 0;
817}
818postcore_initcall(pxa_gpio_sysinit);