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Alessandro Rubini3a95b9f2012-11-24 00:22:56 +00001/* include/linux/amba/pl080.h
Ben Dooksfa7a7882009-03-10 23:57:26 +00002 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * ARM PrimeCell PL080 DMA controller
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Note, there are some Samsung updates to this controller block which
16 * make it not entierly compatible with the PL080 specification from
17 * ARM. When in doubt, check the Samsung documentation first.
18 *
Lucas De Marchi25985ed2011-03-30 22:57:33 -030019 * The Samsung defines are PL080S, and add an extra control register,
Ben Dooksfa7a7882009-03-10 23:57:26 +000020 * the ability to move more than 2^11 counts of data and some extra
21 * OneNAND features.
22*/
23
Viresh Kumar47850a22011-08-05 15:32:26 +053024#ifndef ASM_PL080_H
25#define ASM_PL080_H
26
Ben Dooksfa7a7882009-03-10 23:57:26 +000027#define PL080_INT_STATUS (0x00)
28#define PL080_TC_STATUS (0x04)
29#define PL080_TC_CLEAR (0x08)
30#define PL080_ERR_STATUS (0x0C)
31#define PL080_ERR_CLEAR (0x10)
32#define PL080_RAW_TC_STATUS (0x14)
33#define PL080_RAW_ERR_STATUS (0x18)
34#define PL080_EN_CHAN (0x1c)
35#define PL080_SOFT_BREQ (0x20)
36#define PL080_SOFT_SREQ (0x24)
37#define PL080_SOFT_LBREQ (0x28)
38#define PL080_SOFT_LSREQ (0x2C)
39
40#define PL080_CONFIG (0x30)
41#define PL080_CONFIG_M2_BE (1 << 2)
42#define PL080_CONFIG_M1_BE (1 << 1)
43#define PL080_CONFIG_ENABLE (1 << 0)
44
45#define PL080_SYNC (0x34)
46
47/* Per channel configuration registers */
48
Linus Walleijd92342d2010-08-09 12:47:52 +020049#define PL080_Cx_STRIDE (0x20)
Ben Dooksfa7a7882009-03-10 23:57:26 +000050#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
51#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20)))
52#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20)))
53#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20)))
54#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20)))
55#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20)))
56#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20)))
57#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20)))
58
59#define PL080_CH_SRC_ADDR (0x00)
60#define PL080_CH_DST_ADDR (0x04)
61#define PL080_CH_LLI (0x08)
62#define PL080_CH_CONTROL (0x0C)
63#define PL080_CH_CONFIG (0x10)
64#define PL080S_CH_CONTROL2 (0x10)
65#define PL080S_CH_CONFIG (0x14)
66
67#define PL080_LLI_ADDR_MASK (0x3fffffff << 2)
68#define PL080_LLI_ADDR_SHIFT (2)
69#define PL080_LLI_LM_AHB2 (1 << 0)
70
71#define PL080_CONTROL_TC_IRQ_EN (1 << 31)
72#define PL080_CONTROL_PROT_MASK (0x7 << 28)
73#define PL080_CONTROL_PROT_SHIFT (28)
Linus Walleijd92342d2010-08-09 12:47:52 +020074#define PL080_CONTROL_PROT_CACHE (1 << 30)
75#define PL080_CONTROL_PROT_BUFF (1 << 29)
Ben Dooksfa7a7882009-03-10 23:57:26 +000076#define PL080_CONTROL_PROT_SYS (1 << 28)
77#define PL080_CONTROL_DST_INCR (1 << 27)
78#define PL080_CONTROL_SRC_INCR (1 << 26)
79#define PL080_CONTROL_DST_AHB2 (1 << 25)
80#define PL080_CONTROL_SRC_AHB2 (1 << 24)
81#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21)
82#define PL080_CONTROL_DWIDTH_SHIFT (21)
83#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18)
84#define PL080_CONTROL_SWIDTH_SHIFT (18)
85#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15)
86#define PL080_CONTROL_DB_SIZE_SHIFT (15)
87#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12)
88#define PL080_CONTROL_SB_SIZE_SHIFT (12)
89#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0)
Tomasz Figada1b6c02013-08-11 19:59:17 +020090#define PL080S_CONTROL_TRANSFER_SIZE_MASK (0x1ffffff << 0)
Ben Dooksfa7a7882009-03-10 23:57:26 +000091#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
92
93#define PL080_BSIZE_1 (0x0)
94#define PL080_BSIZE_4 (0x1)
95#define PL080_BSIZE_8 (0x2)
96#define PL080_BSIZE_16 (0x3)
97#define PL080_BSIZE_32 (0x4)
98#define PL080_BSIZE_64 (0x5)
99#define PL080_BSIZE_128 (0x6)
100#define PL080_BSIZE_256 (0x7)
101
102#define PL080_WIDTH_8BIT (0x0)
103#define PL080_WIDTH_16BIT (0x1)
104#define PL080_WIDTH_32BIT (0x2)
105
Linus Walleijaffa1152012-04-12 09:01:49 +0200106#define PL080N_CONFIG_ITPROT (1 << 20)
107#define PL080N_CONFIG_SECPROT (1 << 19)
Ben Dooksfa7a7882009-03-10 23:57:26 +0000108#define PL080_CONFIG_HALT (1 << 18)
109#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */
110#define PL080_CONFIG_LOCK (1 << 16)
111#define PL080_CONFIG_TC_IRQ_MASK (1 << 15)
112#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14)
113#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11)
114#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
115#define PL080_CONFIG_DST_SEL_MASK (0xf << 6)
116#define PL080_CONFIG_DST_SEL_SHIFT (6)
117#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1)
118#define PL080_CONFIG_SRC_SEL_SHIFT (1)
119#define PL080_CONFIG_ENABLE (1 << 0)
120
121#define PL080_FLOW_MEM2MEM (0x0)
122#define PL080_FLOW_MEM2PER (0x1)
123#define PL080_FLOW_PER2MEM (0x2)
124#define PL080_FLOW_SRC2DST (0x3)
125#define PL080_FLOW_SRC2DST_DST (0x4)
126#define PL080_FLOW_MEM2PER_PER (0x5)
127#define PL080_FLOW_PER2MEM_PER (0x6)
128#define PL080_FLOW_SRC2DST_SRC (0x7)
129
130/* DMA linked list chain structure */
131
132struct pl080_lli {
133 u32 src_addr;
134 u32 dst_addr;
135 u32 next_lli;
136 u32 control0;
137};
138
139struct pl080s_lli {
140 u32 src_addr;
141 u32 dst_addr;
142 u32 next_lli;
143 u32 control0;
144 u32 control1;
145};
146
Viresh Kumar47850a22011-08-05 15:32:26 +0530147#endif /* ASM_PL080_H */