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Vimal Singh67ce04b2009-05-12 13:47:03 -07001/*
2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
Russell King763e7352012-04-25 00:16:00 +010012#include <linux/dmaengine.h>
Vimal Singh67ce04b2009-05-12 13:47:03 -070013#include <linux/dma-mapping.h>
14#include <linux/delay.h>
Paul Gortmakera0e5cc52011-07-03 15:17:31 -040015#include <linux/module.h>
Sukumar Ghorai4e070372011-01-28 15:42:06 +053016#include <linux/interrupt.h>
vimal singhc276aca2009-06-27 11:07:06 +053017#include <linux/jiffies.h>
18#include <linux/sched.h>
Vimal Singh67ce04b2009-05-12 13:47:03 -070019#include <linux/mtd/mtd.h>
20#include <linux/mtd/nand.h>
21#include <linux/mtd/partitions.h>
Russell King763e7352012-04-25 00:16:00 +010022#include <linux/omap-dma.h>
Vimal Singh67ce04b2009-05-12 13:47:03 -070023#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090024#include <linux/slab.h>
Philip Avinash62116e52013-01-04 13:26:51 +053025#include <linux/of.h>
26#include <linux/of_device.h>
Vimal Singh67ce04b2009-05-12 13:47:03 -070027
Pekon Gupta32d42a82013-10-24 18:20:23 +053028#include <linux/mtd/nand_bch.h>
Philip Avinash62116e52013-01-04 13:26:51 +053029#include <linux/platform_data/elm.h>
Ivan Djelic0e618ef2012-04-30 12:17:18 +020030
Arnd Bergmann22037472012-08-24 15:21:06 +020031#include <linux/platform_data/mtd-nand-omap2.h>
Vimal Singh67ce04b2009-05-12 13:47:03 -070032
Vimal Singh67ce04b2009-05-12 13:47:03 -070033#define DRIVER_NAME "omap2-nand"
Sukumar Ghorai4e070372011-01-28 15:42:06 +053034#define OMAP_NAND_TIMEOUT_MS 5000
Vimal Singh67ce04b2009-05-12 13:47:03 -070035
Vimal Singh67ce04b2009-05-12 13:47:03 -070036#define NAND_Ecc_P1e (1 << 0)
37#define NAND_Ecc_P2e (1 << 1)
38#define NAND_Ecc_P4e (1 << 2)
39#define NAND_Ecc_P8e (1 << 3)
40#define NAND_Ecc_P16e (1 << 4)
41#define NAND_Ecc_P32e (1 << 5)
42#define NAND_Ecc_P64e (1 << 6)
43#define NAND_Ecc_P128e (1 << 7)
44#define NAND_Ecc_P256e (1 << 8)
45#define NAND_Ecc_P512e (1 << 9)
46#define NAND_Ecc_P1024e (1 << 10)
47#define NAND_Ecc_P2048e (1 << 11)
48
49#define NAND_Ecc_P1o (1 << 16)
50#define NAND_Ecc_P2o (1 << 17)
51#define NAND_Ecc_P4o (1 << 18)
52#define NAND_Ecc_P8o (1 << 19)
53#define NAND_Ecc_P16o (1 << 20)
54#define NAND_Ecc_P32o (1 << 21)
55#define NAND_Ecc_P64o (1 << 22)
56#define NAND_Ecc_P128o (1 << 23)
57#define NAND_Ecc_P256o (1 << 24)
58#define NAND_Ecc_P512o (1 << 25)
59#define NAND_Ecc_P1024o (1 << 26)
60#define NAND_Ecc_P2048o (1 << 27)
61
62#define TF(value) (value ? 1 : 0)
63
64#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
65#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
66#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
67#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
68#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
69#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
70#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
71#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
72
73#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
74#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
75#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
76#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
77#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
78#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
79#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
80#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
81
82#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
83#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
84#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
85#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
86#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
87#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
88#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
89#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
90
91#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
92#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
93#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
94#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
95#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
96#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
97#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
98#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
99
100#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
101#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
102
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700103#define PREFETCH_CONFIG1_CS_SHIFT 24
104#define ECC_CONFIG_CS_SHIFT 1
105#define CS_MASK 0x7
106#define ENABLE_PREFETCH (0x1 << 7)
107#define DMA_MPU_MODE_SHIFT 2
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +0530108#define ECCSIZE0_SHIFT 12
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700109#define ECCSIZE1_SHIFT 22
110#define ECC1RESULTSIZE 0x1
111#define ECCCLEAR 0x100
112#define ECC1 0x1
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530113#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
114#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
115#define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
116#define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
117#define STATUS_BUFF_EMPTY 0x00000001
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700118
Lokesh Vutlad5e7c862012-10-15 14:03:51 -0700119#define OMAP24XX_DMA_GPMC 4
120
Philip Avinash62116e52013-01-04 13:26:51 +0530121#define SECTOR_BYTES 512
122/* 4 bit padding to make byte aligned, 56 = 52 + 4 */
123#define BCH4_BIT_PAD 4
Philip Avinash62116e52013-01-04 13:26:51 +0530124
125/* GPMC ecc engine settings for read */
126#define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
127#define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */
128#define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */
129#define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */
130#define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */
131
132/* GPMC ecc engine settings for write */
133#define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
134#define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
135#define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */
136
Pekon Guptab491da72013-10-24 18:20:22 +0530137#define BADBLOCK_MARKER_LENGTH 2
Pekon Guptaa919e512013-10-24 18:20:21 +0530138
pekon gupta9748fff2014-03-24 16:50:05 +0530139static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55,
140 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78,
141 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93,
142 0x07, 0x0e};
Philip Avinash62116e52013-01-04 13:26:51 +0530143static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
144 0xac, 0x6b, 0xff, 0x99, 0x7b};
145static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
Philip Avinash62116e52013-01-04 13:26:51 +0530146
Rostislav Lisovy1dc338e2014-10-29 11:10:59 +0100147/* Shared among all NAND instances to synchronize access to the ECC Engine */
148static struct nand_hw_control omap_gpmc_controller = {
149 .lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock),
150 .wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq),
151};
vimal singh59e9c5a2009-07-13 16:26:24 +0530152
Vimal Singh67ce04b2009-05-12 13:47:03 -0700153struct omap_nand_info {
Vimal Singh67ce04b2009-05-12 13:47:03 -0700154 struct omap_nand_platform_data *pdata;
155 struct mtd_info mtd;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700156 struct nand_chip nand;
157 struct platform_device *pdev;
158
159 int gpmc_cs;
160 unsigned long phys_base;
Pekon Gupta4e558072014-03-18 18:56:42 +0530161 enum omap_ecc ecc_opt;
vimal singhdfe32892009-07-13 16:29:16 +0530162 struct completion comp;
Russell King763e7352012-04-25 00:16:00 +0100163 struct dma_chan *dma;
Afzal Mohammed5c468452012-08-30 12:53:24 -0700164 int gpmc_irq_fifo;
165 int gpmc_irq_count;
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530166 enum {
167 OMAP_NAND_IO_READ = 0, /* read */
168 OMAP_NAND_IO_WRITE, /* write */
169 } iomode;
170 u_char *buf;
171 int buf_len;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700172 struct gpmc_nand_regs reg;
Rostislav Lisovy94cb4ee2014-10-02 14:16:12 +0200173 /* generated at runtime depending on ECC algorithm and layout selected */
174 struct nand_ecclayout oobinfo;
Pekon Guptaa919e512013-10-24 18:20:21 +0530175 /* fields specific for BCHx_HW ECC scheme */
Philip Avinash62116e52013-01-04 13:26:51 +0530176 struct device *elm_dev;
177 struct device_node *of_node;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700178};
179
180/**
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700181 * omap_prefetch_enable - configures and starts prefetch transfer
182 * @cs: cs (chip select) number
183 * @fifo_th: fifo threshold to be used for read/ write
184 * @dma_mode: dma mode enable (1) or disable (0)
185 * @u32_count: number of bytes to be transferred
186 * @is_write: prefetch read(0) or write post(1) mode
187 */
188static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
189 unsigned int u32_count, int is_write, struct omap_nand_info *info)
190{
191 u32 val;
192
193 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
194 return -1;
195
196 if (readl(info->reg.gpmc_prefetch_control))
197 return -EBUSY;
198
199 /* Set the amount of bytes to be prefetched */
200 writel(u32_count, info->reg.gpmc_prefetch_config2);
201
202 /* Set dma/mpu mode, the prefetch read / post write and
203 * enable the engine. Set which cs is has requested for.
204 */
205 val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
206 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
207 (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
208 writel(val, info->reg.gpmc_prefetch_config1);
209
210 /* Start the prefetch engine */
211 writel(0x1, info->reg.gpmc_prefetch_control);
212
213 return 0;
214}
215
216/**
217 * omap_prefetch_reset - disables and stops the prefetch engine
218 */
219static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
220{
221 u32 config1;
222
223 /* check if the same module/cs is trying to reset */
224 config1 = readl(info->reg.gpmc_prefetch_config1);
225 if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
226 return -EINVAL;
227
228 /* Stop the PFPW engine */
229 writel(0x0, info->reg.gpmc_prefetch_control);
230
231 /* Reset/disable the PFPW engine */
232 writel(0x0, info->reg.gpmc_prefetch_config1);
233
234 return 0;
235}
236
237/**
Vimal Singh67ce04b2009-05-12 13:47:03 -0700238 * omap_hwcontrol - hardware specific access to control-lines
239 * @mtd: MTD device structure
240 * @cmd: command to device
241 * @ctrl:
242 * NAND_NCE: bit 0 -> don't care
243 * NAND_CLE: bit 1 -> Command Latch
244 * NAND_ALE: bit 2 -> Address Latch
245 *
246 * NOTE: boards may use different bits for these!!
247 */
248static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
249{
250 struct omap_nand_info *info = container_of(mtd,
251 struct omap_nand_info, mtd);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700252
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000253 if (cmd != NAND_CMD_NONE) {
254 if (ctrl & NAND_CLE)
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700255 writeb(cmd, info->reg.gpmc_nand_command);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700256
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000257 else if (ctrl & NAND_ALE)
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700258 writeb(cmd, info->reg.gpmc_nand_address);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000259
260 else /* NAND_NCE */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700261 writeb(cmd, info->reg.gpmc_nand_data);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700262 }
Vimal Singh67ce04b2009-05-12 13:47:03 -0700263}
264
265/**
vimal singh59e9c5a2009-07-13 16:26:24 +0530266 * omap_read_buf8 - read data from NAND controller into buffer
267 * @mtd: MTD device structure
268 * @buf: buffer to store date
269 * @len: number of bytes to read
270 */
271static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
272{
273 struct nand_chip *nand = mtd->priv;
274
275 ioread8_rep(nand->IO_ADDR_R, buf, len);
276}
277
278/**
279 * omap_write_buf8 - write buffer to NAND controller
280 * @mtd: MTD device structure
281 * @buf: data buffer
282 * @len: number of bytes to write
283 */
284static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
285{
286 struct omap_nand_info *info = container_of(mtd,
287 struct omap_nand_info, mtd);
288 u_char *p = (u_char *)buf;
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000289 u32 status = 0;
vimal singh59e9c5a2009-07-13 16:26:24 +0530290
291 while (len--) {
292 iowrite8(*p++, info->nand.IO_ADDR_W);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000293 /* wait until buffer is available for write */
294 do {
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700295 status = readl(info->reg.gpmc_status) &
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530296 STATUS_BUFF_EMPTY;
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000297 } while (!status);
vimal singh59e9c5a2009-07-13 16:26:24 +0530298 }
299}
300
301/**
Vimal Singh67ce04b2009-05-12 13:47:03 -0700302 * omap_read_buf16 - read data from NAND controller into buffer
303 * @mtd: MTD device structure
304 * @buf: buffer to store date
305 * @len: number of bytes to read
306 */
307static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
308{
309 struct nand_chip *nand = mtd->priv;
310
vimal singh59e9c5a2009-07-13 16:26:24 +0530311 ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700312}
313
314/**
315 * omap_write_buf16 - write buffer to NAND controller
316 * @mtd: MTD device structure
317 * @buf: data buffer
318 * @len: number of bytes to write
319 */
320static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
321{
322 struct omap_nand_info *info = container_of(mtd,
323 struct omap_nand_info, mtd);
324 u16 *p = (u16 *) buf;
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000325 u32 status = 0;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700326 /* FIXME try bursts of writesw() or DMA ... */
327 len >>= 1;
328
329 while (len--) {
vimal singh59e9c5a2009-07-13 16:26:24 +0530330 iowrite16(*p++, info->nand.IO_ADDR_W);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000331 /* wait until buffer is available for write */
332 do {
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700333 status = readl(info->reg.gpmc_status) &
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530334 STATUS_BUFF_EMPTY;
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000335 } while (!status);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700336 }
337}
vimal singh59e9c5a2009-07-13 16:26:24 +0530338
339/**
340 * omap_read_buf_pref - read data from NAND controller into buffer
341 * @mtd: MTD device structure
342 * @buf: buffer to store date
343 * @len: number of bytes to read
344 */
345static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
346{
347 struct omap_nand_info *info = container_of(mtd,
348 struct omap_nand_info, mtd);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000349 uint32_t r_count = 0;
vimal singh59e9c5a2009-07-13 16:26:24 +0530350 int ret = 0;
351 u32 *p = (u32 *)buf;
352
353 /* take care of subpage reads */
Vimal Singhc3341d02010-01-07 12:16:26 +0530354 if (len % 4) {
355 if (info->nand.options & NAND_BUSWIDTH_16)
356 omap_read_buf16(mtd, buf, len % 4);
357 else
358 omap_read_buf8(mtd, buf, len % 4);
359 p = (u32 *) (buf + len % 4);
360 len -= len % 4;
vimal singh59e9c5a2009-07-13 16:26:24 +0530361 }
vimal singh59e9c5a2009-07-13 16:26:24 +0530362
363 /* configure and start prefetch transfer */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700364 ret = omap_prefetch_enable(info->gpmc_cs,
365 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
vimal singh59e9c5a2009-07-13 16:26:24 +0530366 if (ret) {
367 /* PFPW engine is busy, use cpu copy method */
368 if (info->nand.options & NAND_BUSWIDTH_16)
Kishore Kadiyalac5d8c0c2011-05-11 21:17:27 +0530369 omap_read_buf16(mtd, (u_char *)p, len);
vimal singh59e9c5a2009-07-13 16:26:24 +0530370 else
Kishore Kadiyalac5d8c0c2011-05-11 21:17:27 +0530371 omap_read_buf8(mtd, (u_char *)p, len);
vimal singh59e9c5a2009-07-13 16:26:24 +0530372 } else {
373 do {
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700374 r_count = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530375 r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000376 r_count = r_count >> 2;
377 ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
vimal singh59e9c5a2009-07-13 16:26:24 +0530378 p += r_count;
379 len -= r_count << 2;
380 } while (len);
vimal singh59e9c5a2009-07-13 16:26:24 +0530381 /* disable and stop the PFPW engine */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700382 omap_prefetch_reset(info->gpmc_cs, info);
vimal singh59e9c5a2009-07-13 16:26:24 +0530383 }
384}
385
386/**
387 * omap_write_buf_pref - write buffer to NAND controller
388 * @mtd: MTD device structure
389 * @buf: data buffer
390 * @len: number of bytes to write
391 */
392static void omap_write_buf_pref(struct mtd_info *mtd,
393 const u_char *buf, int len)
394{
395 struct omap_nand_info *info = container_of(mtd,
396 struct omap_nand_info, mtd);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530397 uint32_t w_count = 0;
vimal singh59e9c5a2009-07-13 16:26:24 +0530398 int i = 0, ret = 0;
Kishore Kadiyalac5d8c0c2011-05-11 21:17:27 +0530399 u16 *p = (u16 *)buf;
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530400 unsigned long tim, limit;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700401 u32 val;
vimal singh59e9c5a2009-07-13 16:26:24 +0530402
403 /* take care of subpage writes */
404 if (len % 2 != 0) {
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000405 writeb(*buf, info->nand.IO_ADDR_W);
vimal singh59e9c5a2009-07-13 16:26:24 +0530406 p = (u16 *)(buf + 1);
407 len--;
408 }
409
410 /* configure and start prefetch transfer */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700411 ret = omap_prefetch_enable(info->gpmc_cs,
412 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
vimal singh59e9c5a2009-07-13 16:26:24 +0530413 if (ret) {
414 /* PFPW engine is busy, use cpu copy method */
415 if (info->nand.options & NAND_BUSWIDTH_16)
Kishore Kadiyalac5d8c0c2011-05-11 21:17:27 +0530416 omap_write_buf16(mtd, (u_char *)p, len);
vimal singh59e9c5a2009-07-13 16:26:24 +0530417 else
Kishore Kadiyalac5d8c0c2011-05-11 21:17:27 +0530418 omap_write_buf8(mtd, (u_char *)p, len);
vimal singh59e9c5a2009-07-13 16:26:24 +0530419 } else {
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000420 while (len) {
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700421 w_count = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530422 w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000423 w_count = w_count >> 1;
vimal singh59e9c5a2009-07-13 16:26:24 +0530424 for (i = 0; (i < w_count) && len; i++, len -= 2)
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000425 iowrite16(*p++, info->nand.IO_ADDR_W);
vimal singh59e9c5a2009-07-13 16:26:24 +0530426 }
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000427 /* wait for data to flushed-out before reset the prefetch */
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530428 tim = 0;
429 limit = (loops_per_jiffy *
430 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700431 do {
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530432 cpu_relax();
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700433 val = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530434 val = PREFETCH_STATUS_COUNT(val);
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700435 } while (val && (tim++ < limit));
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530436
vimal singh59e9c5a2009-07-13 16:26:24 +0530437 /* disable and stop the PFPW engine */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700438 omap_prefetch_reset(info->gpmc_cs, info);
vimal singh59e9c5a2009-07-13 16:26:24 +0530439 }
440}
441
vimal singhdfe32892009-07-13 16:29:16 +0530442/*
Russell King2df41d02012-04-25 00:19:39 +0100443 * omap_nand_dma_callback: callback on the completion of dma transfer
vimal singhdfe32892009-07-13 16:29:16 +0530444 * @data: pointer to completion data structure
445 */
Russell King763e7352012-04-25 00:16:00 +0100446static void omap_nand_dma_callback(void *data)
447{
448 complete((struct completion *) data);
449}
vimal singhdfe32892009-07-13 16:29:16 +0530450
451/*
Peter Meerwald4cacbe22012-07-19 13:21:04 +0200452 * omap_nand_dma_transfer: configure and start dma transfer
vimal singhdfe32892009-07-13 16:29:16 +0530453 * @mtd: MTD device structure
454 * @addr: virtual address in RAM of source/destination
455 * @len: number of data bytes to be transferred
456 * @is_write: flag for read/write operation
457 */
458static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
459 unsigned int len, int is_write)
460{
461 struct omap_nand_info *info = container_of(mtd,
462 struct omap_nand_info, mtd);
Russell King2df41d02012-04-25 00:19:39 +0100463 struct dma_async_tx_descriptor *tx;
vimal singhdfe32892009-07-13 16:29:16 +0530464 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
465 DMA_FROM_DEVICE;
Russell King2df41d02012-04-25 00:19:39 +0100466 struct scatterlist sg;
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530467 unsigned long tim, limit;
Russell King2df41d02012-04-25 00:19:39 +0100468 unsigned n;
469 int ret;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700470 u32 val;
vimal singhdfe32892009-07-13 16:29:16 +0530471
472 if (addr >= high_memory) {
473 struct page *p1;
474
475 if (((size_t)addr & PAGE_MASK) !=
476 ((size_t)(addr + len - 1) & PAGE_MASK))
477 goto out_copy;
478 p1 = vmalloc_to_page(addr);
479 if (!p1)
480 goto out_copy;
481 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
482 }
483
Russell King2df41d02012-04-25 00:19:39 +0100484 sg_init_one(&sg, addr, len);
485 n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
486 if (n == 0) {
vimal singhdfe32892009-07-13 16:29:16 +0530487 dev_err(&info->pdev->dev,
488 "Couldn't DMA map a %d byte buffer\n", len);
489 goto out_copy;
490 }
491
Russell King2df41d02012-04-25 00:19:39 +0100492 tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
493 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
494 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
495 if (!tx)
496 goto out_copy_unmap;
497
498 tx->callback = omap_nand_dma_callback;
499 tx->callback_param = &info->comp;
500 dmaengine_submit(tx);
501
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700502 /* configure and start prefetch transfer */
503 ret = omap_prefetch_enable(info->gpmc_cs,
504 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
vimal singhdfe32892009-07-13 16:29:16 +0530505 if (ret)
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530506 /* PFPW engine is busy, use cpu copy method */
Grazvydas Ignotasd7efe222012-04-11 04:04:34 +0300507 goto out_copy_unmap;
vimal singhdfe32892009-07-13 16:29:16 +0530508
509 init_completion(&info->comp);
Russell King2df41d02012-04-25 00:19:39 +0100510 dma_async_issue_pending(info->dma);
vimal singhdfe32892009-07-13 16:29:16 +0530511
512 /* setup and start DMA using dma_addr */
513 wait_for_completion(&info->comp);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530514 tim = 0;
515 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700516
517 do {
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530518 cpu_relax();
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700519 val = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530520 val = PREFETCH_STATUS_COUNT(val);
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700521 } while (val && (tim++ < limit));
vimal singhdfe32892009-07-13 16:29:16 +0530522
vimal singhdfe32892009-07-13 16:29:16 +0530523 /* disable and stop the PFPW engine */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700524 omap_prefetch_reset(info->gpmc_cs, info);
vimal singhdfe32892009-07-13 16:29:16 +0530525
Russell King2df41d02012-04-25 00:19:39 +0100526 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
vimal singhdfe32892009-07-13 16:29:16 +0530527 return 0;
528
Grazvydas Ignotasd7efe222012-04-11 04:04:34 +0300529out_copy_unmap:
Russell King2df41d02012-04-25 00:19:39 +0100530 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
vimal singhdfe32892009-07-13 16:29:16 +0530531out_copy:
532 if (info->nand.options & NAND_BUSWIDTH_16)
533 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
534 : omap_write_buf16(mtd, (u_char *) addr, len);
535 else
536 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
537 : omap_write_buf8(mtd, (u_char *) addr, len);
538 return 0;
539}
vimal singhdfe32892009-07-13 16:29:16 +0530540
541/**
542 * omap_read_buf_dma_pref - read data from NAND controller into buffer
543 * @mtd: MTD device structure
544 * @buf: buffer to store date
545 * @len: number of bytes to read
546 */
547static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
548{
549 if (len <= mtd->oobsize)
550 omap_read_buf_pref(mtd, buf, len);
551 else
552 /* start transfer in DMA mode */
553 omap_nand_dma_transfer(mtd, buf, len, 0x0);
554}
555
556/**
557 * omap_write_buf_dma_pref - write buffer to NAND controller
558 * @mtd: MTD device structure
559 * @buf: data buffer
560 * @len: number of bytes to write
561 */
562static void omap_write_buf_dma_pref(struct mtd_info *mtd,
563 const u_char *buf, int len)
564{
565 if (len <= mtd->oobsize)
566 omap_write_buf_pref(mtd, buf, len);
567 else
568 /* start transfer in DMA mode */
Vimal Singhbdaefc42010-01-05 12:49:24 +0530569 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
vimal singhdfe32892009-07-13 16:29:16 +0530570}
571
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530572/*
Peter Meerwald4cacbe22012-07-19 13:21:04 +0200573 * omap_nand_irq - GPMC irq handler
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530574 * @this_irq: gpmc irq number
575 * @dev: omap_nand_info structure pointer is passed here
576 */
577static irqreturn_t omap_nand_irq(int this_irq, void *dev)
578{
579 struct omap_nand_info *info = (struct omap_nand_info *) dev;
580 u32 bytes;
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530581
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700582 bytes = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530583 bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530584 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
585 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
Afzal Mohammed5c468452012-08-30 12:53:24 -0700586 if (this_irq == info->gpmc_irq_count)
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530587 goto done;
588
589 if (info->buf_len && (info->buf_len < bytes))
590 bytes = info->buf_len;
591 else if (!info->buf_len)
592 bytes = 0;
593 iowrite32_rep(info->nand.IO_ADDR_W,
594 (u32 *)info->buf, bytes >> 2);
595 info->buf = info->buf + bytes;
596 info->buf_len -= bytes;
597
598 } else {
599 ioread32_rep(info->nand.IO_ADDR_R,
600 (u32 *)info->buf, bytes >> 2);
601 info->buf = info->buf + bytes;
602
Afzal Mohammed5c468452012-08-30 12:53:24 -0700603 if (this_irq == info->gpmc_irq_count)
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530604 goto done;
605 }
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530606
607 return IRQ_HANDLED;
608
609done:
610 complete(&info->comp);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530611
Afzal Mohammed5c468452012-08-30 12:53:24 -0700612 disable_irq_nosync(info->gpmc_irq_fifo);
613 disable_irq_nosync(info->gpmc_irq_count);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530614
615 return IRQ_HANDLED;
616}
617
618/*
619 * omap_read_buf_irq_pref - read data from NAND controller into buffer
620 * @mtd: MTD device structure
621 * @buf: buffer to store date
622 * @len: number of bytes to read
623 */
624static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
625{
626 struct omap_nand_info *info = container_of(mtd,
627 struct omap_nand_info, mtd);
628 int ret = 0;
629
630 if (len <= mtd->oobsize) {
631 omap_read_buf_pref(mtd, buf, len);
632 return;
633 }
634
635 info->iomode = OMAP_NAND_IO_READ;
636 info->buf = buf;
637 init_completion(&info->comp);
638
639 /* configure and start prefetch transfer */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700640 ret = omap_prefetch_enable(info->gpmc_cs,
641 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530642 if (ret)
643 /* PFPW engine is busy, use cpu copy method */
644 goto out_copy;
645
646 info->buf_len = len;
Afzal Mohammed5c468452012-08-30 12:53:24 -0700647
648 enable_irq(info->gpmc_irq_count);
649 enable_irq(info->gpmc_irq_fifo);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530650
651 /* waiting for read to complete */
652 wait_for_completion(&info->comp);
653
654 /* disable and stop the PFPW engine */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700655 omap_prefetch_reset(info->gpmc_cs, info);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530656 return;
657
658out_copy:
659 if (info->nand.options & NAND_BUSWIDTH_16)
660 omap_read_buf16(mtd, buf, len);
661 else
662 omap_read_buf8(mtd, buf, len);
663}
664
665/*
666 * omap_write_buf_irq_pref - write buffer to NAND controller
667 * @mtd: MTD device structure
668 * @buf: data buffer
669 * @len: number of bytes to write
670 */
671static void omap_write_buf_irq_pref(struct mtd_info *mtd,
672 const u_char *buf, int len)
673{
674 struct omap_nand_info *info = container_of(mtd,
675 struct omap_nand_info, mtd);
676 int ret = 0;
677 unsigned long tim, limit;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700678 u32 val;
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530679
680 if (len <= mtd->oobsize) {
681 omap_write_buf_pref(mtd, buf, len);
682 return;
683 }
684
685 info->iomode = OMAP_NAND_IO_WRITE;
686 info->buf = (u_char *) buf;
687 init_completion(&info->comp);
688
Sukumar Ghorai317379a2011-01-28 15:42:07 +0530689 /* configure and start prefetch transfer : size=24 */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700690 ret = omap_prefetch_enable(info->gpmc_cs,
691 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530692 if (ret)
693 /* PFPW engine is busy, use cpu copy method */
694 goto out_copy;
695
696 info->buf_len = len;
Afzal Mohammed5c468452012-08-30 12:53:24 -0700697
698 enable_irq(info->gpmc_irq_count);
699 enable_irq(info->gpmc_irq_fifo);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530700
701 /* waiting for write to complete */
702 wait_for_completion(&info->comp);
Afzal Mohammed5c468452012-08-30 12:53:24 -0700703
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530704 /* wait for data to flushed-out before reset the prefetch */
705 tim = 0;
706 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700707 do {
708 val = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530709 val = PREFETCH_STATUS_COUNT(val);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530710 cpu_relax();
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700711 } while (val && (tim++ < limit));
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530712
713 /* disable and stop the PFPW engine */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700714 omap_prefetch_reset(info->gpmc_cs, info);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530715 return;
716
717out_copy:
718 if (info->nand.options & NAND_BUSWIDTH_16)
719 omap_write_buf16(mtd, buf, len);
720 else
721 omap_write_buf8(mtd, buf, len);
722}
723
Vimal Singh67ce04b2009-05-12 13:47:03 -0700724/**
Vimal Singh67ce04b2009-05-12 13:47:03 -0700725 * gen_true_ecc - This function will generate true ECC value
726 * @ecc_buf: buffer to store ecc code
727 *
728 * This generated true ECC value can be used when correcting
729 * data read from NAND flash memory core
730 */
731static void gen_true_ecc(u8 *ecc_buf)
732{
733 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
734 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
735
736 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
737 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
738 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
739 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
740 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
741 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
742}
743
744/**
745 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
746 * @ecc_data1: ecc code from nand spare area
747 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
748 * @page_data: page data
749 *
750 * This function compares two ECC's and indicates if there is an error.
751 * If the error can be corrected it will be corrected to the buffer.
John Ogness74f1b722011-02-28 13:12:46 +0100752 * If there is no error, %0 is returned. If there is an error but it
753 * was corrected, %1 is returned. Otherwise, %-1 is returned.
Vimal Singh67ce04b2009-05-12 13:47:03 -0700754 */
755static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
756 u8 *ecc_data2, /* read from register */
757 u8 *page_data)
758{
759 uint i;
760 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
761 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
762 u8 ecc_bit[24];
763 u8 ecc_sum = 0;
764 u8 find_bit = 0;
765 uint find_byte = 0;
766 int isEccFF;
767
768 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
769
770 gen_true_ecc(ecc_data1);
771 gen_true_ecc(ecc_data2);
772
773 for (i = 0; i <= 2; i++) {
774 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
775 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
776 }
777
778 for (i = 0; i < 8; i++) {
779 tmp0_bit[i] = *ecc_data1 % 2;
780 *ecc_data1 = *ecc_data1 / 2;
781 }
782
783 for (i = 0; i < 8; i++) {
784 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
785 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
786 }
787
788 for (i = 0; i < 8; i++) {
789 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
790 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
791 }
792
793 for (i = 0; i < 8; i++) {
794 comp0_bit[i] = *ecc_data2 % 2;
795 *ecc_data2 = *ecc_data2 / 2;
796 }
797
798 for (i = 0; i < 8; i++) {
799 comp1_bit[i] = *(ecc_data2 + 1) % 2;
800 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
801 }
802
803 for (i = 0; i < 8; i++) {
804 comp2_bit[i] = *(ecc_data2 + 2) % 2;
805 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
806 }
807
808 for (i = 0; i < 6; i++)
809 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
810
811 for (i = 0; i < 8; i++)
812 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
813
814 for (i = 0; i < 8; i++)
815 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
816
817 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
818 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
819
820 for (i = 0; i < 24; i++)
821 ecc_sum += ecc_bit[i];
822
823 switch (ecc_sum) {
824 case 0:
825 /* Not reached because this function is not called if
826 * ECC values are equal
827 */
828 return 0;
829
830 case 1:
831 /* Uncorrectable error */
Brian Norris289c0522011-07-19 10:06:09 -0700832 pr_debug("ECC UNCORRECTED_ERROR 1\n");
Vimal Singh67ce04b2009-05-12 13:47:03 -0700833 return -1;
834
835 case 11:
836 /* UN-Correctable error */
Brian Norris289c0522011-07-19 10:06:09 -0700837 pr_debug("ECC UNCORRECTED_ERROR B\n");
Vimal Singh67ce04b2009-05-12 13:47:03 -0700838 return -1;
839
840 case 12:
841 /* Correctable error */
842 find_byte = (ecc_bit[23] << 8) +
843 (ecc_bit[21] << 7) +
844 (ecc_bit[19] << 6) +
845 (ecc_bit[17] << 5) +
846 (ecc_bit[15] << 4) +
847 (ecc_bit[13] << 3) +
848 (ecc_bit[11] << 2) +
849 (ecc_bit[9] << 1) +
850 ecc_bit[7];
851
852 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
853
Brian Norris0a32a102011-07-19 10:06:10 -0700854 pr_debug("Correcting single bit ECC error at offset: "
855 "%d, bit: %d\n", find_byte, find_bit);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700856
857 page_data[find_byte] ^= (1 << find_bit);
858
John Ogness74f1b722011-02-28 13:12:46 +0100859 return 1;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700860 default:
861 if (isEccFF) {
862 if (ecc_data2[0] == 0 &&
863 ecc_data2[1] == 0 &&
864 ecc_data2[2] == 0)
865 return 0;
866 }
Brian Norris289c0522011-07-19 10:06:09 -0700867 pr_debug("UNCORRECTED_ERROR default\n");
Vimal Singh67ce04b2009-05-12 13:47:03 -0700868 return -1;
869 }
870}
871
872/**
873 * omap_correct_data - Compares the ECC read with HW generated ECC
874 * @mtd: MTD device structure
875 * @dat: page data
876 * @read_ecc: ecc read from nand flash
877 * @calc_ecc: ecc read from HW ECC registers
878 *
879 * Compares the ecc read from nand spare area with ECC registers values
John Ogness74f1b722011-02-28 13:12:46 +0100880 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
881 * detection and correction. If there are no errors, %0 is returned. If
882 * there were errors and all of the errors were corrected, the number of
883 * corrected errors is returned. If uncorrectable errors exist, %-1 is
884 * returned.
Vimal Singh67ce04b2009-05-12 13:47:03 -0700885 */
886static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
887 u_char *read_ecc, u_char *calc_ecc)
888{
889 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
890 mtd);
891 int blockCnt = 0, i = 0, ret = 0;
John Ogness74f1b722011-02-28 13:12:46 +0100892 int stat = 0;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700893
894 /* Ex NAND_ECC_HW12_2048 */
895 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
896 (info->nand.ecc.size == 2048))
897 blockCnt = 4;
898 else
899 blockCnt = 1;
900
901 for (i = 0; i < blockCnt; i++) {
902 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
903 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
904 if (ret < 0)
905 return ret;
John Ogness74f1b722011-02-28 13:12:46 +0100906 /* keep track of the number of corrected errors */
907 stat += ret;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700908 }
909 read_ecc += 3;
910 calc_ecc += 3;
911 dat += 512;
912 }
John Ogness74f1b722011-02-28 13:12:46 +0100913 return stat;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700914}
915
916/**
917 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
918 * @mtd: MTD device structure
919 * @dat: The pointer to data on which ecc is computed
920 * @ecc_code: The ecc_code buffer
921 *
922 * Using noninverted ECC can be considered ugly since writing a blank
923 * page ie. padding will clear the ECC bytes. This is no problem as long
924 * nobody is trying to write data on the seemingly unused page. Reading
925 * an erased page will produce an ECC mismatch between generated and read
926 * ECC bytes that has to be dealt with separately.
927 */
928static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
929 u_char *ecc_code)
930{
931 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
932 mtd);
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700933 u32 val;
934
935 val = readl(info->reg.gpmc_ecc_config);
Roger Quadros40ddbf52014-08-25 16:15:33 -0700936 if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs)
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700937 return -EINVAL;
938
939 /* read ecc result */
940 val = readl(info->reg.gpmc_ecc1_result);
941 *ecc_code++ = val; /* P128e, ..., P1e */
942 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
943 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
944 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
945
946 return 0;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700947}
948
949/**
950 * omap_enable_hwecc - This function enables the hardware ecc functionality
951 * @mtd: MTD device structure
952 * @mode: Read/Write mode
953 */
954static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
955{
956 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
957 mtd);
958 struct nand_chip *chip = mtd->priv;
959 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700960 u32 val;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700961
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700962 /* clear ecc and enable bits */
963 val = ECCCLEAR | ECC1;
964 writel(val, info->reg.gpmc_ecc_control);
965
966 /* program ecc and result sizes */
967 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
968 ECC1RESULTSIZE);
969 writel(val, info->reg.gpmc_ecc_size_config);
970
971 switch (mode) {
972 case NAND_ECC_READ:
973 case NAND_ECC_WRITE:
974 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
975 break;
976 case NAND_ECC_READSYN:
977 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
978 break;
979 default:
980 dev_info(&info->pdev->dev,
981 "error: unrecognized Mode[%d]!\n", mode);
982 break;
983 }
984
985 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
986 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
987 writel(val, info->reg.gpmc_ecc_config);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700988}
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000989
Vimal Singh67ce04b2009-05-12 13:47:03 -0700990/**
991 * omap_wait - wait until the command is done
992 * @mtd: MTD device structure
993 * @chip: NAND Chip structure
994 *
995 * Wait function is called during Program and erase operations and
996 * the way it is called from MTD layer, we should wait till the NAND
997 * chip is ready after the programming/erase operation has completed.
998 *
999 * Erase can take up to 400ms and program up to 20ms according to
1000 * general NAND and SmartMedia specs
1001 */
1002static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
1003{
1004 struct nand_chip *this = mtd->priv;
1005 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1006 mtd);
1007 unsigned long timeo = jiffies;
Ivan Djelica9c465f2012-04-17 13:11:53 +02001008 int status, state = this->state;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001009
1010 if (state == FL_ERASING)
Toan Pham4ff67722013-03-15 10:44:59 -07001011 timeo += msecs_to_jiffies(400);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001012 else
Toan Pham4ff67722013-03-15 10:44:59 -07001013 timeo += msecs_to_jiffies(20);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001014
Afzal Mohammed65b97cf2012-08-30 12:53:22 -07001015 writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001016 while (time_before(jiffies, timeo)) {
Afzal Mohammed65b97cf2012-08-30 12:53:22 -07001017 status = readb(info->reg.gpmc_nand_data);
vimal singhc276aca2009-06-27 11:07:06 +05301018 if (status & NAND_STATUS_READY)
Vimal Singh67ce04b2009-05-12 13:47:03 -07001019 break;
vimal singhc276aca2009-06-27 11:07:06 +05301020 cond_resched();
Vimal Singh67ce04b2009-05-12 13:47:03 -07001021 }
Ivan Djelica9c465f2012-04-17 13:11:53 +02001022
Afzal Mohammed4ea1e4b2012-09-29 11:22:21 +05301023 status = readb(info->reg.gpmc_nand_data);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001024 return status;
1025}
1026
1027/**
1028 * omap_dev_ready - calls the platform specific dev_ready function
1029 * @mtd: MTD device structure
1030 */
1031static int omap_dev_ready(struct mtd_info *mtd)
1032{
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +00001033 unsigned int val = 0;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001034 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1035 mtd);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001036
Afzal Mohammed65b97cf2012-08-30 12:53:22 -07001037 val = readl(info->reg.gpmc_status);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001038
Afzal Mohammed65b97cf2012-08-30 12:53:22 -07001039 if ((val & 0x100) == 0x100) {
1040 return 1;
1041 } else {
1042 return 0;
1043 }
Vimal Singh67ce04b2009-05-12 13:47:03 -07001044}
1045
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001046/**
Pekon Gupta7c977c32014-03-03 15:38:30 +05301047 * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001048 * @mtd: MTD device structure
1049 * @mode: Read/Write mode
Philip Avinash62116e52013-01-04 13:26:51 +05301050 *
Nicholas Mc Guire0760e812015-02-04 12:24:06 -05001051 * When using BCH with SW correction (i.e. no ELM), sector size is set
1052 * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
1053 * for both reading and writing with:
Philip Avinash62116e52013-01-04 13:26:51 +05301054 * eccsize0 = 0 (no additional protected byte in spare area)
1055 * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001056 */
Pekon Gupta7c977c32014-03-03 15:38:30 +05301057static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode)
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001058{
Pekon Gupta16e69322014-03-03 15:38:32 +05301059 unsigned int bch_type;
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301060 unsigned int dev_width, nsectors;
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001061 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1062 mtd);
Pekon Guptac5957a32014-03-03 15:38:31 +05301063 enum omap_ecc ecc_opt = info->ecc_opt;
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001064 struct nand_chip *chip = mtd->priv;
Philip Avinash62116e52013-01-04 13:26:51 +05301065 u32 val, wr_mode;
1066 unsigned int ecc_size1, ecc_size0;
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001067
Pekon Guptac5957a32014-03-03 15:38:31 +05301068 /* GPMC configurations for calculating ECC */
1069 switch (ecc_opt) {
1070 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
Pekon Gupta16e69322014-03-03 15:38:32 +05301071 bch_type = 0;
1072 nsectors = 1;
Nicholas Mc Guire0760e812015-02-04 12:24:06 -05001073 wr_mode = BCH_WRAPMODE_6;
1074 ecc_size0 = BCH_ECC_SIZE0;
1075 ecc_size1 = BCH_ECC_SIZE1;
Pekon Guptac5957a32014-03-03 15:38:31 +05301076 break;
1077 case OMAP_ECC_BCH4_CODE_HW:
Pekon Gupta16e69322014-03-03 15:38:32 +05301078 bch_type = 0;
1079 nsectors = chip->ecc.steps;
Pekon Guptac5957a32014-03-03 15:38:31 +05301080 if (mode == NAND_ECC_READ) {
1081 wr_mode = BCH_WRAPMODE_1;
1082 ecc_size0 = BCH4R_ECC_SIZE0;
1083 ecc_size1 = BCH4R_ECC_SIZE1;
1084 } else {
1085 wr_mode = BCH_WRAPMODE_6;
1086 ecc_size0 = BCH_ECC_SIZE0;
1087 ecc_size1 = BCH_ECC_SIZE1;
1088 }
1089 break;
1090 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
Pekon Gupta16e69322014-03-03 15:38:32 +05301091 bch_type = 1;
1092 nsectors = 1;
Nicholas Mc Guire0760e812015-02-04 12:24:06 -05001093 wr_mode = BCH_WRAPMODE_6;
1094 ecc_size0 = BCH_ECC_SIZE0;
1095 ecc_size1 = BCH_ECC_SIZE1;
Pekon Guptac5957a32014-03-03 15:38:31 +05301096 break;
1097 case OMAP_ECC_BCH8_CODE_HW:
Pekon Gupta16e69322014-03-03 15:38:32 +05301098 bch_type = 1;
1099 nsectors = chip->ecc.steps;
Pekon Guptac5957a32014-03-03 15:38:31 +05301100 if (mode == NAND_ECC_READ) {
1101 wr_mode = BCH_WRAPMODE_1;
1102 ecc_size0 = BCH8R_ECC_SIZE0;
1103 ecc_size1 = BCH8R_ECC_SIZE1;
1104 } else {
1105 wr_mode = BCH_WRAPMODE_6;
1106 ecc_size0 = BCH_ECC_SIZE0;
1107 ecc_size1 = BCH_ECC_SIZE1;
1108 }
1109 break;
pekon gupta9748fff2014-03-24 16:50:05 +05301110 case OMAP_ECC_BCH16_CODE_HW:
1111 bch_type = 0x2;
1112 nsectors = chip->ecc.steps;
1113 if (mode == NAND_ECC_READ) {
1114 wr_mode = 0x01;
1115 ecc_size0 = 52; /* ECC bits in nibbles per sector */
1116 ecc_size1 = 0; /* non-ECC bits in nibbles per sector */
1117 } else {
1118 wr_mode = 0x01;
1119 ecc_size0 = 0; /* extra bits in nibbles per sector */
1120 ecc_size1 = 52; /* OOB bits in nibbles per sector */
1121 }
1122 break;
Pekon Guptac5957a32014-03-03 15:38:31 +05301123 default:
1124 return;
1125 }
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301126
1127 writel(ECC1, info->reg.gpmc_ecc_control);
1128
Philip Avinash62116e52013-01-04 13:26:51 +05301129 /* Configure ecc size for BCH */
1130 val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301131 writel(val, info->reg.gpmc_ecc_size_config);
1132
Philip Avinash62116e52013-01-04 13:26:51 +05301133 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1134
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301135 /* BCH configuration */
1136 val = ((1 << 16) | /* enable BCH */
Pekon Gupta16e69322014-03-03 15:38:32 +05301137 (bch_type << 12) | /* BCH4/BCH8/BCH16 */
Philip Avinash62116e52013-01-04 13:26:51 +05301138 (wr_mode << 8) | /* wrap mode */
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301139 (dev_width << 7) | /* bus width */
1140 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1141 (info->gpmc_cs << 1) | /* ECC CS */
1142 (0x1)); /* enable ECC */
1143
1144 writel(val, info->reg.gpmc_ecc_config);
1145
Philip Avinash62116e52013-01-04 13:26:51 +05301146 /* Clear ecc and enable bits */
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301147 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001148}
Pekon Gupta7c977c32014-03-03 15:38:30 +05301149
Pekon Gupta2c9f2362014-02-26 15:53:13 +05301150static u8 bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f};
Pekon Gupta7bcd1dc2014-02-26 15:53:14 +05301151static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
1152 0x97, 0x79, 0xe5, 0x24, 0xb5};
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001153
1154/**
Pekon Guptaa4c7ca02014-02-26 15:53:11 +05301155 * omap_calculate_ecc_bch - Generate bytes of ECC bytes
Philip Avinash62116e52013-01-04 13:26:51 +05301156 * @mtd: MTD device structure
1157 * @dat: The pointer to data on which ecc is computed
1158 * @ecc_code: The ecc_code buffer
1159 *
1160 * Support calculating of BCH4/8 ecc vectors for the page
1161 */
Pekon Guptaa4c7ca02014-02-26 15:53:11 +05301162static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd,
Pekon Guptaf5dc06f2014-02-26 15:53:12 +05301163 const u_char *dat, u_char *ecc_calc)
Philip Avinash62116e52013-01-04 13:26:51 +05301164{
1165 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1166 mtd);
Pekon Guptaf5dc06f2014-02-26 15:53:12 +05301167 int eccbytes = info->nand.ecc.bytes;
1168 struct gpmc_nand_regs *gpmc_regs = &info->reg;
1169 u8 *ecc_code;
Philip Avinash62116e52013-01-04 13:26:51 +05301170 unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
pekon gupta9748fff2014-03-24 16:50:05 +05301171 u32 val;
Ted Juan2913aae2014-05-28 22:33:06 +08001172 int i, j;
Philip Avinash62116e52013-01-04 13:26:51 +05301173
1174 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
Philip Avinash62116e52013-01-04 13:26:51 +05301175 for (i = 0; i < nsectors; i++) {
Pekon Guptaf5dc06f2014-02-26 15:53:12 +05301176 ecc_code = ecc_calc;
1177 switch (info->ecc_opt) {
Pekon Gupta7bcd1dc2014-02-26 15:53:14 +05301178 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
Pekon Guptaf5dc06f2014-02-26 15:53:12 +05301179 case OMAP_ECC_BCH8_CODE_HW:
1180 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1181 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1182 bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]);
1183 bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]);
Philip Avinash62116e52013-01-04 13:26:51 +05301184 *ecc_code++ = (bch_val4 & 0xFF);
1185 *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1186 *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1187 *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1188 *ecc_code++ = (bch_val3 & 0xFF);
1189 *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1190 *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1191 *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1192 *ecc_code++ = (bch_val2 & 0xFF);
1193 *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1194 *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1195 *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1196 *ecc_code++ = (bch_val1 & 0xFF);
Pekon Guptaf5dc06f2014-02-26 15:53:12 +05301197 break;
Pekon Gupta2c9f2362014-02-26 15:53:13 +05301198 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
Pekon Guptaf5dc06f2014-02-26 15:53:12 +05301199 case OMAP_ECC_BCH4_CODE_HW:
1200 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1201 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
Philip Avinash62116e52013-01-04 13:26:51 +05301202 *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1203 *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1204 *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1205 ((bch_val1 >> 28) & 0xF);
1206 *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1207 *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1208 *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1209 *ecc_code++ = ((bch_val1 & 0xF) << 4);
Pekon Guptaf5dc06f2014-02-26 15:53:12 +05301210 break;
pekon gupta9748fff2014-03-24 16:50:05 +05301211 case OMAP_ECC_BCH16_CODE_HW:
1212 val = readl(gpmc_regs->gpmc_bch_result6[i]);
1213 ecc_code[0] = ((val >> 8) & 0xFF);
1214 ecc_code[1] = ((val >> 0) & 0xFF);
1215 val = readl(gpmc_regs->gpmc_bch_result5[i]);
1216 ecc_code[2] = ((val >> 24) & 0xFF);
1217 ecc_code[3] = ((val >> 16) & 0xFF);
1218 ecc_code[4] = ((val >> 8) & 0xFF);
1219 ecc_code[5] = ((val >> 0) & 0xFF);
1220 val = readl(gpmc_regs->gpmc_bch_result4[i]);
1221 ecc_code[6] = ((val >> 24) & 0xFF);
1222 ecc_code[7] = ((val >> 16) & 0xFF);
1223 ecc_code[8] = ((val >> 8) & 0xFF);
1224 ecc_code[9] = ((val >> 0) & 0xFF);
1225 val = readl(gpmc_regs->gpmc_bch_result3[i]);
1226 ecc_code[10] = ((val >> 24) & 0xFF);
1227 ecc_code[11] = ((val >> 16) & 0xFF);
1228 ecc_code[12] = ((val >> 8) & 0xFF);
1229 ecc_code[13] = ((val >> 0) & 0xFF);
1230 val = readl(gpmc_regs->gpmc_bch_result2[i]);
1231 ecc_code[14] = ((val >> 24) & 0xFF);
1232 ecc_code[15] = ((val >> 16) & 0xFF);
1233 ecc_code[16] = ((val >> 8) & 0xFF);
1234 ecc_code[17] = ((val >> 0) & 0xFF);
1235 val = readl(gpmc_regs->gpmc_bch_result1[i]);
1236 ecc_code[18] = ((val >> 24) & 0xFF);
1237 ecc_code[19] = ((val >> 16) & 0xFF);
1238 ecc_code[20] = ((val >> 8) & 0xFF);
1239 ecc_code[21] = ((val >> 0) & 0xFF);
1240 val = readl(gpmc_regs->gpmc_bch_result0[i]);
1241 ecc_code[22] = ((val >> 24) & 0xFF);
1242 ecc_code[23] = ((val >> 16) & 0xFF);
1243 ecc_code[24] = ((val >> 8) & 0xFF);
1244 ecc_code[25] = ((val >> 0) & 0xFF);
1245 break;
Pekon Guptaf5dc06f2014-02-26 15:53:12 +05301246 default:
1247 return -EINVAL;
Philip Avinash62116e52013-01-04 13:26:51 +05301248 }
Pekon Guptaf5dc06f2014-02-26 15:53:12 +05301249
1250 /* ECC scheme specific syndrome customizations */
1251 switch (info->ecc_opt) {
Pekon Gupta2c9f2362014-02-26 15:53:13 +05301252 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1253 /* Add constant polynomial to remainder, so that
1254 * ECC of blank pages results in 0x0 on reading back */
Ted Juan2913aae2014-05-28 22:33:06 +08001255 for (j = 0; j < eccbytes; j++)
1256 ecc_calc[j] ^= bch4_polynomial[j];
Pekon Gupta2c9f2362014-02-26 15:53:13 +05301257 break;
Pekon Guptaf5dc06f2014-02-26 15:53:12 +05301258 case OMAP_ECC_BCH4_CODE_HW:
1259 /* Set 8th ECC byte as 0x0 for ROM compatibility */
1260 ecc_calc[eccbytes - 1] = 0x0;
1261 break;
Pekon Gupta7bcd1dc2014-02-26 15:53:14 +05301262 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1263 /* Add constant polynomial to remainder, so that
1264 * ECC of blank pages results in 0x0 on reading back */
Ted Juan2913aae2014-05-28 22:33:06 +08001265 for (j = 0; j < eccbytes; j++)
1266 ecc_calc[j] ^= bch8_polynomial[j];
Pekon Gupta7bcd1dc2014-02-26 15:53:14 +05301267 break;
Pekon Guptaf5dc06f2014-02-26 15:53:12 +05301268 case OMAP_ECC_BCH8_CODE_HW:
1269 /* Set 14th ECC byte as 0x0 for ROM compatibility */
1270 ecc_calc[eccbytes - 1] = 0x0;
1271 break;
pekon gupta9748fff2014-03-24 16:50:05 +05301272 case OMAP_ECC_BCH16_CODE_HW:
1273 break;
Pekon Guptaf5dc06f2014-02-26 15:53:12 +05301274 default:
1275 return -EINVAL;
1276 }
1277
1278 ecc_calc += eccbytes;
Philip Avinash62116e52013-01-04 13:26:51 +05301279 }
1280
1281 return 0;
1282}
1283
1284/**
1285 * erased_sector_bitflips - count bit flips
1286 * @data: data sector buffer
1287 * @oob: oob buffer
1288 * @info: omap_nand_info
1289 *
1290 * Check the bit flips in erased page falls below correctable level.
1291 * If falls below, report the page as erased with correctable bit
1292 * flip, else report as uncorrectable page.
1293 */
1294static int erased_sector_bitflips(u_char *data, u_char *oob,
1295 struct omap_nand_info *info)
1296{
1297 int flip_bits = 0, i;
1298
1299 for (i = 0; i < info->nand.ecc.size; i++) {
1300 flip_bits += hweight8(~data[i]);
1301 if (flip_bits > info->nand.ecc.strength)
1302 return 0;
1303 }
1304
1305 for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1306 flip_bits += hweight8(~oob[i]);
1307 if (flip_bits > info->nand.ecc.strength)
1308 return 0;
1309 }
1310
1311 /*
1312 * Bit flips falls in correctable level.
1313 * Fill data area with 0xFF
1314 */
1315 if (flip_bits) {
1316 memset(data, 0xFF, info->nand.ecc.size);
1317 memset(oob, 0xFF, info->nand.ecc.bytes);
1318 }
1319
1320 return flip_bits;
1321}
1322
1323/**
1324 * omap_elm_correct_data - corrects page data area in case error reported
1325 * @mtd: MTD device structure
1326 * @data: page data
1327 * @read_ecc: ecc read from nand flash
1328 * @calc_ecc: ecc read from HW ECC registers
1329 *
1330 * Calculated ecc vector reported as zero in case of non-error pages.
Pekon Gupta78f43c52014-03-18 18:56:44 +05301331 * In case of non-zero ecc vector, first filter out erased-pages, and
1332 * then process data via ELM to detect bit-flips.
Philip Avinash62116e52013-01-04 13:26:51 +05301333 */
1334static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
1335 u_char *read_ecc, u_char *calc_ecc)
1336{
1337 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1338 mtd);
Pekon Guptade0a4d62014-03-18 18:56:43 +05301339 struct nand_ecc_ctrl *ecc = &info->nand.ecc;
Philip Avinash62116e52013-01-04 13:26:51 +05301340 int eccsteps = info->nand.ecc.steps;
1341 int i , j, stat = 0;
Pekon Guptade0a4d62014-03-18 18:56:43 +05301342 int eccflag, actual_eccbytes;
Philip Avinash62116e52013-01-04 13:26:51 +05301343 struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1344 u_char *ecc_vec = calc_ecc;
1345 u_char *spare_ecc = read_ecc;
1346 u_char *erased_ecc_vec;
Pekon Gupta78f43c52014-03-18 18:56:44 +05301347 u_char *buf;
1348 int bitflip_count;
Philip Avinash62116e52013-01-04 13:26:51 +05301349 bool is_error_reported = false;
Pekon Guptab08e1f62014-03-18 18:56:45 +05301350 u32 bit_pos, byte_pos, error_max, pos;
Pekon Gupta13fbe062014-03-18 18:56:46 +05301351 int err;
Philip Avinash62116e52013-01-04 13:26:51 +05301352
Pekon Guptade0a4d62014-03-18 18:56:43 +05301353 switch (info->ecc_opt) {
1354 case OMAP_ECC_BCH4_CODE_HW:
1355 /* omit 7th ECC byte reserved for ROM code compatibility */
1356 actual_eccbytes = ecc->bytes - 1;
Pekon Gupta78f43c52014-03-18 18:56:44 +05301357 erased_ecc_vec = bch4_vector;
Pekon Guptade0a4d62014-03-18 18:56:43 +05301358 break;
1359 case OMAP_ECC_BCH8_CODE_HW:
1360 /* omit 14th ECC byte reserved for ROM code compatibility */
1361 actual_eccbytes = ecc->bytes - 1;
Pekon Gupta78f43c52014-03-18 18:56:44 +05301362 erased_ecc_vec = bch8_vector;
Pekon Guptade0a4d62014-03-18 18:56:43 +05301363 break;
pekon gupta9748fff2014-03-24 16:50:05 +05301364 case OMAP_ECC_BCH16_CODE_HW:
1365 actual_eccbytes = ecc->bytes;
1366 erased_ecc_vec = bch16_vector;
1367 break;
Pekon Guptade0a4d62014-03-18 18:56:43 +05301368 default:
Ezequiel Garcíad2f08c72014-09-20 17:53:13 +01001369 dev_err(&info->pdev->dev, "invalid driver configuration\n");
Pekon Guptade0a4d62014-03-18 18:56:43 +05301370 return -EINVAL;
1371 }
1372
Philip Avinash62116e52013-01-04 13:26:51 +05301373 /* Initialize elm error vector to zero */
1374 memset(err_vec, 0, sizeof(err_vec));
1375
Philip Avinash62116e52013-01-04 13:26:51 +05301376 for (i = 0; i < eccsteps ; i++) {
1377 eccflag = 0; /* initialize eccflag */
1378
1379 /*
1380 * Check any error reported,
1381 * In case of error, non zero ecc reported.
1382 */
Pekon Guptade0a4d62014-03-18 18:56:43 +05301383 for (j = 0; j < actual_eccbytes; j++) {
Philip Avinash62116e52013-01-04 13:26:51 +05301384 if (calc_ecc[j] != 0) {
1385 eccflag = 1; /* non zero ecc, error present */
1386 break;
1387 }
1388 }
1389
1390 if (eccflag == 1) {
Pekon Gupta78f43c52014-03-18 18:56:44 +05301391 if (memcmp(calc_ecc, erased_ecc_vec,
1392 actual_eccbytes) == 0) {
Philip Avinash62116e52013-01-04 13:26:51 +05301393 /*
Pekon Gupta78f43c52014-03-18 18:56:44 +05301394 * calc_ecc[] matches pattern for ECC(all 0xff)
1395 * so this is definitely an erased-page
Philip Avinash62116e52013-01-04 13:26:51 +05301396 */
Philip Avinash62116e52013-01-04 13:26:51 +05301397 } else {
Pekon Gupta78f43c52014-03-18 18:56:44 +05301398 buf = &data[info->nand.ecc.size * i];
1399 /*
1400 * count number of 0-bits in read_buf.
1401 * This check can be removed once a similar
1402 * check is introduced in generic NAND driver
1403 */
1404 bitflip_count = erased_sector_bitflips(
1405 buf, read_ecc, info);
1406 if (bitflip_count) {
1407 /*
1408 * number of 0-bits within ECC limits
1409 * So this may be an erased-page
1410 */
1411 stat += bitflip_count;
1412 } else {
1413 /*
1414 * Too many 0-bits. It may be a
1415 * - programmed-page, OR
1416 * - erased-page with many bit-flips
1417 * So this page requires check by ELM
1418 */
1419 err_vec[i].error_reported = true;
1420 is_error_reported = true;
Philip Avinash62116e52013-01-04 13:26:51 +05301421 }
1422 }
1423 }
1424
1425 /* Update the ecc vector */
Pekon Guptade0a4d62014-03-18 18:56:43 +05301426 calc_ecc += ecc->bytes;
1427 read_ecc += ecc->bytes;
Philip Avinash62116e52013-01-04 13:26:51 +05301428 }
1429
1430 /* Check if any error reported */
1431 if (!is_error_reported)
pekon guptaf306e8c2014-03-20 18:49:58 +05301432 return stat;
Philip Avinash62116e52013-01-04 13:26:51 +05301433
1434 /* Decode BCH error using ELM module */
1435 elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1436
Pekon Gupta13fbe062014-03-18 18:56:46 +05301437 err = 0;
Philip Avinash62116e52013-01-04 13:26:51 +05301438 for (i = 0; i < eccsteps; i++) {
Pekon Gupta13fbe062014-03-18 18:56:46 +05301439 if (err_vec[i].error_uncorrectable) {
Ezequiel Garcíad2f08c72014-09-20 17:53:13 +01001440 dev_err(&info->pdev->dev,
1441 "uncorrectable bit-flips found\n");
Pekon Gupta13fbe062014-03-18 18:56:46 +05301442 err = -EBADMSG;
1443 } else if (err_vec[i].error_reported) {
Philip Avinash62116e52013-01-04 13:26:51 +05301444 for (j = 0; j < err_vec[i].error_count; j++) {
Pekon Guptab08e1f62014-03-18 18:56:45 +05301445 switch (info->ecc_opt) {
1446 case OMAP_ECC_BCH4_CODE_HW:
1447 /* Add 4 bits to take care of padding */
Philip Avinash62116e52013-01-04 13:26:51 +05301448 pos = err_vec[i].error_loc[j] +
1449 BCH4_BIT_PAD;
Pekon Guptab08e1f62014-03-18 18:56:45 +05301450 break;
1451 case OMAP_ECC_BCH8_CODE_HW:
pekon gupta9748fff2014-03-24 16:50:05 +05301452 case OMAP_ECC_BCH16_CODE_HW:
Pekon Guptab08e1f62014-03-18 18:56:45 +05301453 pos = err_vec[i].error_loc[j];
1454 break;
1455 default:
1456 return -EINVAL;
1457 }
1458 error_max = (ecc->size + actual_eccbytes) * 8;
Philip Avinash62116e52013-01-04 13:26:51 +05301459 /* Calculate bit position of error */
1460 bit_pos = pos % 8;
1461
1462 /* Calculate byte position of error */
1463 byte_pos = (error_max - pos - 1) / 8;
1464
1465 if (pos < error_max) {
Pekon Gupta13fbe062014-03-18 18:56:46 +05301466 if (byte_pos < 512) {
1467 pr_debug("bitflip@dat[%d]=%x\n",
1468 byte_pos, data[byte_pos]);
Philip Avinash62116e52013-01-04 13:26:51 +05301469 data[byte_pos] ^= 1 << bit_pos;
Pekon Gupta13fbe062014-03-18 18:56:46 +05301470 } else {
1471 pr_debug("bitflip@oob[%d]=%x\n",
1472 (byte_pos - 512),
1473 spare_ecc[byte_pos - 512]);
Philip Avinash62116e52013-01-04 13:26:51 +05301474 spare_ecc[byte_pos - 512] ^=
1475 1 << bit_pos;
Pekon Gupta13fbe062014-03-18 18:56:46 +05301476 }
1477 } else {
Ezequiel Garcíad2f08c72014-09-20 17:53:13 +01001478 dev_err(&info->pdev->dev,
1479 "invalid bit-flip @ %d:%d\n",
1480 byte_pos, bit_pos);
Pekon Gupta13fbe062014-03-18 18:56:46 +05301481 err = -EBADMSG;
Philip Avinash62116e52013-01-04 13:26:51 +05301482 }
Philip Avinash62116e52013-01-04 13:26:51 +05301483 }
1484 }
1485
1486 /* Update number of correctable errors */
1487 stat += err_vec[i].error_count;
1488
1489 /* Update page data with sector size */
Pekon Guptab08e1f62014-03-18 18:56:45 +05301490 data += ecc->size;
Pekon Guptade0a4d62014-03-18 18:56:43 +05301491 spare_ecc += ecc->bytes;
Philip Avinash62116e52013-01-04 13:26:51 +05301492 }
1493
Pekon Gupta13fbe062014-03-18 18:56:46 +05301494 return (err) ? err : stat;
Philip Avinash62116e52013-01-04 13:26:51 +05301495}
1496
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001497/**
Philip Avinash62116e52013-01-04 13:26:51 +05301498 * omap_write_page_bch - BCH ecc based write page function for entire page
1499 * @mtd: mtd info structure
1500 * @chip: nand chip info structure
1501 * @buf: data buffer
1502 * @oob_required: must write chip->oob_poi to OOB
Boris BREZILLON45aaeff2015-10-13 11:22:18 +02001503 * @page: page
Philip Avinash62116e52013-01-04 13:26:51 +05301504 *
1505 * Custom write page method evolved to support multi sector writing in one shot
1506 */
1507static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
Boris BREZILLON45aaeff2015-10-13 11:22:18 +02001508 const uint8_t *buf, int oob_required, int page)
Philip Avinash62116e52013-01-04 13:26:51 +05301509{
1510 int i;
1511 uint8_t *ecc_calc = chip->buffers->ecccalc;
1512 uint32_t *eccpos = chip->ecc.layout->eccpos;
1513
1514 /* Enable GPMC ecc engine */
1515 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1516
1517 /* Write data */
1518 chip->write_buf(mtd, buf, mtd->writesize);
1519
1520 /* Update ecc vector from GPMC result registers */
1521 chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
1522
1523 for (i = 0; i < chip->ecc.total; i++)
1524 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1525
1526 /* Write ecc vector to OOB area */
1527 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1528 return 0;
1529}
1530
1531/**
1532 * omap_read_page_bch - BCH ecc based page read function for entire page
1533 * @mtd: mtd info structure
1534 * @chip: nand chip info structure
1535 * @buf: buffer to store read data
1536 * @oob_required: caller requires OOB data read to chip->oob_poi
1537 * @page: page number to read
1538 *
1539 * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1540 * used for error correction.
1541 * Custom method evolved to support ELM error correction & multi sector
1542 * reading. On reading page data area is read along with OOB data with
1543 * ecc engine enabled. ecc vector updated after read of OOB data.
1544 * For non error pages ecc vector reported as zero.
1545 */
1546static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1547 uint8_t *buf, int oob_required, int page)
1548{
1549 uint8_t *ecc_calc = chip->buffers->ecccalc;
1550 uint8_t *ecc_code = chip->buffers->ecccode;
1551 uint32_t *eccpos = chip->ecc.layout->eccpos;
1552 uint8_t *oob = &chip->oob_poi[eccpos[0]];
1553 uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0];
1554 int stat;
1555 unsigned int max_bitflips = 0;
1556
1557 /* Enable GPMC ecc engine */
1558 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1559
1560 /* Read data */
1561 chip->read_buf(mtd, buf, mtd->writesize);
1562
1563 /* Read oob bytes */
1564 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
1565 chip->read_buf(mtd, oob, chip->ecc.total);
1566
1567 /* Calculate ecc bytes */
1568 chip->ecc.calculate(mtd, buf, ecc_calc);
1569
1570 memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total);
1571
1572 stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc);
1573
1574 if (stat < 0) {
1575 mtd->ecc_stats.failed++;
1576 } else {
1577 mtd->ecc_stats.corrected += stat;
1578 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1579 }
1580
1581 return max_bitflips;
1582}
1583
1584/**
Pekon Guptaa919e512013-10-24 18:20:21 +05301585 * is_elm_present - checks for presence of ELM module by scanning DT nodes
1586 * @omap_nand_info: NAND device structure containing platform data
Pekon Guptaa919e512013-10-24 18:20:21 +05301587 */
Ezequiel García93af53b2014-09-20 17:53:12 +01001588static bool is_elm_present(struct omap_nand_info *info,
1589 struct device_node *elm_node)
Pekon Guptaa919e512013-10-24 18:20:21 +05301590{
1591 struct platform_device *pdev;
Ezequiel García93af53b2014-09-20 17:53:12 +01001592
Pekon Guptaa919e512013-10-24 18:20:21 +05301593 /* check whether elm-id is passed via DT */
1594 if (!elm_node) {
Ezequiel Garcíad2f08c72014-09-20 17:53:13 +01001595 dev_err(&info->pdev->dev, "ELM devicetree node not found\n");
Ezequiel García93af53b2014-09-20 17:53:12 +01001596 return false;
Pekon Guptaa919e512013-10-24 18:20:21 +05301597 }
1598 pdev = of_find_device_by_node(elm_node);
1599 /* check whether ELM device is registered */
1600 if (!pdev) {
Ezequiel Garcíad2f08c72014-09-20 17:53:13 +01001601 dev_err(&info->pdev->dev, "ELM device not found\n");
Ezequiel García93af53b2014-09-20 17:53:12 +01001602 return false;
Pekon Guptaa919e512013-10-24 18:20:21 +05301603 }
1604 /* ELM module available, now configure it */
1605 info->elm_dev = &pdev->dev;
Ezequiel García93af53b2014-09-20 17:53:12 +01001606 return true;
Pekon Guptaa919e512013-10-24 18:20:21 +05301607}
Ezequiel García93af53b2014-09-20 17:53:12 +01001608
1609static bool omap2_nand_ecc_check(struct omap_nand_info *info,
1610 struct omap_nand_platform_data *pdata)
1611{
1612 bool ecc_needs_bch, ecc_needs_omap_bch, ecc_needs_elm;
1613
1614 switch (info->ecc_opt) {
1615 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1616 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1617 ecc_needs_omap_bch = false;
1618 ecc_needs_bch = true;
1619 ecc_needs_elm = false;
1620 break;
1621 case OMAP_ECC_BCH4_CODE_HW:
1622 case OMAP_ECC_BCH8_CODE_HW:
1623 case OMAP_ECC_BCH16_CODE_HW:
1624 ecc_needs_omap_bch = true;
1625 ecc_needs_bch = false;
1626 ecc_needs_elm = true;
1627 break;
1628 default:
1629 ecc_needs_omap_bch = false;
1630 ecc_needs_bch = false;
1631 ecc_needs_elm = false;
1632 break;
1633 }
1634
1635 if (ecc_needs_bch && !IS_ENABLED(CONFIG_MTD_NAND_ECC_BCH)) {
1636 dev_err(&info->pdev->dev,
1637 "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1638 return false;
1639 }
1640 if (ecc_needs_omap_bch && !IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH)) {
1641 dev_err(&info->pdev->dev,
1642 "CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1643 return false;
1644 }
1645 if (ecc_needs_elm && !is_elm_present(info, pdata->elm_of_node)) {
1646 dev_err(&info->pdev->dev, "ELM not available\n");
1647 return false;
1648 }
1649
1650 return true;
1651}
Pekon Guptaa919e512013-10-24 18:20:21 +05301652
Bill Pemberton06f25512012-11-19 13:23:07 -05001653static int omap_nand_probe(struct platform_device *pdev)
Vimal Singh67ce04b2009-05-12 13:47:03 -07001654{
1655 struct omap_nand_info *info;
1656 struct omap_nand_platform_data *pdata;
Pekon Gupta633deb52013-10-24 18:20:19 +05301657 struct mtd_info *mtd;
1658 struct nand_chip *nand_chip;
Pekon Guptab491da72013-10-24 18:20:22 +05301659 struct nand_ecclayout *ecclayout;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001660 int err;
Pekon Guptab491da72013-10-24 18:20:22 +05301661 int i;
Pekon Gupta633deb52013-10-24 18:20:19 +05301662 dma_cap_mask_t mask;
1663 unsigned sig;
Pekon Guptaeae39cb2014-02-17 13:11:23 +05301664 unsigned oob_index;
Afzal Mohammed9c4c2f82012-08-30 12:53:23 -07001665 struct resource *res;
Daniel Mackccf04c52012-12-14 11:36:41 +01001666 struct mtd_part_parser_data ppdata = {};
Vimal Singh67ce04b2009-05-12 13:47:03 -07001667
Jingoo Han453810b2013-07-30 17:18:33 +09001668 pdata = dev_get_platdata(&pdev->dev);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001669 if (pdata == NULL) {
1670 dev_err(&pdev->dev, "platform data missing\n");
1671 return -ENODEV;
1672 }
1673
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301674 info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
1675 GFP_KERNEL);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001676 if (!info)
1677 return -ENOMEM;
1678
1679 platform_set_drvdata(pdev, info);
1680
Pekon Gupta633deb52013-10-24 18:20:19 +05301681 info->pdev = pdev;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001682 info->gpmc_cs = pdata->cs;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -07001683 info->reg = pdata->reg;
Pekon Guptaa919e512013-10-24 18:20:21 +05301684 info->of_node = pdata->of_node;
Pekon Gupta4e558072014-03-18 18:56:42 +05301685 info->ecc_opt = pdata->ecc_opt;
Pekon Gupta633deb52013-10-24 18:20:19 +05301686 mtd = &info->mtd;
1687 mtd->priv = &info->nand;
Frans Klaver853f1c52015-06-10 22:38:57 +02001688 mtd->dev.parent = &pdev->dev;
Pekon Gupta633deb52013-10-24 18:20:19 +05301689 nand_chip = &info->nand;
Pekon Gupta32d42a82013-10-24 18:20:23 +05301690 nand_chip->ecc.priv = NULL;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001691
Afzal Mohammed9c4c2f82012-08-30 12:53:23 -07001692 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Jingoo Han00d09892014-02-12 11:34:37 +09001693 nand_chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
1694 if (IS_ERR(nand_chip->IO_ADDR_R))
1695 return PTR_ERR(nand_chip->IO_ADDR_R);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001696
Afzal Mohammed9c4c2f82012-08-30 12:53:23 -07001697 info->phys_base = res->start;
vimal singh59e9c5a2009-07-13 16:26:24 +05301698
Rostislav Lisovy1dc338e2014-10-29 11:10:59 +01001699 nand_chip->controller = &omap_gpmc_controller;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001700
Pekon Gupta633deb52013-10-24 18:20:19 +05301701 nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1702 nand_chip->cmd_ctrl = omap_hwcontrol;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001703
Vimal Singh67ce04b2009-05-12 13:47:03 -07001704 /*
1705 * If RDY/BSY line is connected to OMAP then use the omap ready
Peter Meerwald4cacbe22012-07-19 13:21:04 +02001706 * function and the generic nand_wait function which reads the status
1707 * register after monitoring the RDY/BSY line. Otherwise use a standard
Vimal Singh67ce04b2009-05-12 13:47:03 -07001708 * chip delay which is slightly more than tR (AC Timing) of the NAND
1709 * device and read status register until you get a failure or success
1710 */
1711 if (pdata->dev_ready) {
Pekon Gupta633deb52013-10-24 18:20:19 +05301712 nand_chip->dev_ready = omap_dev_ready;
1713 nand_chip->chip_delay = 0;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001714 } else {
Pekon Gupta633deb52013-10-24 18:20:19 +05301715 nand_chip->waitfunc = omap_wait;
1716 nand_chip->chip_delay = 50;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001717 }
1718
Ezequiel Garcíafef775c2014-09-11 12:02:08 -03001719 if (pdata->flash_bbt)
1720 nand_chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1721 else
1722 nand_chip->options |= NAND_SKIP_BBTSCAN;
1723
Pekon Guptaf18befb2013-10-24 18:20:20 +05301724 /* scan NAND device connected to chip controller */
1725 nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16;
1726 if (nand_scan_ident(mtd, 1, NULL)) {
Ezequiel Garcíad2f08c72014-09-20 17:53:13 +01001727 dev_err(&info->pdev->dev, "scan failed, may be bus-width mismatch\n");
Pekon Guptaf18befb2013-10-24 18:20:20 +05301728 err = -ENXIO;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301729 goto return_error;
Pekon Guptaf18befb2013-10-24 18:20:20 +05301730 }
1731
1732 /* re-populate low-level callbacks based on xfer modes */
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301733 switch (pdata->xfer_type) {
1734 case NAND_OMAP_PREFETCH_POLLED:
Pekon Gupta633deb52013-10-24 18:20:19 +05301735 nand_chip->read_buf = omap_read_buf_pref;
1736 nand_chip->write_buf = omap_write_buf_pref;
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301737 break;
vimal singhdfe32892009-07-13 16:29:16 +05301738
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301739 case NAND_OMAP_POLLED:
Brian Norriscf0e4d22013-10-30 19:39:51 -04001740 /* Use nand_base defaults for {read,write}_buf */
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301741 break;
1742
1743 case NAND_OMAP_PREFETCH_DMA:
Russell King763e7352012-04-25 00:16:00 +01001744 dma_cap_zero(mask);
1745 dma_cap_set(DMA_SLAVE, mask);
1746 sig = OMAP24XX_DMA_GPMC;
1747 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1748 if (!info->dma) {
Russell King2df41d02012-04-25 00:19:39 +01001749 dev_err(&pdev->dev, "DMA engine request failed\n");
1750 err = -ENXIO;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301751 goto return_error;
Russell King763e7352012-04-25 00:16:00 +01001752 } else {
1753 struct dma_slave_config cfg;
Russell King763e7352012-04-25 00:16:00 +01001754
1755 memset(&cfg, 0, sizeof(cfg));
1756 cfg.src_addr = info->phys_base;
1757 cfg.dst_addr = info->phys_base;
1758 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1759 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1760 cfg.src_maxburst = 16;
1761 cfg.dst_maxburst = 16;
Arnd Bergmannd680e2c2012-08-04 11:05:25 +00001762 err = dmaengine_slave_config(info->dma, &cfg);
1763 if (err) {
Russell King763e7352012-04-25 00:16:00 +01001764 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
Arnd Bergmannd680e2c2012-08-04 11:05:25 +00001765 err);
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301766 goto return_error;
Russell King763e7352012-04-25 00:16:00 +01001767 }
Pekon Gupta633deb52013-10-24 18:20:19 +05301768 nand_chip->read_buf = omap_read_buf_dma_pref;
1769 nand_chip->write_buf = omap_write_buf_dma_pref;
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301770 }
1771 break;
1772
Sukumar Ghorai4e070372011-01-28 15:42:06 +05301773 case NAND_OMAP_PREFETCH_IRQ:
Afzal Mohammed5c468452012-08-30 12:53:24 -07001774 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1775 if (info->gpmc_irq_fifo <= 0) {
1776 dev_err(&pdev->dev, "error getting fifo irq\n");
1777 err = -ENODEV;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301778 goto return_error;
Afzal Mohammed5c468452012-08-30 12:53:24 -07001779 }
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301780 err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
1781 omap_nand_irq, IRQF_SHARED,
1782 "gpmc-nand-fifo", info);
Sukumar Ghorai4e070372011-01-28 15:42:06 +05301783 if (err) {
1784 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
Afzal Mohammed5c468452012-08-30 12:53:24 -07001785 info->gpmc_irq_fifo, err);
1786 info->gpmc_irq_fifo = 0;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301787 goto return_error;
Sukumar Ghorai4e070372011-01-28 15:42:06 +05301788 }
Afzal Mohammed5c468452012-08-30 12:53:24 -07001789
1790 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1791 if (info->gpmc_irq_count <= 0) {
1792 dev_err(&pdev->dev, "error getting count irq\n");
1793 err = -ENODEV;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301794 goto return_error;
Afzal Mohammed5c468452012-08-30 12:53:24 -07001795 }
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301796 err = devm_request_irq(&pdev->dev, info->gpmc_irq_count,
1797 omap_nand_irq, IRQF_SHARED,
1798 "gpmc-nand-count", info);
Afzal Mohammed5c468452012-08-30 12:53:24 -07001799 if (err) {
1800 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1801 info->gpmc_irq_count, err);
1802 info->gpmc_irq_count = 0;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301803 goto return_error;
Afzal Mohammed5c468452012-08-30 12:53:24 -07001804 }
1805
Pekon Gupta633deb52013-10-24 18:20:19 +05301806 nand_chip->read_buf = omap_read_buf_irq_pref;
1807 nand_chip->write_buf = omap_write_buf_irq_pref;
Afzal Mohammed5c468452012-08-30 12:53:24 -07001808
Sukumar Ghorai4e070372011-01-28 15:42:06 +05301809 break;
1810
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301811 default:
1812 dev_err(&pdev->dev,
1813 "xfer_type(%d) not supported!\n", pdata->xfer_type);
1814 err = -EINVAL;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301815 goto return_error;
vimal singh59e9c5a2009-07-13 16:26:24 +05301816 }
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301817
Ezequiel García93af53b2014-09-20 17:53:12 +01001818 if (!omap2_nand_ecc_check(info, pdata)) {
1819 err = -EINVAL;
1820 goto return_error;
1821 }
1822
Pekon Guptaa919e512013-10-24 18:20:21 +05301823 /* populate MTD interface based on ECC scheme */
Rostislav Lisovy94cb4ee2014-10-02 14:16:12 +02001824 ecclayout = &info->oobinfo;
Pekon Gupta4e558072014-03-18 18:56:42 +05301825 switch (info->ecc_opt) {
Roger Quadros7d5929c2014-08-25 16:15:32 -07001826 case OMAP_ECC_HAM1_CODE_SW:
1827 nand_chip->ecc.mode = NAND_ECC_SOFT;
1828 break;
1829
Pekon Guptaa919e512013-10-24 18:20:21 +05301830 case OMAP_ECC_HAM1_CODE_HW:
1831 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
1832 nand_chip->ecc.mode = NAND_ECC_HW;
Pekon Gupta633deb52013-10-24 18:20:19 +05301833 nand_chip->ecc.bytes = 3;
1834 nand_chip->ecc.size = 512;
1835 nand_chip->ecc.strength = 1;
1836 nand_chip->ecc.calculate = omap_calculate_ecc;
1837 nand_chip->ecc.hwctl = omap_enable_hwecc;
1838 nand_chip->ecc.correct = omap_correct_data;
Pekon Guptab491da72013-10-24 18:20:22 +05301839 /* define ECC layout */
1840 ecclayout->eccbytes = nand_chip->ecc.bytes *
1841 (mtd->writesize /
1842 nand_chip->ecc.size);
1843 if (nand_chip->options & NAND_BUSWIDTH_16)
Pekon Guptaeae39cb2014-02-17 13:11:23 +05301844 oob_index = BADBLOCK_MARKER_LENGTH;
Pekon Guptab491da72013-10-24 18:20:22 +05301845 else
Pekon Guptaeae39cb2014-02-17 13:11:23 +05301846 oob_index = 1;
1847 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1848 ecclayout->eccpos[i] = oob_index;
Pekon Guptaaa6092f2014-02-17 13:11:24 +05301849 /* no reserved-marker in ecclayout for this ecc-scheme */
1850 ecclayout->oobfree->offset =
1851 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
Pekon Guptaa919e512013-10-24 18:20:21 +05301852 break;
1853
1854 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
Pekon Guptaa919e512013-10-24 18:20:21 +05301855 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
1856 nand_chip->ecc.mode = NAND_ECC_HW;
1857 nand_chip->ecc.size = 512;
1858 nand_chip->ecc.bytes = 7;
1859 nand_chip->ecc.strength = 4;
Pekon Gupta7c977c32014-03-03 15:38:30 +05301860 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
Pekon Gupta32d42a82013-10-24 18:20:23 +05301861 nand_chip->ecc.correct = nand_bch_correct_data;
Pekon Gupta2c9f2362014-02-26 15:53:13 +05301862 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
Pekon Guptab491da72013-10-24 18:20:22 +05301863 /* define ECC layout */
1864 ecclayout->eccbytes = nand_chip->ecc.bytes *
1865 (mtd->writesize /
1866 nand_chip->ecc.size);
Pekon Guptaeae39cb2014-02-17 13:11:23 +05301867 oob_index = BADBLOCK_MARKER_LENGTH;
1868 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1869 ecclayout->eccpos[i] = oob_index;
1870 if (((i + 1) % nand_chip->ecc.bytes) == 0)
1871 oob_index++;
1872 }
Pekon Guptaaa6092f2014-02-17 13:11:24 +05301873 /* include reserved-marker in ecclayout->oobfree calculation */
1874 ecclayout->oobfree->offset = 1 +
1875 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
Pekon Guptaa919e512013-10-24 18:20:21 +05301876 /* software bch library is used for locating errors */
Pekon Gupta32d42a82013-10-24 18:20:23 +05301877 nand_chip->ecc.priv = nand_bch_init(mtd,
1878 nand_chip->ecc.size,
1879 nand_chip->ecc.bytes,
Roger Quadros7d5929c2014-08-25 16:15:32 -07001880 &ecclayout);
Pekon Gupta32d42a82013-10-24 18:20:23 +05301881 if (!nand_chip->ecc.priv) {
Ezequiel Garcíad2f08c72014-09-20 17:53:13 +01001882 dev_err(&info->pdev->dev, "unable to use BCH library\n");
Pekon Guptaa919e512013-10-24 18:20:21 +05301883 err = -EINVAL;
Ezequiel Garcíad2f08c72014-09-20 17:53:13 +01001884 goto return_error;
Pekon Guptaa919e512013-10-24 18:20:21 +05301885 }
1886 break;
Pekon Guptaa919e512013-10-24 18:20:21 +05301887
1888 case OMAP_ECC_BCH4_CODE_HW:
Pekon Guptaa919e512013-10-24 18:20:21 +05301889 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
1890 nand_chip->ecc.mode = NAND_ECC_HW;
1891 nand_chip->ecc.size = 512;
1892 /* 14th bit is kept reserved for ROM-code compatibility */
1893 nand_chip->ecc.bytes = 7 + 1;
1894 nand_chip->ecc.strength = 4;
Pekon Gupta7c977c32014-03-03 15:38:30 +05301895 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
Pekon Guptaa919e512013-10-24 18:20:21 +05301896 nand_chip->ecc.correct = omap_elm_correct_data;
Pekon Guptaa4c7ca02014-02-26 15:53:11 +05301897 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
Pekon Guptaa919e512013-10-24 18:20:21 +05301898 nand_chip->ecc.read_page = omap_read_page_bch;
1899 nand_chip->ecc.write_page = omap_write_page_bch;
Pekon Guptab491da72013-10-24 18:20:22 +05301900 /* define ECC layout */
1901 ecclayout->eccbytes = nand_chip->ecc.bytes *
1902 (mtd->writesize /
1903 nand_chip->ecc.size);
Pekon Guptaeae39cb2014-02-17 13:11:23 +05301904 oob_index = BADBLOCK_MARKER_LENGTH;
1905 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1906 ecclayout->eccpos[i] = oob_index;
Pekon Guptaaa6092f2014-02-17 13:11:24 +05301907 /* reserved marker already included in ecclayout->eccbytes */
1908 ecclayout->oobfree->offset =
1909 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
Ezequiel García93af53b2014-09-20 17:53:12 +01001910
1911 err = elm_config(info->elm_dev, BCH4_ECC,
1912 info->mtd.writesize / nand_chip->ecc.size,
1913 nand_chip->ecc.size, nand_chip->ecc.bytes);
1914 if (err < 0)
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301915 goto return_error;
Pekon Guptaa919e512013-10-24 18:20:21 +05301916 break;
Pekon Guptaa919e512013-10-24 18:20:21 +05301917
1918 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
Pekon Guptaa919e512013-10-24 18:20:21 +05301919 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
1920 nand_chip->ecc.mode = NAND_ECC_HW;
1921 nand_chip->ecc.size = 512;
1922 nand_chip->ecc.bytes = 13;
1923 nand_chip->ecc.strength = 8;
Pekon Gupta7c977c32014-03-03 15:38:30 +05301924 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
Pekon Gupta32d42a82013-10-24 18:20:23 +05301925 nand_chip->ecc.correct = nand_bch_correct_data;
Pekon Gupta7bcd1dc2014-02-26 15:53:14 +05301926 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
Pekon Guptab491da72013-10-24 18:20:22 +05301927 /* define ECC layout */
1928 ecclayout->eccbytes = nand_chip->ecc.bytes *
1929 (mtd->writesize /
1930 nand_chip->ecc.size);
Pekon Guptaeae39cb2014-02-17 13:11:23 +05301931 oob_index = BADBLOCK_MARKER_LENGTH;
1932 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1933 ecclayout->eccpos[i] = oob_index;
1934 if (((i + 1) % nand_chip->ecc.bytes) == 0)
1935 oob_index++;
1936 }
Pekon Guptaaa6092f2014-02-17 13:11:24 +05301937 /* include reserved-marker in ecclayout->oobfree calculation */
1938 ecclayout->oobfree->offset = 1 +
1939 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
Pekon Guptaa919e512013-10-24 18:20:21 +05301940 /* software bch library is used for locating errors */
Pekon Gupta32d42a82013-10-24 18:20:23 +05301941 nand_chip->ecc.priv = nand_bch_init(mtd,
1942 nand_chip->ecc.size,
1943 nand_chip->ecc.bytes,
Roger Quadros7d5929c2014-08-25 16:15:32 -07001944 &ecclayout);
Pekon Gupta32d42a82013-10-24 18:20:23 +05301945 if (!nand_chip->ecc.priv) {
Ezequiel Garcíad2f08c72014-09-20 17:53:13 +01001946 dev_err(&info->pdev->dev, "unable to use BCH library\n");
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001947 err = -EINVAL;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301948 goto return_error;
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001949 }
Pekon Guptaa919e512013-10-24 18:20:21 +05301950 break;
Pekon Guptaa919e512013-10-24 18:20:21 +05301951
1952 case OMAP_ECC_BCH8_CODE_HW:
Pekon Guptaa919e512013-10-24 18:20:21 +05301953 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
1954 nand_chip->ecc.mode = NAND_ECC_HW;
1955 nand_chip->ecc.size = 512;
1956 /* 14th bit is kept reserved for ROM-code compatibility */
1957 nand_chip->ecc.bytes = 13 + 1;
1958 nand_chip->ecc.strength = 8;
Pekon Gupta7c977c32014-03-03 15:38:30 +05301959 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
Pekon Guptaa919e512013-10-24 18:20:21 +05301960 nand_chip->ecc.correct = omap_elm_correct_data;
Pekon Guptaa4c7ca02014-02-26 15:53:11 +05301961 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
Pekon Guptaa919e512013-10-24 18:20:21 +05301962 nand_chip->ecc.read_page = omap_read_page_bch;
1963 nand_chip->ecc.write_page = omap_write_page_bch;
Ezequiel García93af53b2014-09-20 17:53:12 +01001964
1965 err = elm_config(info->elm_dev, BCH8_ECC,
1966 info->mtd.writesize / nand_chip->ecc.size,
1967 nand_chip->ecc.size, nand_chip->ecc.bytes);
1968 if (err < 0)
Pekon Gupta70ba6d72013-10-24 18:20:25 +05301969 goto return_error;
Ezequiel García93af53b2014-09-20 17:53:12 +01001970
Pekon Guptab491da72013-10-24 18:20:22 +05301971 /* define ECC layout */
1972 ecclayout->eccbytes = nand_chip->ecc.bytes *
1973 (mtd->writesize /
1974 nand_chip->ecc.size);
Pekon Guptaeae39cb2014-02-17 13:11:23 +05301975 oob_index = BADBLOCK_MARKER_LENGTH;
1976 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1977 ecclayout->eccpos[i] = oob_index;
Pekon Guptaaa6092f2014-02-17 13:11:24 +05301978 /* reserved marker already included in ecclayout->eccbytes */
1979 ecclayout->oobfree->offset =
1980 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
Pekon Guptaa919e512013-10-24 18:20:21 +05301981 break;
Pekon Guptaa919e512013-10-24 18:20:21 +05301982
pekon gupta9748fff2014-03-24 16:50:05 +05301983 case OMAP_ECC_BCH16_CODE_HW:
pekon gupta9748fff2014-03-24 16:50:05 +05301984 pr_info("using OMAP_ECC_BCH16_CODE_HW ECC scheme\n");
1985 nand_chip->ecc.mode = NAND_ECC_HW;
1986 nand_chip->ecc.size = 512;
1987 nand_chip->ecc.bytes = 26;
1988 nand_chip->ecc.strength = 16;
1989 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1990 nand_chip->ecc.correct = omap_elm_correct_data;
1991 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1992 nand_chip->ecc.read_page = omap_read_page_bch;
1993 nand_chip->ecc.write_page = omap_write_page_bch;
Ezequiel García93af53b2014-09-20 17:53:12 +01001994
1995 err = elm_config(info->elm_dev, BCH16_ECC,
1996 info->mtd.writesize / nand_chip->ecc.size,
1997 nand_chip->ecc.size, nand_chip->ecc.bytes);
1998 if (err < 0)
pekon gupta9748fff2014-03-24 16:50:05 +05301999 goto return_error;
Ezequiel García93af53b2014-09-20 17:53:12 +01002000
pekon gupta9748fff2014-03-24 16:50:05 +05302001 /* define ECC layout */
2002 ecclayout->eccbytes = nand_chip->ecc.bytes *
2003 (mtd->writesize /
2004 nand_chip->ecc.size);
2005 oob_index = BADBLOCK_MARKER_LENGTH;
2006 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
2007 ecclayout->eccpos[i] = oob_index;
2008 /* reserved marker already included in ecclayout->eccbytes */
2009 ecclayout->oobfree->offset =
2010 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
2011 break;
Pekon Guptaa919e512013-10-24 18:20:21 +05302012 default:
Ezequiel Garcíad2f08c72014-09-20 17:53:13 +01002013 dev_err(&info->pdev->dev, "invalid or unsupported ECC scheme\n");
Pekon Guptaa919e512013-10-24 18:20:21 +05302014 err = -EINVAL;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05302015 goto return_error;
Sukumar Ghoraif3d73f32011-01-28 15:42:08 +05302016 }
Vimal Singh67ce04b2009-05-12 13:47:03 -07002017
Roger Quadros7d5929c2014-08-25 16:15:32 -07002018 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW)
2019 goto scan_tail;
2020
Pekon Guptabb38eef2014-02-17 13:11:25 +05302021 /* all OOB bytes from oobfree->offset till end off OOB are free */
2022 ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
Pekon Guptab491da72013-10-24 18:20:22 +05302023 /* check if NAND device's OOB is enough to store ECC signatures */
2024 if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) {
Ezequiel Garcíad2f08c72014-09-20 17:53:13 +01002025 dev_err(&info->pdev->dev,
2026 "not enough OOB bytes required = %d, available=%d\n",
2027 ecclayout->eccbytes, mtd->oobsize);
Pekon Guptab491da72013-10-24 18:20:22 +05302028 err = -EINVAL;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05302029 goto return_error;
Sukumar Ghoraif040d332011-01-28 15:42:09 +05302030 }
Roger Quadros7d5929c2014-08-25 16:15:32 -07002031 nand_chip->ecc.layout = ecclayout;
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05302032
Roger Quadros7d5929c2014-08-25 16:15:32 -07002033scan_tail:
Jan Weitzela80f1c12011-04-19 16:15:34 +02002034 /* second phase scan */
Pekon Gupta633deb52013-10-24 18:20:19 +05302035 if (nand_scan_tail(mtd)) {
Jan Weitzela80f1c12011-04-19 16:15:34 +02002036 err = -ENXIO;
Pekon Gupta70ba6d72013-10-24 18:20:25 +05302037 goto return_error;
Jan Weitzela80f1c12011-04-19 16:15:34 +02002038 }
2039
Daniel Mackccf04c52012-12-14 11:36:41 +01002040 ppdata.of_node = pdata->of_node;
Pekon Gupta633deb52013-10-24 18:20:19 +05302041 mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts,
Artem Bityutskiy42d7fbe2012-03-09 19:24:26 +02002042 pdata->nr_parts);
Vimal Singh67ce04b2009-05-12 13:47:03 -07002043
Pekon Gupta633deb52013-10-24 18:20:19 +05302044 platform_set_drvdata(pdev, mtd);
Vimal Singh67ce04b2009-05-12 13:47:03 -07002045
2046 return 0;
2047
Pekon Gupta70ba6d72013-10-24 18:20:25 +05302048return_error:
Russell King763e7352012-04-25 00:16:00 +01002049 if (info->dma)
2050 dma_release_channel(info->dma);
Pekon Gupta32d42a82013-10-24 18:20:23 +05302051 if (nand_chip->ecc.priv) {
2052 nand_bch_free(nand_chip->ecc.priv);
2053 nand_chip->ecc.priv = NULL;
2054 }
Vimal Singh67ce04b2009-05-12 13:47:03 -07002055 return err;
2056}
2057
2058static int omap_nand_remove(struct platform_device *pdev)
2059{
2060 struct mtd_info *mtd = platform_get_drvdata(pdev);
Pekon Gupta633deb52013-10-24 18:20:19 +05302061 struct nand_chip *nand_chip = mtd->priv;
Vimal Singhf35b6ed2010-01-05 16:01:08 +05302062 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
2063 mtd);
Pekon Gupta32d42a82013-10-24 18:20:23 +05302064 if (nand_chip->ecc.priv) {
2065 nand_bch_free(nand_chip->ecc.priv);
2066 nand_chip->ecc.priv = NULL;
2067 }
Russell King763e7352012-04-25 00:16:00 +01002068 if (info->dma)
2069 dma_release_channel(info->dma);
Pekon Gupta633deb52013-10-24 18:20:19 +05302070 nand_release(mtd);
Vimal Singh67ce04b2009-05-12 13:47:03 -07002071 return 0;
2072}
2073
2074static struct platform_driver omap_nand_driver = {
2075 .probe = omap_nand_probe,
2076 .remove = omap_nand_remove,
2077 .driver = {
2078 .name = DRIVER_NAME,
Vimal Singh67ce04b2009-05-12 13:47:03 -07002079 },
2080};
2081
Axel Linf99640d2011-11-27 20:45:03 +08002082module_platform_driver(omap_nand_driver);
Vimal Singh67ce04b2009-05-12 13:47:03 -07002083
Axel Linc804c732011-03-07 11:04:24 +08002084MODULE_ALIAS("platform:" DRIVER_NAME);
Vimal Singh67ce04b2009-05-12 13:47:03 -07002085MODULE_LICENSE("GPL");
2086MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");