blob: 06177bf5b1d65e8f8fe6b96703361b8afe5d6d70 [file] [log] [blame]
Mark.Zhana240a462006-05-06 17:04:20 +08001/*
2 * irq.c: GT64120 Interrupt Controller
3 *
4 * Copyright (C) 2006, Wind River System Inc.
5 * Author: Rongkai.Zhan, <rongkai.zhan@windriver.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/kernel_stat.h>
15#include <linux/module.h>
16#include <linux/signal.h>
17#include <linux/sched.h>
18#include <linux/types.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/timex.h>
22#include <linux/slab.h>
23#include <linux/random.h>
24#include <linux/bitops.h>
25#include <asm/bootinfo.h>
26#include <asm/io.h>
27#include <asm/bitops.h>
28#include <asm/mipsregs.h>
29#include <asm/system.h>
30#include <asm/irq_cpu.h>
31#include <asm/gt64120.h>
32
Ralf Baechle937a8012006-10-07 19:44:33 +010033asmlinkage void plat_irq_dispatch(void)
Mark.Zhan92478572006-06-20 18:15:02 +080034{
Thiemo Seufer119537c2007-03-19 00:13:37 +000035 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
Mark.Zhan92478572006-06-20 18:15:02 +080036
37 if (pending & STATUSF_IP7)
Ralf Baechle937a8012006-10-07 19:44:33 +010038 do_IRQ(WRPPMC_MIPS_TIMER_IRQ); /* CPU Compare/Count internal timer */
Mark.Zhan92478572006-06-20 18:15:02 +080039 else if (pending & STATUSF_IP6)
Ralf Baechle937a8012006-10-07 19:44:33 +010040 do_IRQ(WRPPMC_UART16550_IRQ); /* UART 16550 port */
Mark.Zhan92478572006-06-20 18:15:02 +080041 else if (pending & STATUSF_IP3)
Ralf Baechle937a8012006-10-07 19:44:33 +010042 do_IRQ(WRPPMC_PCI_INTA_IRQ); /* PCI INT_A */
Mark.Zhan92478572006-06-20 18:15:02 +080043 else
Ralf Baechle937a8012006-10-07 19:44:33 +010044 spurious_interrupt();
Mark.Zhan92478572006-06-20 18:15:02 +080045}
Mark.Zhana240a462006-05-06 17:04:20 +080046
47/**
48 * Initialize GT64120 Interrupt Controller
49 */
50void gt64120_init_pic(void)
51{
52 /* clear CPU Interrupt Cause Registers */
53 GT_WRITE(GT_INTRCAUSE_OFS, (0x1F << 21));
54 GT_WRITE(GT_HINTRCAUSE_OFS, 0x00);
55
56 /* Disable all interrupts from GT64120 bridge chip */
57 GT_WRITE(GT_INTRMASK_OFS, 0x00);
58 GT_WRITE(GT_HINTRMASK_OFS, 0x00);
59 GT_WRITE(GT_PCI0_ICMASK_OFS, 0x00);
60 GT_WRITE(GT_PCI0_HICMASK_OFS, 0x00);
61}
62
63void __init arch_init_irq(void)
64{
Mark.Zhana240a462006-05-06 17:04:20 +080065 /* IRQ 0 - 7 are for MIPS common irq_cpu controller */
Atsushi Nemoto97dcb822007-01-08 02:14:29 +090066 mips_cpu_irq_init();
Mark.Zhana240a462006-05-06 17:04:20 +080067
68 gt64120_init_pic();
69}