blob: 65c54160028b2833c3a9576f57e7081506cd0260 [file] [log] [blame]
Rafał Miłeckie55d3e62012-05-06 17:29:44 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Christian König
25 * Rafał Miłecki
26 */
27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "radeon_asic.h"
31#include "evergreend.h"
32#include "atom.h"
33
34/*
35 * update the N and CTS parameters for a given pixel clock rate
36 */
37static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
38{
39 struct drm_device *dev = encoder->dev;
40 struct radeon_device *rdev = dev->dev_private;
41 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +020042 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
44 uint32_t offset = dig->afmt->offset;
Rafał Miłeckie55d3e62012-05-06 17:29:44 +020045
46 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
47 WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
48
49 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
50 WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
51
52 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
53 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
54}
55
56/*
57 * calculate the crc for a given info frame
58 */
59static void evergreen_hdmi_infoframe_checksum(uint8_t packetType,
60 uint8_t versionNumber,
61 uint8_t length,
62 uint8_t *frame)
63{
64 int i;
65 frame[0] = packetType + versionNumber + length;
66 for (i = 1; i <= length; i++)
67 frame[0] += frame[i];
68 frame[0] = 0x100 - frame[0];
69}
70
71/*
72 * build a HDMI Video Info Frame
73 */
74static void evergreen_hdmi_videoinfoframe(
75 struct drm_encoder *encoder,
76 uint8_t color_format,
77 int active_information_present,
78 uint8_t active_format_aspect_ratio,
79 uint8_t scan_information,
80 uint8_t colorimetry,
81 uint8_t ex_colorimetry,
82 uint8_t quantization,
83 int ITC,
84 uint8_t picture_aspect_ratio,
85 uint8_t video_format_identification,
86 uint8_t pixel_repetition,
87 uint8_t non_uniform_picture_scaling,
88 uint8_t bar_info_data_valid,
89 uint16_t top_bar,
90 uint16_t bottom_bar,
91 uint16_t left_bar,
92 uint16_t right_bar
93)
94{
95 struct drm_device *dev = encoder->dev;
96 struct radeon_device *rdev = dev->dev_private;
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +020097 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
98 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
99 uint32_t offset = dig->afmt->offset;
Rafał Miłeckie55d3e62012-05-06 17:29:44 +0200100
101 uint8_t frame[14];
102
103 frame[0x0] = 0;
104 frame[0x1] =
105 (scan_information & 0x3) |
106 ((bar_info_data_valid & 0x3) << 2) |
107 ((active_information_present & 0x1) << 4) |
108 ((color_format & 0x3) << 5);
109 frame[0x2] =
110 (active_format_aspect_ratio & 0xF) |
111 ((picture_aspect_ratio & 0x3) << 4) |
112 ((colorimetry & 0x3) << 6);
113 frame[0x3] =
114 (non_uniform_picture_scaling & 0x3) |
115 ((quantization & 0x3) << 2) |
116 ((ex_colorimetry & 0x7) << 4) |
117 ((ITC & 0x1) << 7);
118 frame[0x4] = (video_format_identification & 0x7F);
119 frame[0x5] = (pixel_repetition & 0xF);
120 frame[0x6] = (top_bar & 0xFF);
121 frame[0x7] = (top_bar >> 8);
122 frame[0x8] = (bottom_bar & 0xFF);
123 frame[0x9] = (bottom_bar >> 8);
124 frame[0xA] = (left_bar & 0xFF);
125 frame[0xB] = (left_bar >> 8);
126 frame[0xC] = (right_bar & 0xFF);
127 frame[0xD] = (right_bar >> 8);
128
129 evergreen_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
130 /* Our header values (type, version, length) should be alright, Intel
131 * is using the same. Checksum function also seems to be OK, it works
132 * fine for audio infoframe. However calculated value is always lower
133 * by 2 in comparison to fglrx. It breaks displaying anything in case
134 * of TVs that strictly check the checksum. Hack it manually here to
135 * workaround this issue. */
136 frame[0x0] += 2;
137
138 WREG32(AFMT_AVI_INFO0 + offset,
139 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
140 WREG32(AFMT_AVI_INFO1 + offset,
141 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
142 WREG32(AFMT_AVI_INFO2 + offset,
143 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
144 WREG32(AFMT_AVI_INFO3 + offset,
145 frame[0xC] | (frame[0xD] << 8));
146}
147
148/*
149 * update the info frames with the data from the current display mode
150 */
151void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
152{
153 struct drm_device *dev = encoder->dev;
154 struct radeon_device *rdev = dev->dev_private;
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200155 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
156 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
157 uint32_t offset;
Rafał Miłeckie55d3e62012-05-06 17:29:44 +0200158
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200159 /* Silent, r600_hdmi_enable will raise WARN for us */
160 if (!dig->afmt->enabled)
Rafał Miłeckie55d3e62012-05-06 17:29:44 +0200161 return;
Rafał Miłeckicfcbd6d2012-05-14 16:52:30 +0200162 offset = dig->afmt->offset;
Rafał Miłeckie55d3e62012-05-06 17:29:44 +0200163
164 r600_audio_set_clock(encoder, mode->clock);
165
Rafał Miłecki1c3439f2012-05-06 17:29:45 +0200166 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
167 HDMI_NULL_SEND); /* send null packets when required */
168
Rafał Miłeckie55d3e62012-05-06 17:29:44 +0200169 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
Rafał Miłeckie55d3e62012-05-06 17:29:44 +0200170
Rafał Miłecki1c3439f2012-05-06 17:29:45 +0200171 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
172 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
173 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
Rafał Miłeckie55d3e62012-05-06 17:29:44 +0200174
Rafał Miłecki1c3439f2012-05-06 17:29:45 +0200175 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
176 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
177 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
Rafał Miłeckie55d3e62012-05-06 17:29:44 +0200178
Rafał Miłecki1c3439f2012-05-06 17:29:45 +0200179 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
180 HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
181 HDMI_ACR_SOURCE); /* select SW CTS value */
Rafał Miłeckie55d3e62012-05-06 17:29:44 +0200182
Rafał Miłecki1c3439f2012-05-06 17:29:45 +0200183 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
184 HDMI_NULL_SEND | /* send null packets when required */
185 HDMI_GC_SEND | /* send general control packets */
186 HDMI_GC_CONT); /* send general control packets every frame */
Rafał Miłeckie55d3e62012-05-06 17:29:44 +0200187
Rafał Miłecki1c3439f2012-05-06 17:29:45 +0200188 WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
189 HDMI_AVI_INFO_SEND | /* enable AVI info frames */
190 HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */
191 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
192 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
193
194 WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
195 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
196
197 WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
198 HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */
199 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
200
201 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
Rafał Miłeckie55d3e62012-05-06 17:29:44 +0200202
203 evergreen_hdmi_videoinfoframe(encoder, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
204 0, 0, 0, 0, 0, 0);
205
Rafał Miłecki1c3439f2012-05-06 17:29:45 +0200206 evergreen_hdmi_update_ACR(encoder, mode->clock);
207
Rafał Miłeckie55d3e62012-05-06 17:29:44 +0200208 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
209 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
210 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
211 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
212 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
Rafał Miłeckie55d3e62012-05-06 17:29:44 +0200213}