blob: 0966f2637ad2dc849f12d7224dbf7d6af1c75c13 [file] [log] [blame]
Tomoya MORINAGA49a36792011-01-12 17:00:22 -08001/*
2 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
Paul Gortmakerbb207ef2011-07-03 13:38:09 -040017#include <linux/module.h>
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080018#include <linux/kernel.h>
Andrew Morton545554e2011-05-24 17:13:43 -070019#include <linux/slab.h>
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080020#include <linux/pci.h>
21#include <linux/gpio.h>
Tomoya MORINAGA54be5662011-08-05 13:04:21 +090022#include <linux/interrupt.h>
23#include <linux/irq.h>
24
25#define IOH_EDGE_FALLING 0
26#define IOH_EDGE_RISING BIT(0)
27#define IOH_LEVEL_L BIT(1)
28#define IOH_LEVEL_H (BIT(0) | BIT(1))
29#define IOH_EDGE_BOTH BIT(2)
30#define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
31
32#define IOH_IRQ_BASE 0
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080033
34#define PCI_VENDOR_ID_ROHM 0x10DB
35
36struct ioh_reg_comn {
37 u32 ien;
38 u32 istatus;
39 u32 idisp;
40 u32 iclr;
41 u32 imask;
42 u32 imaskclr;
43 u32 po;
44 u32 pi;
45 u32 pm;
46 u32 im_0;
47 u32 im_1;
48 u32 reserved;
49};
50
51struct ioh_regs {
52 struct ioh_reg_comn regs[8];
53 u32 reserve1[16];
54 u32 ioh_sel_reg[4];
55 u32 reserve2[11];
56 u32 srst;
57};
58
59/**
60 * struct ioh_gpio_reg_data - The register store data.
Tomoya MORINAGA54be5662011-08-05 13:04:21 +090061 * @ien_reg To store contents of interrupt enable register.
62 * @imask_reg: To store contents of interrupt mask regist
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080063 * @po_reg: To store contents of PO register.
64 * @pm_reg: To store contents of PM register.
Tomoya MORINAGA54be5662011-08-05 13:04:21 +090065 * @im0_reg: To store contents of interrupt mode regist0
66 * @im1_reg: To store contents of interrupt mode regist1
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +090067 * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080068 */
69struct ioh_gpio_reg_data {
Tomoya MORINAGA54be5662011-08-05 13:04:21 +090070 u32 ien_reg;
71 u32 imask_reg;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080072 u32 po_reg;
73 u32 pm_reg;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +090074 u32 im0_reg;
75 u32 im1_reg;
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +090076 u32 use_sel_reg;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080077};
78
79/**
80 * struct ioh_gpio - GPIO private data structure.
81 * @base: PCI base address of Memory mapped I/O register.
82 * @reg: Memory mapped IOH GPIO register list.
83 * @dev: Pointer to device structure.
84 * @gpio: Data for GPIO infrastructure.
85 * @ioh_gpio_reg: Memory mapped Register data is saved here
86 * when suspend.
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +090087 * @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080088 * @ch: Indicate GPIO channel
Tomoya MORINAGA54be5662011-08-05 13:04:21 +090089 * @irq_base: Save base of IRQ number for interrupt
Axel Lin02a67942012-07-29 10:54:42 +080090 * @spinlock: Used for register access protection
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080091 */
92struct ioh_gpio {
93 void __iomem *base;
94 struct ioh_regs __iomem *reg;
95 struct device *dev;
96 struct gpio_chip gpio;
97 struct ioh_gpio_reg_data ioh_gpio_reg;
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +090098 u32 gpio_use_sel;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -080099 int ch;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900100 int irq_base;
101 spinlock_t spinlock;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800102};
103
104static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
105
106static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
107{
108 u32 reg_val;
109 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
Axel Lin02a67942012-07-29 10:54:42 +0800110 unsigned long flags;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800111
Axel Lin02a67942012-07-29 10:54:42 +0800112 spin_lock_irqsave(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800113 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
114 if (val)
115 reg_val |= (1 << nr);
116 else
117 reg_val &= ~(1 << nr);
118
119 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
Axel Lin02a67942012-07-29 10:54:42 +0800120 spin_unlock_irqrestore(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800121}
122
123static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
124{
125 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
126
127 return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
128}
129
130static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
131 int val)
132{
133 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
134 u32 pm;
135 u32 reg_val;
Axel Lin02a67942012-07-29 10:54:42 +0800136 unsigned long flags;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800137
Axel Lin02a67942012-07-29 10:54:42 +0800138 spin_lock_irqsave(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800139 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
140 ((1 << num_ports[chip->ch]) - 1);
141 pm |= (1 << nr);
142 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
143
144 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
145 if (val)
146 reg_val |= (1 << nr);
147 else
148 reg_val &= ~(1 << nr);
Peter Tyserba438612011-03-24 18:17:14 -0500149 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800150
Axel Lin02a67942012-07-29 10:54:42 +0800151 spin_unlock_irqrestore(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800152
153 return 0;
154}
155
156static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
157{
158 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
159 u32 pm;
Axel Lin02a67942012-07-29 10:54:42 +0800160 unsigned long flags;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800161
Axel Lin02a67942012-07-29 10:54:42 +0800162 spin_lock_irqsave(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800163 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
164 ((1 << num_ports[chip->ch]) - 1);
165 pm &= ~(1 << nr);
166 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
Axel Lin02a67942012-07-29 10:54:42 +0800167 spin_unlock_irqrestore(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800168
169 return 0;
170}
171
Andrew Morton545554e2011-05-24 17:13:43 -0700172#ifdef CONFIG_PM
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800173/*
174 * Save register configuration and disable interrupts.
175 */
176static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
177{
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +0900178 int i;
179
180 for (i = 0; i < 8; i ++, chip++) {
181 chip->ioh_gpio_reg.po_reg =
182 ioread32(&chip->reg->regs[chip->ch].po);
183 chip->ioh_gpio_reg.pm_reg =
184 ioread32(&chip->reg->regs[chip->ch].pm);
185 chip->ioh_gpio_reg.ien_reg =
186 ioread32(&chip->reg->regs[chip->ch].ien);
187 chip->ioh_gpio_reg.imask_reg =
188 ioread32(&chip->reg->regs[chip->ch].imask);
189 chip->ioh_gpio_reg.im0_reg =
190 ioread32(&chip->reg->regs[chip->ch].im_0);
191 chip->ioh_gpio_reg.im1_reg =
192 ioread32(&chip->reg->regs[chip->ch].im_1);
193 if (i < 4)
194 chip->ioh_gpio_reg.use_sel_reg =
195 ioread32(&chip->reg->ioh_sel_reg[i]);
196 }
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800197}
198
199/*
200 * This function restores the register configuration of the GPIO device.
201 */
202static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
203{
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +0900204 int i;
205
206 for (i = 0; i < 8; i ++, chip++) {
207 iowrite32(chip->ioh_gpio_reg.po_reg,
208 &chip->reg->regs[chip->ch].po);
209 iowrite32(chip->ioh_gpio_reg.pm_reg,
210 &chip->reg->regs[chip->ch].pm);
211 iowrite32(chip->ioh_gpio_reg.ien_reg,
212 &chip->reg->regs[chip->ch].ien);
213 iowrite32(chip->ioh_gpio_reg.imask_reg,
214 &chip->reg->regs[chip->ch].imask);
215 iowrite32(chip->ioh_gpio_reg.im0_reg,
216 &chip->reg->regs[chip->ch].im_0);
217 iowrite32(chip->ioh_gpio_reg.im1_reg,
218 &chip->reg->regs[chip->ch].im_1);
219 if (i < 4)
220 iowrite32(chip->ioh_gpio_reg.use_sel_reg,
221 &chip->reg->ioh_sel_reg[i]);
222 }
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800223}
Andrew Morton545554e2011-05-24 17:13:43 -0700224#endif
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800225
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900226static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
227{
228 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
229 return chip->irq_base + offset;
230}
231
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800232static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
233{
234 struct gpio_chip *gpio = &chip->gpio;
235
236 gpio->label = dev_name(chip->dev);
237 gpio->owner = THIS_MODULE;
238 gpio->direction_input = ioh_gpio_direction_input;
239 gpio->get = ioh_gpio_get;
240 gpio->direction_output = ioh_gpio_direction_output;
241 gpio->set = ioh_gpio_set;
242 gpio->dbg_show = NULL;
243 gpio->base = -1;
244 gpio->ngpio = num_port;
245 gpio->can_sleep = 0;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900246 gpio->to_irq = ioh_gpio_to_irq;
247}
248
249static int ioh_irq_type(struct irq_data *d, unsigned int type)
250{
251 u32 im;
Márton Némethdd9328a2012-01-15 10:57:34 +0100252 void __iomem *im_reg;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900253 u32 ien;
254 u32 im_pos;
255 int ch;
256 unsigned long flags;
257 u32 val;
258 int irq = d->irq;
259 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
260 struct ioh_gpio *chip = gc->private;
261
262 ch = irq - chip->irq_base;
263 if (irq <= chip->irq_base + 7) {
264 im_reg = &chip->reg->regs[chip->ch].im_0;
265 im_pos = ch;
266 } else {
267 im_reg = &chip->reg->regs[chip->ch].im_1;
268 im_pos = ch - 8;
269 }
270 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
271 __func__, irq, type, ch, im_pos, type);
272
273 spin_lock_irqsave(&chip->spinlock, flags);
274
275 switch (type) {
276 case IRQ_TYPE_EDGE_RISING:
277 val = IOH_EDGE_RISING;
278 break;
279 case IRQ_TYPE_EDGE_FALLING:
280 val = IOH_EDGE_FALLING;
281 break;
282 case IRQ_TYPE_EDGE_BOTH:
283 val = IOH_EDGE_BOTH;
284 break;
285 case IRQ_TYPE_LEVEL_HIGH:
286 val = IOH_LEVEL_H;
287 break;
288 case IRQ_TYPE_LEVEL_LOW:
289 val = IOH_LEVEL_L;
290 break;
291 case IRQ_TYPE_PROBE:
292 goto end;
293 default:
294 dev_warn(chip->dev, "%s: unknown type(%dd)",
295 __func__, type);
296 goto end;
297 }
298
299 /* Set interrupt mode */
300 im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
301 iowrite32(im | (val << (im_pos * 4)), im_reg);
302
303 /* iclr */
304 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
305
306 /* IMASKCLR */
307 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
308
309 /* Enable interrupt */
310 ien = ioread32(&chip->reg->regs[chip->ch].ien);
311 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
312end:
313 spin_unlock_irqrestore(&chip->spinlock, flags);
314
315 return 0;
316}
317
318static void ioh_irq_unmask(struct irq_data *d)
319{
320 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
321 struct ioh_gpio *chip = gc->private;
322
323 iowrite32(1 << (d->irq - chip->irq_base),
324 &chip->reg->regs[chip->ch].imaskclr);
325}
326
327static void ioh_irq_mask(struct irq_data *d)
328{
329 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
330 struct ioh_gpio *chip = gc->private;
331
332 iowrite32(1 << (d->irq - chip->irq_base),
333 &chip->reg->regs[chip->ch].imask);
334}
335
Feng Tang4d052212011-12-13 23:53:50 +0800336static void ioh_irq_disable(struct irq_data *d)
337{
338 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
339 struct ioh_gpio *chip = gc->private;
340 unsigned long flags;
341 u32 ien;
342
343 spin_lock_irqsave(&chip->spinlock, flags);
344 ien = ioread32(&chip->reg->regs[chip->ch].ien);
345 ien &= ~(1 << (d->irq - chip->irq_base));
346 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
347 spin_unlock_irqrestore(&chip->spinlock, flags);
348}
349
350static void ioh_irq_enable(struct irq_data *d)
351{
352 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
353 struct ioh_gpio *chip = gc->private;
354 unsigned long flags;
355 u32 ien;
356
357 spin_lock_irqsave(&chip->spinlock, flags);
358 ien = ioread32(&chip->reg->regs[chip->ch].ien);
359 ien |= 1 << (d->irq - chip->irq_base);
360 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
361 spin_unlock_irqrestore(&chip->spinlock, flags);
362}
363
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900364static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
365{
366 struct ioh_gpio *chip = dev_id;
367 u32 reg_val;
368 int i, j;
369 int ret = IRQ_NONE;
370
Feng Tangf9ea14e2011-12-13 23:53:49 +0800371 for (i = 0; i < 8; i++, chip++) {
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900372 reg_val = ioread32(&chip->reg->regs[i].istatus);
373 for (j = 0; j < num_ports[i]; j++) {
374 if (reg_val & BIT(j)) {
375 dev_dbg(chip->dev,
376 "%s:[%d]:irq=%d status=0x%x\n",
377 __func__, j, irq, reg_val);
378 iowrite32(BIT(j),
379 &chip->reg->regs[chip->ch].iclr);
380 generic_handle_irq(chip->irq_base + j);
381 ret = IRQ_HANDLED;
382 }
383 }
384 }
385 return ret;
386}
387
Bill Pemberton38363092012-11-19 13:22:34 -0500388static void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900389 unsigned int irq_start, unsigned int num)
390{
391 struct irq_chip_generic *gc;
392 struct irq_chip_type *ct;
393
394 gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base,
395 handle_simple_irq);
396 gc->private = chip;
397 ct = gc->chip_types;
398
399 ct->chip.irq_mask = ioh_irq_mask;
400 ct->chip.irq_unmask = ioh_irq_unmask;
401 ct->chip.irq_set_type = ioh_irq_type;
Feng Tang4d052212011-12-13 23:53:50 +0800402 ct->chip.irq_disable = ioh_irq_disable;
403 ct->chip.irq_enable = ioh_irq_enable;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900404
405 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
406 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800407}
408
Bill Pemberton38363092012-11-19 13:22:34 -0500409static int ioh_gpio_probe(struct pci_dev *pdev,
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800410 const struct pci_device_id *id)
411{
412 int ret;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900413 int i, j;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800414 struct ioh_gpio *chip;
415 void __iomem *base;
Márton Némethdd9328a2012-01-15 10:57:34 +0100416 void *chip_save;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900417 int irq_base;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800418
419 ret = pci_enable_device(pdev);
420 if (ret) {
421 dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
422 goto err_pci_enable;
423 }
424
425 ret = pci_request_regions(pdev, KBUILD_MODNAME);
426 if (ret) {
427 dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
428 goto err_request_regions;
429 }
430
431 base = pci_iomap(pdev, 1, 0);
Márton Németh2bd1c852012-01-15 10:57:43 +0100432 if (!base) {
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800433 dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
434 ret = -ENOMEM;
435 goto err_iomap;
436 }
437
438 chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL);
439 if (chip_save == NULL) {
440 dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
441 ret = -ENOMEM;
442 goto err_kzalloc;
443 }
444
445 chip = chip_save;
446 for (i = 0; i < 8; i++, chip++) {
447 chip->dev = &pdev->dev;
448 chip->base = base;
449 chip->reg = chip->base;
450 chip->ch = i;
Axel Lin7e3a70f2012-02-01 10:50:05 +0800451 spin_lock_init(&chip->spinlock);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800452 ioh_gpio_setup(chip, num_ports[i]);
453 ret = gpiochip_add(&chip->gpio);
454 if (ret) {
455 dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
456 goto err_gpiochip_add;
457 }
458 }
459
460 chip = chip_save;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900461 for (j = 0; j < 8; j++, chip++) {
462 irq_base = irq_alloc_descs(-1, IOH_IRQ_BASE, num_ports[j],
Tomoya MORINAGAa7aaa4f2011-10-19 10:37:40 +0900463 NUMA_NO_NODE);
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900464 if (irq_base < 0) {
465 dev_warn(&pdev->dev,
466 "ml_ioh_gpio: Failed to get IRQ base num\n");
467 chip->irq_base = -1;
468 goto err_irq_alloc_descs;
469 }
470 chip->irq_base = irq_base;
471 ioh_gpio_alloc_generic_chip(chip, irq_base, num_ports[j]);
472 }
473
474 chip = chip_save;
475 ret = request_irq(pdev->irq, ioh_gpio_handler,
476 IRQF_SHARED, KBUILD_MODNAME, chip);
477 if (ret != 0) {
478 dev_err(&pdev->dev,
479 "%s request_irq failed\n", __func__);
480 goto err_request_irq;
481 }
482
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800483 pci_set_drvdata(pdev, chip);
484
485 return 0;
486
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900487err_request_irq:
488 chip = chip_save;
489err_irq_alloc_descs:
490 while (--j >= 0) {
491 chip--;
492 irq_free_descs(chip->irq_base, num_ports[j]);
493 }
494
495 chip = chip_save;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800496err_gpiochip_add:
Axel Lin33300572011-06-14 19:12:57 +0800497 while (--i >= 0) {
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800498 chip--;
Axel Lincfb10892013-05-19 14:00:47 +0800499 if (gpiochip_remove(&chip->gpio))
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800500 dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i);
501 }
502 kfree(chip_save);
503
504err_kzalloc:
505 pci_iounmap(pdev, base);
506
507err_iomap:
508 pci_release_regions(pdev);
509
510err_request_regions:
511 pci_disable_device(pdev);
512
513err_pci_enable:
514
515 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
516 return ret;
517}
518
Bill Pemberton206210c2012-11-19 13:25:50 -0500519static void ioh_gpio_remove(struct pci_dev *pdev)
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800520{
521 int err;
522 int i;
523 struct ioh_gpio *chip = pci_get_drvdata(pdev);
Márton Némethdd9328a2012-01-15 10:57:34 +0100524 void *chip_save;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800525
526 chip_save = chip;
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900527
528 free_irq(pdev->irq, chip);
529
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800530 for (i = 0; i < 8; i++, chip++) {
Tomoya MORINAGA54be5662011-08-05 13:04:21 +0900531 irq_free_descs(chip->irq_base, num_ports[i]);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800532 err = gpiochip_remove(&chip->gpio);
533 if (err)
534 dev_err(&pdev->dev, "Failed gpiochip_remove\n");
535 }
536
537 chip = chip_save;
538 pci_iounmap(pdev, chip->base);
539 pci_release_regions(pdev);
540 pci_disable_device(pdev);
541 kfree(chip);
542}
543
544#ifdef CONFIG_PM
545static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
546{
547 s32 ret;
548 struct ioh_gpio *chip = pci_get_drvdata(pdev);
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +0900549 unsigned long flags;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800550
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +0900551 spin_lock_irqsave(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800552 ioh_gpio_save_reg_conf(chip);
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +0900553 spin_unlock_irqrestore(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800554
555 ret = pci_save_state(pdev);
556 if (ret) {
557 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
558 return ret;
559 }
560 pci_disable_device(pdev);
561 pci_set_power_state(pdev, PCI_D0);
562 ret = pci_enable_wake(pdev, PCI_D0, 1);
563 if (ret)
564 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
565
566 return 0;
567}
568
569static int ioh_gpio_resume(struct pci_dev *pdev)
570{
571 s32 ret;
572 struct ioh_gpio *chip = pci_get_drvdata(pdev);
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +0900573 unsigned long flags;
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800574
575 ret = pci_enable_wake(pdev, PCI_D0, 0);
576
577 pci_set_power_state(pdev, PCI_D0);
578 ret = pci_enable_device(pdev);
579 if (ret) {
580 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
581 return ret;
582 }
583 pci_restore_state(pdev);
584
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +0900585 spin_lock_irqsave(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800586 iowrite32(0x01, &chip->reg->srst);
587 iowrite32(0x00, &chip->reg->srst);
588 ioh_gpio_restore_reg_conf(chip);
Tomoya MORINAGAb490fa02011-08-05 13:04:22 +0900589 spin_unlock_irqrestore(&chip->spinlock, flags);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800590
591 return 0;
592}
593#else
594#define ioh_gpio_suspend NULL
595#define ioh_gpio_resume NULL
596#endif
597
598static DEFINE_PCI_DEVICE_TABLE(ioh_gpio_pcidev_id) = {
599 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
600 { 0, }
601};
Axel Lin19234cd2011-03-11 14:58:30 -0800602MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800603
604static struct pci_driver ioh_gpio_driver = {
605 .name = "ml_ioh_gpio",
606 .id_table = ioh_gpio_pcidev_id,
607 .probe = ioh_gpio_probe,
Bill Pemberton8283c4f2012-11-19 13:20:08 -0500608 .remove = ioh_gpio_remove,
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800609 .suspend = ioh_gpio_suspend,
610 .resume = ioh_gpio_resume
611};
612
Axel Lin93baa652012-04-06 20:13:30 +0800613module_pci_driver(ioh_gpio_driver);
Tomoya MORINAGA49a36792011-01-12 17:00:22 -0800614
615MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
616MODULE_LICENSE("GPL");