blob: 6bc68bdcf433cf06a68d52d95b063f9a42795194 [file] [log] [blame]
Eric Anholt62fdfea2010-05-21 13:26:39 -07001/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
David Howells760285e2012-10-02 18:01:07 +010030#include <drm/drmP.h>
Eric Anholt62fdfea2010-05-21 13:26:39 -070031#include "i915_drv.h"
David Howells760285e2012-10-02 18:01:07 +010032#include <drm/i915_drm.h>
Eric Anholt62fdfea2010-05-21 13:26:39 -070033#include "i915_trace.h"
Xiang, Haihao881f47b2010-09-19 14:40:43 +010034#include "intel_drv.h"
Eric Anholt62fdfea2010-05-21 13:26:39 -070035
Chris Wilsonc7dca472011-01-20 17:00:10 +000036static inline int ring_space(struct intel_ring_buffer *ring)
37{
Ville Syrjälä633cf8f2012-12-03 18:43:32 +020038 int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
Chris Wilsonc7dca472011-01-20 17:00:10 +000039 if (space < 0)
40 space += ring->size;
41 return space;
42}
43
Chris Wilson09246732013-08-10 22:16:32 +010044void __intel_ring_advance(struct intel_ring_buffer *ring)
45{
46 struct drm_i915_private *dev_priv = ring->dev->dev_private;
47
48 ring->tail &= ring->size - 1;
49 if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
50 return;
51 ring->write_tail(ring, ring->tail);
52}
53
Chris Wilsonb72f3ac2011-01-04 17:34:02 +000054static int
Chris Wilson46f0f8d2012-04-18 11:12:11 +010055gen2_render_ring_flush(struct intel_ring_buffer *ring,
56 u32 invalidate_domains,
57 u32 flush_domains)
58{
59 u32 cmd;
60 int ret;
61
62 cmd = MI_FLUSH;
Daniel Vetter31b14c92012-04-19 16:45:22 +020063 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
Chris Wilson46f0f8d2012-04-18 11:12:11 +010064 cmd |= MI_NO_WRITE_FLUSH;
65
66 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
67 cmd |= MI_READ_FLUSH;
68
69 ret = intel_ring_begin(ring, 2);
70 if (ret)
71 return ret;
72
73 intel_ring_emit(ring, cmd);
74 intel_ring_emit(ring, MI_NOOP);
75 intel_ring_advance(ring);
76
77 return 0;
78}
79
80static int
81gen4_render_ring_flush(struct intel_ring_buffer *ring,
82 u32 invalidate_domains,
83 u32 flush_domains)
Eric Anholt62fdfea2010-05-21 13:26:39 -070084{
Chris Wilson78501ea2010-10-27 12:18:21 +010085 struct drm_device *dev = ring->dev;
Chris Wilson6f392d5482010-08-07 11:01:22 +010086 u32 cmd;
Chris Wilsonb72f3ac2011-01-04 17:34:02 +000087 int ret;
Chris Wilson6f392d5482010-08-07 11:01:22 +010088
Chris Wilson36d527d2011-03-19 22:26:49 +000089 /*
90 * read/write caches:
91 *
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
95 *
96 * read-only caches:
97 *
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
100 *
101 * I915_GEM_DOMAIN_COMMAND may not exist?
102 *
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
105 *
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
108 *
109 * TLBs:
110 *
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
115 */
116
117 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
Chris Wilson46f0f8d2012-04-18 11:12:11 +0100118 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
Chris Wilson36d527d2011-03-19 22:26:49 +0000119 cmd &= ~MI_NO_WRITE_FLUSH;
Chris Wilson36d527d2011-03-19 22:26:49 +0000120 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
121 cmd |= MI_EXE_FLUSH;
122
123 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
124 (IS_G4X(dev) || IS_GEN5(dev)))
125 cmd |= MI_INVALIDATE_ISP;
126
127 ret = intel_ring_begin(ring, 2);
128 if (ret)
129 return ret;
130
131 intel_ring_emit(ring, cmd);
132 intel_ring_emit(ring, MI_NOOP);
133 intel_ring_advance(ring);
Chris Wilsonb72f3ac2011-01-04 17:34:02 +0000134
135 return 0;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800136}
137
Jesse Barnes8d315282011-10-16 10:23:31 +0200138/**
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
142 *
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
146 * 0.
147 *
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
150 *
151 * And the workaround for these two requires this workaround first:
152 *
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
155 * flushes.
156 *
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
159 * volume 2 part 1:
160 *
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
168 *
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
174 */
175static int
176intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
177{
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100178 u32 scratch_addr = ring->scratch.gtt_offset + 128;
Jesse Barnes8d315282011-10-16 10:23:31 +0200179 int ret;
180
181
182 ret = intel_ring_begin(ring, 6);
183 if (ret)
184 return ret;
185
186 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
187 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
188 PIPE_CONTROL_STALL_AT_SCOREBOARD);
189 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
190 intel_ring_emit(ring, 0); /* low dword */
191 intel_ring_emit(ring, 0); /* high dword */
192 intel_ring_emit(ring, MI_NOOP);
193 intel_ring_advance(ring);
194
195 ret = intel_ring_begin(ring, 6);
196 if (ret)
197 return ret;
198
199 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
200 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
201 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
202 intel_ring_emit(ring, 0);
203 intel_ring_emit(ring, 0);
204 intel_ring_emit(ring, MI_NOOP);
205 intel_ring_advance(ring);
206
207 return 0;
208}
209
210static int
211gen6_render_ring_flush(struct intel_ring_buffer *ring,
212 u32 invalidate_domains, u32 flush_domains)
213{
214 u32 flags = 0;
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100215 u32 scratch_addr = ring->scratch.gtt_offset + 128;
Jesse Barnes8d315282011-10-16 10:23:31 +0200216 int ret;
217
Paulo Zanonib3111502012-08-17 18:35:42 -0300218 /* Force SNB workarounds for PIPE_CONTROL flushes */
219 ret = intel_emit_post_sync_nonzero_flush(ring);
220 if (ret)
221 return ret;
222
Jesse Barnes8d315282011-10-16 10:23:31 +0200223 /* Just flush everything. Experiments have shown that reducing the
224 * number of bits based on the write domains has little performance
225 * impact.
226 */
Chris Wilson7d54a902012-08-10 10:18:10 +0100227 if (flush_domains) {
228 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
229 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
230 /*
231 * Ensure that any following seqno writes only happen
232 * when the render cache is indeed flushed.
233 */
Daniel Vetter97f209b2012-06-28 09:48:42 +0200234 flags |= PIPE_CONTROL_CS_STALL;
Chris Wilson7d54a902012-08-10 10:18:10 +0100235 }
236 if (invalidate_domains) {
237 flags |= PIPE_CONTROL_TLB_INVALIDATE;
238 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
239 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
240 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
243 /*
244 * TLB invalidate requires a post-sync write.
245 */
Jesse Barnes3ac78312012-10-25 12:15:47 -0700246 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
Chris Wilson7d54a902012-08-10 10:18:10 +0100247 }
Jesse Barnes8d315282011-10-16 10:23:31 +0200248
Chris Wilson6c6cf5a2012-07-20 18:02:28 +0100249 ret = intel_ring_begin(ring, 4);
Jesse Barnes8d315282011-10-16 10:23:31 +0200250 if (ret)
251 return ret;
252
Chris Wilson6c6cf5a2012-07-20 18:02:28 +0100253 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
Jesse Barnes8d315282011-10-16 10:23:31 +0200254 intel_ring_emit(ring, flags);
255 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
Chris Wilson6c6cf5a2012-07-20 18:02:28 +0100256 intel_ring_emit(ring, 0);
Jesse Barnes8d315282011-10-16 10:23:31 +0200257 intel_ring_advance(ring);
258
259 return 0;
260}
261
Chris Wilson6c6cf5a2012-07-20 18:02:28 +0100262static int
Paulo Zanonif3987632012-08-17 18:35:43 -0300263gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
264{
265 int ret;
266
267 ret = intel_ring_begin(ring, 4);
268 if (ret)
269 return ret;
270
271 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
272 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
273 PIPE_CONTROL_STALL_AT_SCOREBOARD);
274 intel_ring_emit(ring, 0);
275 intel_ring_emit(ring, 0);
276 intel_ring_advance(ring);
277
278 return 0;
279}
280
Rodrigo Vivifd3da6c2013-06-06 16:58:16 -0300281static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
282{
283 int ret;
284
285 if (!ring->fbc_dirty)
286 return 0;
287
Ville Syrjälä37c1d942013-11-06 23:02:20 +0200288 ret = intel_ring_begin(ring, 6);
Rodrigo Vivifd3da6c2013-06-06 16:58:16 -0300289 if (ret)
290 return ret;
Rodrigo Vivifd3da6c2013-06-06 16:58:16 -0300291 /* WaFbcNukeOn3DBlt:ivb/hsw */
292 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
293 intel_ring_emit(ring, MSG_FBC_REND_STATE);
294 intel_ring_emit(ring, value);
Ville Syrjälä37c1d942013-11-06 23:02:20 +0200295 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
296 intel_ring_emit(ring, MSG_FBC_REND_STATE);
297 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
Rodrigo Vivifd3da6c2013-06-06 16:58:16 -0300298 intel_ring_advance(ring);
299
300 ring->fbc_dirty = false;
301 return 0;
302}
303
Paulo Zanonif3987632012-08-17 18:35:43 -0300304static int
Paulo Zanoni4772eae2012-08-17 18:35:41 -0300305gen7_render_ring_flush(struct intel_ring_buffer *ring,
306 u32 invalidate_domains, u32 flush_domains)
307{
308 u32 flags = 0;
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100309 u32 scratch_addr = ring->scratch.gtt_offset + 128;
Paulo Zanoni4772eae2012-08-17 18:35:41 -0300310 int ret;
311
Paulo Zanonif3987632012-08-17 18:35:43 -0300312 /*
313 * Ensure that any following seqno writes only happen when the render
314 * cache is indeed flushed.
315 *
316 * Workaround: 4th PIPE_CONTROL command (except the ones with only
317 * read-cache invalidate bits set) must have the CS_STALL bit set. We
318 * don't try to be clever and just set it unconditionally.
319 */
320 flags |= PIPE_CONTROL_CS_STALL;
321
Paulo Zanoni4772eae2012-08-17 18:35:41 -0300322 /* Just flush everything. Experiments have shown that reducing the
323 * number of bits based on the write domains has little performance
324 * impact.
325 */
326 if (flush_domains) {
327 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
328 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
Paulo Zanoni4772eae2012-08-17 18:35:41 -0300329 }
330 if (invalidate_domains) {
331 flags |= PIPE_CONTROL_TLB_INVALIDATE;
332 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
333 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
334 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
335 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
336 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
337 /*
338 * TLB invalidate requires a post-sync write.
339 */
340 flags |= PIPE_CONTROL_QW_WRITE;
Ville Syrjäläb9e1faa2013-02-14 21:53:51 +0200341 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
Paulo Zanonif3987632012-08-17 18:35:43 -0300342
343 /* Workaround: we must issue a pipe_control with CS-stall bit
344 * set before a pipe_control command that has the state cache
345 * invalidate bit set. */
346 gen7_render_ring_cs_stall_wa(ring);
Paulo Zanoni4772eae2012-08-17 18:35:41 -0300347 }
348
349 ret = intel_ring_begin(ring, 4);
350 if (ret)
351 return ret;
352
353 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
354 intel_ring_emit(ring, flags);
Ville Syrjäläb9e1faa2013-02-14 21:53:51 +0200355 intel_ring_emit(ring, scratch_addr);
Paulo Zanoni4772eae2012-08-17 18:35:41 -0300356 intel_ring_emit(ring, 0);
357 intel_ring_advance(ring);
358
Ville Syrjälä9688eca2013-11-06 23:02:19 +0200359 if (!invalidate_domains && flush_domains)
Rodrigo Vivifd3da6c2013-06-06 16:58:16 -0300360 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
361
Paulo Zanoni4772eae2012-08-17 18:35:41 -0300362 return 0;
363}
364
Ben Widawskya5f3d682013-11-02 21:07:27 -0700365static int
366gen8_render_ring_flush(struct intel_ring_buffer *ring,
367 u32 invalidate_domains, u32 flush_domains)
368{
369 u32 flags = 0;
370 u32 scratch_addr = ring->scratch.gtt_offset + 128;
371 int ret;
372
373 flags |= PIPE_CONTROL_CS_STALL;
374
375 if (flush_domains) {
376 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
377 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
378 }
379 if (invalidate_domains) {
380 flags |= PIPE_CONTROL_TLB_INVALIDATE;
381 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
382 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
383 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
384 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
385 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
386 flags |= PIPE_CONTROL_QW_WRITE;
387 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
388 }
389
390 ret = intel_ring_begin(ring, 6);
391 if (ret)
392 return ret;
393
394 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
395 intel_ring_emit(ring, flags);
396 intel_ring_emit(ring, scratch_addr);
397 intel_ring_emit(ring, 0);
398 intel_ring_emit(ring, 0);
399 intel_ring_emit(ring, 0);
400 intel_ring_advance(ring);
401
402 return 0;
403
404}
405
Chris Wilson78501ea2010-10-27 12:18:21 +0100406static void ring_write_tail(struct intel_ring_buffer *ring,
Chris Wilson297b0c52010-10-22 17:02:41 +0100407 u32 value)
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800408{
Jani Nikula4640c4f2014-03-31 14:27:19 +0300409 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Chris Wilson297b0c52010-10-22 17:02:41 +0100410 I915_WRITE_TAIL(ring, value);
Xiang, Haihaod46eefa2010-09-16 10:43:12 +0800411}
412
Chris Wilson50877442014-03-21 12:41:53 +0000413u64 intel_ring_get_active_head(struct intel_ring_buffer *ring)
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800414{
Jani Nikula4640c4f2014-03-31 14:27:19 +0300415 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Chris Wilson50877442014-03-21 12:41:53 +0000416 u64 acthd;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800417
Chris Wilson50877442014-03-21 12:41:53 +0000418 if (INTEL_INFO(ring->dev)->gen >= 8)
419 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
420 RING_ACTHD_UDW(ring->mmio_base));
421 else if (INTEL_INFO(ring->dev)->gen >= 4)
422 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
423 else
424 acthd = I915_READ(ACTHD);
425
426 return acthd;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800427}
428
Daniel Vetter035dc1e2013-07-03 12:56:54 +0200429static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
430{
431 struct drm_i915_private *dev_priv = ring->dev->dev_private;
432 u32 addr;
433
434 addr = dev_priv->status_page_dmah->busaddr;
435 if (INTEL_INFO(ring->dev)->gen >= 4)
436 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
437 I915_WRITE(HWS_PGA, addr);
438}
439
Chris Wilson78501ea2010-10-27 12:18:21 +0100440static int init_ring_common(struct intel_ring_buffer *ring)
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800441{
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200442 struct drm_device *dev = ring->dev;
Jani Nikula4640c4f2014-03-31 14:27:19 +0300443 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson05394f32010-11-08 19:18:58 +0000444 struct drm_i915_gem_object *obj = ring->obj;
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200445 int ret = 0;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800446 u32 head;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800447
Deepak Sc8d9a592013-11-23 14:55:42 +0530448 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200449
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800450 /* Stop the ring if it's running. */
Daniel Vetter7f2ab692010-08-02 17:06:59 +0200451 I915_WRITE_CTL(ring, 0);
Daniel Vetter570ef602010-08-02 17:06:23 +0200452 I915_WRITE_HEAD(ring, 0);
Chris Wilson78501ea2010-10-27 12:18:21 +0100453 ring->write_tail(ring, 0);
Naresh Kumar Kachhie9fea572014-03-12 16:39:41 +0530454 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000))
455 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800456
Naresh Kumar Kachhia51435a2014-03-12 16:39:40 +0530457 if (I915_NEED_GFX_HWS(dev))
458 intel_ring_setup_status_page(ring);
459 else
460 ring_setup_phys_status_page(ring);
461
Daniel Vetter570ef602010-08-02 17:06:23 +0200462 head = I915_READ_HEAD(ring) & HEAD_ADDR;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800463
464 /* G45 ring initialization fails to reset head to zero */
465 if (head != 0) {
Chris Wilson6fd0d562010-12-05 20:42:33 +0000466 DRM_DEBUG_KMS("%s head not reset to zero "
467 "ctl %08x head %08x tail %08x start %08x\n",
468 ring->name,
469 I915_READ_CTL(ring),
470 I915_READ_HEAD(ring),
471 I915_READ_TAIL(ring),
472 I915_READ_START(ring));
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800473
Daniel Vetter570ef602010-08-02 17:06:23 +0200474 I915_WRITE_HEAD(ring, 0);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800475
Chris Wilson6fd0d562010-12-05 20:42:33 +0000476 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
477 DRM_ERROR("failed to set %s head to zero "
478 "ctl %08x head %08x tail %08x start %08x\n",
479 ring->name,
480 I915_READ_CTL(ring),
481 I915_READ_HEAD(ring),
482 I915_READ_TAIL(ring),
483 I915_READ_START(ring));
484 }
Eric Anholt62fdfea2010-05-21 13:26:39 -0700485 }
486
Daniel Vetter0d8957c2012-08-07 09:54:14 +0200487 /* Initialize the ring. This must happen _after_ we've cleared the ring
488 * registers with the above sequence (the readback of the HEAD registers
489 * also enforces ordering), otherwise the hw might lose the new ring
490 * register values. */
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700491 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
Daniel Vetter7f2ab692010-08-02 17:06:59 +0200492 I915_WRITE_CTL(ring,
Chris Wilsonae69b422010-11-07 11:45:52 +0000493 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
Chris Wilson5d031e52012-02-08 13:34:13 +0000494 | RING_VALID);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800495
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800496 /* If the head is still not zero, the ring is dead */
Sean Paulf01db982012-03-16 12:43:22 -0400497 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700498 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
Sean Paulf01db982012-03-16 12:43:22 -0400499 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
Chris Wilsone74cfed2010-11-09 10:16:56 +0000500 DRM_ERROR("%s initialization failed "
501 "ctl %08x head %08x tail %08x start %08x\n",
502 ring->name,
503 I915_READ_CTL(ring),
504 I915_READ_HEAD(ring),
505 I915_READ_TAIL(ring),
506 I915_READ_START(ring));
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200507 ret = -EIO;
508 goto out;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800509 }
510
Chris Wilson78501ea2010-10-27 12:18:21 +0100511 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
512 i915_kernel_lost_context(ring->dev);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800513 else {
Chris Wilsonc7dca472011-01-20 17:00:10 +0000514 ring->head = I915_READ_HEAD(ring);
Daniel Vetter870e86d2010-08-02 16:29:44 +0200515 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
Chris Wilsonc7dca472011-01-20 17:00:10 +0000516 ring->space = ring_space(ring);
Chris Wilsonc3b20032012-05-28 22:33:02 +0100517 ring->last_retired_head = -1;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800518 }
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000519
Chris Wilson50f018d2013-06-10 11:20:19 +0100520 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
521
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200522out:
Deepak Sc8d9a592013-11-23 14:55:42 +0530523 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200524
525 return ret;
Eric Anholt62fdfea2010-05-21 13:26:39 -0700526}
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800527
Chris Wilsonc6df5412010-12-15 09:56:50 +0000528static int
529init_pipe_control(struct intel_ring_buffer *ring)
530{
Chris Wilsonc6df5412010-12-15 09:56:50 +0000531 int ret;
532
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100533 if (ring->scratch.obj)
Chris Wilsonc6df5412010-12-15 09:56:50 +0000534 return 0;
535
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100536 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
537 if (ring->scratch.obj == NULL) {
Chris Wilsonc6df5412010-12-15 09:56:50 +0000538 DRM_ERROR("Failed to allocate seqno page\n");
539 ret = -ENOMEM;
540 goto err;
541 }
Chris Wilsone4ffd172011-04-04 09:44:39 +0100542
Daniel Vettera9cc7262014-02-14 14:01:13 +0100543 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
544 if (ret)
545 goto err_unref;
Chris Wilsonc6df5412010-12-15 09:56:50 +0000546
Daniel Vetter1ec9e262014-02-14 14:01:11 +0100547 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
Chris Wilsonc6df5412010-12-15 09:56:50 +0000548 if (ret)
549 goto err_unref;
550
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100551 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
552 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
553 if (ring->scratch.cpu_page == NULL) {
Wei Yongjun56b085a2013-05-28 17:51:44 +0800554 ret = -ENOMEM;
Chris Wilsonc6df5412010-12-15 09:56:50 +0000555 goto err_unpin;
Wei Yongjun56b085a2013-05-28 17:51:44 +0800556 }
Chris Wilsonc6df5412010-12-15 09:56:50 +0000557
Ville Syrjälä2b1086c2013-02-12 22:01:38 +0200558 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100559 ring->name, ring->scratch.gtt_offset);
Chris Wilsonc6df5412010-12-15 09:56:50 +0000560 return 0;
561
562err_unpin:
Ben Widawskyd7f46fc2013-12-06 14:10:55 -0800563 i915_gem_object_ggtt_unpin(ring->scratch.obj);
Chris Wilsonc6df5412010-12-15 09:56:50 +0000564err_unref:
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100565 drm_gem_object_unreference(&ring->scratch.obj->base);
Chris Wilsonc6df5412010-12-15 09:56:50 +0000566err:
Chris Wilsonc6df5412010-12-15 09:56:50 +0000567 return ret;
568}
569
Chris Wilson78501ea2010-10-27 12:18:21 +0100570static int init_render_ring(struct intel_ring_buffer *ring)
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800571{
Chris Wilson78501ea2010-10-27 12:18:21 +0100572 struct drm_device *dev = ring->dev;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000573 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson78501ea2010-10-27 12:18:21 +0100574 int ret = init_ring_common(ring);
Zhenyu Wanga69ffdb2010-08-30 16:12:42 +0800575
Akash Goel61a563a2014-03-25 18:01:50 +0530576 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
577 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
Daniel Vetter6b26c862012-04-24 14:04:12 +0200578 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
Chris Wilson1c8c38c2013-01-20 16:11:20 +0000579
580 /* We need to disable the AsyncFlip performance optimisations in order
581 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
582 * programmed to '1' on all products.
Damien Lespiau8693a822013-05-03 18:48:11 +0100583 *
Ville Syrjälä82852222014-02-27 21:59:03 +0200584 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
Chris Wilson1c8c38c2013-01-20 16:11:20 +0000585 */
586 if (INTEL_INFO(dev)->gen >= 6)
587 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
588
Chris Wilsonf05bb0c2013-01-20 16:33:32 +0000589 /* Required for the hardware to program scanline values for waiting */
590 if (INTEL_INFO(dev)->gen == 6)
591 I915_WRITE(GFX_MODE,
592 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
593
Chris Wilson1c8c38c2013-01-20 16:11:20 +0000594 if (IS_GEN7(dev))
595 I915_WRITE(GFX_MODE_GEN7,
596 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
597 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
Chris Wilson78501ea2010-10-27 12:18:21 +0100598
Jesse Barnes8d315282011-10-16 10:23:31 +0200599 if (INTEL_INFO(dev)->gen >= 5) {
Chris Wilsonc6df5412010-12-15 09:56:50 +0000600 ret = init_pipe_control(ring);
601 if (ret)
602 return ret;
603 }
604
Daniel Vetter5e13a0c2012-05-08 13:39:59 +0200605 if (IS_GEN6(dev)) {
Kenneth Graunke3a69ddd2012-04-27 12:44:41 -0700606 /* From the Sandybridge PRM, volume 1 part 3, page 24:
607 * "If this bit is set, STCunit will have LRA as replacement
608 * policy. [...] This bit must be reset. LRA replacement
609 * policy is not supported."
610 */
611 I915_WRITE(CACHE_MODE_0,
Daniel Vetter5e13a0c2012-05-08 13:39:59 +0200612 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
Ben Widawsky12b02862012-06-04 14:42:50 -0700613
614 /* This is not explicitly set for GEN6, so read the register.
615 * see intel_ring_mi_set_context() for why we care.
616 * TODO: consider explicitly setting the bit for GEN5
617 */
618 ring->itlb_before_ctx_switch =
619 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
Ben Widawsky84f9f932011-12-12 19:21:58 -0800620 }
621
Daniel Vetter6b26c862012-04-24 14:04:12 +0200622 if (INTEL_INFO(dev)->gen >= 6)
623 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
Chris Wilsonc6df5412010-12-15 09:56:50 +0000624
Ben Widawsky040d2ba2013-09-19 11:01:40 -0700625 if (HAS_L3_DPF(dev))
Ben Widawsky35a85ac2013-09-19 11:13:41 -0700626 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
Ben Widawsky15b9f802012-05-25 16:56:23 -0700627
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800628 return ret;
629}
630
Chris Wilsonc6df5412010-12-15 09:56:50 +0000631static void render_ring_cleanup(struct intel_ring_buffer *ring)
632{
Daniel Vetterb45305f2012-12-17 16:21:27 +0100633 struct drm_device *dev = ring->dev;
634
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100635 if (ring->scratch.obj == NULL)
Chris Wilsonc6df5412010-12-15 09:56:50 +0000636 return;
637
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100638 if (INTEL_INFO(dev)->gen >= 5) {
639 kunmap(sg_page(ring->scratch.obj->pages->sgl));
Ben Widawskyd7f46fc2013-12-06 14:10:55 -0800640 i915_gem_object_ggtt_unpin(ring->scratch.obj);
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100641 }
Daniel Vetterb45305f2012-12-17 16:21:27 +0100642
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100643 drm_gem_object_unreference(&ring->scratch.obj->base);
644 ring->scratch.obj = NULL;
Chris Wilsonc6df5412010-12-15 09:56:50 +0000645}
646
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000647static void
Ben Widawskyc8c99b02011-09-14 20:32:47 -0700648update_mboxes(struct intel_ring_buffer *ring,
Chris Wilson9d7730912012-11-27 16:22:52 +0000649 u32 mmio_offset)
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000650{
Ben Widawskyad776f82013-05-28 19:22:18 -0700651/* NB: In order to be able to do semaphore MBOX updates for varying number
652 * of rings, it's easiest if we round up each individual update to a
653 * multiple of 2 (since ring updates must always be a multiple of 2)
654 * even though the actual update only requires 3 dwords.
655 */
656#define MBOX_UPDATE_DWORDS 4
Chris Wilson1c8b46f2012-11-14 09:15:14 +0000657 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
Ben Widawskyc8c99b02011-09-14 20:32:47 -0700658 intel_ring_emit(ring, mmio_offset);
Chris Wilson18235212013-09-04 10:45:51 +0100659 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
Ben Widawskyad776f82013-05-28 19:22:18 -0700660 intel_ring_emit(ring, MI_NOOP);
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000661}
662
Ben Widawskyc8c99b02011-09-14 20:32:47 -0700663/**
664 * gen6_add_request - Update the semaphore mailbox registers
665 *
666 * @ring - ring that is adding a request
667 * @seqno - return seqno stuck into the ring
668 *
669 * Update the mailbox registers in the *other* rings with the current seqno.
670 * This acts like a signal in the canonical semaphore.
671 */
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000672static int
Chris Wilson9d7730912012-11-27 16:22:52 +0000673gen6_add_request(struct intel_ring_buffer *ring)
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000674{
Ben Widawskyad776f82013-05-28 19:22:18 -0700675 struct drm_device *dev = ring->dev;
676 struct drm_i915_private *dev_priv = dev->dev_private;
677 struct intel_ring_buffer *useless;
Ben Widawsky52ed2322013-12-16 20:50:38 -0800678 int i, ret, num_dwords = 4;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000679
Ben Widawsky52ed2322013-12-16 20:50:38 -0800680 if (i915_semaphore_is_enabled(dev))
681 num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS);
682#undef MBOX_UPDATE_DWORDS
683
684 ret = intel_ring_begin(ring, num_dwords);
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000685 if (ret)
686 return ret;
687
Ben Widawskyf0a9f742013-12-17 20:06:00 -0800688 if (i915_semaphore_is_enabled(dev)) {
689 for_each_ring(useless, dev_priv, i) {
690 u32 mbox_reg = ring->signal_mbox[i];
691 if (mbox_reg != GEN6_NOSYNC)
692 update_mboxes(ring, mbox_reg);
693 }
Ben Widawskyad776f82013-05-28 19:22:18 -0700694 }
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000695
696 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
697 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
Chris Wilson18235212013-09-04 10:45:51 +0100698 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000699 intel_ring_emit(ring, MI_USER_INTERRUPT);
Chris Wilson09246732013-08-10 22:16:32 +0100700 __intel_ring_advance(ring);
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000701
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000702 return 0;
703}
704
Mika Kuoppalaf72b3432012-12-10 15:41:48 +0200705static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
706 u32 seqno)
707{
708 struct drm_i915_private *dev_priv = dev->dev_private;
709 return dev_priv->last_seqno < seqno;
710}
711
Ben Widawskyc8c99b02011-09-14 20:32:47 -0700712/**
713 * intel_ring_sync - sync the waiter to the signaller on seqno
714 *
715 * @waiter - ring that is waiting
716 * @signaller - ring which has, or will signal
717 * @seqno - seqno which the waiter will block on
718 */
719static int
Daniel Vetter686cb5f2012-04-11 22:12:52 +0200720gen6_ring_sync(struct intel_ring_buffer *waiter,
721 struct intel_ring_buffer *signaller,
722 u32 seqno)
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000723{
724 int ret;
Ben Widawskyc8c99b02011-09-14 20:32:47 -0700725 u32 dw1 = MI_SEMAPHORE_MBOX |
726 MI_SEMAPHORE_COMPARE |
727 MI_SEMAPHORE_REGISTER;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000728
Ben Widawsky1500f7e2012-04-11 11:18:21 -0700729 /* Throughout all of the GEM code, seqno passed implies our current
730 * seqno is >= the last seqno executed. However for hardware the
731 * comparison is strictly greater than.
732 */
733 seqno -= 1;
734
Daniel Vetter686cb5f2012-04-11 22:12:52 +0200735 WARN_ON(signaller->semaphore_register[waiter->id] ==
736 MI_SEMAPHORE_SYNC_INVALID);
737
Ben Widawskyc8c99b02011-09-14 20:32:47 -0700738 ret = intel_ring_begin(waiter, 4);
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000739 if (ret)
740 return ret;
741
Mika Kuoppalaf72b3432012-12-10 15:41:48 +0200742 /* If seqno wrap happened, omit the wait with no-ops */
743 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
744 intel_ring_emit(waiter,
745 dw1 |
746 signaller->semaphore_register[waiter->id]);
747 intel_ring_emit(waiter, seqno);
748 intel_ring_emit(waiter, 0);
749 intel_ring_emit(waiter, MI_NOOP);
750 } else {
751 intel_ring_emit(waiter, MI_NOOP);
752 intel_ring_emit(waiter, MI_NOOP);
753 intel_ring_emit(waiter, MI_NOOP);
754 intel_ring_emit(waiter, MI_NOOP);
755 }
Ben Widawskyc8c99b02011-09-14 20:32:47 -0700756 intel_ring_advance(waiter);
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000757
758 return 0;
759}
760
Chris Wilsonc6df5412010-12-15 09:56:50 +0000761#define PIPE_CONTROL_FLUSH(ring__, addr__) \
762do { \
Kenneth Graunkefcbc34e2011-10-11 23:41:08 +0200763 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
764 PIPE_CONTROL_DEPTH_STALL); \
Chris Wilsonc6df5412010-12-15 09:56:50 +0000765 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
766 intel_ring_emit(ring__, 0); \
767 intel_ring_emit(ring__, 0); \
768} while (0)
769
770static int
Chris Wilson9d7730912012-11-27 16:22:52 +0000771pc_render_add_request(struct intel_ring_buffer *ring)
Chris Wilsonc6df5412010-12-15 09:56:50 +0000772{
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100773 u32 scratch_addr = ring->scratch.gtt_offset + 128;
Chris Wilsonc6df5412010-12-15 09:56:50 +0000774 int ret;
775
776 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
777 * incoherent with writes to memory, i.e. completely fubar,
778 * so we need to use PIPE_NOTIFY instead.
779 *
780 * However, we also need to workaround the qword write
781 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
782 * memory before requesting an interrupt.
783 */
784 ret = intel_ring_begin(ring, 32);
785 if (ret)
786 return ret;
787
Kenneth Graunkefcbc34e2011-10-11 23:41:08 +0200788 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200789 PIPE_CONTROL_WRITE_FLUSH |
790 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100791 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
Chris Wilson18235212013-09-04 10:45:51 +0100792 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
Chris Wilsonc6df5412010-12-15 09:56:50 +0000793 intel_ring_emit(ring, 0);
794 PIPE_CONTROL_FLUSH(ring, scratch_addr);
795 scratch_addr += 128; /* write to separate cachelines */
796 PIPE_CONTROL_FLUSH(ring, scratch_addr);
797 scratch_addr += 128;
798 PIPE_CONTROL_FLUSH(ring, scratch_addr);
799 scratch_addr += 128;
800 PIPE_CONTROL_FLUSH(ring, scratch_addr);
801 scratch_addr += 128;
802 PIPE_CONTROL_FLUSH(ring, scratch_addr);
803 scratch_addr += 128;
804 PIPE_CONTROL_FLUSH(ring, scratch_addr);
Chris Wilsona71d8d92012-02-15 11:25:36 +0000805
Kenneth Graunkefcbc34e2011-10-11 23:41:08 +0200806 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200807 PIPE_CONTROL_WRITE_FLUSH |
808 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
Chris Wilsonc6df5412010-12-15 09:56:50 +0000809 PIPE_CONTROL_NOTIFY);
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100810 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
Chris Wilson18235212013-09-04 10:45:51 +0100811 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
Chris Wilsonc6df5412010-12-15 09:56:50 +0000812 intel_ring_emit(ring, 0);
Chris Wilson09246732013-08-10 22:16:32 +0100813 __intel_ring_advance(ring);
Chris Wilsonc6df5412010-12-15 09:56:50 +0000814
Chris Wilsonc6df5412010-12-15 09:56:50 +0000815 return 0;
816}
817
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800818static u32
Chris Wilsonb2eadbc2012-08-09 10:58:30 +0100819gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
Daniel Vetter4cd53c02012-12-14 16:01:25 +0100820{
Daniel Vetter4cd53c02012-12-14 16:01:25 +0100821 /* Workaround to force correct ordering between irq and seqno writes on
822 * ivb (and maybe also on snb) by reading from a CS register (like
823 * ACTHD) before reading the status page. */
Chris Wilson50877442014-03-21 12:41:53 +0000824 if (!lazy_coherency) {
825 struct drm_i915_private *dev_priv = ring->dev->dev_private;
826 POSTING_READ(RING_ACTHD(ring->mmio_base));
827 }
828
Daniel Vetter4cd53c02012-12-14 16:01:25 +0100829 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
830}
831
832static u32
Chris Wilsonb2eadbc2012-08-09 10:58:30 +0100833ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800834{
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000835 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
836}
837
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +0200838static void
839ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
840{
841 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
842}
843
Chris Wilsonc6df5412010-12-15 09:56:50 +0000844static u32
Chris Wilsonb2eadbc2012-08-09 10:58:30 +0100845pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
Chris Wilsonc6df5412010-12-15 09:56:50 +0000846{
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100847 return ring->scratch.cpu_page[0];
Chris Wilsonc6df5412010-12-15 09:56:50 +0000848}
849
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +0200850static void
851pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
852{
Chris Wilson0d1aaca2013-08-26 20:58:11 +0100853 ring->scratch.cpu_page[0] = seqno;
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +0200854}
855
Chris Wilsonb13c2b92010-12-13 16:54:50 +0000856static bool
Daniel Vettere48d8632012-04-11 22:12:54 +0200857gen5_ring_get_irq(struct intel_ring_buffer *ring)
858{
859 struct drm_device *dev = ring->dev;
Jani Nikula4640c4f2014-03-31 14:27:19 +0300860 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson7338aef2012-04-24 21:48:47 +0100861 unsigned long flags;
Daniel Vettere48d8632012-04-11 22:12:54 +0200862
863 if (!dev->irq_enabled)
864 return false;
865
Chris Wilson7338aef2012-04-24 21:48:47 +0100866 spin_lock_irqsave(&dev_priv->irq_lock, flags);
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300867 if (ring->irq_refcount++ == 0)
868 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
Chris Wilson7338aef2012-04-24 21:48:47 +0100869 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
Daniel Vettere48d8632012-04-11 22:12:54 +0200870
871 return true;
872}
873
874static void
875gen5_ring_put_irq(struct intel_ring_buffer *ring)
876{
877 struct drm_device *dev = ring->dev;
Jani Nikula4640c4f2014-03-31 14:27:19 +0300878 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson7338aef2012-04-24 21:48:47 +0100879 unsigned long flags;
Daniel Vettere48d8632012-04-11 22:12:54 +0200880
Chris Wilson7338aef2012-04-24 21:48:47 +0100881 spin_lock_irqsave(&dev_priv->irq_lock, flags);
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300882 if (--ring->irq_refcount == 0)
883 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
Chris Wilson7338aef2012-04-24 21:48:47 +0100884 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
Daniel Vettere48d8632012-04-11 22:12:54 +0200885}
886
887static bool
Daniel Vettere3670312012-04-11 22:12:53 +0200888i9xx_ring_get_irq(struct intel_ring_buffer *ring)
Eric Anholt62fdfea2010-05-21 13:26:39 -0700889{
Chris Wilson78501ea2010-10-27 12:18:21 +0100890 struct drm_device *dev = ring->dev;
Jani Nikula4640c4f2014-03-31 14:27:19 +0300891 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson7338aef2012-04-24 21:48:47 +0100892 unsigned long flags;
Eric Anholt62fdfea2010-05-21 13:26:39 -0700893
Chris Wilsonb13c2b92010-12-13 16:54:50 +0000894 if (!dev->irq_enabled)
895 return false;
896
Chris Wilson7338aef2012-04-24 21:48:47 +0100897 spin_lock_irqsave(&dev_priv->irq_lock, flags);
Daniel Vetterc7113cc2013-07-04 23:35:29 +0200898 if (ring->irq_refcount++ == 0) {
Daniel Vetterf637fde2012-04-11 22:12:59 +0200899 dev_priv->irq_mask &= ~ring->irq_enable_mask;
900 I915_WRITE(IMR, dev_priv->irq_mask);
901 POSTING_READ(IMR);
902 }
Chris Wilson7338aef2012-04-24 21:48:47 +0100903 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
Chris Wilsonb13c2b92010-12-13 16:54:50 +0000904
905 return true;
Eric Anholt62fdfea2010-05-21 13:26:39 -0700906}
907
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800908static void
Daniel Vettere3670312012-04-11 22:12:53 +0200909i9xx_ring_put_irq(struct intel_ring_buffer *ring)
Eric Anholt62fdfea2010-05-21 13:26:39 -0700910{
Chris Wilson78501ea2010-10-27 12:18:21 +0100911 struct drm_device *dev = ring->dev;
Jani Nikula4640c4f2014-03-31 14:27:19 +0300912 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson7338aef2012-04-24 21:48:47 +0100913 unsigned long flags;
Eric Anholt62fdfea2010-05-21 13:26:39 -0700914
Chris Wilson7338aef2012-04-24 21:48:47 +0100915 spin_lock_irqsave(&dev_priv->irq_lock, flags);
Daniel Vetterc7113cc2013-07-04 23:35:29 +0200916 if (--ring->irq_refcount == 0) {
Daniel Vetterf637fde2012-04-11 22:12:59 +0200917 dev_priv->irq_mask |= ring->irq_enable_mask;
918 I915_WRITE(IMR, dev_priv->irq_mask);
919 POSTING_READ(IMR);
920 }
Chris Wilson7338aef2012-04-24 21:48:47 +0100921 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
Eric Anholt62fdfea2010-05-21 13:26:39 -0700922}
923
Chris Wilsonc2798b12012-04-22 21:13:57 +0100924static bool
925i8xx_ring_get_irq(struct intel_ring_buffer *ring)
926{
927 struct drm_device *dev = ring->dev;
Jani Nikula4640c4f2014-03-31 14:27:19 +0300928 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson7338aef2012-04-24 21:48:47 +0100929 unsigned long flags;
Chris Wilsonc2798b12012-04-22 21:13:57 +0100930
931 if (!dev->irq_enabled)
932 return false;
933
Chris Wilson7338aef2012-04-24 21:48:47 +0100934 spin_lock_irqsave(&dev_priv->irq_lock, flags);
Daniel Vetterc7113cc2013-07-04 23:35:29 +0200935 if (ring->irq_refcount++ == 0) {
Chris Wilsonc2798b12012-04-22 21:13:57 +0100936 dev_priv->irq_mask &= ~ring->irq_enable_mask;
937 I915_WRITE16(IMR, dev_priv->irq_mask);
938 POSTING_READ16(IMR);
939 }
Chris Wilson7338aef2012-04-24 21:48:47 +0100940 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
Chris Wilsonc2798b12012-04-22 21:13:57 +0100941
942 return true;
943}
944
945static void
946i8xx_ring_put_irq(struct intel_ring_buffer *ring)
947{
948 struct drm_device *dev = ring->dev;
Jani Nikula4640c4f2014-03-31 14:27:19 +0300949 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson7338aef2012-04-24 21:48:47 +0100950 unsigned long flags;
Chris Wilsonc2798b12012-04-22 21:13:57 +0100951
Chris Wilson7338aef2012-04-24 21:48:47 +0100952 spin_lock_irqsave(&dev_priv->irq_lock, flags);
Daniel Vetterc7113cc2013-07-04 23:35:29 +0200953 if (--ring->irq_refcount == 0) {
Chris Wilsonc2798b12012-04-22 21:13:57 +0100954 dev_priv->irq_mask |= ring->irq_enable_mask;
955 I915_WRITE16(IMR, dev_priv->irq_mask);
956 POSTING_READ16(IMR);
957 }
Chris Wilson7338aef2012-04-24 21:48:47 +0100958 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
Chris Wilsonc2798b12012-04-22 21:13:57 +0100959}
960
Chris Wilson78501ea2010-10-27 12:18:21 +0100961void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800962{
Eric Anholt45930102011-05-06 17:12:35 -0700963 struct drm_device *dev = ring->dev;
Jani Nikula4640c4f2014-03-31 14:27:19 +0300964 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Eric Anholt45930102011-05-06 17:12:35 -0700965 u32 mmio = 0;
966
967 /* The ring status page addresses are no longer next to the rest of
968 * the ring registers as of gen7.
969 */
970 if (IS_GEN7(dev)) {
971 switch (ring->id) {
Daniel Vetter96154f22011-12-14 13:57:00 +0100972 case RCS:
Eric Anholt45930102011-05-06 17:12:35 -0700973 mmio = RENDER_HWS_PGA_GEN7;
974 break;
Daniel Vetter96154f22011-12-14 13:57:00 +0100975 case BCS:
Eric Anholt45930102011-05-06 17:12:35 -0700976 mmio = BLT_HWS_PGA_GEN7;
977 break;
Daniel Vetter96154f22011-12-14 13:57:00 +0100978 case VCS:
Eric Anholt45930102011-05-06 17:12:35 -0700979 mmio = BSD_HWS_PGA_GEN7;
980 break;
Ben Widawsky4a3dd192013-05-28 19:22:19 -0700981 case VECS:
Ben Widawsky9a8a2212013-05-28 19:22:23 -0700982 mmio = VEBOX_HWS_PGA_GEN7;
983 break;
Eric Anholt45930102011-05-06 17:12:35 -0700984 }
985 } else if (IS_GEN6(ring->dev)) {
986 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
987 } else {
Ben Widawskyeb0d4b72013-11-07 21:40:50 -0800988 /* XXX: gen8 returns to sanity */
Eric Anholt45930102011-05-06 17:12:35 -0700989 mmio = RING_HWS_PGA(ring->mmio_base);
990 }
991
Chris Wilson78501ea2010-10-27 12:18:21 +0100992 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
993 POSTING_READ(mmio);
Chris Wilson884020b2013-08-06 19:01:14 +0100994
Damien Lespiaudc616b82014-03-13 01:40:28 +0000995 /*
996 * Flush the TLB for this page
997 *
998 * FIXME: These two bits have disappeared on gen8, so a question
999 * arises: do we still need this and if so how should we go about
1000 * invalidating the TLB?
1001 */
1002 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
Chris Wilson884020b2013-08-06 19:01:14 +01001003 u32 reg = RING_INSTPM(ring->mmio_base);
Naresh Kumar Kachhi02f6a1e2014-03-12 16:39:42 +05301004
1005 /* ring should be idle before issuing a sync flush*/
1006 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1007
Chris Wilson884020b2013-08-06 19:01:14 +01001008 I915_WRITE(reg,
1009 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1010 INSTPM_SYNC_FLUSH));
1011 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1012 1000))
1013 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1014 ring->name);
1015 }
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001016}
1017
Chris Wilsonb72f3ac2011-01-04 17:34:02 +00001018static int
Chris Wilson78501ea2010-10-27 12:18:21 +01001019bsd_ring_flush(struct intel_ring_buffer *ring,
1020 u32 invalidate_domains,
1021 u32 flush_domains)
Zou Nan haid1b851f2010-05-21 09:08:57 +08001022{
Chris Wilsonb72f3ac2011-01-04 17:34:02 +00001023 int ret;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001024
Chris Wilsonb72f3ac2011-01-04 17:34:02 +00001025 ret = intel_ring_begin(ring, 2);
1026 if (ret)
1027 return ret;
1028
1029 intel_ring_emit(ring, MI_FLUSH);
1030 intel_ring_emit(ring, MI_NOOP);
1031 intel_ring_advance(ring);
1032 return 0;
Zou Nan haid1b851f2010-05-21 09:08:57 +08001033}
1034
Chris Wilson3cce4692010-10-27 16:11:02 +01001035static int
Chris Wilson9d7730912012-11-27 16:22:52 +00001036i9xx_add_request(struct intel_ring_buffer *ring)
Zou Nan haid1b851f2010-05-21 09:08:57 +08001037{
Chris Wilson3cce4692010-10-27 16:11:02 +01001038 int ret;
1039
1040 ret = intel_ring_begin(ring, 4);
1041 if (ret)
1042 return ret;
Chris Wilson6f392d5482010-08-07 11:01:22 +01001043
Chris Wilson3cce4692010-10-27 16:11:02 +01001044 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1045 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
Chris Wilson18235212013-09-04 10:45:51 +01001046 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
Chris Wilson3cce4692010-10-27 16:11:02 +01001047 intel_ring_emit(ring, MI_USER_INTERRUPT);
Chris Wilson09246732013-08-10 22:16:32 +01001048 __intel_ring_advance(ring);
Zou Nan haid1b851f2010-05-21 09:08:57 +08001049
Chris Wilson3cce4692010-10-27 16:11:02 +01001050 return 0;
Zou Nan haid1b851f2010-05-21 09:08:57 +08001051}
1052
Chris Wilsonb13c2b92010-12-13 16:54:50 +00001053static bool
Ben Widawsky25c06302012-03-29 19:11:27 -07001054gen6_ring_get_irq(struct intel_ring_buffer *ring)
Chris Wilson0f468322011-01-04 17:35:21 +00001055{
1056 struct drm_device *dev = ring->dev;
Jani Nikula4640c4f2014-03-31 14:27:19 +03001057 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson7338aef2012-04-24 21:48:47 +01001058 unsigned long flags;
Chris Wilson0f468322011-01-04 17:35:21 +00001059
1060 if (!dev->irq_enabled)
1061 return false;
1062
Chris Wilson7338aef2012-04-24 21:48:47 +01001063 spin_lock_irqsave(&dev_priv->irq_lock, flags);
Daniel Vetterc7113cc2013-07-04 23:35:29 +02001064 if (ring->irq_refcount++ == 0) {
Ben Widawsky040d2ba2013-09-19 11:01:40 -07001065 if (HAS_L3_DPF(dev) && ring->id == RCS)
Ben Widawskycc609d52013-05-28 19:22:29 -07001066 I915_WRITE_IMR(ring,
1067 ~(ring->irq_enable_mask |
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001068 GT_PARITY_ERROR(dev)));
Ben Widawsky15b9f802012-05-25 16:56:23 -07001069 else
1070 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
Paulo Zanoni43eaea12013-08-06 18:57:12 -03001071 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
Chris Wilson0f468322011-01-04 17:35:21 +00001072 }
Chris Wilson7338aef2012-04-24 21:48:47 +01001073 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
Chris Wilson0f468322011-01-04 17:35:21 +00001074
1075 return true;
1076}
1077
1078static void
Ben Widawsky25c06302012-03-29 19:11:27 -07001079gen6_ring_put_irq(struct intel_ring_buffer *ring)
Chris Wilson0f468322011-01-04 17:35:21 +00001080{
1081 struct drm_device *dev = ring->dev;
Jani Nikula4640c4f2014-03-31 14:27:19 +03001082 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson7338aef2012-04-24 21:48:47 +01001083 unsigned long flags;
Chris Wilson0f468322011-01-04 17:35:21 +00001084
Chris Wilson7338aef2012-04-24 21:48:47 +01001085 spin_lock_irqsave(&dev_priv->irq_lock, flags);
Daniel Vetterc7113cc2013-07-04 23:35:29 +02001086 if (--ring->irq_refcount == 0) {
Ben Widawsky040d2ba2013-09-19 11:01:40 -07001087 if (HAS_L3_DPF(dev) && ring->id == RCS)
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001088 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
Ben Widawsky15b9f802012-05-25 16:56:23 -07001089 else
1090 I915_WRITE_IMR(ring, ~0);
Paulo Zanoni43eaea12013-08-06 18:57:12 -03001091 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001092 }
Chris Wilson7338aef2012-04-24 21:48:47 +01001093 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001094}
1095
Ben Widawskya19d2932013-05-28 19:22:30 -07001096static bool
1097hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1098{
1099 struct drm_device *dev = ring->dev;
1100 struct drm_i915_private *dev_priv = dev->dev_private;
1101 unsigned long flags;
1102
1103 if (!dev->irq_enabled)
1104 return false;
1105
Daniel Vetter59cdb632013-07-04 23:35:28 +02001106 spin_lock_irqsave(&dev_priv->irq_lock, flags);
Daniel Vetterc7113cc2013-07-04 23:35:29 +02001107 if (ring->irq_refcount++ == 0) {
Ben Widawskya19d2932013-05-28 19:22:30 -07001108 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
Paulo Zanoniedbfdb42013-08-06 18:57:13 -03001109 snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
Ben Widawskya19d2932013-05-28 19:22:30 -07001110 }
Daniel Vetter59cdb632013-07-04 23:35:28 +02001111 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
Ben Widawskya19d2932013-05-28 19:22:30 -07001112
1113 return true;
1114}
1115
1116static void
1117hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1118{
1119 struct drm_device *dev = ring->dev;
1120 struct drm_i915_private *dev_priv = dev->dev_private;
1121 unsigned long flags;
1122
1123 if (!dev->irq_enabled)
1124 return;
1125
Daniel Vetter59cdb632013-07-04 23:35:28 +02001126 spin_lock_irqsave(&dev_priv->irq_lock, flags);
Daniel Vetterc7113cc2013-07-04 23:35:29 +02001127 if (--ring->irq_refcount == 0) {
Ben Widawskya19d2932013-05-28 19:22:30 -07001128 I915_WRITE_IMR(ring, ~0);
Paulo Zanoniedbfdb42013-08-06 18:57:13 -03001129 snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
Ben Widawskya19d2932013-05-28 19:22:30 -07001130 }
Daniel Vetter59cdb632013-07-04 23:35:28 +02001131 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
Ben Widawskya19d2932013-05-28 19:22:30 -07001132}
1133
Ben Widawskyabd58f02013-11-02 21:07:09 -07001134static bool
1135gen8_ring_get_irq(struct intel_ring_buffer *ring)
1136{
1137 struct drm_device *dev = ring->dev;
1138 struct drm_i915_private *dev_priv = dev->dev_private;
1139 unsigned long flags;
1140
1141 if (!dev->irq_enabled)
1142 return false;
1143
1144 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1145 if (ring->irq_refcount++ == 0) {
1146 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1147 I915_WRITE_IMR(ring,
1148 ~(ring->irq_enable_mask |
1149 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1150 } else {
1151 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1152 }
1153 POSTING_READ(RING_IMR(ring->mmio_base));
1154 }
1155 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1156
1157 return true;
1158}
1159
1160static void
1161gen8_ring_put_irq(struct intel_ring_buffer *ring)
1162{
1163 struct drm_device *dev = ring->dev;
1164 struct drm_i915_private *dev_priv = dev->dev_private;
1165 unsigned long flags;
1166
1167 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1168 if (--ring->irq_refcount == 0) {
1169 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1170 I915_WRITE_IMR(ring,
1171 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1172 } else {
1173 I915_WRITE_IMR(ring, ~0);
1174 }
1175 POSTING_READ(RING_IMR(ring->mmio_base));
1176 }
1177 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1178}
1179
Zou Nan haid1b851f2010-05-21 09:08:57 +08001180static int
Chris Wilsond7d4eed2012-10-17 12:09:54 +01001181i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1182 u32 offset, u32 length,
1183 unsigned flags)
Zou Nan haid1b851f2010-05-21 09:08:57 +08001184{
Chris Wilsone1f99ce2010-10-27 12:45:26 +01001185 int ret;
Chris Wilson78501ea2010-10-27 12:18:21 +01001186
Chris Wilsone1f99ce2010-10-27 12:45:26 +01001187 ret = intel_ring_begin(ring, 2);
1188 if (ret)
1189 return ret;
1190
Chris Wilson78501ea2010-10-27 12:18:21 +01001191 intel_ring_emit(ring,
Chris Wilson65f56872012-04-17 16:38:12 +01001192 MI_BATCH_BUFFER_START |
1193 MI_BATCH_GTT |
Chris Wilsond7d4eed2012-10-17 12:09:54 +01001194 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
Chris Wilsonc4e7a412010-11-30 14:10:25 +00001195 intel_ring_emit(ring, offset);
Chris Wilson78501ea2010-10-27 12:18:21 +01001196 intel_ring_advance(ring);
1197
Zou Nan haid1b851f2010-05-21 09:08:57 +08001198 return 0;
1199}
1200
Daniel Vetterb45305f2012-12-17 16:21:27 +01001201/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1202#define I830_BATCH_LIMIT (256*1024)
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001203static int
Daniel Vetterfb3256d2012-04-11 22:12:56 +02001204i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
Chris Wilsond7d4eed2012-10-17 12:09:54 +01001205 u32 offset, u32 len,
1206 unsigned flags)
Eric Anholt62fdfea2010-05-21 13:26:39 -07001207{
Chris Wilsonc4e7a412010-11-30 14:10:25 +00001208 int ret;
Eric Anholt62fdfea2010-05-21 13:26:39 -07001209
Daniel Vetterb45305f2012-12-17 16:21:27 +01001210 if (flags & I915_DISPATCH_PINNED) {
1211 ret = intel_ring_begin(ring, 4);
1212 if (ret)
1213 return ret;
Eric Anholt62fdfea2010-05-21 13:26:39 -07001214
Daniel Vetterb45305f2012-12-17 16:21:27 +01001215 intel_ring_emit(ring, MI_BATCH_BUFFER);
1216 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1217 intel_ring_emit(ring, offset + len - 8);
1218 intel_ring_emit(ring, MI_NOOP);
1219 intel_ring_advance(ring);
1220 } else {
Chris Wilson0d1aaca2013-08-26 20:58:11 +01001221 u32 cs_offset = ring->scratch.gtt_offset;
Daniel Vetterb45305f2012-12-17 16:21:27 +01001222
1223 if (len > I830_BATCH_LIMIT)
1224 return -ENOSPC;
1225
1226 ret = intel_ring_begin(ring, 9+3);
1227 if (ret)
1228 return ret;
1229 /* Blit the batch (which has now all relocs applied) to the stable batch
1230 * scratch bo area (so that the CS never stumbles over its tlb
1231 * invalidation bug) ... */
1232 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1233 XY_SRC_COPY_BLT_WRITE_ALPHA |
1234 XY_SRC_COPY_BLT_WRITE_RGB);
1235 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1236 intel_ring_emit(ring, 0);
1237 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1238 intel_ring_emit(ring, cs_offset);
1239 intel_ring_emit(ring, 0);
1240 intel_ring_emit(ring, 4096);
1241 intel_ring_emit(ring, offset);
1242 intel_ring_emit(ring, MI_FLUSH);
1243
1244 /* ... and execute it. */
1245 intel_ring_emit(ring, MI_BATCH_BUFFER);
1246 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1247 intel_ring_emit(ring, cs_offset + len - 8);
1248 intel_ring_advance(ring);
1249 }
Chris Wilsone1f99ce2010-10-27 12:45:26 +01001250
Daniel Vetterfb3256d2012-04-11 22:12:56 +02001251 return 0;
1252}
1253
1254static int
1255i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
Chris Wilsond7d4eed2012-10-17 12:09:54 +01001256 u32 offset, u32 len,
1257 unsigned flags)
Daniel Vetterfb3256d2012-04-11 22:12:56 +02001258{
1259 int ret;
1260
1261 ret = intel_ring_begin(ring, 2);
1262 if (ret)
1263 return ret;
1264
Chris Wilson65f56872012-04-17 16:38:12 +01001265 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
Chris Wilsond7d4eed2012-10-17 12:09:54 +01001266 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
Chris Wilsonc4e7a412010-11-30 14:10:25 +00001267 intel_ring_advance(ring);
Eric Anholt62fdfea2010-05-21 13:26:39 -07001268
Eric Anholt62fdfea2010-05-21 13:26:39 -07001269 return 0;
1270}
1271
Chris Wilson78501ea2010-10-27 12:18:21 +01001272static void cleanup_status_page(struct intel_ring_buffer *ring)
Eric Anholt62fdfea2010-05-21 13:26:39 -07001273{
Chris Wilson05394f32010-11-08 19:18:58 +00001274 struct drm_i915_gem_object *obj;
Eric Anholt62fdfea2010-05-21 13:26:39 -07001275
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001276 obj = ring->status_page.obj;
1277 if (obj == NULL)
Eric Anholt62fdfea2010-05-21 13:26:39 -07001278 return;
Eric Anholt62fdfea2010-05-21 13:26:39 -07001279
Chris Wilson9da3da62012-06-01 15:20:22 +01001280 kunmap(sg_page(obj->pages->sgl));
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08001281 i915_gem_object_ggtt_unpin(obj);
Chris Wilson05394f32010-11-08 19:18:58 +00001282 drm_gem_object_unreference(&obj->base);
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001283 ring->status_page.obj = NULL;
Eric Anholt62fdfea2010-05-21 13:26:39 -07001284}
1285
Chris Wilson78501ea2010-10-27 12:18:21 +01001286static int init_status_page(struct intel_ring_buffer *ring)
Eric Anholt62fdfea2010-05-21 13:26:39 -07001287{
Chris Wilson78501ea2010-10-27 12:18:21 +01001288 struct drm_device *dev = ring->dev;
Chris Wilson05394f32010-11-08 19:18:58 +00001289 struct drm_i915_gem_object *obj;
Eric Anholt62fdfea2010-05-21 13:26:39 -07001290 int ret;
1291
Eric Anholt62fdfea2010-05-21 13:26:39 -07001292 obj = i915_gem_alloc_object(dev, 4096);
1293 if (obj == NULL) {
1294 DRM_ERROR("Failed to allocate status page\n");
1295 ret = -ENOMEM;
1296 goto err;
1297 }
Chris Wilsone4ffd172011-04-04 09:44:39 +01001298
Daniel Vettere01f6922014-02-14 14:01:16 +01001299 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1300 if (ret)
1301 goto err_unref;
Eric Anholt62fdfea2010-05-21 13:26:39 -07001302
Daniel Vetter9a6bbb62014-02-14 14:01:15 +01001303 ret = i915_gem_obj_ggtt_pin(obj, 4096, 0);
Daniel Vetter1ec9e262014-02-14 14:01:11 +01001304 if (ret)
Eric Anholt62fdfea2010-05-21 13:26:39 -07001305 goto err_unref;
Eric Anholt62fdfea2010-05-21 13:26:39 -07001306
Ben Widawskyf343c5f2013-07-05 14:41:04 -07001307 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
Chris Wilson9da3da62012-06-01 15:20:22 +01001308 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001309 if (ring->status_page.page_addr == NULL) {
Ben Widawsky2e6c21e2012-07-12 23:16:12 -07001310 ret = -ENOMEM;
Eric Anholt62fdfea2010-05-21 13:26:39 -07001311 goto err_unpin;
1312 }
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001313 ring->status_page.obj = obj;
1314 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
Eric Anholt62fdfea2010-05-21 13:26:39 -07001315
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001316 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1317 ring->name, ring->status_page.gfx_addr);
Eric Anholt62fdfea2010-05-21 13:26:39 -07001318
1319 return 0;
1320
1321err_unpin:
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08001322 i915_gem_object_ggtt_unpin(obj);
Eric Anholt62fdfea2010-05-21 13:26:39 -07001323err_unref:
Chris Wilson05394f32010-11-08 19:18:58 +00001324 drm_gem_object_unreference(&obj->base);
Eric Anholt62fdfea2010-05-21 13:26:39 -07001325err:
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001326 return ret;
Eric Anholt62fdfea2010-05-21 13:26:39 -07001327}
1328
Daniel Vetter035dc1e2013-07-03 12:56:54 +02001329static int init_phys_status_page(struct intel_ring_buffer *ring)
Chris Wilson6b8294a2012-11-16 11:43:20 +00001330{
1331 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Chris Wilson6b8294a2012-11-16 11:43:20 +00001332
1333 if (!dev_priv->status_page_dmah) {
1334 dev_priv->status_page_dmah =
1335 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1336 if (!dev_priv->status_page_dmah)
1337 return -ENOMEM;
1338 }
1339
Chris Wilson6b8294a2012-11-16 11:43:20 +00001340 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1341 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1342
1343 return 0;
1344}
1345
Ben Widawskyc43b5632012-04-16 14:07:40 -07001346static int intel_init_ring_buffer(struct drm_device *dev,
1347 struct intel_ring_buffer *ring)
Eric Anholt62fdfea2010-05-21 13:26:39 -07001348{
Chris Wilson05394f32010-11-08 19:18:58 +00001349 struct drm_i915_gem_object *obj;
Daniel Vetterdd2757f2012-06-07 15:55:57 +02001350 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsondd785e32010-08-07 11:01:34 +01001351 int ret;
1352
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001353 ring->dev = dev;
Chris Wilson23bc5982010-09-29 16:10:57 +01001354 INIT_LIST_HEAD(&ring->active_list);
1355 INIT_LIST_HEAD(&ring->request_list);
Daniel Vetterdfc9ef22012-04-11 22:12:47 +02001356 ring->size = 32 * PAGE_SIZE;
Chris Wilson9d7730912012-11-27 16:22:52 +00001357 memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
Chris Wilson0dc79fb2011-01-05 10:32:24 +00001358
Chris Wilsonb259f672011-03-29 13:19:09 +01001359 init_waitqueue_head(&ring->irq_queue);
Eric Anholt62fdfea2010-05-21 13:26:39 -07001360
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001361 if (I915_NEED_GFX_HWS(dev)) {
Chris Wilson78501ea2010-10-27 12:18:21 +01001362 ret = init_status_page(ring);
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001363 if (ret)
1364 return ret;
Chris Wilson6b8294a2012-11-16 11:43:20 +00001365 } else {
1366 BUG_ON(ring->id != RCS);
Daniel Vetter035dc1e2013-07-03 12:56:54 +02001367 ret = init_phys_status_page(ring);
Chris Wilson6b8294a2012-11-16 11:43:20 +00001368 if (ret)
1369 return ret;
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001370 }
Eric Anholt62fdfea2010-05-21 13:26:39 -07001371
Chris Wilsonebc052e2012-11-15 11:32:28 +00001372 obj = NULL;
1373 if (!HAS_LLC(dev))
1374 obj = i915_gem_object_create_stolen(dev, ring->size);
1375 if (obj == NULL)
1376 obj = i915_gem_alloc_object(dev, ring->size);
Eric Anholt62fdfea2010-05-21 13:26:39 -07001377 if (obj == NULL) {
1378 DRM_ERROR("Failed to allocate ringbuffer\n");
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001379 ret = -ENOMEM;
Chris Wilsondd785e32010-08-07 11:01:34 +01001380 goto err_hws;
Eric Anholt62fdfea2010-05-21 13:26:39 -07001381 }
Eric Anholt62fdfea2010-05-21 13:26:39 -07001382
Chris Wilson05394f32010-11-08 19:18:58 +00001383 ring->obj = obj;
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001384
Daniel Vetter1ec9e262014-02-14 14:01:11 +01001385 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
Chris Wilsondd785e32010-08-07 11:01:34 +01001386 if (ret)
1387 goto err_unref;
Eric Anholt62fdfea2010-05-21 13:26:39 -07001388
Chris Wilson3eef8912012-06-04 17:05:40 +01001389 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1390 if (ret)
1391 goto err_unpin;
1392
Daniel Vetterdd2757f2012-06-07 15:55:57 +02001393 ring->virtual_start =
Ben Widawskyf343c5f2013-07-05 14:41:04 -07001394 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
Daniel Vetterdd2757f2012-06-07 15:55:57 +02001395 ring->size);
Daniel Vetter4225d0f2012-04-26 23:28:16 +02001396 if (ring->virtual_start == NULL) {
Eric Anholt62fdfea2010-05-21 13:26:39 -07001397 DRM_ERROR("Failed to map ringbuffer.\n");
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001398 ret = -EINVAL;
Chris Wilsondd785e32010-08-07 11:01:34 +01001399 goto err_unpin;
Eric Anholt62fdfea2010-05-21 13:26:39 -07001400 }
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001401
Chris Wilson78501ea2010-10-27 12:18:21 +01001402 ret = ring->init(ring);
Chris Wilsondd785e32010-08-07 11:01:34 +01001403 if (ret)
1404 goto err_unmap;
Eric Anholt62fdfea2010-05-21 13:26:39 -07001405
Chris Wilson55249ba2010-12-22 14:04:47 +00001406 /* Workaround an erratum on the i830 which causes a hang if
1407 * the TAIL pointer points to within the last 2 cachelines
1408 * of the buffer.
1409 */
1410 ring->effective_size = ring->size;
Chris Wilson27c1cbd2012-04-09 13:59:46 +01001411 if (IS_I830(ring->dev) || IS_845G(ring->dev))
Chris Wilson55249ba2010-12-22 14:04:47 +00001412 ring->effective_size -= 128;
1413
Brad Volkin351e3db2014-02-18 10:15:46 -08001414 i915_cmd_parser_init_ring(ring);
1415
Chris Wilsonc584fe42010-10-29 18:15:52 +01001416 return 0;
Chris Wilsondd785e32010-08-07 11:01:34 +01001417
1418err_unmap:
Daniel Vetter4225d0f2012-04-26 23:28:16 +02001419 iounmap(ring->virtual_start);
Chris Wilsondd785e32010-08-07 11:01:34 +01001420err_unpin:
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08001421 i915_gem_object_ggtt_unpin(obj);
Chris Wilsondd785e32010-08-07 11:01:34 +01001422err_unref:
Chris Wilson05394f32010-11-08 19:18:58 +00001423 drm_gem_object_unreference(&obj->base);
1424 ring->obj = NULL;
Chris Wilsondd785e32010-08-07 11:01:34 +01001425err_hws:
Chris Wilson78501ea2010-10-27 12:18:21 +01001426 cleanup_status_page(ring);
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001427 return ret;
Eric Anholt62fdfea2010-05-21 13:26:39 -07001428}
1429
Chris Wilson78501ea2010-10-27 12:18:21 +01001430void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
Eric Anholt62fdfea2010-05-21 13:26:39 -07001431{
Chris Wilson33626e62010-10-29 16:18:36 +01001432 struct drm_i915_private *dev_priv;
1433 int ret;
1434
Chris Wilson05394f32010-11-08 19:18:58 +00001435 if (ring->obj == NULL)
Eric Anholt62fdfea2010-05-21 13:26:39 -07001436 return;
1437
Chris Wilson33626e62010-10-29 16:18:36 +01001438 /* Disable the ring buffer. The ring must be idle at this point */
1439 dev_priv = ring->dev->dev_private;
Chris Wilson3e960502012-11-27 16:22:54 +00001440 ret = intel_ring_idle(ring);
Ben Widawsky3d57e5b2013-10-14 10:01:36 -07001441 if (ret && !i915_reset_in_progress(&dev_priv->gpu_error))
Chris Wilson29ee3992011-01-24 16:35:42 +00001442 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1443 ring->name, ret);
1444
Chris Wilson33626e62010-10-29 16:18:36 +01001445 I915_WRITE_CTL(ring, 0);
1446
Daniel Vetter4225d0f2012-04-26 23:28:16 +02001447 iounmap(ring->virtual_start);
Eric Anholt62fdfea2010-05-21 13:26:39 -07001448
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08001449 i915_gem_object_ggtt_unpin(ring->obj);
Chris Wilson05394f32010-11-08 19:18:58 +00001450 drm_gem_object_unreference(&ring->obj->base);
1451 ring->obj = NULL;
Ben Widawsky3d57e5b2013-10-14 10:01:36 -07001452 ring->preallocated_lazy_request = NULL;
1453 ring->outstanding_lazy_seqno = 0;
Chris Wilson78501ea2010-10-27 12:18:21 +01001454
Zou Nan hai8d192152010-11-02 16:31:01 +08001455 if (ring->cleanup)
1456 ring->cleanup(ring);
1457
Chris Wilson78501ea2010-10-27 12:18:21 +01001458 cleanup_status_page(ring);
Eric Anholt62fdfea2010-05-21 13:26:39 -07001459}
1460
Chris Wilsona71d8d92012-02-15 11:25:36 +00001461static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1462{
1463 struct drm_i915_gem_request *request;
Chris Wilson1f709992014-01-27 22:43:07 +00001464 u32 seqno = 0, tail;
Chris Wilsona71d8d92012-02-15 11:25:36 +00001465 int ret;
1466
Chris Wilsona71d8d92012-02-15 11:25:36 +00001467 if (ring->last_retired_head != -1) {
1468 ring->head = ring->last_retired_head;
1469 ring->last_retired_head = -1;
Chris Wilson1f709992014-01-27 22:43:07 +00001470
Chris Wilsona71d8d92012-02-15 11:25:36 +00001471 ring->space = ring_space(ring);
1472 if (ring->space >= n)
1473 return 0;
1474 }
1475
1476 list_for_each_entry(request, &ring->request_list, list) {
1477 int space;
1478
1479 if (request->tail == -1)
1480 continue;
1481
Ville Syrjälä633cf8f2012-12-03 18:43:32 +02001482 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
Chris Wilsona71d8d92012-02-15 11:25:36 +00001483 if (space < 0)
1484 space += ring->size;
1485 if (space >= n) {
1486 seqno = request->seqno;
Chris Wilson1f709992014-01-27 22:43:07 +00001487 tail = request->tail;
Chris Wilsona71d8d92012-02-15 11:25:36 +00001488 break;
1489 }
1490
1491 /* Consume this request in case we need more space than
1492 * is available and so need to prevent a race between
1493 * updating last_retired_head and direct reads of
1494 * I915_RING_HEAD. It also provides a nice sanity check.
1495 */
1496 request->tail = -1;
1497 }
1498
1499 if (seqno == 0)
1500 return -ENOSPC;
1501
Chris Wilson1f709992014-01-27 22:43:07 +00001502 ret = i915_wait_seqno(ring, seqno);
Chris Wilsona71d8d92012-02-15 11:25:36 +00001503 if (ret)
1504 return ret;
1505
Chris Wilson1f709992014-01-27 22:43:07 +00001506 ring->head = tail;
Chris Wilsona71d8d92012-02-15 11:25:36 +00001507 ring->space = ring_space(ring);
1508 if (WARN_ON(ring->space < n))
1509 return -ENOSPC;
1510
1511 return 0;
1512}
1513
Chris Wilson3e960502012-11-27 16:22:54 +00001514static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
Eric Anholt62fdfea2010-05-21 13:26:39 -07001515{
Chris Wilson78501ea2010-10-27 12:18:21 +01001516 struct drm_device *dev = ring->dev;
Zou Nan haicae58522010-11-09 17:17:32 +08001517 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson78501ea2010-10-27 12:18:21 +01001518 unsigned long end;
Chris Wilsona71d8d92012-02-15 11:25:36 +00001519 int ret;
Chris Wilsonc7dca472011-01-20 17:00:10 +00001520
Chris Wilsona71d8d92012-02-15 11:25:36 +00001521 ret = intel_ring_wait_request(ring, n);
1522 if (ret != -ENOSPC)
1523 return ret;
1524
Chris Wilson09246732013-08-10 22:16:32 +01001525 /* force the tail write in case we have been skipping them */
1526 __intel_ring_advance(ring);
1527
Chris Wilsondb53a302011-02-03 11:57:46 +00001528 trace_i915_ring_wait_begin(ring);
Daniel Vetter63ed2cb2012-04-23 16:50:50 +02001529 /* With GEM the hangcheck timer should kick us out of the loop,
1530 * leaving it early runs the risk of corrupting GEM state (due
1531 * to running on almost untested codepaths). But on resume
1532 * timers don't work yet, so prevent a complete hang in that
1533 * case by choosing an insanely large timeout. */
1534 end = jiffies + 60 * HZ;
Daniel Vettere6bfaf82011-12-14 13:56:59 +01001535
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001536 do {
Chris Wilsonc7dca472011-01-20 17:00:10 +00001537 ring->head = I915_READ_HEAD(ring);
1538 ring->space = ring_space(ring);
Eric Anholt62fdfea2010-05-21 13:26:39 -07001539 if (ring->space >= n) {
Chris Wilsondb53a302011-02-03 11:57:46 +00001540 trace_i915_ring_wait_end(ring);
Eric Anholt62fdfea2010-05-21 13:26:39 -07001541 return 0;
1542 }
1543
Daniel Vetterfb19e2a2014-02-12 23:44:34 +01001544 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1545 dev->primary->master) {
Eric Anholt62fdfea2010-05-21 13:26:39 -07001546 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1547 if (master_priv->sarea_priv)
1548 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1549 }
Zou Nan haid1b851f2010-05-21 09:08:57 +08001550
Chris Wilsone60a0b12010-10-13 10:09:14 +01001551 msleep(1);
Daniel Vetterd6b2c792012-07-04 22:54:13 +02001552
Daniel Vetter33196de2012-11-14 17:14:05 +01001553 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1554 dev_priv->mm.interruptible);
Daniel Vetterd6b2c792012-07-04 22:54:13 +02001555 if (ret)
1556 return ret;
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001557 } while (!time_after(jiffies, end));
Chris Wilsondb53a302011-02-03 11:57:46 +00001558 trace_i915_ring_wait_end(ring);
Eric Anholt62fdfea2010-05-21 13:26:39 -07001559 return -EBUSY;
1560}
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001561
Chris Wilson3e960502012-11-27 16:22:54 +00001562static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1563{
1564 uint32_t __iomem *virt;
1565 int rem = ring->size - ring->tail;
1566
1567 if (ring->space < rem) {
1568 int ret = ring_wait_for_space(ring, rem);
1569 if (ret)
1570 return ret;
1571 }
1572
1573 virt = ring->virtual_start + ring->tail;
1574 rem /= 4;
1575 while (rem--)
1576 iowrite32(MI_NOOP, virt++);
1577
1578 ring->tail = 0;
1579 ring->space = ring_space(ring);
1580
1581 return 0;
1582}
1583
1584int intel_ring_idle(struct intel_ring_buffer *ring)
1585{
1586 u32 seqno;
1587 int ret;
1588
1589 /* We need to add any requests required to flush the objects and ring */
Chris Wilson18235212013-09-04 10:45:51 +01001590 if (ring->outstanding_lazy_seqno) {
Mika Kuoppala0025c072013-06-12 12:35:30 +03001591 ret = i915_add_request(ring, NULL);
Chris Wilson3e960502012-11-27 16:22:54 +00001592 if (ret)
1593 return ret;
1594 }
1595
1596 /* Wait upon the last request to be completed */
1597 if (list_empty(&ring->request_list))
1598 return 0;
1599
1600 seqno = list_entry(ring->request_list.prev,
1601 struct drm_i915_gem_request,
1602 list)->seqno;
1603
1604 return i915_wait_seqno(ring, seqno);
1605}
1606
Chris Wilson9d7730912012-11-27 16:22:52 +00001607static int
1608intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1609{
Chris Wilson18235212013-09-04 10:45:51 +01001610 if (ring->outstanding_lazy_seqno)
Chris Wilson9d7730912012-11-27 16:22:52 +00001611 return 0;
1612
Chris Wilson3c0e2342013-09-04 10:45:52 +01001613 if (ring->preallocated_lazy_request == NULL) {
1614 struct drm_i915_gem_request *request;
1615
1616 request = kmalloc(sizeof(*request), GFP_KERNEL);
1617 if (request == NULL)
1618 return -ENOMEM;
1619
1620 ring->preallocated_lazy_request = request;
1621 }
1622
Chris Wilson18235212013-09-04 10:45:51 +01001623 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
Chris Wilson9d7730912012-11-27 16:22:52 +00001624}
1625
Chris Wilson304d6952014-01-02 14:32:35 +00001626static int __intel_ring_prepare(struct intel_ring_buffer *ring,
1627 int bytes)
Mika Kuoppalacbcc80d2012-12-04 15:12:03 +02001628{
1629 int ret;
1630
1631 if (unlikely(ring->tail + bytes > ring->effective_size)) {
1632 ret = intel_wrap_ring_buffer(ring);
1633 if (unlikely(ret))
1634 return ret;
1635 }
1636
1637 if (unlikely(ring->space < bytes)) {
1638 ret = ring_wait_for_space(ring, bytes);
1639 if (unlikely(ret))
1640 return ret;
1641 }
1642
Mika Kuoppalacbcc80d2012-12-04 15:12:03 +02001643 return 0;
1644}
1645
Chris Wilsone1f99ce2010-10-27 12:45:26 +01001646int intel_ring_begin(struct intel_ring_buffer *ring,
1647 int num_dwords)
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001648{
Jani Nikula4640c4f2014-03-31 14:27:19 +03001649 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01001650 int ret;
Chris Wilson78501ea2010-10-27 12:18:21 +01001651
Daniel Vetter33196de2012-11-14 17:14:05 +01001652 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1653 dev_priv->mm.interruptible);
Daniel Vetterde2b9982012-07-04 22:52:50 +02001654 if (ret)
1655 return ret;
Chris Wilson21dd3732011-01-26 15:55:56 +00001656
Chris Wilson304d6952014-01-02 14:32:35 +00001657 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1658 if (ret)
1659 return ret;
1660
Chris Wilson9d7730912012-11-27 16:22:52 +00001661 /* Preallocate the olr before touching the ring */
1662 ret = intel_ring_alloc_seqno(ring);
1663 if (ret)
1664 return ret;
1665
Chris Wilson304d6952014-01-02 14:32:35 +00001666 ring->space -= num_dwords * sizeof(uint32_t);
1667 return 0;
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001668}
1669
Ville Syrjälä753b1ad2014-02-11 19:52:05 +02001670/* Align the ring tail to a cacheline boundary */
1671int intel_ring_cacheline_align(struct intel_ring_buffer *ring)
1672{
1673 int num_dwords = (64 - (ring->tail & 63)) / sizeof(uint32_t);
1674 int ret;
1675
1676 if (num_dwords == 0)
1677 return 0;
1678
1679 ret = intel_ring_begin(ring, num_dwords);
1680 if (ret)
1681 return ret;
1682
1683 while (num_dwords--)
1684 intel_ring_emit(ring, MI_NOOP);
1685
1686 intel_ring_advance(ring);
1687
1688 return 0;
1689}
1690
Mika Kuoppalaf7e98ad2012-12-19 11:13:06 +02001691void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
Mika Kuoppala498d2ac2012-12-04 15:12:04 +02001692{
Mika Kuoppalaf7e98ad2012-12-19 11:13:06 +02001693 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Mika Kuoppala498d2ac2012-12-04 15:12:04 +02001694
Chris Wilson18235212013-09-04 10:45:51 +01001695 BUG_ON(ring->outstanding_lazy_seqno);
Mika Kuoppala498d2ac2012-12-04 15:12:04 +02001696
Mika Kuoppalaf7e98ad2012-12-19 11:13:06 +02001697 if (INTEL_INFO(ring->dev)->gen >= 6) {
1698 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1699 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
Ben Widawsky50201502013-08-12 16:53:03 -07001700 if (HAS_VEBOX(ring->dev))
1701 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
Chris Wilson78501ea2010-10-27 12:18:21 +01001702 }
Chris Wilson297b0c52010-10-22 17:02:41 +01001703
Mika Kuoppalaf7e98ad2012-12-19 11:13:06 +02001704 ring->set_seqno(ring, seqno);
Mika Kuoppala92cab732013-05-24 17:16:07 +03001705 ring->hangcheck.seqno = seqno;
Chris Wilson549f7362010-10-19 11:19:32 +01001706}
1707
Chris Wilsonab6f8e32010-09-19 17:53:44 +01001708static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1709 u32 value)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001710{
Jani Nikula4640c4f2014-03-31 14:27:19 +03001711 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001712
1713 /* Every tail move must follow the sequence below */
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001714
Chris Wilson12f55812012-07-05 17:14:01 +01001715 /* Disable notification that the ring is IDLE. The GT
1716 * will then assume that it is busy and bring it out of rc6.
1717 */
1718 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1719 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1720
1721 /* Clear the context id. Here be magic! */
1722 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1723
1724 /* Wait for the ring not to be idle, i.e. for it to wake up. */
Akshay Joshi0206e352011-08-16 15:34:10 -04001725 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
Chris Wilson12f55812012-07-05 17:14:01 +01001726 GEN6_BSD_SLEEP_INDICATOR) == 0,
1727 50))
1728 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001729
Chris Wilson12f55812012-07-05 17:14:01 +01001730 /* Now that the ring is fully powered up, update the tail */
Akshay Joshi0206e352011-08-16 15:34:10 -04001731 I915_WRITE_TAIL(ring, value);
Chris Wilson12f55812012-07-05 17:14:01 +01001732 POSTING_READ(RING_TAIL(ring->mmio_base));
1733
1734 /* Let the ring send IDLE messages to the GT again,
1735 * and so let it sleep to conserve power when idle.
1736 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001737 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
Chris Wilson12f55812012-07-05 17:14:01 +01001738 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001739}
1740
Ben Widawskyea251322013-05-28 19:22:21 -07001741static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1742 u32 invalidate, u32 flush)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001743{
Chris Wilson71a77e02011-02-02 12:13:49 +00001744 uint32_t cmd;
Chris Wilsonb72f3ac2011-01-04 17:34:02 +00001745 int ret;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001746
Chris Wilsonb72f3ac2011-01-04 17:34:02 +00001747 ret = intel_ring_begin(ring, 4);
1748 if (ret)
1749 return ret;
1750
Chris Wilson71a77e02011-02-02 12:13:49 +00001751 cmd = MI_FLUSH_DW;
Ben Widawsky075b3bb2013-11-02 21:07:13 -07001752 if (INTEL_INFO(ring->dev)->gen >= 8)
1753 cmd += 1;
Jesse Barnes9a289772012-10-26 09:42:42 -07001754 /*
1755 * Bspec vol 1c.5 - video engine command streamer:
1756 * "If ENABLED, all TLBs will be invalidated once the flush
1757 * operation is complete. This bit is only valid when the
1758 * Post-Sync Operation field is a value of 1h or 3h."
1759 */
Chris Wilson71a77e02011-02-02 12:13:49 +00001760 if (invalidate & I915_GEM_GPU_DOMAINS)
Jesse Barnes9a289772012-10-26 09:42:42 -07001761 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1762 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
Chris Wilson71a77e02011-02-02 12:13:49 +00001763 intel_ring_emit(ring, cmd);
Jesse Barnes9a289772012-10-26 09:42:42 -07001764 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
Ben Widawsky075b3bb2013-11-02 21:07:13 -07001765 if (INTEL_INFO(ring->dev)->gen >= 8) {
1766 intel_ring_emit(ring, 0); /* upper addr */
1767 intel_ring_emit(ring, 0); /* value */
1768 } else {
1769 intel_ring_emit(ring, 0);
1770 intel_ring_emit(ring, MI_NOOP);
1771 }
Chris Wilsonb72f3ac2011-01-04 17:34:02 +00001772 intel_ring_advance(ring);
1773 return 0;
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001774}
1775
1776static int
Ben Widawsky1c7a0622013-11-02 21:07:12 -07001777gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1778 u32 offset, u32 len,
1779 unsigned flags)
1780{
Ben Widawsky28cf5412013-11-02 21:07:26 -07001781 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1782 bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
1783 !(flags & I915_DISPATCH_SECURE);
Ben Widawsky1c7a0622013-11-02 21:07:12 -07001784 int ret;
1785
1786 ret = intel_ring_begin(ring, 4);
1787 if (ret)
1788 return ret;
1789
1790 /* FIXME(BDW): Address space and security selectors. */
Ben Widawsky28cf5412013-11-02 21:07:26 -07001791 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
Ben Widawsky1c7a0622013-11-02 21:07:12 -07001792 intel_ring_emit(ring, offset);
1793 intel_ring_emit(ring, 0);
1794 intel_ring_emit(ring, MI_NOOP);
1795 intel_ring_advance(ring);
1796
1797 return 0;
1798}
1799
1800static int
Chris Wilsond7d4eed2012-10-17 12:09:54 +01001801hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1802 u32 offset, u32 len,
1803 unsigned flags)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001804{
Akshay Joshi0206e352011-08-16 15:34:10 -04001805 int ret;
Chris Wilsonab6f8e32010-09-19 17:53:44 +01001806
Akshay Joshi0206e352011-08-16 15:34:10 -04001807 ret = intel_ring_begin(ring, 2);
1808 if (ret)
1809 return ret;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01001810
Chris Wilsond7d4eed2012-10-17 12:09:54 +01001811 intel_ring_emit(ring,
1812 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1813 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1814 /* bit0-7 is the length on GEN6+ */
1815 intel_ring_emit(ring, offset);
1816 intel_ring_advance(ring);
1817
1818 return 0;
1819}
1820
1821static int
1822gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1823 u32 offset, u32 len,
1824 unsigned flags)
1825{
1826 int ret;
1827
1828 ret = intel_ring_begin(ring, 2);
1829 if (ret)
1830 return ret;
1831
1832 intel_ring_emit(ring,
1833 MI_BATCH_BUFFER_START |
1834 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
Akshay Joshi0206e352011-08-16 15:34:10 -04001835 /* bit0-7 is the length on GEN6+ */
1836 intel_ring_emit(ring, offset);
1837 intel_ring_advance(ring);
Chris Wilsonab6f8e32010-09-19 17:53:44 +01001838
Akshay Joshi0206e352011-08-16 15:34:10 -04001839 return 0;
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001840}
1841
Chris Wilson549f7362010-10-19 11:19:32 +01001842/* Blitter support (SandyBridge+) */
1843
Ben Widawskyea251322013-05-28 19:22:21 -07001844static int gen6_ring_flush(struct intel_ring_buffer *ring,
1845 u32 invalidate, u32 flush)
Zou Nan hai8d192152010-11-02 16:31:01 +08001846{
Rodrigo Vivifd3da6c2013-06-06 16:58:16 -03001847 struct drm_device *dev = ring->dev;
Chris Wilson71a77e02011-02-02 12:13:49 +00001848 uint32_t cmd;
Chris Wilsonb72f3ac2011-01-04 17:34:02 +00001849 int ret;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001850
Daniel Vetter6a233c72011-12-14 13:57:07 +01001851 ret = intel_ring_begin(ring, 4);
Chris Wilsonb72f3ac2011-01-04 17:34:02 +00001852 if (ret)
1853 return ret;
1854
Chris Wilson71a77e02011-02-02 12:13:49 +00001855 cmd = MI_FLUSH_DW;
Ben Widawsky075b3bb2013-11-02 21:07:13 -07001856 if (INTEL_INFO(ring->dev)->gen >= 8)
1857 cmd += 1;
Jesse Barnes9a289772012-10-26 09:42:42 -07001858 /*
1859 * Bspec vol 1c.3 - blitter engine command streamer:
1860 * "If ENABLED, all TLBs will be invalidated once the flush
1861 * operation is complete. This bit is only valid when the
1862 * Post-Sync Operation field is a value of 1h or 3h."
1863 */
Chris Wilson71a77e02011-02-02 12:13:49 +00001864 if (invalidate & I915_GEM_DOMAIN_RENDER)
Jesse Barnes9a289772012-10-26 09:42:42 -07001865 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
Daniel Vetterb3fcabb2012-11-04 12:24:47 +01001866 MI_FLUSH_DW_OP_STOREDW;
Chris Wilson71a77e02011-02-02 12:13:49 +00001867 intel_ring_emit(ring, cmd);
Jesse Barnes9a289772012-10-26 09:42:42 -07001868 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
Ben Widawsky075b3bb2013-11-02 21:07:13 -07001869 if (INTEL_INFO(ring->dev)->gen >= 8) {
1870 intel_ring_emit(ring, 0); /* upper addr */
1871 intel_ring_emit(ring, 0); /* value */
1872 } else {
1873 intel_ring_emit(ring, 0);
1874 intel_ring_emit(ring, MI_NOOP);
1875 }
Chris Wilsonb72f3ac2011-01-04 17:34:02 +00001876 intel_ring_advance(ring);
Rodrigo Vivifd3da6c2013-06-06 16:58:16 -03001877
Ville Syrjälä9688eca2013-11-06 23:02:19 +02001878 if (IS_GEN7(dev) && !invalidate && flush)
Rodrigo Vivifd3da6c2013-06-06 16:58:16 -03001879 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1880
Chris Wilsonb72f3ac2011-01-04 17:34:02 +00001881 return 0;
Zou Nan hai8d192152010-11-02 16:31:01 +08001882}
1883
Xiang, Haihao5c1143b2010-09-16 10:43:11 +08001884int intel_init_render_ring_buffer(struct drm_device *dev)
1885{
Jani Nikula4640c4f2014-03-31 14:27:19 +03001886 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001887 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Xiang, Haihao5c1143b2010-09-16 10:43:11 +08001888
Daniel Vetter59465b52012-04-11 22:12:48 +02001889 ring->name = "render ring";
1890 ring->id = RCS;
1891 ring->mmio_base = RENDER_RING_BASE;
1892
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001893 if (INTEL_INFO(dev)->gen >= 6) {
1894 ring->add_request = gen6_add_request;
Paulo Zanoni4772eae2012-08-17 18:35:41 -03001895 ring->flush = gen7_render_ring_flush;
Chris Wilson6c6cf5a2012-07-20 18:02:28 +01001896 if (INTEL_INFO(dev)->gen == 6)
Paulo Zanonib3111502012-08-17 18:35:42 -03001897 ring->flush = gen6_render_ring_flush;
Ben Widawskyabd58f02013-11-02 21:07:09 -07001898 if (INTEL_INFO(dev)->gen >= 8) {
Ben Widawskya5f3d682013-11-02 21:07:27 -07001899 ring->flush = gen8_render_ring_flush;
Ben Widawskyabd58f02013-11-02 21:07:09 -07001900 ring->irq_get = gen8_ring_get_irq;
1901 ring->irq_put = gen8_ring_put_irq;
1902 } else {
1903 ring->irq_get = gen6_ring_get_irq;
1904 ring->irq_put = gen6_ring_put_irq;
1905 }
Ben Widawskycc609d52013-05-28 19:22:29 -07001906 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
Daniel Vetter4cd53c02012-12-14 16:01:25 +01001907 ring->get_seqno = gen6_ring_get_seqno;
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +02001908 ring->set_seqno = ring_set_seqno;
Daniel Vetter686cb5f2012-04-11 22:12:52 +02001909 ring->sync_to = gen6_ring_sync;
Ben Widawsky55861812013-05-28 19:22:17 -07001910 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1911 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1912 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
Ben Widawsky1950de12013-05-28 19:22:20 -07001913 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
Ben Widawskyad776f82013-05-28 19:22:18 -07001914 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1915 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1916 ring->signal_mbox[BCS] = GEN6_BRSYNC;
Ben Widawsky1950de12013-05-28 19:22:20 -07001917 ring->signal_mbox[VECS] = GEN6_VERSYNC;
Chris Wilsonc6df5412010-12-15 09:56:50 +00001918 } else if (IS_GEN5(dev)) {
1919 ring->add_request = pc_render_add_request;
Chris Wilson46f0f8d2012-04-18 11:12:11 +01001920 ring->flush = gen4_render_ring_flush;
Chris Wilsonc6df5412010-12-15 09:56:50 +00001921 ring->get_seqno = pc_render_get_seqno;
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +02001922 ring->set_seqno = pc_render_set_seqno;
Daniel Vettere48d8632012-04-11 22:12:54 +02001923 ring->irq_get = gen5_ring_get_irq;
1924 ring->irq_put = gen5_ring_put_irq;
Ben Widawskycc609d52013-05-28 19:22:29 -07001925 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1926 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
Daniel Vetter59465b52012-04-11 22:12:48 +02001927 } else {
Daniel Vetter8620a3a2012-04-11 22:12:57 +02001928 ring->add_request = i9xx_add_request;
Chris Wilson46f0f8d2012-04-18 11:12:11 +01001929 if (INTEL_INFO(dev)->gen < 4)
1930 ring->flush = gen2_render_ring_flush;
1931 else
1932 ring->flush = gen4_render_ring_flush;
Daniel Vetter59465b52012-04-11 22:12:48 +02001933 ring->get_seqno = ring_get_seqno;
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +02001934 ring->set_seqno = ring_set_seqno;
Chris Wilsonc2798b12012-04-22 21:13:57 +01001935 if (IS_GEN2(dev)) {
1936 ring->irq_get = i8xx_ring_get_irq;
1937 ring->irq_put = i8xx_ring_put_irq;
1938 } else {
1939 ring->irq_get = i9xx_ring_get_irq;
1940 ring->irq_put = i9xx_ring_put_irq;
1941 }
Daniel Vettere3670312012-04-11 22:12:53 +02001942 ring->irq_enable_mask = I915_USER_INTERRUPT;
Xiang, Haihao5c1143b2010-09-16 10:43:11 +08001943 }
Daniel Vetter59465b52012-04-11 22:12:48 +02001944 ring->write_tail = ring_write_tail;
Chris Wilsond7d4eed2012-10-17 12:09:54 +01001945 if (IS_HASWELL(dev))
1946 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
Ben Widawsky1c7a0622013-11-02 21:07:12 -07001947 else if (IS_GEN8(dev))
1948 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
Chris Wilsond7d4eed2012-10-17 12:09:54 +01001949 else if (INTEL_INFO(dev)->gen >= 6)
Daniel Vetterfb3256d2012-04-11 22:12:56 +02001950 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1951 else if (INTEL_INFO(dev)->gen >= 4)
1952 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1953 else if (IS_I830(dev) || IS_845G(dev))
1954 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1955 else
1956 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
Daniel Vetter59465b52012-04-11 22:12:48 +02001957 ring->init = init_render_ring;
1958 ring->cleanup = render_ring_cleanup;
1959
Daniel Vetterb45305f2012-12-17 16:21:27 +01001960 /* Workaround batchbuffer to combat CS tlb bug. */
1961 if (HAS_BROKEN_CS_TLB(dev)) {
1962 struct drm_i915_gem_object *obj;
1963 int ret;
1964
1965 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1966 if (obj == NULL) {
1967 DRM_ERROR("Failed to allocate batch bo\n");
1968 return -ENOMEM;
1969 }
1970
Daniel Vetterbe1fa122014-02-14 14:01:14 +01001971 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
Daniel Vetterb45305f2012-12-17 16:21:27 +01001972 if (ret != 0) {
1973 drm_gem_object_unreference(&obj->base);
1974 DRM_ERROR("Failed to ping batch bo\n");
1975 return ret;
1976 }
1977
Chris Wilson0d1aaca2013-08-26 20:58:11 +01001978 ring->scratch.obj = obj;
1979 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
Daniel Vetterb45305f2012-12-17 16:21:27 +01001980 }
1981
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001982 return intel_init_ring_buffer(dev, ring);
Xiang, Haihao5c1143b2010-09-16 10:43:11 +08001983}
1984
Chris Wilsone8616b62011-01-20 09:57:11 +00001985int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1986{
Jani Nikula4640c4f2014-03-31 14:27:19 +03001987 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone8616b62011-01-20 09:57:11 +00001988 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Chris Wilson6b8294a2012-11-16 11:43:20 +00001989 int ret;
Chris Wilsone8616b62011-01-20 09:57:11 +00001990
Daniel Vetter59465b52012-04-11 22:12:48 +02001991 ring->name = "render ring";
1992 ring->id = RCS;
1993 ring->mmio_base = RENDER_RING_BASE;
1994
Chris Wilsone8616b62011-01-20 09:57:11 +00001995 if (INTEL_INFO(dev)->gen >= 6) {
Daniel Vetterb4178f82012-04-11 22:12:51 +02001996 /* non-kms not supported on gen6+ */
1997 return -ENODEV;
Chris Wilsone8616b62011-01-20 09:57:11 +00001998 }
Daniel Vetter28f0cbf2012-04-11 22:12:58 +02001999
2000 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2001 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2002 * the special gen5 functions. */
2003 ring->add_request = i9xx_add_request;
Chris Wilson46f0f8d2012-04-18 11:12:11 +01002004 if (INTEL_INFO(dev)->gen < 4)
2005 ring->flush = gen2_render_ring_flush;
2006 else
2007 ring->flush = gen4_render_ring_flush;
Daniel Vetter28f0cbf2012-04-11 22:12:58 +02002008 ring->get_seqno = ring_get_seqno;
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +02002009 ring->set_seqno = ring_set_seqno;
Chris Wilsonc2798b12012-04-22 21:13:57 +01002010 if (IS_GEN2(dev)) {
2011 ring->irq_get = i8xx_ring_get_irq;
2012 ring->irq_put = i8xx_ring_put_irq;
2013 } else {
2014 ring->irq_get = i9xx_ring_get_irq;
2015 ring->irq_put = i9xx_ring_put_irq;
2016 }
Daniel Vetter28f0cbf2012-04-11 22:12:58 +02002017 ring->irq_enable_mask = I915_USER_INTERRUPT;
Daniel Vetter59465b52012-04-11 22:12:48 +02002018 ring->write_tail = ring_write_tail;
Daniel Vetterfb3256d2012-04-11 22:12:56 +02002019 if (INTEL_INFO(dev)->gen >= 4)
2020 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2021 else if (IS_I830(dev) || IS_845G(dev))
2022 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2023 else
2024 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
Daniel Vetter59465b52012-04-11 22:12:48 +02002025 ring->init = init_render_ring;
2026 ring->cleanup = render_ring_cleanup;
Chris Wilsone8616b62011-01-20 09:57:11 +00002027
2028 ring->dev = dev;
2029 INIT_LIST_HEAD(&ring->active_list);
2030 INIT_LIST_HEAD(&ring->request_list);
Chris Wilsone8616b62011-01-20 09:57:11 +00002031
2032 ring->size = size;
2033 ring->effective_size = ring->size;
Mika Kuoppala17f10fd2012-10-29 16:59:26 +02002034 if (IS_I830(ring->dev) || IS_845G(ring->dev))
Chris Wilsone8616b62011-01-20 09:57:11 +00002035 ring->effective_size -= 128;
2036
Daniel Vetter4225d0f2012-04-26 23:28:16 +02002037 ring->virtual_start = ioremap_wc(start, size);
2038 if (ring->virtual_start == NULL) {
Chris Wilsone8616b62011-01-20 09:57:11 +00002039 DRM_ERROR("can not ioremap virtual address for"
2040 " ring buffer\n");
2041 return -ENOMEM;
2042 }
2043
Chris Wilson6b8294a2012-11-16 11:43:20 +00002044 if (!I915_NEED_GFX_HWS(dev)) {
Daniel Vetter035dc1e2013-07-03 12:56:54 +02002045 ret = init_phys_status_page(ring);
Chris Wilson6b8294a2012-11-16 11:43:20 +00002046 if (ret)
2047 return ret;
2048 }
2049
Chris Wilsone8616b62011-01-20 09:57:11 +00002050 return 0;
2051}
2052
Xiang, Haihao5c1143b2010-09-16 10:43:11 +08002053int intel_init_bsd_ring_buffer(struct drm_device *dev)
2054{
Jani Nikula4640c4f2014-03-31 14:27:19 +03002055 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002056 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
Xiang, Haihao5c1143b2010-09-16 10:43:11 +08002057
Daniel Vetter58fa3832012-04-11 22:12:49 +02002058 ring->name = "bsd ring";
2059 ring->id = VCS;
2060
Daniel Vetter0fd2c202012-04-11 22:12:55 +02002061 ring->write_tail = ring_write_tail;
Ben Widawsky780f18c2013-11-02 21:07:28 -07002062 if (INTEL_INFO(dev)->gen >= 6) {
Daniel Vetter58fa3832012-04-11 22:12:49 +02002063 ring->mmio_base = GEN6_BSD_RING_BASE;
Daniel Vetter0fd2c202012-04-11 22:12:55 +02002064 /* gen6 bsd needs a special wa for tail updates */
2065 if (IS_GEN6(dev))
2066 ring->write_tail = gen6_bsd_ring_write_tail;
Ben Widawskyea251322013-05-28 19:22:21 -07002067 ring->flush = gen6_bsd_ring_flush;
Daniel Vetter58fa3832012-04-11 22:12:49 +02002068 ring->add_request = gen6_add_request;
2069 ring->get_seqno = gen6_ring_get_seqno;
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +02002070 ring->set_seqno = ring_set_seqno;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002071 if (INTEL_INFO(dev)->gen >= 8) {
2072 ring->irq_enable_mask =
2073 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2074 ring->irq_get = gen8_ring_get_irq;
2075 ring->irq_put = gen8_ring_put_irq;
Ben Widawsky1c7a0622013-11-02 21:07:12 -07002076 ring->dispatch_execbuffer =
2077 gen8_ring_dispatch_execbuffer;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002078 } else {
2079 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2080 ring->irq_get = gen6_ring_get_irq;
2081 ring->irq_put = gen6_ring_put_irq;
Ben Widawsky1c7a0622013-11-02 21:07:12 -07002082 ring->dispatch_execbuffer =
2083 gen6_ring_dispatch_execbuffer;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002084 }
Daniel Vetter686cb5f2012-04-11 22:12:52 +02002085 ring->sync_to = gen6_ring_sync;
Ben Widawsky55861812013-05-28 19:22:17 -07002086 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
2087 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2088 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
Ben Widawsky1950de12013-05-28 19:22:20 -07002089 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
Ben Widawskyad776f82013-05-28 19:22:18 -07002090 ring->signal_mbox[RCS] = GEN6_RVSYNC;
2091 ring->signal_mbox[VCS] = GEN6_NOSYNC;
2092 ring->signal_mbox[BCS] = GEN6_BVSYNC;
Ben Widawsky1950de12013-05-28 19:22:20 -07002093 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
Daniel Vetter58fa3832012-04-11 22:12:49 +02002094 } else {
2095 ring->mmio_base = BSD_RING_BASE;
Daniel Vetter58fa3832012-04-11 22:12:49 +02002096 ring->flush = bsd_ring_flush;
Daniel Vetter8620a3a2012-04-11 22:12:57 +02002097 ring->add_request = i9xx_add_request;
Daniel Vetter58fa3832012-04-11 22:12:49 +02002098 ring->get_seqno = ring_get_seqno;
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +02002099 ring->set_seqno = ring_set_seqno;
Daniel Vettere48d8632012-04-11 22:12:54 +02002100 if (IS_GEN5(dev)) {
Ben Widawskycc609d52013-05-28 19:22:29 -07002101 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
Daniel Vettere48d8632012-04-11 22:12:54 +02002102 ring->irq_get = gen5_ring_get_irq;
2103 ring->irq_put = gen5_ring_put_irq;
2104 } else {
Daniel Vettere3670312012-04-11 22:12:53 +02002105 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
Daniel Vettere48d8632012-04-11 22:12:54 +02002106 ring->irq_get = i9xx_ring_get_irq;
2107 ring->irq_put = i9xx_ring_put_irq;
2108 }
Daniel Vetterfb3256d2012-04-11 22:12:56 +02002109 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
Daniel Vetter58fa3832012-04-11 22:12:49 +02002110 }
2111 ring->init = init_ring_common;
2112
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002113 return intel_init_ring_buffer(dev, ring);
Xiang, Haihao5c1143b2010-09-16 10:43:11 +08002114}
Chris Wilson549f7362010-10-19 11:19:32 +01002115
2116int intel_init_blt_ring_buffer(struct drm_device *dev)
2117{
Jani Nikula4640c4f2014-03-31 14:27:19 +03002118 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002119 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
Chris Wilson549f7362010-10-19 11:19:32 +01002120
Daniel Vetter3535d9d2012-04-11 22:12:50 +02002121 ring->name = "blitter ring";
2122 ring->id = BCS;
2123
2124 ring->mmio_base = BLT_RING_BASE;
2125 ring->write_tail = ring_write_tail;
Ben Widawskyea251322013-05-28 19:22:21 -07002126 ring->flush = gen6_ring_flush;
Daniel Vetter3535d9d2012-04-11 22:12:50 +02002127 ring->add_request = gen6_add_request;
2128 ring->get_seqno = gen6_ring_get_seqno;
Mika Kuoppalab70ec5b2012-12-19 11:13:05 +02002129 ring->set_seqno = ring_set_seqno;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002130 if (INTEL_INFO(dev)->gen >= 8) {
2131 ring->irq_enable_mask =
2132 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2133 ring->irq_get = gen8_ring_get_irq;
2134 ring->irq_put = gen8_ring_put_irq;
Ben Widawsky1c7a0622013-11-02 21:07:12 -07002135 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002136 } else {
2137 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2138 ring->irq_get = gen6_ring_get_irq;
2139 ring->irq_put = gen6_ring_put_irq;
Ben Widawsky1c7a0622013-11-02 21:07:12 -07002140 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002141 }
Daniel Vetter686cb5f2012-04-11 22:12:52 +02002142 ring->sync_to = gen6_ring_sync;
Ben Widawsky55861812013-05-28 19:22:17 -07002143 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
2144 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
2145 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
Ben Widawsky1950de12013-05-28 19:22:20 -07002146 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
Ben Widawskyad776f82013-05-28 19:22:18 -07002147 ring->signal_mbox[RCS] = GEN6_RBSYNC;
2148 ring->signal_mbox[VCS] = GEN6_VBSYNC;
2149 ring->signal_mbox[BCS] = GEN6_NOSYNC;
Ben Widawsky1950de12013-05-28 19:22:20 -07002150 ring->signal_mbox[VECS] = GEN6_VEBSYNC;
Daniel Vetter3535d9d2012-04-11 22:12:50 +02002151 ring->init = init_ring_common;
Chris Wilson549f7362010-10-19 11:19:32 +01002152
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002153 return intel_init_ring_buffer(dev, ring);
Chris Wilson549f7362010-10-19 11:19:32 +01002154}
Chris Wilsona7b97612012-07-20 12:41:08 +01002155
Ben Widawsky9a8a2212013-05-28 19:22:23 -07002156int intel_init_vebox_ring_buffer(struct drm_device *dev)
2157{
Jani Nikula4640c4f2014-03-31 14:27:19 +03002158 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky9a8a2212013-05-28 19:22:23 -07002159 struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2160
2161 ring->name = "video enhancement ring";
2162 ring->id = VECS;
2163
2164 ring->mmio_base = VEBOX_RING_BASE;
2165 ring->write_tail = ring_write_tail;
2166 ring->flush = gen6_ring_flush;
2167 ring->add_request = gen6_add_request;
2168 ring->get_seqno = gen6_ring_get_seqno;
2169 ring->set_seqno = ring_set_seqno;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002170
2171 if (INTEL_INFO(dev)->gen >= 8) {
2172 ring->irq_enable_mask =
Daniel Vetter40c499f2013-11-07 21:40:39 -08002173 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002174 ring->irq_get = gen8_ring_get_irq;
2175 ring->irq_put = gen8_ring_put_irq;
Ben Widawsky1c7a0622013-11-02 21:07:12 -07002176 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002177 } else {
2178 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2179 ring->irq_get = hsw_vebox_get_irq;
2180 ring->irq_put = hsw_vebox_put_irq;
Ben Widawsky1c7a0622013-11-02 21:07:12 -07002181 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002182 }
Ben Widawsky9a8a2212013-05-28 19:22:23 -07002183 ring->sync_to = gen6_ring_sync;
2184 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
2185 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
2186 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
2187 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2188 ring->signal_mbox[RCS] = GEN6_RVESYNC;
2189 ring->signal_mbox[VCS] = GEN6_VVESYNC;
2190 ring->signal_mbox[BCS] = GEN6_BVESYNC;
2191 ring->signal_mbox[VECS] = GEN6_NOSYNC;
2192 ring->init = init_ring_common;
2193
2194 return intel_init_ring_buffer(dev, ring);
2195}
2196
Chris Wilsona7b97612012-07-20 12:41:08 +01002197int
2198intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2199{
2200 int ret;
2201
2202 if (!ring->gpu_caches_dirty)
2203 return 0;
2204
2205 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2206 if (ret)
2207 return ret;
2208
2209 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2210
2211 ring->gpu_caches_dirty = false;
2212 return 0;
2213}
2214
2215int
2216intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2217{
2218 uint32_t flush_domains;
2219 int ret;
2220
2221 flush_domains = 0;
2222 if (ring->gpu_caches_dirty)
2223 flush_domains = I915_GEM_GPU_DOMAINS;
2224
2225 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2226 if (ret)
2227 return ret;
2228
2229 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2230
2231 ring->gpu_caches_dirty = false;
2232 return 0;
2233}