Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * ahci.c - AHCI SATA support |
| 3 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
| 5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
| 6 | * on emails. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 8 | * Copyright 2004-2005 Red Hat, Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2, or (at your option) |
| 14 | * any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; see the file COPYING. If not, write to |
| 23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 24 | * |
| 25 | * |
| 26 | * libata documentation is available via 'make {ps|pdf}docs', |
| 27 | * as Documentation/DocBook/libata.* |
| 28 | * |
| 29 | * AHCI hardware documentation: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | * |
| 33 | */ |
| 34 | |
| 35 | #include <linux/kernel.h> |
| 36 | #include <linux/module.h> |
| 37 | #include <linux/pci.h> |
| 38 | #include <linux/init.h> |
| 39 | #include <linux/blkdev.h> |
| 40 | #include <linux/delay.h> |
| 41 | #include <linux/interrupt.h> |
| 42 | #include <linux/sched.h> |
domen@coderock.org | 87507cf | 2005-04-08 09:53:06 +0200 | [diff] [blame] | 43 | #include <linux/dma-mapping.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 44 | #include <linux/device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | #include <scsi/scsi_host.h> |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 46 | #include <scsi/scsi_cmnd.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | #include <linux/libata.h> |
| 48 | #include <asm/io.h> |
| 49 | |
| 50 | #define DRV_NAME "ahci" |
Jeff Garzik | 7bdd720 | 2005-11-16 11:06:59 -0500 | [diff] [blame] | 51 | #define DRV_VERSION "1.2" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | |
| 53 | |
| 54 | enum { |
| 55 | AHCI_PCI_BAR = 5, |
| 56 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
| 57 | AHCI_DMA_BOUNDARY = 0xffffffff, |
| 58 | AHCI_USE_CLUSTERING = 0, |
| 59 | AHCI_CMD_SLOT_SZ = 32 * 32, |
| 60 | AHCI_RX_FIS_SZ = 256, |
| 61 | AHCI_CMD_TBL_HDR = 0x80, |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 62 | AHCI_CMD_TBL_CDB = 0x40, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16), |
| 64 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ + |
| 65 | AHCI_RX_FIS_SZ, |
| 66 | AHCI_IRQ_ON_SG = (1 << 31), |
| 67 | AHCI_CMD_ATAPI = (1 << 5), |
| 68 | AHCI_CMD_WRITE = (1 << 6), |
Tejun Heo | 4b10e55 | 2006-03-12 11:25:27 +0900 | [diff] [blame] | 69 | AHCI_CMD_PREFETCH = (1 << 7), |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 70 | AHCI_CMD_RESET = (1 << 8), |
| 71 | AHCI_CMD_CLR_BUSY = (1 << 10), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | |
| 73 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ |
| 74 | |
| 75 | board_ahci = 0, |
| 76 | |
| 77 | /* global controller registers */ |
| 78 | HOST_CAP = 0x00, /* host capabilities */ |
| 79 | HOST_CTL = 0x04, /* global host control */ |
| 80 | HOST_IRQ_STAT = 0x08, /* interrupt status */ |
| 81 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ |
| 82 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ |
| 83 | |
| 84 | /* HOST_CTL bits */ |
| 85 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ |
| 86 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ |
| 87 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ |
| 88 | |
| 89 | /* HOST_CAP bits */ |
| 90 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 91 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | |
| 93 | /* registers for each SATA port */ |
| 94 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ |
| 95 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ |
| 96 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ |
| 97 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ |
| 98 | PORT_IRQ_STAT = 0x10, /* interrupt status */ |
| 99 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ |
| 100 | PORT_CMD = 0x18, /* port command */ |
| 101 | PORT_TFDATA = 0x20, /* taskfile data */ |
| 102 | PORT_SIG = 0x24, /* device TF signature */ |
| 103 | PORT_CMD_ISSUE = 0x38, /* command issue */ |
| 104 | PORT_SCR = 0x28, /* SATA phy register block */ |
| 105 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
| 106 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ |
| 107 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ |
| 108 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ |
| 109 | |
| 110 | /* PORT_IRQ_{STAT,MASK} bits */ |
| 111 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ |
| 112 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ |
| 113 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ |
| 114 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ |
| 115 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ |
| 116 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ |
| 117 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ |
| 118 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ |
| 119 | |
| 120 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ |
| 121 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ |
| 122 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ |
| 123 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ |
| 124 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ |
| 125 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ |
| 126 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ |
| 127 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ |
| 128 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ |
| 129 | |
| 130 | PORT_IRQ_FATAL = PORT_IRQ_TF_ERR | |
| 131 | PORT_IRQ_HBUS_ERR | |
| 132 | PORT_IRQ_HBUS_DATA_ERR | |
| 133 | PORT_IRQ_IF_ERR, |
| 134 | DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY | |
| 135 | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE | |
| 136 | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS | |
| 137 | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS | |
| 138 | PORT_IRQ_D2H_REG_FIS, |
| 139 | |
| 140 | /* PORT_CMD bits */ |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 141 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 142 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
| 143 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ |
| 144 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 145 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 146 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
| 147 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ |
| 148 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ |
| 149 | |
| 150 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
| 151 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ |
| 152 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ |
Jeff Garzik | 4b0060f | 2005-06-04 00:50:22 -0400 | [diff] [blame] | 153 | |
| 154 | /* hpriv->flags bits */ |
| 155 | AHCI_FLAG_MSI = (1 << 0), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | }; |
| 157 | |
| 158 | struct ahci_cmd_hdr { |
| 159 | u32 opts; |
| 160 | u32 status; |
| 161 | u32 tbl_addr; |
| 162 | u32 tbl_addr_hi; |
| 163 | u32 reserved[4]; |
| 164 | }; |
| 165 | |
| 166 | struct ahci_sg { |
| 167 | u32 addr; |
| 168 | u32 addr_hi; |
| 169 | u32 reserved; |
| 170 | u32 flags_size; |
| 171 | }; |
| 172 | |
| 173 | struct ahci_host_priv { |
| 174 | unsigned long flags; |
| 175 | u32 cap; /* cache of HOST_CAP register */ |
| 176 | u32 port_map; /* cache of HOST_PORTS_IMPL reg */ |
| 177 | }; |
| 178 | |
| 179 | struct ahci_port_priv { |
| 180 | struct ahci_cmd_hdr *cmd_slot; |
| 181 | dma_addr_t cmd_slot_dma; |
| 182 | void *cmd_tbl; |
| 183 | dma_addr_t cmd_tbl_dma; |
| 184 | struct ahci_sg *cmd_tbl_sg; |
| 185 | void *rx_fis; |
| 186 | dma_addr_t rx_fis_dma; |
| 187 | }; |
| 188 | |
| 189 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg); |
| 190 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); |
| 191 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 192 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 193 | static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 194 | static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 195 | static void ahci_irq_clear(struct ata_port *ap); |
| 196 | static void ahci_eng_timeout(struct ata_port *ap); |
| 197 | static int ahci_port_start(struct ata_port *ap); |
| 198 | static void ahci_port_stop(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
| 200 | static void ahci_qc_prep(struct ata_queued_cmd *qc); |
| 201 | static u8 ahci_check_status(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 202 | static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc); |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 203 | static void ahci_remove_one (struct pci_dev *pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 204 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 205 | static struct scsi_host_template ahci_sht = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 206 | .module = THIS_MODULE, |
| 207 | .name = DRV_NAME, |
| 208 | .ioctl = ata_scsi_ioctl, |
| 209 | .queuecommand = ata_scsi_queuecmd, |
| 210 | .eh_strategy_handler = ata_scsi_error, |
| 211 | .can_queue = ATA_DEF_QUEUE, |
| 212 | .this_id = ATA_SHT_THIS_ID, |
| 213 | .sg_tablesize = AHCI_MAX_SG, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 214 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 215 | .emulated = ATA_SHT_EMULATED, |
| 216 | .use_clustering = AHCI_USE_CLUSTERING, |
| 217 | .proc_name = DRV_NAME, |
| 218 | .dma_boundary = AHCI_DMA_BOUNDARY, |
| 219 | .slave_configure = ata_scsi_slave_config, |
| 220 | .bios_param = ata_std_bios_param, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 221 | }; |
| 222 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 223 | static const struct ata_port_operations ahci_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 224 | .port_disable = ata_port_disable, |
| 225 | |
| 226 | .check_status = ahci_check_status, |
| 227 | .check_altstatus = ahci_check_status, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 228 | .dev_select = ata_noop_dev_select, |
| 229 | |
| 230 | .tf_read = ahci_tf_read, |
| 231 | |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 232 | .probe_reset = ahci_probe_reset, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | |
| 234 | .qc_prep = ahci_qc_prep, |
| 235 | .qc_issue = ahci_qc_issue, |
| 236 | |
| 237 | .eng_timeout = ahci_eng_timeout, |
| 238 | |
| 239 | .irq_handler = ahci_interrupt, |
| 240 | .irq_clear = ahci_irq_clear, |
| 241 | |
| 242 | .scr_read = ahci_scr_read, |
| 243 | .scr_write = ahci_scr_write, |
| 244 | |
| 245 | .port_start = ahci_port_start, |
| 246 | .port_stop = ahci_port_stop, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 247 | }; |
| 248 | |
Arjan van de Ven | 98ac62d | 2005-11-28 10:06:23 +0100 | [diff] [blame] | 249 | static const struct ata_port_info ahci_port_info[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 250 | /* board_ahci */ |
| 251 | { |
| 252 | .sht = &ahci_sht, |
| 253 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 254 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, |
Brett Russ | 7da7931 | 2005-09-01 21:53:34 -0400 | [diff] [blame] | 255 | .pio_mask = 0x1f, /* pio0-4 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 256 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
| 257 | .port_ops = &ahci_ops, |
| 258 | }, |
| 259 | }; |
| 260 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 261 | static const struct pci_device_id ahci_pci_tbl[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 262 | { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 263 | board_ahci }, /* ICH6 */ |
| 264 | { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 265 | board_ahci }, /* ICH6M */ |
| 266 | { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 267 | board_ahci }, /* ICH7 */ |
| 268 | { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 269 | board_ahci }, /* ICH7M */ |
| 270 | { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 271 | board_ahci }, /* ICH7R */ |
| 272 | { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 273 | board_ahci }, /* ULi M5288 */ |
Jason Gaston | 680d323 | 2005-04-16 15:24:45 -0700 | [diff] [blame] | 274 | { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 275 | board_ahci }, /* ESB2 */ |
| 276 | { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 277 | board_ahci }, /* ESB2 */ |
| 278 | { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 279 | board_ahci }, /* ESB2 */ |
Jason Gaston | 3db368f | 2005-08-10 06:18:43 -0700 | [diff] [blame] | 280 | { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 281 | board_ahci }, /* ICH7-M DH */ |
Jason Gaston | f285757 | 2006-01-09 11:09:13 -0800 | [diff] [blame] | 282 | { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 283 | board_ahci }, /* ICH8 */ |
| 284 | { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 285 | board_ahci }, /* ICH8 */ |
| 286 | { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 287 | board_ahci }, /* ICH8 */ |
| 288 | { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 289 | board_ahci }, /* ICH8M */ |
| 290 | { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 291 | board_ahci }, /* ICH8M */ |
Jeff Garzik | bd12097 | 2006-01-29 02:47:03 -0500 | [diff] [blame] | 292 | { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 293 | board_ahci }, /* JMicron JMB360 */ |
Jeff Garzik | 9220a2d | 2006-01-29 12:40:57 -0500 | [diff] [blame] | 294 | { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 295 | board_ahci }, /* JMicron JMB363 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | { } /* terminate list */ |
| 297 | }; |
| 298 | |
| 299 | |
| 300 | static struct pci_driver ahci_pci_driver = { |
| 301 | .name = DRV_NAME, |
| 302 | .id_table = ahci_pci_tbl, |
| 303 | .probe = ahci_init_one, |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 304 | .remove = ahci_remove_one, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 305 | }; |
| 306 | |
| 307 | |
| 308 | static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port) |
| 309 | { |
| 310 | return base + 0x100 + (port * 0x80); |
| 311 | } |
| 312 | |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 313 | static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 314 | { |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 315 | return (void __iomem *) ahci_port_base_ul((unsigned long)base, port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 316 | } |
| 317 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 318 | static int ahci_port_start(struct ata_port *ap) |
| 319 | { |
| 320 | struct device *dev = ap->host_set->dev; |
| 321 | struct ahci_host_priv *hpriv = ap->host_set->private_data; |
| 322 | struct ahci_port_priv *pp; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 323 | void __iomem *mmio = ap->host_set->mmio_base; |
| 324 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
| 325 | void *mem; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 326 | dma_addr_t mem_dma; |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 327 | int rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 328 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 329 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); |
Tejun Heo | 0a139e7 | 2005-06-26 23:52:50 +0900 | [diff] [blame] | 330 | if (!pp) |
| 331 | return -ENOMEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 332 | memset(pp, 0, sizeof(*pp)); |
| 333 | |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 334 | rc = ata_pad_alloc(ap, dev); |
| 335 | if (rc) { |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 336 | kfree(pp); |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 337 | return rc; |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 338 | } |
| 339 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 340 | mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL); |
| 341 | if (!mem) { |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 342 | ata_pad_free(ap, dev); |
Tejun Heo | 0a139e7 | 2005-06-26 23:52:50 +0900 | [diff] [blame] | 343 | kfree(pp); |
| 344 | return -ENOMEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 345 | } |
| 346 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
| 347 | |
| 348 | /* |
| 349 | * First item in chunk of DMA memory: 32-slot command table, |
| 350 | * 32 bytes each in size |
| 351 | */ |
| 352 | pp->cmd_slot = mem; |
| 353 | pp->cmd_slot_dma = mem_dma; |
| 354 | |
| 355 | mem += AHCI_CMD_SLOT_SZ; |
| 356 | mem_dma += AHCI_CMD_SLOT_SZ; |
| 357 | |
| 358 | /* |
| 359 | * Second item: Received-FIS area |
| 360 | */ |
| 361 | pp->rx_fis = mem; |
| 362 | pp->rx_fis_dma = mem_dma; |
| 363 | |
| 364 | mem += AHCI_RX_FIS_SZ; |
| 365 | mem_dma += AHCI_RX_FIS_SZ; |
| 366 | |
| 367 | /* |
| 368 | * Third item: data area for storing a single command |
| 369 | * and its scatter-gather table |
| 370 | */ |
| 371 | pp->cmd_tbl = mem; |
| 372 | pp->cmd_tbl_dma = mem_dma; |
| 373 | |
| 374 | pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR; |
| 375 | |
| 376 | ap->private_data = pp; |
| 377 | |
| 378 | if (hpriv->cap & HOST_CAP_64) |
| 379 | writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI); |
| 380 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); |
| 381 | readl(port_mmio + PORT_LST_ADDR); /* flush */ |
| 382 | |
| 383 | if (hpriv->cap & HOST_CAP_64) |
| 384 | writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI); |
| 385 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); |
| 386 | readl(port_mmio + PORT_FIS_ADDR); /* flush */ |
| 387 | |
| 388 | writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | |
| 389 | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | |
| 390 | PORT_CMD_START, port_mmio + PORT_CMD); |
| 391 | readl(port_mmio + PORT_CMD); /* flush */ |
| 392 | |
| 393 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 394 | } |
| 395 | |
| 396 | |
| 397 | static void ahci_port_stop(struct ata_port *ap) |
| 398 | { |
| 399 | struct device *dev = ap->host_set->dev; |
| 400 | struct ahci_port_priv *pp = ap->private_data; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 401 | void __iomem *mmio = ap->host_set->mmio_base; |
| 402 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 403 | u32 tmp; |
| 404 | |
| 405 | tmp = readl(port_mmio + PORT_CMD); |
| 406 | tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX); |
| 407 | writel(tmp, port_mmio + PORT_CMD); |
| 408 | readl(port_mmio + PORT_CMD); /* flush */ |
| 409 | |
| 410 | /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so |
| 411 | * this is slightly incorrect. |
| 412 | */ |
| 413 | msleep(500); |
| 414 | |
| 415 | ap->private_data = NULL; |
| 416 | dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, |
| 417 | pp->cmd_slot, pp->cmd_slot_dma); |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 418 | ata_pad_free(ap, dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 419 | kfree(pp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 420 | } |
| 421 | |
| 422 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) |
| 423 | { |
| 424 | unsigned int sc_reg; |
| 425 | |
| 426 | switch (sc_reg_in) { |
| 427 | case SCR_STATUS: sc_reg = 0; break; |
| 428 | case SCR_CONTROL: sc_reg = 1; break; |
| 429 | case SCR_ERROR: sc_reg = 2; break; |
| 430 | case SCR_ACTIVE: sc_reg = 3; break; |
| 431 | default: |
| 432 | return 0xffffffffU; |
| 433 | } |
| 434 | |
Al Viro | 1e4f2a9 | 2005-10-21 06:46:02 +0100 | [diff] [blame] | 435 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 436 | } |
| 437 | |
| 438 | |
| 439 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in, |
| 440 | u32 val) |
| 441 | { |
| 442 | unsigned int sc_reg; |
| 443 | |
| 444 | switch (sc_reg_in) { |
| 445 | case SCR_STATUS: sc_reg = 0; break; |
| 446 | case SCR_CONTROL: sc_reg = 1; break; |
| 447 | case SCR_ERROR: sc_reg = 2; break; |
| 448 | case SCR_ACTIVE: sc_reg = 3; break; |
| 449 | default: |
| 450 | return; |
| 451 | } |
| 452 | |
Al Viro | 1e4f2a9 | 2005-10-21 06:46:02 +0100 | [diff] [blame] | 453 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 454 | } |
| 455 | |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 456 | static int ahci_stop_engine(struct ata_port *ap) |
| 457 | { |
| 458 | void __iomem *mmio = ap->host_set->mmio_base; |
| 459 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
| 460 | int work; |
| 461 | u32 tmp; |
| 462 | |
| 463 | tmp = readl(port_mmio + PORT_CMD); |
| 464 | tmp &= ~PORT_CMD_START; |
| 465 | writel(tmp, port_mmio + PORT_CMD); |
| 466 | |
| 467 | /* wait for engine to stop. TODO: this could be |
| 468 | * as long as 500 msec |
| 469 | */ |
| 470 | work = 1000; |
| 471 | while (work-- > 0) { |
| 472 | tmp = readl(port_mmio + PORT_CMD); |
| 473 | if ((tmp & PORT_CMD_LIST_ON) == 0) |
| 474 | return 0; |
| 475 | udelay(10); |
| 476 | } |
| 477 | |
| 478 | return -EIO; |
| 479 | } |
| 480 | |
| 481 | static void ahci_start_engine(struct ata_port *ap) |
| 482 | { |
| 483 | void __iomem *mmio = ap->host_set->mmio_base; |
| 484 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
| 485 | u32 tmp; |
| 486 | |
| 487 | tmp = readl(port_mmio + PORT_CMD); |
| 488 | tmp |= PORT_CMD_START; |
| 489 | writel(tmp, port_mmio + PORT_CMD); |
| 490 | readl(port_mmio + PORT_CMD); /* flush */ |
| 491 | } |
| 492 | |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 493 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 494 | { |
| 495 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
| 496 | struct ata_taskfile tf; |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 497 | u32 tmp; |
| 498 | |
| 499 | tmp = readl(port_mmio + PORT_SIG); |
| 500 | tf.lbah = (tmp >> 24) & 0xff; |
| 501 | tf.lbam = (tmp >> 16) & 0xff; |
| 502 | tf.lbal = (tmp >> 8) & 0xff; |
| 503 | tf.nsect = (tmp) & 0xff; |
| 504 | |
| 505 | return ata_dev_classify(&tf); |
| 506 | } |
| 507 | |
Tejun Heo | a42fc65 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 508 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, u32 opts) |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 509 | { |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 510 | pp->cmd_slot[0].opts = cpu_to_le32(opts); |
| 511 | pp->cmd_slot[0].status = 0; |
| 512 | pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff); |
| 513 | pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16); |
| 514 | } |
| 515 | |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 516 | static int ahci_hardreset(struct ata_port *ap, int verbose, unsigned int *class) |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 517 | { |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 518 | int rc; |
| 519 | |
| 520 | DPRINTK("ENTER\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 521 | |
Tejun Heo | e0bfd14 | 2006-01-23 16:31:53 +0900 | [diff] [blame] | 522 | ahci_stop_engine(ap); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 523 | rc = sata_std_hardreset(ap, verbose, class); |
Tejun Heo | e0bfd14 | 2006-01-23 16:31:53 +0900 | [diff] [blame] | 524 | ahci_start_engine(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 525 | |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 526 | if (rc == 0) |
| 527 | *class = ahci_dev_classify(ap); |
| 528 | if (*class == ATA_DEV_UNKNOWN) |
| 529 | *class = ATA_DEV_NONE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 530 | |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 531 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
| 532 | return rc; |
| 533 | } |
| 534 | |
| 535 | static void ahci_postreset(struct ata_port *ap, unsigned int *class) |
| 536 | { |
| 537 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
| 538 | u32 new_tmp, tmp; |
| 539 | |
| 540 | ata_std_postreset(ap, class); |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 541 | |
| 542 | /* Make sure port's ATAPI bit is set appropriately */ |
| 543 | new_tmp = tmp = readl(port_mmio + PORT_CMD); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 544 | if (*class == ATA_DEV_ATAPI) |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 545 | new_tmp |= PORT_CMD_ATAPI; |
| 546 | else |
| 547 | new_tmp &= ~PORT_CMD_ATAPI; |
| 548 | if (new_tmp != tmp) { |
| 549 | writel(new_tmp, port_mmio + PORT_CMD); |
| 550 | readl(port_mmio + PORT_CMD); /* flush */ |
| 551 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 552 | } |
| 553 | |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 554 | static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes) |
| 555 | { |
| 556 | return ata_drive_probe_reset(ap, NULL, NULL, ahci_hardreset, |
| 557 | ahci_postreset, classes); |
| 558 | } |
| 559 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 560 | static u8 ahci_check_status(struct ata_port *ap) |
| 561 | { |
Al Viro | 1e4f2a9 | 2005-10-21 06:46:02 +0100 | [diff] [blame] | 562 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 563 | |
| 564 | return readl(mmio + PORT_TFDATA) & 0xFF; |
| 565 | } |
| 566 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 567 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
| 568 | { |
| 569 | struct ahci_port_priv *pp = ap->private_data; |
| 570 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 571 | |
| 572 | ata_tf_from_fis(d2h_fis, tf); |
| 573 | } |
| 574 | |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 575 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 576 | { |
| 577 | struct ahci_port_priv *pp = qc->ap->private_data; |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 578 | struct scatterlist *sg; |
| 579 | struct ahci_sg *ahci_sg; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 580 | unsigned int n_sg = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 581 | |
| 582 | VPRINTK("ENTER\n"); |
| 583 | |
| 584 | /* |
| 585 | * Next, the S/G list. |
| 586 | */ |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 587 | ahci_sg = pp->cmd_tbl_sg; |
| 588 | ata_for_each_sg(sg, qc) { |
| 589 | dma_addr_t addr = sg_dma_address(sg); |
| 590 | u32 sg_len = sg_dma_len(sg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 591 | |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 592 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); |
| 593 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); |
| 594 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 595 | |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 596 | ahci_sg++; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 597 | n_sg++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 598 | } |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 599 | |
| 600 | return n_sg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 601 | } |
| 602 | |
| 603 | static void ahci_qc_prep(struct ata_queued_cmd *qc) |
| 604 | { |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 605 | struct ata_port *ap = qc->ap; |
| 606 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 607 | int is_atapi = is_atapi_taskfile(&qc->tf); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 608 | u32 opts; |
| 609 | const u32 cmd_fis_len = 5; /* five dwords */ |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 610 | unsigned int n_elem; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 611 | |
| 612 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 613 | * Fill in command table information. First, the header, |
| 614 | * a SATA Register - Host to Device command FIS. |
| 615 | */ |
| 616 | ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 617 | if (is_atapi) { |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 618 | memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
Tejun Heo | 6e7846e | 2006-02-12 23:32:58 +0900 | [diff] [blame] | 619 | memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, |
| 620 | qc->dev->cdb_len); |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 621 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 623 | n_elem = 0; |
| 624 | if (qc->flags & ATA_QCFLAG_DMAMAP) |
| 625 | n_elem = ahci_fill_sg(qc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 626 | |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 627 | /* |
| 628 | * Fill in command slot information. |
| 629 | */ |
| 630 | opts = cmd_fis_len | n_elem << 16; |
| 631 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
| 632 | opts |= AHCI_CMD_WRITE; |
| 633 | if (is_atapi) |
Tejun Heo | 4b10e55 | 2006-03-12 11:25:27 +0900 | [diff] [blame] | 634 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 635 | |
Tejun Heo | a42fc65 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 636 | ahci_fill_cmd_slot(pp, opts); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 637 | } |
| 638 | |
Jeff Garzik | c2cd76f | 2005-11-16 09:23:30 -0500 | [diff] [blame] | 639 | static void ahci_restart_port(struct ata_port *ap, u32 irq_stat) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 640 | { |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 641 | void __iomem *mmio = ap->host_set->mmio_base; |
| 642 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 643 | u32 tmp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 644 | |
Jeff Garzik | c2cd76f | 2005-11-16 09:23:30 -0500 | [diff] [blame] | 645 | if ((ap->device[0].class != ATA_DEV_ATAPI) || |
| 646 | ((irq_stat & PORT_IRQ_TF_ERR) == 0)) |
| 647 | printk(KERN_WARNING "ata%u: port reset, " |
| 648 | "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n", |
| 649 | ap->id, |
| 650 | irq_stat, |
| 651 | readl(mmio + HOST_IRQ_STAT), |
| 652 | readl(port_mmio + PORT_IRQ_STAT), |
| 653 | readl(port_mmio + PORT_CMD), |
| 654 | readl(port_mmio + PORT_TFDATA), |
| 655 | readl(port_mmio + PORT_SCR_STAT), |
| 656 | readl(port_mmio + PORT_SCR_ERR)); |
Jeff Garzik | 9f68a24 | 2005-11-15 14:03:47 -0500 | [diff] [blame] | 657 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 658 | /* stop DMA */ |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 659 | ahci_stop_engine(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 660 | |
| 661 | /* clear SATA phy error, if any */ |
| 662 | tmp = readl(port_mmio + PORT_SCR_ERR); |
| 663 | writel(tmp, port_mmio + PORT_SCR_ERR); |
| 664 | |
| 665 | /* if DRQ/BSY is set, device needs to be reset. |
| 666 | * if so, issue COMRESET |
| 667 | */ |
| 668 | tmp = readl(port_mmio + PORT_TFDATA); |
| 669 | if (tmp & (ATA_BUSY | ATA_DRQ)) { |
| 670 | writel(0x301, port_mmio + PORT_SCR_CTL); |
| 671 | readl(port_mmio + PORT_SCR_CTL); /* flush */ |
| 672 | udelay(10); |
| 673 | writel(0x300, port_mmio + PORT_SCR_CTL); |
| 674 | readl(port_mmio + PORT_SCR_CTL); /* flush */ |
| 675 | } |
| 676 | |
| 677 | /* re-start DMA */ |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 678 | ahci_start_engine(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 679 | } |
| 680 | |
| 681 | static void ahci_eng_timeout(struct ata_port *ap) |
| 682 | { |
Jeff Garzik | b8f6153 | 2005-08-25 22:01:20 -0400 | [diff] [blame] | 683 | struct ata_host_set *host_set = ap->host_set; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 684 | void __iomem *mmio = host_set->mmio_base; |
| 685 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 686 | struct ata_queued_cmd *qc; |
Jeff Garzik | b8f6153 | 2005-08-25 22:01:20 -0400 | [diff] [blame] | 687 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 688 | |
Jeff Garzik | 9f68a24 | 2005-11-15 14:03:47 -0500 | [diff] [blame] | 689 | printk(KERN_WARNING "ata%u: handling error/timeout\n", ap->id); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 690 | |
Jeff Garzik | b8f6153 | 2005-08-25 22:01:20 -0400 | [diff] [blame] | 691 | spin_lock_irqsave(&host_set->lock, flags); |
| 692 | |
Tejun Heo | f637902 | 2006-02-10 15:10:48 +0900 | [diff] [blame] | 693 | ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 694 | qc = ata_qc_from_tag(ap, ap->active_tag); |
Tejun Heo | f637902 | 2006-02-10 15:10:48 +0900 | [diff] [blame] | 695 | qc->err_mask |= AC_ERR_TIMEOUT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 696 | |
Jeff Garzik | b8f6153 | 2005-08-25 22:01:20 -0400 | [diff] [blame] | 697 | spin_unlock_irqrestore(&host_set->lock, flags); |
Tejun Heo | a72ec4c | 2006-01-23 13:09:37 +0900 | [diff] [blame] | 698 | |
Tejun Heo | f637902 | 2006-02-10 15:10:48 +0900 | [diff] [blame] | 699 | ata_eh_qc_complete(qc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 700 | } |
| 701 | |
| 702 | static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc) |
| 703 | { |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 704 | void __iomem *mmio = ap->host_set->mmio_base; |
| 705 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 706 | u32 status, serr, ci; |
| 707 | |
| 708 | serr = readl(port_mmio + PORT_SCR_ERR); |
| 709 | writel(serr, port_mmio + PORT_SCR_ERR); |
| 710 | |
| 711 | status = readl(port_mmio + PORT_IRQ_STAT); |
| 712 | writel(status, port_mmio + PORT_IRQ_STAT); |
| 713 | |
| 714 | ci = readl(port_mmio + PORT_CMD_ISSUE); |
| 715 | if (likely((ci & 0x1) == 0)) { |
| 716 | if (qc) { |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 717 | WARN_ON(qc->err_mask); |
Albert Lee | a22e2eb | 2005-12-05 15:38:02 +0800 | [diff] [blame] | 718 | ata_qc_complete(qc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 719 | qc = NULL; |
| 720 | } |
| 721 | } |
| 722 | |
| 723 | if (status & PORT_IRQ_FATAL) { |
Jeff Garzik | ad36d1a | 2005-11-14 13:56:37 -0500 | [diff] [blame] | 724 | unsigned int err_mask; |
| 725 | if (status & PORT_IRQ_TF_ERR) |
| 726 | err_mask = AC_ERR_DEV; |
| 727 | else if (status & PORT_IRQ_IF_ERR) |
| 728 | err_mask = AC_ERR_ATA_BUS; |
| 729 | else |
| 730 | err_mask = AC_ERR_HOST_BUS; |
| 731 | |
Jeff Garzik | 9f68a24 | 2005-11-15 14:03:47 -0500 | [diff] [blame] | 732 | /* command processing has stopped due to error; restart */ |
Jeff Garzik | c2cd76f | 2005-11-16 09:23:30 -0500 | [diff] [blame] | 733 | ahci_restart_port(ap, status); |
Jeff Garzik | 9f68a24 | 2005-11-15 14:03:47 -0500 | [diff] [blame] | 734 | |
Albert Lee | a22e2eb | 2005-12-05 15:38:02 +0800 | [diff] [blame] | 735 | if (qc) { |
Tejun Heo | 284b648 | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 736 | qc->err_mask |= err_mask; |
Albert Lee | a22e2eb | 2005-12-05 15:38:02 +0800 | [diff] [blame] | 737 | ata_qc_complete(qc); |
| 738 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 739 | } |
| 740 | |
| 741 | return 1; |
| 742 | } |
| 743 | |
| 744 | static void ahci_irq_clear(struct ata_port *ap) |
| 745 | { |
| 746 | /* TODO */ |
| 747 | } |
| 748 | |
| 749 | static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs) |
| 750 | { |
| 751 | struct ata_host_set *host_set = dev_instance; |
| 752 | struct ahci_host_priv *hpriv; |
| 753 | unsigned int i, handled = 0; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 754 | void __iomem *mmio; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 755 | u32 irq_stat, irq_ack = 0; |
| 756 | |
| 757 | VPRINTK("ENTER\n"); |
| 758 | |
| 759 | hpriv = host_set->private_data; |
| 760 | mmio = host_set->mmio_base; |
| 761 | |
| 762 | /* sigh. 0xffffffff is a valid return from h/w */ |
| 763 | irq_stat = readl(mmio + HOST_IRQ_STAT); |
| 764 | irq_stat &= hpriv->port_map; |
| 765 | if (!irq_stat) |
| 766 | return IRQ_NONE; |
| 767 | |
| 768 | spin_lock(&host_set->lock); |
| 769 | |
| 770 | for (i = 0; i < host_set->n_ports; i++) { |
| 771 | struct ata_port *ap; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 772 | |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 773 | if (!(irq_stat & (1 << i))) |
| 774 | continue; |
| 775 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 776 | ap = host_set->ports[i]; |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 777 | if (ap) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 778 | struct ata_queued_cmd *qc; |
| 779 | qc = ata_qc_from_tag(ap, ap->active_tag); |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 780 | if (!ahci_host_intr(ap, qc)) |
Tejun Heo | 6971ed1 | 2006-03-11 12:47:54 +0900 | [diff] [blame] | 781 | if (ata_ratelimit()) |
| 782 | dev_printk(KERN_WARNING, host_set->dev, |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 783 | "unhandled interrupt on port %u\n", |
| 784 | i); |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 785 | |
| 786 | VPRINTK("port %u\n", i); |
| 787 | } else { |
| 788 | VPRINTK("port %u (no irq)\n", i); |
Tejun Heo | 6971ed1 | 2006-03-11 12:47:54 +0900 | [diff] [blame] | 789 | if (ata_ratelimit()) |
| 790 | dev_printk(KERN_WARNING, host_set->dev, |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 791 | "interrupt on disabled port %u\n", i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 792 | } |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 793 | |
| 794 | irq_ack |= (1 << i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 795 | } |
| 796 | |
| 797 | if (irq_ack) { |
| 798 | writel(irq_ack, mmio + HOST_IRQ_STAT); |
| 799 | handled = 1; |
| 800 | } |
| 801 | |
| 802 | spin_unlock(&host_set->lock); |
| 803 | |
| 804 | VPRINTK("EXIT\n"); |
| 805 | |
| 806 | return IRQ_RETVAL(handled); |
| 807 | } |
| 808 | |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 809 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 810 | { |
| 811 | struct ata_port *ap = qc->ap; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 812 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 813 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 814 | writel(1, port_mmio + PORT_CMD_ISSUE); |
| 815 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
| 816 | |
| 817 | return 0; |
| 818 | } |
| 819 | |
| 820 | static void ahci_setup_port(struct ata_ioports *port, unsigned long base, |
| 821 | unsigned int port_idx) |
| 822 | { |
| 823 | VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx); |
| 824 | base = ahci_port_base_ul(base, port_idx); |
| 825 | VPRINTK("base now==0x%lx\n", base); |
| 826 | |
| 827 | port->cmd_addr = base; |
| 828 | port->scr_addr = base + PORT_SCR; |
| 829 | |
| 830 | VPRINTK("EXIT\n"); |
| 831 | } |
| 832 | |
| 833 | static int ahci_host_init(struct ata_probe_ent *probe_ent) |
| 834 | { |
| 835 | struct ahci_host_priv *hpriv = probe_ent->private_data; |
| 836 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); |
| 837 | void __iomem *mmio = probe_ent->mmio_base; |
| 838 | u32 tmp, cap_save; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 839 | unsigned int i, j, using_dac; |
| 840 | int rc; |
| 841 | void __iomem *port_mmio; |
| 842 | |
| 843 | cap_save = readl(mmio + HOST_CAP); |
| 844 | cap_save &= ( (1<<28) | (1<<17) ); |
| 845 | cap_save |= (1 << 27); |
| 846 | |
| 847 | /* global controller reset */ |
| 848 | tmp = readl(mmio + HOST_CTL); |
| 849 | if ((tmp & HOST_RESET) == 0) { |
| 850 | writel(tmp | HOST_RESET, mmio + HOST_CTL); |
| 851 | readl(mmio + HOST_CTL); /* flush */ |
| 852 | } |
| 853 | |
| 854 | /* reset must complete within 1 second, or |
| 855 | * the hardware should be considered fried. |
| 856 | */ |
| 857 | ssleep(1); |
| 858 | |
| 859 | tmp = readl(mmio + HOST_CTL); |
| 860 | if (tmp & HOST_RESET) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 861 | dev_printk(KERN_ERR, &pdev->dev, |
| 862 | "controller reset failed (0x%x)\n", tmp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 863 | return -EIO; |
| 864 | } |
| 865 | |
| 866 | writel(HOST_AHCI_EN, mmio + HOST_CTL); |
| 867 | (void) readl(mmio + HOST_CTL); /* flush */ |
| 868 | writel(cap_save, mmio + HOST_CAP); |
| 869 | writel(0xf, mmio + HOST_PORTS_IMPL); |
| 870 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ |
| 871 | |
Jeff Garzik | bd12097 | 2006-01-29 02:47:03 -0500 | [diff] [blame] | 872 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
| 873 | u16 tmp16; |
| 874 | |
| 875 | pci_read_config_word(pdev, 0x92, &tmp16); |
| 876 | tmp16 |= 0xf; |
| 877 | pci_write_config_word(pdev, 0x92, tmp16); |
| 878 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 879 | |
| 880 | hpriv->cap = readl(mmio + HOST_CAP); |
| 881 | hpriv->port_map = readl(mmio + HOST_PORTS_IMPL); |
| 882 | probe_ent->n_ports = (hpriv->cap & 0x1f) + 1; |
| 883 | |
| 884 | VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n", |
| 885 | hpriv->cap, hpriv->port_map, probe_ent->n_ports); |
| 886 | |
| 887 | using_dac = hpriv->cap & HOST_CAP_64; |
| 888 | if (using_dac && |
| 889 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
| 890 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
| 891 | if (rc) { |
| 892 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 893 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 894 | dev_printk(KERN_ERR, &pdev->dev, |
| 895 | "64-bit DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 896 | return rc; |
| 897 | } |
| 898 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 899 | } else { |
| 900 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
| 901 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 902 | dev_printk(KERN_ERR, &pdev->dev, |
| 903 | "32-bit DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 904 | return rc; |
| 905 | } |
| 906 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 907 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 908 | dev_printk(KERN_ERR, &pdev->dev, |
| 909 | "32-bit consistent DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 910 | return rc; |
| 911 | } |
| 912 | } |
| 913 | |
| 914 | for (i = 0; i < probe_ent->n_ports; i++) { |
| 915 | #if 0 /* BIOSen initialize this incorrectly */ |
| 916 | if (!(hpriv->port_map & (1 << i))) |
| 917 | continue; |
| 918 | #endif |
| 919 | |
| 920 | port_mmio = ahci_port_base(mmio, i); |
| 921 | VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio); |
| 922 | |
| 923 | ahci_setup_port(&probe_ent->port[i], |
| 924 | (unsigned long) mmio, i); |
| 925 | |
| 926 | /* make sure port is not active */ |
| 927 | tmp = readl(port_mmio + PORT_CMD); |
| 928 | VPRINTK("PORT_CMD 0x%x\n", tmp); |
| 929 | if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | |
| 930 | PORT_CMD_FIS_RX | PORT_CMD_START)) { |
| 931 | tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | |
| 932 | PORT_CMD_FIS_RX | PORT_CMD_START); |
| 933 | writel(tmp, port_mmio + PORT_CMD); |
| 934 | readl(port_mmio + PORT_CMD); /* flush */ |
| 935 | |
| 936 | /* spec says 500 msecs for each bit, so |
| 937 | * this is slightly incorrect. |
| 938 | */ |
| 939 | msleep(500); |
| 940 | } |
| 941 | |
| 942 | writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); |
| 943 | |
| 944 | j = 0; |
| 945 | while (j < 100) { |
| 946 | msleep(10); |
| 947 | tmp = readl(port_mmio + PORT_SCR_STAT); |
| 948 | if ((tmp & 0xf) == 0x3) |
| 949 | break; |
| 950 | j++; |
| 951 | } |
| 952 | |
| 953 | tmp = readl(port_mmio + PORT_SCR_ERR); |
| 954 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); |
| 955 | writel(tmp, port_mmio + PORT_SCR_ERR); |
| 956 | |
| 957 | /* ack any pending irq events for this port */ |
| 958 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 959 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); |
| 960 | if (tmp) |
| 961 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
| 962 | |
| 963 | writel(1 << i, mmio + HOST_IRQ_STAT); |
| 964 | |
| 965 | /* set irq mask (enables interrupts) */ |
| 966 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); |
| 967 | } |
| 968 | |
| 969 | tmp = readl(mmio + HOST_CTL); |
| 970 | VPRINTK("HOST_CTL 0x%x\n", tmp); |
| 971 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); |
| 972 | tmp = readl(mmio + HOST_CTL); |
| 973 | VPRINTK("HOST_CTL 0x%x\n", tmp); |
| 974 | |
| 975 | pci_set_master(pdev); |
| 976 | |
| 977 | return 0; |
| 978 | } |
| 979 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 980 | static void ahci_print_info(struct ata_probe_ent *probe_ent) |
| 981 | { |
| 982 | struct ahci_host_priv *hpriv = probe_ent->private_data; |
| 983 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 984 | void __iomem *mmio = probe_ent->mmio_base; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 985 | u32 vers, cap, impl, speed; |
| 986 | const char *speed_s; |
| 987 | u16 cc; |
| 988 | const char *scc_s; |
| 989 | |
| 990 | vers = readl(mmio + HOST_VERSION); |
| 991 | cap = hpriv->cap; |
| 992 | impl = hpriv->port_map; |
| 993 | |
| 994 | speed = (cap >> 20) & 0xf; |
| 995 | if (speed == 1) |
| 996 | speed_s = "1.5"; |
| 997 | else if (speed == 2) |
| 998 | speed_s = "3"; |
| 999 | else |
| 1000 | speed_s = "?"; |
| 1001 | |
| 1002 | pci_read_config_word(pdev, 0x0a, &cc); |
| 1003 | if (cc == 0x0101) |
| 1004 | scc_s = "IDE"; |
| 1005 | else if (cc == 0x0106) |
| 1006 | scc_s = "SATA"; |
| 1007 | else if (cc == 0x0104) |
| 1008 | scc_s = "RAID"; |
| 1009 | else |
| 1010 | scc_s = "unknown"; |
| 1011 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1012 | dev_printk(KERN_INFO, &pdev->dev, |
| 1013 | "AHCI %02x%02x.%02x%02x " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1014 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
| 1015 | , |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1016 | |
| 1017 | (vers >> 24) & 0xff, |
| 1018 | (vers >> 16) & 0xff, |
| 1019 | (vers >> 8) & 0xff, |
| 1020 | vers & 0xff, |
| 1021 | |
| 1022 | ((cap >> 8) & 0x1f) + 1, |
| 1023 | (cap & 0x1f) + 1, |
| 1024 | speed_s, |
| 1025 | impl, |
| 1026 | scc_s); |
| 1027 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1028 | dev_printk(KERN_INFO, &pdev->dev, |
| 1029 | "flags: " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1030 | "%s%s%s%s%s%s" |
| 1031 | "%s%s%s%s%s%s%s\n" |
| 1032 | , |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1033 | |
| 1034 | cap & (1 << 31) ? "64bit " : "", |
| 1035 | cap & (1 << 30) ? "ncq " : "", |
| 1036 | cap & (1 << 28) ? "ilck " : "", |
| 1037 | cap & (1 << 27) ? "stag " : "", |
| 1038 | cap & (1 << 26) ? "pm " : "", |
| 1039 | cap & (1 << 25) ? "led " : "", |
| 1040 | |
| 1041 | cap & (1 << 24) ? "clo " : "", |
| 1042 | cap & (1 << 19) ? "nz " : "", |
| 1043 | cap & (1 << 18) ? "only " : "", |
| 1044 | cap & (1 << 17) ? "pmp " : "", |
| 1045 | cap & (1 << 15) ? "pio " : "", |
| 1046 | cap & (1 << 14) ? "slum " : "", |
| 1047 | cap & (1 << 13) ? "part " : "" |
| 1048 | ); |
| 1049 | } |
| 1050 | |
| 1051 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
| 1052 | { |
| 1053 | static int printed_version; |
| 1054 | struct ata_probe_ent *probe_ent = NULL; |
| 1055 | struct ahci_host_priv *hpriv; |
| 1056 | unsigned long base; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 1057 | void __iomem *mmio_base; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1058 | unsigned int board_idx = (unsigned int) ent->driver_data; |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1059 | int have_msi, pci_dev_busy = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1060 | int rc; |
| 1061 | |
| 1062 | VPRINTK("ENTER\n"); |
| 1063 | |
| 1064 | if (!printed_version++) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1065 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1066 | |
| 1067 | rc = pci_enable_device(pdev); |
| 1068 | if (rc) |
| 1069 | return rc; |
| 1070 | |
| 1071 | rc = pci_request_regions(pdev, DRV_NAME); |
| 1072 | if (rc) { |
| 1073 | pci_dev_busy = 1; |
| 1074 | goto err_out; |
| 1075 | } |
| 1076 | |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1077 | if (pci_enable_msi(pdev) == 0) |
| 1078 | have_msi = 1; |
| 1079 | else { |
| 1080 | pci_intx(pdev, 1); |
| 1081 | have_msi = 0; |
| 1082 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1083 | |
| 1084 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); |
| 1085 | if (probe_ent == NULL) { |
| 1086 | rc = -ENOMEM; |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1087 | goto err_out_msi; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1088 | } |
| 1089 | |
| 1090 | memset(probe_ent, 0, sizeof(*probe_ent)); |
| 1091 | probe_ent->dev = pci_dev_to_dev(pdev); |
| 1092 | INIT_LIST_HEAD(&probe_ent->node); |
| 1093 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 1094 | mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1095 | if (mmio_base == NULL) { |
| 1096 | rc = -ENOMEM; |
| 1097 | goto err_out_free_ent; |
| 1098 | } |
| 1099 | base = (unsigned long) mmio_base; |
| 1100 | |
| 1101 | hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL); |
| 1102 | if (!hpriv) { |
| 1103 | rc = -ENOMEM; |
| 1104 | goto err_out_iounmap; |
| 1105 | } |
| 1106 | memset(hpriv, 0, sizeof(*hpriv)); |
| 1107 | |
| 1108 | probe_ent->sht = ahci_port_info[board_idx].sht; |
| 1109 | probe_ent->host_flags = ahci_port_info[board_idx].host_flags; |
| 1110 | probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask; |
| 1111 | probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask; |
| 1112 | probe_ent->port_ops = ahci_port_info[board_idx].port_ops; |
| 1113 | |
| 1114 | probe_ent->irq = pdev->irq; |
| 1115 | probe_ent->irq_flags = SA_SHIRQ; |
| 1116 | probe_ent->mmio_base = mmio_base; |
| 1117 | probe_ent->private_data = hpriv; |
| 1118 | |
Jeff Garzik | 4b0060f | 2005-06-04 00:50:22 -0400 | [diff] [blame] | 1119 | if (have_msi) |
| 1120 | hpriv->flags |= AHCI_FLAG_MSI; |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1121 | |
Jeff Garzik | bd12097 | 2006-01-29 02:47:03 -0500 | [diff] [blame] | 1122 | /* JMicron-specific fixup: make sure we're in AHCI mode */ |
| 1123 | if (pdev->vendor == 0x197b) |
| 1124 | pci_write_config_byte(pdev, 0x41, 0xa1); |
| 1125 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1126 | /* initialize adapter */ |
| 1127 | rc = ahci_host_init(probe_ent); |
| 1128 | if (rc) |
| 1129 | goto err_out_hpriv; |
| 1130 | |
| 1131 | ahci_print_info(probe_ent); |
| 1132 | |
| 1133 | /* FIXME: check ata_device_add return value */ |
| 1134 | ata_device_add(probe_ent); |
| 1135 | kfree(probe_ent); |
| 1136 | |
| 1137 | return 0; |
| 1138 | |
| 1139 | err_out_hpriv: |
| 1140 | kfree(hpriv); |
| 1141 | err_out_iounmap: |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 1142 | pci_iounmap(pdev, mmio_base); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1143 | err_out_free_ent: |
| 1144 | kfree(probe_ent); |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1145 | err_out_msi: |
| 1146 | if (have_msi) |
| 1147 | pci_disable_msi(pdev); |
| 1148 | else |
| 1149 | pci_intx(pdev, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1150 | pci_release_regions(pdev); |
| 1151 | err_out: |
| 1152 | if (!pci_dev_busy) |
| 1153 | pci_disable_device(pdev); |
| 1154 | return rc; |
| 1155 | } |
| 1156 | |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1157 | static void ahci_remove_one (struct pci_dev *pdev) |
| 1158 | { |
| 1159 | struct device *dev = pci_dev_to_dev(pdev); |
| 1160 | struct ata_host_set *host_set = dev_get_drvdata(dev); |
| 1161 | struct ahci_host_priv *hpriv = host_set->private_data; |
| 1162 | struct ata_port *ap; |
| 1163 | unsigned int i; |
| 1164 | int have_msi; |
| 1165 | |
| 1166 | for (i = 0; i < host_set->n_ports; i++) { |
| 1167 | ap = host_set->ports[i]; |
| 1168 | |
| 1169 | scsi_remove_host(ap->host); |
| 1170 | } |
| 1171 | |
Jeff Garzik | 4b0060f | 2005-06-04 00:50:22 -0400 | [diff] [blame] | 1172 | have_msi = hpriv->flags & AHCI_FLAG_MSI; |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1173 | free_irq(host_set->irq, host_set); |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1174 | |
| 1175 | for (i = 0; i < host_set->n_ports; i++) { |
| 1176 | ap = host_set->ports[i]; |
| 1177 | |
| 1178 | ata_scsi_release(ap->host); |
| 1179 | scsi_host_put(ap->host); |
| 1180 | } |
| 1181 | |
Jeff Garzik | e005f01 | 2005-08-30 04:18:28 -0400 | [diff] [blame] | 1182 | kfree(hpriv); |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 1183 | pci_iounmap(pdev, host_set->mmio_base); |
Jeff Garzik | ead5de9 | 2005-05-31 11:53:57 -0400 | [diff] [blame] | 1184 | kfree(host_set); |
| 1185 | |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1186 | if (have_msi) |
| 1187 | pci_disable_msi(pdev); |
| 1188 | else |
| 1189 | pci_intx(pdev, 0); |
| 1190 | pci_release_regions(pdev); |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1191 | pci_disable_device(pdev); |
| 1192 | dev_set_drvdata(dev, NULL); |
| 1193 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1194 | |
| 1195 | static int __init ahci_init(void) |
| 1196 | { |
| 1197 | return pci_module_init(&ahci_pci_driver); |
| 1198 | } |
| 1199 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1200 | static void __exit ahci_exit(void) |
| 1201 | { |
| 1202 | pci_unregister_driver(&ahci_pci_driver); |
| 1203 | } |
| 1204 | |
| 1205 | |
| 1206 | MODULE_AUTHOR("Jeff Garzik"); |
| 1207 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); |
| 1208 | MODULE_LICENSE("GPL"); |
| 1209 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); |
Jeff Garzik | 6885433 | 2005-08-23 02:53:51 -0400 | [diff] [blame] | 1210 | MODULE_VERSION(DRV_VERSION); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1211 | |
| 1212 | module_init(ahci_init); |
| 1213 | module_exit(ahci_exit); |