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Magnus Damm9570ef22009-05-01 06:51:00 +00001/*
2 * SuperH Timer Support - TMU
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/clk.h>
28#include <linux/irq.h>
29#include <linux/err.h>
30#include <linux/clocksource.h>
31#include <linux/clockchips.h>
Paul Mundt46a12f72009-05-03 17:57:17 +090032#include <linux/sh_timer.h>
Magnus Damm9570ef22009-05-01 06:51:00 +000033
34struct sh_tmu_priv {
35 void __iomem *mapbase;
36 struct clk *clk;
37 struct irqaction irqaction;
38 struct platform_device *pdev;
39 unsigned long rate;
40 unsigned long periodic;
41 struct clock_event_device ced;
42 struct clocksource cs;
43};
44
45static DEFINE_SPINLOCK(sh_tmu_lock);
46
47#define TSTR -1 /* shared register */
48#define TCOR 0 /* channel register */
49#define TCNT 1 /* channel register */
50#define TCR 2 /* channel register */
51
52static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
53{
Paul Mundt46a12f72009-05-03 17:57:17 +090054 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
Magnus Damm9570ef22009-05-01 06:51:00 +000055 void __iomem *base = p->mapbase;
56 unsigned long offs;
57
58 if (reg_nr == TSTR)
59 return ioread8(base - cfg->channel_offset);
60
61 offs = reg_nr << 2;
62
63 if (reg_nr == TCR)
64 return ioread16(base + offs);
65 else
66 return ioread32(base + offs);
67}
68
69static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
70 unsigned long value)
71{
Paul Mundt46a12f72009-05-03 17:57:17 +090072 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
Magnus Damm9570ef22009-05-01 06:51:00 +000073 void __iomem *base = p->mapbase;
74 unsigned long offs;
75
76 if (reg_nr == TSTR) {
77 iowrite8(value, base - cfg->channel_offset);
78 return;
79 }
80
81 offs = reg_nr << 2;
82
83 if (reg_nr == TCR)
84 iowrite16(value, base + offs);
85 else
86 iowrite32(value, base + offs);
87}
88
89static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
90{
Paul Mundt46a12f72009-05-03 17:57:17 +090091 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
Magnus Damm9570ef22009-05-01 06:51:00 +000092 unsigned long flags, value;
93
94 /* start stop register shared by multiple timer channels */
95 spin_lock_irqsave(&sh_tmu_lock, flags);
96 value = sh_tmu_read(p, TSTR);
97
98 if (start)
99 value |= 1 << cfg->timer_bit;
100 else
101 value &= ~(1 << cfg->timer_bit);
102
103 sh_tmu_write(p, TSTR, value);
104 spin_unlock_irqrestore(&sh_tmu_lock, flags);
105}
106
107static int sh_tmu_enable(struct sh_tmu_priv *p)
108{
Paul Mundt46a12f72009-05-03 17:57:17 +0900109 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
Magnus Damm9570ef22009-05-01 06:51:00 +0000110 int ret;
111
112 /* enable clock */
113 ret = clk_enable(p->clk);
114 if (ret) {
115 pr_err("sh_tmu: cannot enable clock \"%s\"\n", cfg->clk);
116 return ret;
117 }
118
119 /* make sure channel is disabled */
120 sh_tmu_start_stop_ch(p, 0);
121
122 /* maximum timeout */
123 sh_tmu_write(p, TCOR, 0xffffffff);
124 sh_tmu_write(p, TCNT, 0xffffffff);
125
126 /* configure channel to parent clock / 4, irq off */
127 p->rate = clk_get_rate(p->clk) / 4;
128 sh_tmu_write(p, TCR, 0x0000);
129
130 /* enable channel */
131 sh_tmu_start_stop_ch(p, 1);
132
133 return 0;
134}
135
136static void sh_tmu_disable(struct sh_tmu_priv *p)
137{
138 /* disable channel */
139 sh_tmu_start_stop_ch(p, 0);
140
141 /* stop clock */
142 clk_disable(p->clk);
143}
144
145static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
146 int periodic)
147{
148 /* stop timer */
149 sh_tmu_start_stop_ch(p, 0);
150
151 /* acknowledge interrupt */
152 sh_tmu_read(p, TCR);
153
154 /* enable interrupt */
155 sh_tmu_write(p, TCR, 0x0020);
156
157 /* reload delta value in case of periodic timer */
158 if (periodic)
159 sh_tmu_write(p, TCOR, delta);
160 else
161 sh_tmu_write(p, TCOR, 0);
162
163 sh_tmu_write(p, TCNT, delta);
164
165 /* start timer */
166 sh_tmu_start_stop_ch(p, 1);
167}
168
169static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
170{
171 struct sh_tmu_priv *p = dev_id;
172
173 /* disable or acknowledge interrupt */
174 if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
175 sh_tmu_write(p, TCR, 0x0000);
176 else
177 sh_tmu_write(p, TCR, 0x0020);
178
179 /* notify clockevent layer */
180 p->ced.event_handler(&p->ced);
181 return IRQ_HANDLED;
182}
183
184static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs)
185{
186 return container_of(cs, struct sh_tmu_priv, cs);
187}
188
189static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
190{
191 struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
192
193 return sh_tmu_read(p, TCNT) ^ 0xffffffff;
194}
195
196static int sh_tmu_clocksource_enable(struct clocksource *cs)
197{
198 struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
199 int ret;
200
201 ret = sh_tmu_enable(p);
202 if (ret)
203 return ret;
204
205 /* TODO: calculate good shift from rate and counter bit width */
206 cs->shift = 10;
207 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
208 return 0;
209}
210
211static void sh_tmu_clocksource_disable(struct clocksource *cs)
212{
213 sh_tmu_disable(cs_to_sh_tmu(cs));
214}
215
216static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
217 char *name, unsigned long rating)
218{
219 struct clocksource *cs = &p->cs;
220
221 cs->name = name;
222 cs->rating = rating;
223 cs->read = sh_tmu_clocksource_read;
224 cs->enable = sh_tmu_clocksource_enable;
225 cs->disable = sh_tmu_clocksource_disable;
226 cs->mask = CLOCKSOURCE_MASK(32);
227 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
228 pr_info("sh_tmu: %s used as clock source\n", cs->name);
229 clocksource_register(cs);
230 return 0;
231}
232
233static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced)
234{
235 return container_of(ced, struct sh_tmu_priv, ced);
236}
237
238static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
239{
240 struct clock_event_device *ced = &p->ced;
241
242 sh_tmu_enable(p);
243
244 /* TODO: calculate good shift from rate and counter bit width */
245
246 ced->shift = 32;
247 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
248 ced->max_delta_ns = clockevent_delta2ns(0xffffffff, ced);
249 ced->min_delta_ns = 5000;
250
251 if (periodic) {
252 p->periodic = (p->rate + HZ/2) / HZ;
253 sh_tmu_set_next(p, p->periodic, 1);
254 }
255}
256
257static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
258 struct clock_event_device *ced)
259{
260 struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
261 int disabled = 0;
262
263 /* deal with old setting first */
264 switch (ced->mode) {
265 case CLOCK_EVT_MODE_PERIODIC:
266 case CLOCK_EVT_MODE_ONESHOT:
267 sh_tmu_disable(p);
268 disabled = 1;
269 break;
270 default:
271 break;
272 }
273
274 switch (mode) {
275 case CLOCK_EVT_MODE_PERIODIC:
276 pr_info("sh_tmu: %s used for periodic clock events\n",
277 ced->name);
278 sh_tmu_clock_event_start(p, 1);
279 break;
280 case CLOCK_EVT_MODE_ONESHOT:
281 pr_info("sh_tmu: %s used for oneshot clock events\n",
282 ced->name);
283 sh_tmu_clock_event_start(p, 0);
284 break;
285 case CLOCK_EVT_MODE_UNUSED:
286 if (!disabled)
287 sh_tmu_disable(p);
288 break;
289 case CLOCK_EVT_MODE_SHUTDOWN:
290 default:
291 break;
292 }
293}
294
295static int sh_tmu_clock_event_next(unsigned long delta,
296 struct clock_event_device *ced)
297{
298 struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
299
300 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
301
302 /* program new delta value */
303 sh_tmu_set_next(p, delta, 0);
304 return 0;
305}
306
307static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
308 char *name, unsigned long rating)
309{
310 struct clock_event_device *ced = &p->ced;
311 int ret;
312
313 memset(ced, 0, sizeof(*ced));
314
315 ced->name = name;
316 ced->features = CLOCK_EVT_FEAT_PERIODIC;
317 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
318 ced->rating = rating;
319 ced->cpumask = cpumask_of(0);
320 ced->set_next_event = sh_tmu_clock_event_next;
321 ced->set_mode = sh_tmu_clock_event_mode;
322
323 ret = setup_irq(p->irqaction.irq, &p->irqaction);
324 if (ret) {
325 pr_err("sh_tmu: failed to request irq %d\n",
326 p->irqaction.irq);
327 return;
328 }
329
330 pr_info("sh_tmu: %s used for clock events\n", ced->name);
331 clockevents_register_device(ced);
332}
333
334static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
335 unsigned long clockevent_rating,
336 unsigned long clocksource_rating)
337{
338 if (clockevent_rating)
339 sh_tmu_register_clockevent(p, name, clockevent_rating);
340 else if (clocksource_rating)
341 sh_tmu_register_clocksource(p, name, clocksource_rating);
342
343 return 0;
344}
345
346static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
347{
Paul Mundt46a12f72009-05-03 17:57:17 +0900348 struct sh_timer_config *cfg = pdev->dev.platform_data;
Magnus Damm9570ef22009-05-01 06:51:00 +0000349 struct resource *res;
350 int irq, ret;
351 ret = -ENXIO;
352
353 memset(p, 0, sizeof(*p));
354 p->pdev = pdev;
355
356 if (!cfg) {
357 dev_err(&p->pdev->dev, "missing platform data\n");
358 goto err0;
359 }
360
361 platform_set_drvdata(pdev, p);
362
363 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
364 if (!res) {
365 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
366 goto err0;
367 }
368
369 irq = platform_get_irq(p->pdev, 0);
370 if (irq < 0) {
371 dev_err(&p->pdev->dev, "failed to get irq\n");
372 goto err0;
373 }
374
375 /* map memory, let mapbase point to our channel */
376 p->mapbase = ioremap_nocache(res->start, resource_size(res));
377 if (p->mapbase == NULL) {
378 pr_err("sh_tmu: failed to remap I/O memory\n");
379 goto err0;
380 }
381
382 /* setup data for setup_irq() (too early for request_irq()) */
383 p->irqaction.name = cfg->name;
384 p->irqaction.handler = sh_tmu_interrupt;
385 p->irqaction.dev_id = p;
386 p->irqaction.irq = irq;
387 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
388 p->irqaction.mask = CPU_MASK_NONE;
389
390 /* get hold of clock */
391 p->clk = clk_get(&p->pdev->dev, cfg->clk);
392 if (IS_ERR(p->clk)) {
393 pr_err("sh_tmu: cannot get clock \"%s\"\n", cfg->clk);
394 ret = PTR_ERR(p->clk);
395 goto err1;
396 }
397
398 return sh_tmu_register(p, cfg->name,
399 cfg->clockevent_rating,
400 cfg->clocksource_rating);
401 err1:
402 iounmap(p->mapbase);
403 err0:
404 return ret;
405}
406
407static int __devinit sh_tmu_probe(struct platform_device *pdev)
408{
409 struct sh_tmu_priv *p = platform_get_drvdata(pdev);
Paul Mundt46a12f72009-05-03 17:57:17 +0900410 struct sh_timer_config *cfg = pdev->dev.platform_data;
Magnus Damm9570ef22009-05-01 06:51:00 +0000411 int ret;
412
413 if (p) {
414 pr_info("sh_tmu: %s kept as earlytimer\n", cfg->name);
415 return 0;
416 }
417
418 p = kmalloc(sizeof(*p), GFP_KERNEL);
419 if (p == NULL) {
420 dev_err(&pdev->dev, "failed to allocate driver data\n");
421 return -ENOMEM;
422 }
423
424 ret = sh_tmu_setup(p, pdev);
425 if (ret) {
426 kfree(p);
427 platform_set_drvdata(pdev, NULL);
428 }
429 return ret;
430}
431
432static int __devexit sh_tmu_remove(struct platform_device *pdev)
433{
434 return -EBUSY; /* cannot unregister clockevent and clocksource */
435}
436
437static struct platform_driver sh_tmu_device_driver = {
438 .probe = sh_tmu_probe,
439 .remove = __devexit_p(sh_tmu_remove),
440 .driver = {
441 .name = "sh_tmu",
442 }
443};
444
445static int __init sh_tmu_init(void)
446{
447 return platform_driver_register(&sh_tmu_device_driver);
448}
449
450static void __exit sh_tmu_exit(void)
451{
452 platform_driver_unregister(&sh_tmu_device_driver);
453}
454
455early_platform_init("earlytimer", &sh_tmu_device_driver);
456module_init(sh_tmu_init);
457module_exit(sh_tmu_exit);
458
459MODULE_AUTHOR("Magnus Damm");
460MODULE_DESCRIPTION("SuperH TMU Timer Driver");
461MODULE_LICENSE("GPL v2");