blob: 9e6bf0e311bb69e2857121be784c3e85060072b0 [file] [log] [blame]
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001/*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
40
41#include <dt-bindings/gpio/gpio.h>
42#include <dt-bindings/interrupt-controller/irq.h>
43#include <dt-bindings/interrupt-controller/arm-gic.h>
44#include <dt-bindings/pinctrl/rockchip.h>
45#include <dt-bindings/clock/rk3228-cru.h>
Caesar Wang77960312016-02-15 15:33:32 +080046#include <dt-bindings/thermal/thermal.h>
Jeffy Chen9848ebe2015-12-11 09:30:51 +080047#include "skeleton.dtsi"
48
49/ {
Jeffy Chen9848ebe2015-12-11 09:30:51 +080050 interrupt-parent = <&gic>;
51
52 aliases {
53 serial0 = &uart0;
54 serial1 = &uart1;
55 serial2 = &uart2;
56 };
57
58 cpus {
59 #address-cells = <1>;
60 #size-cells = <0>;
61
62 cpu0: cpu@f00 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a7";
65 reg = <0xf00>;
66 resets = <&cru SRST_CORE0>;
67 operating-points = <
68 /* KHz uV */
69 816000 1000000
70 >;
Caesar Wang77960312016-02-15 15:33:32 +080071 #cooling-cells = <2>; /* min followed by max */
Jeffy Chen9848ebe2015-12-11 09:30:51 +080072 clock-latency = <40000>;
73 clocks = <&cru ARMCLK>;
74 };
75
76 cpu1: cpu@f01 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a7";
79 reg = <0xf01>;
80 resets = <&cru SRST_CORE1>;
81 };
82
83 cpu2: cpu@f02 {
84 device_type = "cpu";
85 compatible = "arm,cortex-a7";
86 reg = <0xf02>;
87 resets = <&cru SRST_CORE2>;
88 };
89
90 cpu3: cpu@f03 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a7";
93 reg = <0xf03>;
94 resets = <&cru SRST_CORE3>;
95 };
96 };
97
98 amba {
Masahiro Yamada2ef7d5f2016-03-09 13:26:45 +090099 compatible = "simple-bus";
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges;
103
104 pdma: pdma@110f0000 {
105 compatible = "arm,pl330", "arm,primecell";
106 reg = <0x110f0000 0x4000>;
107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
109 #dma-cells = <1>;
110 clocks = <&cru ACLK_DMAC>;
111 clock-names = "apb_pclk";
112 };
113 };
114
115 arm-pmu {
116 compatible = "arm,cortex-a7-pmu";
117 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
121 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
122 };
123
124 timer {
125 compatible = "arm,armv7-timer";
126 arm,cpu-registers-not-fw-configured;
127 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
128 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
129 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
130 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
131 clock-frequency = <24000000>;
132 };
133
134 xin24m: oscillator {
135 compatible = "fixed-clock";
136 clock-frequency = <24000000>;
137 clock-output-names = "xin24m";
138 #clock-cells = <0>;
139 };
140
Xing Zhengccada242016-06-22 11:16:51 +0800141 i2s1: i2s1@100b0000 {
142 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
143 reg = <0x100b0000 0x4000>;
144 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
145 #address-cells = <1>;
146 #size-cells = <0>;
147 clock-names = "i2s_clk", "i2s_hclk";
148 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
149 dmas = <&pdma 14>, <&pdma 15>;
150 dma-names = "tx", "rx";
151 pinctrl-names = "default";
152 pinctrl-0 = <&i2s1_bus>;
153 status = "disabled";
154 };
155
156 i2s0: i2s0@100c0000 {
157 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
158 reg = <0x100c0000 0x4000>;
159 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 clock-names = "i2s_clk", "i2s_hclk";
163 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
164 dmas = <&pdma 11>, <&pdma 12>;
165 dma-names = "tx", "rx";
166 status = "disabled";
167 };
168
169 i2s2: i2s2@100e0000 {
170 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
171 reg = <0x100e0000 0x4000>;
172 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
173 #address-cells = <1>;
174 #size-cells = <0>;
175 clock-names = "i2s_clk", "i2s_hclk";
176 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
177 dmas = <&pdma 0>, <&pdma 1>;
178 dma-names = "tx", "rx";
179 status = "disabled";
180 };
181
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800182 grf: syscon@11000000 {
183 compatible = "syscon";
184 reg = <0x11000000 0x1000>;
185 };
186
187 uart0: serial@11010000 {
188 compatible = "snps,dw-apb-uart";
189 reg = <0x11010000 0x100>;
190 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
191 clock-frequency = <24000000>;
192 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
193 clock-names = "baudclk", "apb_pclk";
194 pinctrl-names = "default";
195 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
196 reg-shift = <2>;
197 reg-io-width = <4>;
198 status = "disabled";
199 };
200
201 uart1: serial@11020000 {
202 compatible = "snps,dw-apb-uart";
203 reg = <0x11020000 0x100>;
204 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
205 clock-frequency = <24000000>;
206 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
207 clock-names = "baudclk", "apb_pclk";
208 pinctrl-names = "default";
209 pinctrl-0 = <&uart1_xfer>;
210 reg-shift = <2>;
211 reg-io-width = <4>;
212 status = "disabled";
213 };
214
215 uart2: serial@11030000 {
216 compatible = "snps,dw-apb-uart";
217 reg = <0x11030000 0x100>;
218 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
219 clock-frequency = <24000000>;
220 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
221 clock-names = "baudclk", "apb_pclk";
222 pinctrl-names = "default";
223 pinctrl-0 = <&uart2_xfer>;
224 reg-shift = <2>;
225 reg-io-width = <4>;
226 status = "disabled";
227 };
228
Yakir Yangd549df42016-03-14 11:11:42 +0800229 i2c0: i2c@11050000 {
230 compatible = "rockchip,rk3228-i2c";
231 reg = <0x11050000 0x1000>;
232 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
233 #address-cells = <1>;
234 #size-cells = <0>;
235 clock-names = "i2c";
236 clocks = <&cru PCLK_I2C0>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&i2c0_xfer>;
239 status = "disabled";
240 };
241
242 i2c1: i2c@11060000 {
243 compatible = "rockchip,rk3228-i2c";
244 reg = <0x11060000 0x1000>;
245 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 clock-names = "i2c";
249 clocks = <&cru PCLK_I2C1>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&i2c1_xfer>;
252 status = "disabled";
253 };
254
255 i2c2: i2c@11070000 {
256 compatible = "rockchip,rk3228-i2c";
257 reg = <0x11070000 0x1000>;
258 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
259 #address-cells = <1>;
260 #size-cells = <0>;
261 clock-names = "i2c";
262 clocks = <&cru PCLK_I2C2>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&i2c2_xfer>;
265 status = "disabled";
266 };
267
268 i2c3: i2c@11080000 {
269 compatible = "rockchip,rk3228-i2c";
270 reg = <0x11080000 0x1000>;
271 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
272 #address-cells = <1>;
273 #size-cells = <0>;
274 clock-names = "i2c";
275 clocks = <&cru PCLK_I2C3>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&i2c3_xfer>;
278 status = "disabled";
279 };
280
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800281 pwm0: pwm@110b0000 {
282 compatible = "rockchip,rk3288-pwm";
283 reg = <0x110b0000 0x10>;
284 #pwm-cells = <3>;
285 clocks = <&cru PCLK_PWM>;
286 clock-names = "pwm";
287 pinctrl-names = "default";
288 pinctrl-0 = <&pwm0_pin>;
289 status = "disabled";
290 };
291
292 pwm1: pwm@110b0010 {
293 compatible = "rockchip,rk3288-pwm";
294 reg = <0x110b0010 0x10>;
295 #pwm-cells = <3>;
296 clocks = <&cru PCLK_PWM>;
297 clock-names = "pwm";
298 pinctrl-names = "default";
299 pinctrl-0 = <&pwm1_pin>;
300 status = "disabled";
301 };
302
303 pwm2: pwm@110b0020 {
304 compatible = "rockchip,rk3288-pwm";
305 reg = <0x110b0020 0x10>;
306 #pwm-cells = <3>;
307 clocks = <&cru PCLK_PWM>;
308 clock-names = "pwm";
309 pinctrl-names = "default";
310 pinctrl-0 = <&pwm2_pin>;
311 status = "disabled";
312 };
313
314 pwm3: pwm@110b0030 {
315 compatible = "rockchip,rk3288-pwm";
316 reg = <0x110b0030 0x10>;
317 #pwm-cells = <2>;
318 clocks = <&cru PCLK_PWM>;
319 clock-names = "pwm";
320 pinctrl-names = "default";
321 pinctrl-0 = <&pwm3_pin>;
322 status = "disabled";
323 };
324
325 timer: timer@110c0000 {
326 compatible = "rockchip,rk3288-timer";
327 reg = <0x110c0000 0x20>;
328 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&xin24m>, <&cru PCLK_TIMER>;
330 clock-names = "timer", "pclk";
331 };
332
333 cru: clock-controller@110e0000 {
334 compatible = "rockchip,rk3228-cru";
335 reg = <0x110e0000 0x1000>;
336 rockchip,grf = <&grf>;
337 #clock-cells = <1>;
338 #reset-cells = <1>;
339 assigned-clocks = <&cru PLL_GPLL>;
340 assigned-clock-rates = <594000000>;
341 };
342
Caesar Wang77960312016-02-15 15:33:32 +0800343 thermal-zones {
344 cpu_thermal: cpu-thermal {
345 polling-delay-passive = <100>; /* milliseconds */
346 polling-delay = <5000>; /* milliseconds */
347
348 thermal-sensors = <&tsadc 0>;
349
350 trips {
351 cpu_alert0: cpu_alert0 {
352 temperature = <70000>; /* millicelsius */
353 hysteresis = <2000>; /* millicelsius */
354 type = "passive";
355 };
356 cpu_alert1: cpu_alert1 {
357 temperature = <75000>; /* millicelsius */
358 hysteresis = <2000>; /* millicelsius */
359 type = "passive";
360 };
361 cpu_crit: cpu_crit {
362 temperature = <90000>; /* millicelsius */
363 hysteresis = <2000>; /* millicelsius */
364 type = "critical";
365 };
366 };
367
368 cooling-maps {
369 map0 {
370 trip = <&cpu_alert0>;
371 cooling-device =
372 <&cpu0 THERMAL_NO_LIMIT 6>;
373 };
374 map1 {
375 trip = <&cpu_alert1>;
376 cooling-device =
377 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
378 };
379 };
380 };
381 };
382
383 tsadc: tsadc@11150000 {
384 compatible = "rockchip,rk3228-tsadc";
385 reg = <0x11150000 0x100>;
386 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
388 clock-names = "tsadc", "apb_pclk";
389 resets = <&cru SRST_TSADC>;
390 reset-names = "tsadc-apb";
391 pinctrl-names = "init", "default", "sleep";
392 pinctrl-0 = <&otp_gpio>;
393 pinctrl-1 = <&otp_out>;
394 pinctrl-2 = <&otp_gpio>;
395 #thermal-sensor-cells = <0>;
396 rockchip,hw-tshut-temp = <95000>;
397 status = "disabled";
398 };
399
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800400 emmc: dwmmc@30020000 {
401 compatible = "rockchip,rk3288-dw-mshc";
402 reg = <0x30020000 0x4000>;
403 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
404 clock-frequency = <37500000>;
405 clock-freq-min-max = <400000 37500000>;
406 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
407 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
408 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
409 bus-width = <8>;
410 default-sample-phase = <158>;
411 num-slots = <1>;
412 fifo-depth = <0x100>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
415 status = "disabled";
416 };
417
Xing Zheng5d3d7c72016-06-22 11:16:52 +0800418 gmac: ethernet@30200000 {
419 compatible = "rockchip,rk3228-gmac";
420 reg = <0x30200000 0x10000>;
421 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
422 interrupt-names = "macirq";
423 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
424 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
425 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
426 <&cru PCLK_GMAC>;
427 clock-names = "stmmaceth", "mac_clk_rx",
428 "mac_clk_tx", "clk_mac_ref",
429 "clk_mac_refout", "aclk_mac",
430 "pclk_mac";
431 resets = <&cru SRST_GMAC>;
432 reset-names = "stmmaceth";
433 rockchip,grf = <&grf>;
434 status = "disabled";
435 };
436
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800437 gic: interrupt-controller@32010000 {
438 compatible = "arm,gic-400";
439 interrupt-controller;
440 #interrupt-cells = <3>;
441 #address-cells = <0>;
442
443 reg = <0x32011000 0x1000>,
444 <0x32012000 0x1000>,
445 <0x32014000 0x2000>,
446 <0x32016000 0x2000>;
447 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
448 };
449
450 pinctrl: pinctrl {
451 compatible = "rockchip,rk3228-pinctrl";
452 rockchip,grf = <&grf>;
453 #address-cells = <1>;
454 #size-cells = <1>;
455 ranges;
456
457 gpio0: gpio0@11110000 {
458 compatible = "rockchip,gpio-bank";
459 reg = <0x11110000 0x100>;
460 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&cru PCLK_GPIO0>;
462
463 gpio-controller;
464 #gpio-cells = <2>;
465
466 interrupt-controller;
467 #interrupt-cells = <2>;
468 };
469
470 gpio1: gpio1@11120000 {
471 compatible = "rockchip,gpio-bank";
472 reg = <0x11120000 0x100>;
473 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&cru PCLK_GPIO1>;
475
476 gpio-controller;
477 #gpio-cells = <2>;
478
479 interrupt-controller;
480 #interrupt-cells = <2>;
481 };
482
483 gpio2: gpio2@11130000 {
484 compatible = "rockchip,gpio-bank";
485 reg = <0x11130000 0x100>;
486 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&cru PCLK_GPIO2>;
488
489 gpio-controller;
490 #gpio-cells = <2>;
491
492 interrupt-controller;
493 #interrupt-cells = <2>;
494 };
495
496 gpio3: gpio3@11140000 {
497 compatible = "rockchip,gpio-bank";
498 reg = <0x11140000 0x100>;
499 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&cru PCLK_GPIO3>;
501
502 gpio-controller;
503 #gpio-cells = <2>;
504
505 interrupt-controller;
506 #interrupt-cells = <2>;
507 };
508
509 pcfg_pull_up: pcfg-pull-up {
510 bias-pull-up;
511 };
512
513 pcfg_pull_down: pcfg-pull-down {
514 bias-pull-down;
515 };
516
517 pcfg_pull_none: pcfg-pull-none {
518 bias-disable;
519 };
520
Xing Zheng5d3d7c72016-06-22 11:16:52 +0800521 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
522 drive-strength = <12>;
523 };
524
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800525 emmc {
526 emmc_clk: emmc-clk {
527 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
528 };
529
530 emmc_cmd: emmc-cmd {
531 rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
532 };
533
534 emmc_bus8: emmc-bus8 {
535 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
536 <1 25 RK_FUNC_2 &pcfg_pull_none>,
537 <1 26 RK_FUNC_2 &pcfg_pull_none>,
538 <1 27 RK_FUNC_2 &pcfg_pull_none>,
539 <1 28 RK_FUNC_2 &pcfg_pull_none>,
540 <1 29 RK_FUNC_2 &pcfg_pull_none>,
541 <1 30 RK_FUNC_2 &pcfg_pull_none>,
542 <1 31 RK_FUNC_2 &pcfg_pull_none>;
543 };
544 };
545
Xing Zheng5d3d7c72016-06-22 11:16:52 +0800546 gmac {
547 rgmii_pins: rgmii-pins {
548 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
549 <2 12 RK_FUNC_1 &pcfg_pull_none>,
550 <2 25 RK_FUNC_1 &pcfg_pull_none>,
551 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
552 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
553 <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
554 <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
555 <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
556 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
557 <2 17 RK_FUNC_1 &pcfg_pull_none>,
558 <2 16 RK_FUNC_1 &pcfg_pull_none>,
559 <2 21 RK_FUNC_2 &pcfg_pull_none>,
560 <2 20 RK_FUNC_2 &pcfg_pull_none>,
561 <2 11 RK_FUNC_1 &pcfg_pull_none>,
562 <2 8 RK_FUNC_1 &pcfg_pull_none>;
563 };
564
565 rmii_pins: rmii-pins {
566 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
567 <2 12 RK_FUNC_1 &pcfg_pull_none>,
568 <2 25 RK_FUNC_1 &pcfg_pull_none>,
569 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
570 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
571 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
572 <2 17 RK_FUNC_1 &pcfg_pull_none>,
573 <2 16 RK_FUNC_1 &pcfg_pull_none>,
574 <2 8 RK_FUNC_1 &pcfg_pull_none>,
575 <2 15 RK_FUNC_1 &pcfg_pull_none>;
576 };
577
578 phy_pins: phy-pins {
579 rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
580 <2 8 RK_FUNC_2 &pcfg_pull_none>;
581 };
582 };
583
Yakir Yangd549df42016-03-14 11:11:42 +0800584 i2c0 {
585 i2c0_xfer: i2c0-xfer {
586 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
587 <0 1 RK_FUNC_1 &pcfg_pull_none>;
588 };
589 };
590
591 i2c1 {
592 i2c1_xfer: i2c1-xfer {
593 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
594 <0 3 RK_FUNC_1 &pcfg_pull_none>;
595 };
596 };
597
598 i2c2 {
599 i2c2_xfer: i2c2-xfer {
600 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
601 <2 21 RK_FUNC_1 &pcfg_pull_none>;
602 };
603 };
604
605 i2c3 {
606 i2c3_xfer: i2c3-xfer {
607 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
608 <0 7 RK_FUNC_1 &pcfg_pull_none>;
609 };
610 };
611
Xing Zhengccada242016-06-22 11:16:51 +0800612 i2s1 {
613 i2s1_bus: i2s1-bus {
614 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
615 <0 9 RK_FUNC_1 &pcfg_pull_none>,
616 <0 11 RK_FUNC_1 &pcfg_pull_none>,
617 <0 12 RK_FUNC_1 &pcfg_pull_none>,
618 <0 13 RK_FUNC_1 &pcfg_pull_none>,
619 <0 14 RK_FUNC_1 &pcfg_pull_none>,
620 <1 2 RK_FUNC_1 &pcfg_pull_none>,
621 <1 4 RK_FUNC_1 &pcfg_pull_none>,
622 <1 5 RK_FUNC_1 &pcfg_pull_none>;
623 };
624 };
625
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800626 pwm0 {
627 pwm0_pin: pwm0-pin {
628 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
629 };
630 };
631
632 pwm1 {
633 pwm1_pin: pwm1-pin {
634 rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
635 };
636 };
637
638 pwm2 {
639 pwm2_pin: pwm2-pin {
640 rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
641 };
642 };
643
644 pwm3 {
645 pwm3_pin: pwm3-pin {
646 rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
647 };
648 };
649
Caesar Wang77960312016-02-15 15:33:32 +0800650 tsadc {
651 otp_gpio: otp-gpio {
652 rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
653 };
654
655 otp_out: otp-out {
656 rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
657 };
658 };
659
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800660 uart0 {
661 uart0_xfer: uart0-xfer {
662 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
663 <2 27 RK_FUNC_1 &pcfg_pull_none>;
664 };
665
666 uart0_cts: uart0-cts {
667 rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
668 };
669
670 uart0_rts: uart0-rts {
671 rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
672 };
673 };
674
675 uart1 {
676 uart1_xfer: uart1-xfer {
677 rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
678 <1 10 RK_FUNC_1 &pcfg_pull_none>;
679 };
680
681 uart1_cts: uart1-cts {
682 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
683 };
684
685 uart1_rts: uart1-rts {
686 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
687 };
688 };
689
690 uart2 {
691 uart2_xfer: uart2-xfer {
692 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
693 <1 19 RK_FUNC_2 &pcfg_pull_none>;
694 };
695
696 uart2_cts: uart2-cts {
697 rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
698 };
699
700 uart2_rts: uart2-rts {
701 rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
702 };
703 };
704 };
705};