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Maxime Coquelin338a6aa2015-06-03 16:54:02 +02001/*
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include "armv7-m.dtsi"
Maxime Coquelin2dbd0592015-10-14 18:12:10 +020049#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
Maxime Coquelin338a6aa2015-06-03 16:54:02 +020050
51/ {
52 clocks {
Daniel Thompson9dc24a22015-06-10 22:09:00 +020053 clk_hse: clk-hse {
Maxime Coquelin338a6aa2015-06-03 16:54:02 +020054 #clock-cells = <0>;
55 compatible = "fixed-clock";
Daniel Thompson9dc24a22015-06-10 22:09:00 +020056 clock-frequency = <0>;
Maxime Coquelin338a6aa2015-06-03 16:54:02 +020057 };
58 };
59
60 soc {
Maxime Coquelinb2aa7f72015-12-02 17:47:17 +010061 dma-ranges = <0xc0000000 0x0 0x10000000>;
62
Maxime Coquelin338a6aa2015-06-03 16:54:02 +020063 timer2: timer@40000000 {
64 compatible = "st,stm32-timer";
65 reg = <0x40000000 0x400>;
66 interrupts = <28>;
Daniel Thompson9dc24a22015-06-10 22:09:00 +020067 clocks = <&rcc 0 128>;
Maxime Coquelin338a6aa2015-06-03 16:54:02 +020068 status = "disabled";
69 };
70
71 timer3: timer@40000400 {
72 compatible = "st,stm32-timer";
73 reg = <0x40000400 0x400>;
74 interrupts = <29>;
Daniel Thompson9dc24a22015-06-10 22:09:00 +020075 clocks = <&rcc 0 129>;
Maxime Coquelin338a6aa2015-06-03 16:54:02 +020076 status = "disabled";
77 };
78
79 timer4: timer@40000800 {
80 compatible = "st,stm32-timer";
81 reg = <0x40000800 0x400>;
82 interrupts = <30>;
Daniel Thompson9dc24a22015-06-10 22:09:00 +020083 clocks = <&rcc 0 130>;
Maxime Coquelin338a6aa2015-06-03 16:54:02 +020084 status = "disabled";
85 };
86
87 timer5: timer@40000c00 {
88 compatible = "st,stm32-timer";
89 reg = <0x40000c00 0x400>;
90 interrupts = <50>;
Daniel Thompson9dc24a22015-06-10 22:09:00 +020091 clocks = <&rcc 0 131>;
Maxime Coquelin338a6aa2015-06-03 16:54:02 +020092 };
93
94 timer6: timer@40001000 {
95 compatible = "st,stm32-timer";
96 reg = <0x40001000 0x400>;
97 interrupts = <54>;
Daniel Thompson9dc24a22015-06-10 22:09:00 +020098 clocks = <&rcc 0 132>;
Maxime Coquelin338a6aa2015-06-03 16:54:02 +020099 status = "disabled";
100 };
101
102 timer7: timer@40001400 {
103 compatible = "st,stm32-timer";
104 reg = <0x40001400 0x400>;
105 interrupts = <55>;
Daniel Thompson9dc24a22015-06-10 22:09:00 +0200106 clocks = <&rcc 0 133>;
Maxime Coquelin338a6aa2015-06-03 16:54:02 +0200107 status = "disabled";
108 };
109
110 usart2: serial@40004400 {
111 compatible = "st,stm32-usart", "st,stm32-uart";
112 reg = <0x40004400 0x400>;
113 interrupts = <38>;
Daniel Thompson9dc24a22015-06-10 22:09:00 +0200114 clocks = <&rcc 0 145>;
Maxime Coquelin338a6aa2015-06-03 16:54:02 +0200115 status = "disabled";
116 };
117
118 usart3: serial@40004800 {
119 compatible = "st,stm32-usart", "st,stm32-uart";
120 reg = <0x40004800 0x400>;
121 interrupts = <39>;
Daniel Thompson9dc24a22015-06-10 22:09:00 +0200122 clocks = <&rcc 0 146>;
Maxime Coquelin338a6aa2015-06-03 16:54:02 +0200123 status = "disabled";
124 };
125
126 usart4: serial@40004c00 {
127 compatible = "st,stm32-uart";
128 reg = <0x40004c00 0x400>;
129 interrupts = <52>;
Daniel Thompson9dc24a22015-06-10 22:09:00 +0200130 clocks = <&rcc 0 147>;
Maxime Coquelin338a6aa2015-06-03 16:54:02 +0200131 status = "disabled";
132 };
133
134 usart5: serial@40005000 {
135 compatible = "st,stm32-uart";
136 reg = <0x40005000 0x400>;
137 interrupts = <53>;
Daniel Thompson9dc24a22015-06-10 22:09:00 +0200138 clocks = <&rcc 0 148>;
Maxime Coquelin338a6aa2015-06-03 16:54:02 +0200139 status = "disabled";
140 };
141
142 usart7: serial@40007800 {
143 compatible = "st,stm32-usart", "st,stm32-uart";
144 reg = <0x40007800 0x400>;
145 interrupts = <82>;
Daniel Thompson9dc24a22015-06-10 22:09:00 +0200146 clocks = <&rcc 0 158>;
Maxime Coquelin338a6aa2015-06-03 16:54:02 +0200147 status = "disabled";
148 };
149
150 usart8: serial@40007c00 {
151 compatible = "st,stm32-usart", "st,stm32-uart";
152 reg = <0x40007c00 0x400>;
153 interrupts = <83>;
Daniel Thompson9dc24a22015-06-10 22:09:00 +0200154 clocks = <&rcc 0 159>;
Maxime Coquelin338a6aa2015-06-03 16:54:02 +0200155 status = "disabled";
156 };
157
158 usart1: serial@40011000 {
159 compatible = "st,stm32-usart", "st,stm32-uart";
160 reg = <0x40011000 0x400>;
161 interrupts = <37>;
Daniel Thompson9dc24a22015-06-10 22:09:00 +0200162 clocks = <&rcc 0 164>;
Maxime Coquelin338a6aa2015-06-03 16:54:02 +0200163 status = "disabled";
164 };
165
166 usart6: serial@40011400 {
167 compatible = "st,stm32-usart", "st,stm32-uart";
168 reg = <0x40011400 0x400>;
169 interrupts = <71>;
Daniel Thompson9dc24a22015-06-10 22:09:00 +0200170 clocks = <&rcc 0 165>;
Maxime Coquelin338a6aa2015-06-03 16:54:02 +0200171 status = "disabled";
172 };
Daniel Thompson9dc24a22015-06-10 22:09:00 +0200173
Alexandre TORGUEe78b6552016-02-29 17:29:00 +0100174 syscfg: system-config@40013800 {
175 compatible = "syscon";
176 reg = <0x40013800 0x400>;
177 };
178
Maxime Coquelin2dbd0592015-10-14 18:12:10 +0200179 pin-controller {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 compatible = "st,stm32f429-pinctrl";
183 ranges = <0 0x40020000 0x3000>;
184 pins-are-numbered;
185
186 gpioa: gpio@40020000 {
187 gpio-controller;
188 #gpio-cells = <2>;
189 reg = <0x0 0x400>;
Maxime Coquelina985b662016-02-23 13:35:25 +0100190 clocks = <&rcc 0 0>;
Maxime Coquelin2dbd0592015-10-14 18:12:10 +0200191 st,bank-name = "GPIOA";
192 };
193
194 gpiob: gpio@40020400 {
195 gpio-controller;
196 #gpio-cells = <2>;
197 reg = <0x400 0x400>;
Maxime Coquelina985b662016-02-23 13:35:25 +0100198 clocks = <&rcc 0 1>;
Maxime Coquelin2dbd0592015-10-14 18:12:10 +0200199 st,bank-name = "GPIOB";
200 };
201
202 gpioc: gpio@40020800 {
203 gpio-controller;
204 #gpio-cells = <2>;
205 reg = <0x800 0x400>;
Maxime Coquelina985b662016-02-23 13:35:25 +0100206 clocks = <&rcc 0 2>;
Maxime Coquelin2dbd0592015-10-14 18:12:10 +0200207 st,bank-name = "GPIOC";
208 };
209
210 gpiod: gpio@40020c00 {
211 gpio-controller;
212 #gpio-cells = <2>;
213 reg = <0xc00 0x400>;
Maxime Coquelina985b662016-02-23 13:35:25 +0100214 clocks = <&rcc 0 3>;
Maxime Coquelin2dbd0592015-10-14 18:12:10 +0200215 st,bank-name = "GPIOD";
216 };
217
218 gpioe: gpio@40021000 {
219 gpio-controller;
220 #gpio-cells = <2>;
221 reg = <0x1000 0x400>;
Maxime Coquelina985b662016-02-23 13:35:25 +0100222 clocks = <&rcc 0 4>;
Maxime Coquelin2dbd0592015-10-14 18:12:10 +0200223 st,bank-name = "GPIOE";
224 };
225
226 gpiof: gpio@40021400 {
227 gpio-controller;
228 #gpio-cells = <2>;
229 reg = <0x1400 0x400>;
Maxime Coquelina985b662016-02-23 13:35:25 +0100230 clocks = <&rcc 0 5>;
Maxime Coquelin2dbd0592015-10-14 18:12:10 +0200231 st,bank-name = "GPIOF";
232 };
233
234 gpiog: gpio@40021800 {
235 gpio-controller;
236 #gpio-cells = <2>;
237 reg = <0x1800 0x400>;
Maxime Coquelina985b662016-02-23 13:35:25 +0100238 clocks = <&rcc 0 6>;
Maxime Coquelin2dbd0592015-10-14 18:12:10 +0200239 st,bank-name = "GPIOG";
240 };
241
242 gpioh: gpio@40021c00 {
243 gpio-controller;
244 #gpio-cells = <2>;
245 reg = <0x1c00 0x400>;
Maxime Coquelina985b662016-02-23 13:35:25 +0100246 clocks = <&rcc 0 7>;
Maxime Coquelin2dbd0592015-10-14 18:12:10 +0200247 st,bank-name = "GPIOH";
248 };
249
250 gpioi: gpio@40022000 {
251 gpio-controller;
252 #gpio-cells = <2>;
253 reg = <0x2000 0x400>;
Maxime Coquelina985b662016-02-23 13:35:25 +0100254 clocks = <&rcc 0 8>;
Maxime Coquelin2dbd0592015-10-14 18:12:10 +0200255 st,bank-name = "GPIOI";
256 };
257
258 gpioj: gpio@40022400 {
259 gpio-controller;
260 #gpio-cells = <2>;
261 reg = <0x2400 0x400>;
Maxime Coquelina985b662016-02-23 13:35:25 +0100262 clocks = <&rcc 0 9>;
Maxime Coquelin2dbd0592015-10-14 18:12:10 +0200263 st,bank-name = "GPIOJ";
264 };
265
266 gpiok: gpio@40022800 {
267 gpio-controller;
268 #gpio-cells = <2>;
269 reg = <0x2800 0x400>;
Maxime Coquelina985b662016-02-23 13:35:25 +0100270 clocks = <&rcc 0 10>;
Maxime Coquelin2dbd0592015-10-14 18:12:10 +0200271 st,bank-name = "GPIOK";
272 };
Maxime Coquelin521df6f2015-10-14 18:15:04 +0200273
274 usart1_pins_a: usart1@0 {
275 pins1 {
276 pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
277 bias-disable;
278 drive-push-pull;
279 slew-rate = <0>;
280 };
281 pins2 {
282 pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
283 bias-disable;
284 };
285 };
Maxime Coquelinc8cc1b72016-02-23 17:11:42 +0100286
287 usbotg_hs_pins_a: usbotg_hs@0 {
288 pins {
289 pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
290 <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
291 <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
292 <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
293 <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
294 <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
295 <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
296 <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
297 <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
298 <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
299 <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
300 <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
301 bias-disable;
302 drive-push-pull;
303 slew-rate = <2>;
304 };
305 };
Alexandre TORGUE9ee33d62016-02-29 17:29:00 +0100306
307 ethernet0_mii: mii@0 {
308 pins {
309 pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
310 <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
311 <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
312 <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
313 <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
314 <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
315 <STM32F429_PA2_FUNC_ETH_MDIO>,
316 <STM32F429_PC1_FUNC_ETH_MDC>,
317 <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
318 <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
319 <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
320 <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
321 <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
322 <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
323 slew-rate = <2>;
324 };
325 };
Maxime Coquelin2dbd0592015-10-14 18:12:10 +0200326 };
327
Daniel Thompson9dc24a22015-06-10 22:09:00 +0200328 rcc: rcc@40023810 {
329 #clock-cells = <2>;
330 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
331 reg = <0x40023800 0x400>;
332 clocks = <&clk_hse>;
333 };
Daniel Thompsonb47c9fa2015-10-12 09:21:30 +0100334
M'boumba Cedric Madianga9ee9e282015-10-16 15:59:00 +0200335 dma1: dma-controller@40026000 {
336 compatible = "st,stm32-dma";
337 reg = <0x40026000 0x400>;
338 interrupts = <11>,
339 <12>,
340 <13>,
341 <14>,
342 <15>,
343 <16>,
344 <17>,
345 <47>;
346 clocks = <&rcc 0 21>;
347 #dma-cells = <4>;
348 };
349
350 dma2: dma-controller@40026400 {
351 compatible = "st,stm32-dma";
352 reg = <0x40026400 0x400>;
353 interrupts = <56>,
354 <57>,
355 <58>,
356 <59>,
357 <60>,
358 <68>,
359 <69>,
360 <70>;
361 clocks = <&rcc 0 22>;
362 #dma-cells = <4>;
363 st,mem2mem;
364 };
365
Alexandre TORGUE9ee33d62016-02-29 17:29:00 +0100366 ethernet0: dwmac@40028000 {
367 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
368 reg = <0x40028000 0x8000>;
369 reg-names = "stmmaceth";
370 interrupts = <61>, <62>;
371 interrupt-names = "macirq", "eth_wake_irq";
372 clock-names = "stmmaceth", "tx-clk", "rx-clk";
373 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
374 st,syscon = <&syscfg 0x4>;
375 snps,pbl = <8>;
376 snps,mixed-burst;
377 dma-ranges;
378 status = "disabled";
379 };
380
Maxime Coquelinc8cc1b72016-02-23 17:11:42 +0100381 usbotg_hs: usb@40040000 {
382 compatible = "snps,dwc2";
383 dma-ranges;
384 reg = <0x40040000 0x40000>;
385 interrupts = <77>;
386 clocks = <&rcc 0 29>;
387 clock-names = "otg";
388 status = "disabled";
389 };
390
Daniel Thompsonb47c9fa2015-10-12 09:21:30 +0100391 rng: rng@50060800 {
392 compatible = "st,stm32-rng";
393 reg = <0x50060800 0x400>;
394 interrupts = <80>;
395 clocks = <&rcc 0 38>;
396 };
Maxime Coquelin338a6aa2015-06-03 16:54:02 +0200397 };
398};
399
400&systick {
Daniel Thompson9dc24a22015-06-10 22:09:00 +0200401 clocks = <&rcc 1 0>;
Maxime Coquelin338a6aa2015-06-03 16:54:02 +0200402 status = "okay";
403};