Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 473359bc28e193031a76d99f71e8b6c4808719a6 / . / drivers / gpu / drm / radeon / cikd.h
blob: 6a92f491cb91e35a9729fc82d8557cf71cf03b3d [file] [log] [blame]
Alex Deucher8cc1a532013-04-09 12:41:24 -0400[diff] [blame]1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#ifndef CIK_H
25#define CIK_H
26
27#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
28
29#define CIK_RB_BITMAP_WIDTH_PER_SH 2
30
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]31/* DIDT IND registers */
32#define DIDT_SQ_CTRL0 0x0
33# define DIDT_CTRL_EN (1 << 0)
34#define DIDT_DB_CTRL0 0x20
35#define DIDT_TD_CTRL0 0x40
36#define DIDT_TCP_CTRL0 0x60
37
Alex Deucher2c679122013-04-09 13:32:18 -0400[diff] [blame]38/* SMC IND registers */
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]39#define DPM_TABLE_475 0x3F768
40# define SamuBootLevel(x) ((x) << 0)
41# define SamuBootLevel_MASK 0x000000ff
42# define SamuBootLevel_SHIFT 0
43# define AcpBootLevel(x) ((x) << 8)
44# define AcpBootLevel_MASK 0x0000ff00
45# define AcpBootLevel_SHIFT 8
46# define VceBootLevel(x) ((x) << 16)
47# define VceBootLevel_MASK 0x00ff0000
48# define VceBootLevel_SHIFT 16
49# define UvdBootLevel(x) ((x) << 24)
50# define UvdBootLevel_MASK 0xff000000
51# define UvdBootLevel_SHIFT 24
52
53#define FIRMWARE_FLAGS 0x3F800
54# define INTERRUPTS_ENABLED (1 << 0)
55
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]56#define NB_DPM_CONFIG_1 0x3F9E8
57# define Dpm0PgNbPsLo(x) ((x) << 0)
58# define Dpm0PgNbPsLo_MASK 0x000000ff
59# define Dpm0PgNbPsLo_SHIFT 0
60# define Dpm0PgNbPsHi(x) ((x) << 8)
61# define Dpm0PgNbPsHi_MASK 0x0000ff00
62# define Dpm0PgNbPsHi_SHIFT 8
63# define DpmXNbPsLo(x) ((x) << 16)
64# define DpmXNbPsLo_MASK 0x00ff0000
65# define DpmXNbPsLo_SHIFT 16
66# define DpmXNbPsHi(x) ((x) << 24)
67# define DpmXNbPsHi_MASK 0xff000000
68# define DpmXNbPsHi_SHIFT 24
69
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]70#define SMC_SYSCON_RESET_CNTL 0x80000000
71# define RST_REG (1 << 0)
72#define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
73# define CK_DISABLE (1 << 0)
74# define CKEN (1 << 24)
75
76#define SMC_SYSCON_MISC_CNTL 0x80000010
77
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]78#define SMC_SYSCON_MSG_ARG_0 0x80000068
79
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]80#define SMC_PC_C 0x80000370
81
82#define SMC_SCRATCH9 0x80000424
83
84#define RCU_UC_EVENTS 0xC0000004
85# define BOOT_SEQ_DONE (1 << 7)
86
Alex Deucher2c679122013-04-09 13:32:18 -0400[diff] [blame]87#define GENERAL_PWRMGT 0xC0200000
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]88# define GLOBAL_PWRMGT_EN (1 << 0)
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]89# define STATIC_PM_EN (1 << 1)
90# define THERMAL_PROTECTION_DIS (1 << 2)
91# define THERMAL_PROTECTION_TYPE (1 << 3)
92# define SW_SMIO_INDEX(x) ((x) << 6)
93# define SW_SMIO_INDEX_MASK (1 << 6)
94# define SW_SMIO_INDEX_SHIFT 6
95# define VOLT_PWRMGT_EN (1 << 10)
Alex Deucher2c679122013-04-09 13:32:18 -0400[diff] [blame]96# define GPU_COUNTER_CLK (1 << 15)
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]97# define DYN_SPREAD_SPECTRUM_EN (1 << 23)
98
99#define CNB_PWRMGT_CNTL 0xC0200004
100# define GNB_SLOW_MODE(x) ((x) << 0)
101# define GNB_SLOW_MODE_MASK (3 << 0)
102# define GNB_SLOW_MODE_SHIFT 0
103# define GNB_SLOW (1 << 2)
104# define FORCE_NB_PS1 (1 << 3)
105# define DPM_ENABLED (1 << 4)
Alex Deucher2c679122013-04-09 13:32:18 -0400[diff] [blame]106
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]107#define SCLK_PWRMGT_CNTL 0xC0200008
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]108# define SCLK_PWRMGT_OFF (1 << 0)
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]109# define RESET_BUSY_CNT (1 << 4)
110# define RESET_SCLK_CNT (1 << 5)
111# define DYNAMIC_PM_EN (1 << 21)
112
Alex Deucher94b4adc2013-07-15 17:34:33 -0400[diff] [blame]113#define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014
114# define CURRENT_STATE_MASK (0xf << 4)
115# define CURRENT_STATE_SHIFT 4
116# define CURR_MCLK_INDEX_MASK (0xf << 8)
117# define CURR_MCLK_INDEX_SHIFT 8
118# define CURR_SCLK_INDEX_MASK (0x1f << 16)
119# define CURR_SCLK_INDEX_SHIFT 16
120
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]121#define CG_SSP 0xC0200044
122# define SST(x) ((x) << 0)
123# define SST_MASK (0xffff << 0)
124# define SSTU(x) ((x) << 16)
125# define SSTU_MASK (0xf << 16)
126
127#define CG_DISPLAY_GAP_CNTL 0xC0200060
128# define DISP_GAP(x) ((x) << 0)
129# define DISP_GAP_MASK (3 << 0)
130# define VBI_TIMER_COUNT(x) ((x) << 4)
131# define VBI_TIMER_COUNT_MASK (0x3fff << 4)
132# define VBI_TIMER_UNIT(x) ((x) << 20)
133# define VBI_TIMER_UNIT_MASK (7 << 20)
134# define DISP_GAP_MCHG(x) ((x) << 24)
135# define DISP_GAP_MCHG_MASK (3 << 24)
136
Alex Deucherae3e40e2013-07-18 16:39:53 -0400[diff] [blame]137#define SMU_VOLTAGE_STATUS 0xC0200094
138# define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1)
139# define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1
140
Alex Deucher94b4adc2013-07-15 17:34:33 -0400[diff] [blame]141#define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0
142# define CURR_PCIE_INDEX_MASK (0xf << 24)
143# define CURR_PCIE_INDEX_SHIFT 24
144
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]145#define CG_ULV_PARAMETER 0xC0200158
146
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]147#define CG_FTV_0 0xC02001A8
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]148#define CG_FTV_1 0xC02001AC
149#define CG_FTV_2 0xC02001B0
150#define CG_FTV_3 0xC02001B4
151#define CG_FTV_4 0xC02001B8
152#define CG_FTV_5 0xC02001BC
153#define CG_FTV_6 0xC02001C0
154#define CG_FTV_7 0xC02001C4
155
156#define CG_DISPLAY_GAP_CNTL2 0xC0200230
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]157
158#define LCAC_SX0_OVR_SEL 0xC0400D04
159#define LCAC_SX0_OVR_VAL 0xC0400D08
160
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]161#define LCAC_MC0_CNTL 0xC0400D30
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]162#define LCAC_MC0_OVR_SEL 0xC0400D34
163#define LCAC_MC0_OVR_VAL 0xC0400D38
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]164#define LCAC_MC1_CNTL 0xC0400D3C
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]165#define LCAC_MC1_OVR_SEL 0xC0400D40
166#define LCAC_MC1_OVR_VAL 0xC0400D44
167
168#define LCAC_MC2_OVR_SEL 0xC0400D4C
169#define LCAC_MC2_OVR_VAL 0xC0400D50
170
171#define LCAC_MC3_OVR_SEL 0xC0400D58
172#define LCAC_MC3_OVR_VAL 0xC0400D5C
173
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]174#define LCAC_CPL_CNTL 0xC0400D80
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]175#define LCAC_CPL_OVR_SEL 0xC0400D84
176#define LCAC_CPL_OVR_VAL 0xC0400D88
177
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]178/* dGPU */
179#define CG_THERMAL_CTRL 0xC0300004
180#define DPM_EVENT_SRC(x) ((x) << 0)
181#define DPM_EVENT_SRC_MASK (7 << 0)
182#define DIG_THERM_DPM(x) ((x) << 14)
183#define DIG_THERM_DPM_MASK 0x003FC000
184#define DIG_THERM_DPM_SHIFT 14
185
186#define CG_THERMAL_INT 0xC030000C
187#define CI_DIG_THERM_INTH(x) ((x) << 8)
188#define CI_DIG_THERM_INTH_MASK 0x0000FF00
189#define CI_DIG_THERM_INTH_SHIFT 8
190#define CI_DIG_THERM_INTL(x) ((x) << 16)
191#define CI_DIG_THERM_INTL_MASK 0x00FF0000
192#define CI_DIG_THERM_INTL_SHIFT 16
193#define THERM_INT_MASK_HIGH (1 << 24)
194#define THERM_INT_MASK_LOW (1 << 25)
195
Alex Deucher286d9cc2013-06-21 15:50:47 -0400[diff] [blame]196#define CG_MULT_THERMAL_STATUS 0xC0300014
197#define ASIC_MAX_TEMP(x) ((x) << 0)
198#define ASIC_MAX_TEMP_MASK 0x000001ff
199#define ASIC_MAX_TEMP_SHIFT 0
200#define CTF_TEMP(x) ((x) << 9)
201#define CTF_TEMP_MASK 0x0003fe00
202#define CTF_TEMP_SHIFT 9
203
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]204#define CG_SPLL_FUNC_CNTL 0xC0500140
205#define SPLL_RESET (1 << 0)
206#define SPLL_PWRON (1 << 1)
207#define SPLL_BYPASS_EN (1 << 3)
208#define SPLL_REF_DIV(x) ((x) << 5)
209#define SPLL_REF_DIV_MASK (0x3f << 5)
210#define SPLL_PDIV_A(x) ((x) << 20)
211#define SPLL_PDIV_A_MASK (0x7f << 20)
212#define SPLL_PDIV_A_SHIFT 20
213#define CG_SPLL_FUNC_CNTL_2 0xC0500144
214#define SCLK_MUX_SEL(x) ((x) << 0)
215#define SCLK_MUX_SEL_MASK (0x1ff << 0)
216#define CG_SPLL_FUNC_CNTL_3 0xC0500148
217#define SPLL_FB_DIV(x) ((x) << 0)
218#define SPLL_FB_DIV_MASK (0x3ffffff << 0)
219#define SPLL_FB_DIV_SHIFT 0
220#define SPLL_DITHEN (1 << 28)
221#define CG_SPLL_FUNC_CNTL_4 0xC050014C
222
223#define CG_SPLL_SPREAD_SPECTRUM 0xC0500164
224#define SSEN (1 << 0)
225#define CLK_S(x) ((x) << 4)
226#define CLK_S_MASK (0xfff << 4)
227#define CLK_S_SHIFT 4
228#define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168
229#define CLK_V(x) ((x) << 0)
230#define CLK_V_MASK (0x3ffffff << 0)
231#define CLK_V_SHIFT 0
232
Alex Deucher7235711a42013-04-04 13:58:09 -0400[diff] [blame]233#define MPLL_BYPASSCLK_SEL 0xC050019C
234# define MPLL_CLKOUT_SEL(x) ((x) << 8)
235# define MPLL_CLKOUT_SEL_MASK 0xFF00
Alex Deucher2c679122013-04-09 13:32:18 -0400[diff] [blame]236#define CG_CLKPIN_CNTL 0xC05001A0
237# define XTALIN_DIVIDE (1 << 1)
Alex Deucher7235711a42013-04-04 13:58:09 -0400[diff] [blame]238# define BCLK_AS_XCLK (1 << 2)
239#define CG_CLKPIN_CNTL_2 0xC05001A4
240# define FORCE_BIF_REFCLK_EN (1 << 3)
241# define MUX_TCLK_TO_XCLK (1 << 8)
242#define THM_CLK_CNTL 0xC05001A8
243# define CMON_CLK_SEL(x) ((x) << 0)
244# define CMON_CLK_SEL_MASK 0xFF
245# define TMON_CLK_SEL(x) ((x) << 8)
246# define TMON_CLK_SEL_MASK 0xFF00
247#define MISC_CLK_CTRL 0xC05001AC
248# define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)
249# define DEEP_SLEEP_CLK_SEL_MASK 0xFF
250# define ZCLK_SEL(x) ((x) << 8)
251# define ZCLK_SEL_MASK 0xFF00
Alex Deucher2c679122013-04-09 13:32:18 -0400[diff] [blame]252
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]253/* KV/KB */
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]254#define CG_THERMAL_INT_CTRL 0xC2100028
255#define DIG_THERM_INTH(x) ((x) << 0)
256#define DIG_THERM_INTH_MASK 0x000000FF
257#define DIG_THERM_INTH_SHIFT 0
258#define DIG_THERM_INTL(x) ((x) << 8)
259#define DIG_THERM_INTL_MASK 0x0000FF00
260#define DIG_THERM_INTL_SHIFT 8
261#define THERM_INTH_MASK (1 << 24)
262#define THERM_INTL_MASK (1 << 25)
263
Alex Deucher8a7cd272013-08-06 11:29:39 -0400[diff] [blame]264/* PCIE registers idx/data 0x38/0x3c */
Alex Deucher7235711a42013-04-04 13:58:09 -0400[diff] [blame]265#define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */
266# define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
267# define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
268# define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
269# define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
270# define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
271# define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
272# define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
273# define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
274# define PLL_RAMP_UP_TIME_0_SHIFT 24
275#define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */
276# define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
277# define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
278# define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
279# define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
280# define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
281# define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
282# define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
283# define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
284# define PLL_RAMP_UP_TIME_1_SHIFT 24
285
286#define PCIE_CNTL2 0x1001001c /* PCIE */
287# define SLV_MEM_LS_EN (1 << 16)
Alex Deucher473359b2013-08-09 11:18:39 -0400[diff] [blame^]288# define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)
Alex Deucher7235711a42013-04-04 13:58:09 -0400[diff] [blame]289# define MST_MEM_LS_EN (1 << 18)
290# define REPLAY_MEM_LS_EN (1 << 19)
291
Alex Deucher8a7cd272013-08-06 11:29:39 -0400[diff] [blame]292#define PCIE_LC_STATUS1 0x1400028 /* PCIE */
293# define LC_REVERSE_RCVR (1 << 0)
294# define LC_REVERSE_XMIT (1 << 1)
295# define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
296# define LC_OPERATING_LINK_WIDTH_SHIFT 2
297# define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)
298# define LC_DETECTED_LINK_WIDTH_SHIFT 5
299
Alex Deucher7235711a42013-04-04 13:58:09 -0400[diff] [blame]300#define PCIE_P_CNTL 0x1400040 /* PCIE */
301# define P_IGNORE_EDB_ERR (1 << 6)
302
303#define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */
304#define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */
305
306#define PCIE_LC_CNTL 0x100100A0 /* PCIE */
307# define LC_L0S_INACTIVITY(x) ((x) << 8)
308# define LC_L0S_INACTIVITY_MASK (0xf << 8)
309# define LC_L0S_INACTIVITY_SHIFT 8
310# define LC_L1_INACTIVITY(x) ((x) << 12)
311# define LC_L1_INACTIVITY_MASK (0xf << 12)
312# define LC_L1_INACTIVITY_SHIFT 12
313# define LC_PMI_TO_L1_DIS (1 << 16)
314# define LC_ASPM_TO_L1_DIS (1 << 24)
315
Alex Deucher8a7cd272013-08-06 11:29:39 -0400[diff] [blame]316#define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */
317# define LC_LINK_WIDTH_SHIFT 0
318# define LC_LINK_WIDTH_MASK 0x7
319# define LC_LINK_WIDTH_X0 0
320# define LC_LINK_WIDTH_X1 1
321# define LC_LINK_WIDTH_X2 2
322# define LC_LINK_WIDTH_X4 3
323# define LC_LINK_WIDTH_X8 4
324# define LC_LINK_WIDTH_X16 6
325# define LC_LINK_WIDTH_RD_SHIFT 4
326# define LC_LINK_WIDTH_RD_MASK 0x70
327# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
328# define LC_RECONFIG_NOW (1 << 8)
329# define LC_RENEGOTIATION_SUPPORT (1 << 9)
330# define LC_RENEGOTIATE_EN (1 << 10)
331# define LC_SHORT_RECONFIG_EN (1 << 11)
332# define LC_UPCONFIGURE_SUPPORT (1 << 12)
333# define LC_UPCONFIGURE_DIS (1 << 13)
334# define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
335# define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
336# define LC_DYN_LANES_PWR_STATE_SHIFT 21
Alex Deucher7235711a42013-04-04 13:58:09 -0400[diff] [blame]337#define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */
338# define LC_XMIT_N_FTS(x) ((x) << 0)
339# define LC_XMIT_N_FTS_MASK (0xff << 0)
340# define LC_XMIT_N_FTS_SHIFT 0
341# define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
342# define LC_N_FTS_MASK (0xff << 24)
Alex Deucher8a7cd272013-08-06 11:29:39 -0400[diff] [blame]343#define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */
344# define LC_GEN2_EN_STRAP (1 << 0)
345# define LC_GEN3_EN_STRAP (1 << 1)
346# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
347# define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)
348# define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3
349# define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
350# define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
351# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
352# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
353# define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
354# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)
355# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10
356# define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
357# define LC_CURRENT_DATA_RATE_SHIFT 13
358# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
359# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
360# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
361# define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
362# define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
363
Alex Deucher7235711a42013-04-04 13:58:09 -0400[diff] [blame]364#define PCIE_LC_CNTL2 0x100100B1 /* PCIE */
365# define LC_ALLOW_PDWN_IN_L1 (1 << 17)
366# define LC_ALLOW_PDWN_IN_L23 (1 << 18)
367
368#define PCIE_LC_CNTL3 0x100100B5 /* PCIE */
369# define LC_GO_TO_RECOVERY (1 << 30)
Alex Deucher8a7cd272013-08-06 11:29:39 -0400[diff] [blame]370#define PCIE_LC_CNTL4 0x100100B6 /* PCIE */
371# define LC_REDO_EQ (1 << 5)
372# define LC_SET_QUIESCE (1 << 13)
373
374/* direct registers */
Alex Deucher6e2c3c02013-04-03 19:28:32 -0400[diff] [blame]375#define PCIE_INDEX 0x38
376#define PCIE_DATA 0x3C
377
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]378#define SMC_IND_INDEX_0 0x200
379#define SMC_IND_DATA_0 0x204
380
381#define SMC_IND_ACCESS_CNTL 0x240
382#define AUTO_INCREMENT_IND_0 (1 << 0)
383
384#define SMC_MESSAGE_0 0x250
385#define SMC_MSG_MASK 0xffff
386#define SMC_RESP_0 0x254
387#define SMC_RESP_MASK 0xffff
388
389#define SMC_MSG_ARG_0 0x290
390
Alex Deucher1c491652013-04-09 12:45:26 -0400[diff] [blame]391#define VGA_HDP_CONTROL 0x328
392#define VGA_MEMORY_DISABLE (1 << 4)
393
Alex Deucher8cc1a532013-04-09 12:41:24 -0400[diff] [blame]394#define DMIF_ADDR_CALC 0xC00
395
Alex Deucher1c491652013-04-09 12:45:26 -0400[diff] [blame]396#define SRBM_GFX_CNTL 0xE44
397#define PIPEID(x) ((x) << 0)
398#define MEID(x) ((x) << 2)
399#define VMID(x) ((x) << 4)
400#define QUEUEID(x) ((x) << 8)
401
Alex Deucher6f2043c2013-04-09 12:43:41 -0400[diff] [blame]402#define SRBM_STATUS2 0xE4C
Alex Deuchercc066712013-04-09 12:59:51 -0400[diff] [blame]403#define SDMA_BUSY (1 << 5)
404#define SDMA1_BUSY (1 << 6)
Alex Deucher6f2043c2013-04-09 12:43:41 -0400[diff] [blame]405#define SRBM_STATUS 0xE50
Alex Deuchercc066712013-04-09 12:59:51 -0400[diff] [blame]406#define UVD_RQ_PENDING (1 << 1)
407#define GRBM_RQ_PENDING (1 << 5)
408#define VMC_BUSY (1 << 8)
409#define MCB_BUSY (1 << 9)
410#define MCB_NON_DISPLAY_BUSY (1 << 10)
411#define MCC_BUSY (1 << 11)
412#define MCD_BUSY (1 << 12)
413#define SEM_BUSY (1 << 14)
414#define IH_BUSY (1 << 17)
415#define UVD_BUSY (1 << 19)
Alex Deucher6f2043c2013-04-09 12:43:41 -0400[diff] [blame]416
Alex Deucher21a93e12013-04-09 12:47:11 -0400[diff] [blame]417#define SRBM_SOFT_RESET 0xE60
418#define SOFT_RESET_BIF (1 << 1)
419#define SOFT_RESET_R0PLL (1 << 4)
420#define SOFT_RESET_DC (1 << 5)
421#define SOFT_RESET_SDMA1 (1 << 6)
422#define SOFT_RESET_GRBM (1 << 8)
423#define SOFT_RESET_HDP (1 << 9)
424#define SOFT_RESET_IH (1 << 10)
425#define SOFT_RESET_MC (1 << 11)
426#define SOFT_RESET_ROM (1 << 14)
427#define SOFT_RESET_SEM (1 << 15)
428#define SOFT_RESET_VMC (1 << 17)
429#define SOFT_RESET_SDMA (1 << 20)
430#define SOFT_RESET_TST (1 << 21)
431#define SOFT_RESET_REGBB (1 << 22)
432#define SOFT_RESET_ORB (1 << 23)
433#define SOFT_RESET_VCE (1 << 24)
434
Alex Deucher1c491652013-04-09 12:45:26 -0400[diff] [blame]435#define VM_L2_CNTL 0x1400
436#define ENABLE_L2_CACHE (1 << 0)
437#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
438#define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
439#define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
440#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
441#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
442#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
443#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
444#define VM_L2_CNTL2 0x1404
445#define INVALIDATE_ALL_L1_TLBS (1 << 0)
446#define INVALIDATE_L2_CACHE (1 << 1)
447#define INVALIDATE_CACHE_MODE(x) ((x) << 26)
448#define INVALIDATE_PTE_AND_PDE_CACHES 0
449#define INVALIDATE_ONLY_PTE_CACHES 1
450#define INVALIDATE_ONLY_PDE_CACHES 2
451#define VM_L2_CNTL3 0x1408
452#define BANK_SELECT(x) ((x) << 0)
453#define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
454#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
455#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
456#define VM_L2_STATUS 0x140C
457#define L2_BUSY (1 << 0)
458#define VM_CONTEXT0_CNTL 0x1410
459#define ENABLE_CONTEXT (1 << 0)
460#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
Alex Deuchera00024b2012-09-18 16:06:01 -0400[diff] [blame]461#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
Alex Deucher1c491652013-04-09 12:45:26 -0400[diff] [blame]462#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
Alex Deuchera00024b2012-09-18 16:06:01 -0400[diff] [blame]463#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
464#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
465#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
466#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
467#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
468#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
469#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
470#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
471#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
472#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
Alex Deucher1c491652013-04-09 12:45:26 -0400[diff] [blame]473#define VM_CONTEXT1_CNTL 0x1414
474#define VM_CONTEXT0_CNTL2 0x1430
475#define VM_CONTEXT1_CNTL2 0x1434
476#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
477#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
478#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
479#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
480#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
481#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
482#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
483#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
484
485#define VM_INVALIDATE_REQUEST 0x1478
486#define VM_INVALIDATE_RESPONSE 0x147c
487
Alex Deucher9d97c992012-09-06 14:24:48 -0400[diff] [blame]488#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
Alex Deucher3ec7d112013-06-14 10:42:22 -0400[diff] [blame]489#define PROTECTIONS_MASK (0xf << 0)
490#define PROTECTIONS_SHIFT 0
491 /* bit 0: range
492 * bit 1: pde0
493 * bit 2: valid
494 * bit 3: read
495 * bit 4: write
496 */
497#define MEMORY_CLIENT_ID_MASK (0xff << 12)
498#define MEMORY_CLIENT_ID_SHIFT 12
499#define MEMORY_CLIENT_RW_MASK (1 << 24)
500#define MEMORY_CLIENT_RW_SHIFT 24
501#define FAULT_VMID_MASK (0xf << 25)
502#define FAULT_VMID_SHIFT 25
503
504#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4
Alex Deucher9d97c992012-09-06 14:24:48 -0400[diff] [blame]505
506#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
507
Alex Deucher1c491652013-04-09 12:45:26 -0400[diff] [blame]508#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
509#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
510
511#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
512#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
513#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
514#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
515#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
516#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
517#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
518#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
519#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
520#define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
521
522#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
523#define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
524
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]525#define VM_L2_CG 0x15c0
526#define MC_CG_ENABLE (1 << 18)
527#define MC_LS_ENABLE (1 << 19)
528
Alex Deucher8cc1a532013-04-09 12:41:24 -0400[diff] [blame]529#define MC_SHARED_CHMAP 0x2004
530#define NOOFCHAN_SHIFT 12
531#define NOOFCHAN_MASK 0x0000f000
532#define MC_SHARED_CHREMAP 0x2008
533
Alex Deucher1c491652013-04-09 12:45:26 -0400[diff] [blame]534#define CHUB_CONTROL 0x1864
535#define BYPASS_VM (1 << 0)
536
537#define MC_VM_FB_LOCATION 0x2024
538#define MC_VM_AGP_TOP 0x2028
539#define MC_VM_AGP_BOT 0x202C
540#define MC_VM_AGP_BASE 0x2030
541#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
542#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
543#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
544
545#define MC_VM_MX_L1_TLB_CNTL 0x2064
546#define ENABLE_L1_TLB (1 << 0)
547#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
548#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
549#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
550#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
551#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
552#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
553#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
554#define MC_VM_FB_OFFSET 0x2068
555
Alex Deucherbc8273f2012-06-29 19:44:04 -0400[diff] [blame]556#define MC_SHARED_BLACKOUT_CNTL 0x20ac
557
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]558#define MC_HUB_MISC_HUB_CG 0x20b8
559#define MC_HUB_MISC_VM_CG 0x20bc
560
561#define MC_HUB_MISC_SIP_CG 0x20c0
562
563#define MC_XPB_CLK_GAT 0x2478
564
565#define MC_CITF_MISC_RD_CG 0x2648
566#define MC_CITF_MISC_WR_CG 0x264c
567#define MC_CITF_MISC_VM_CG 0x2650
568
Alex Deucher8cc1a532013-04-09 12:41:24 -0400[diff] [blame]569#define MC_ARB_RAMCFG 0x2760
570#define NOOFBANK_SHIFT 0
571#define NOOFBANK_MASK 0x00000003
572#define NOOFRANK_SHIFT 2
573#define NOOFRANK_MASK 0x00000004
574#define NOOFROWS_SHIFT 3
575#define NOOFROWS_MASK 0x00000038
576#define NOOFCOLS_SHIFT 6
577#define NOOFCOLS_MASK 0x000000C0
578#define CHANSIZE_SHIFT 8
579#define CHANSIZE_MASK 0x00000100
580#define NOOFGROUPS_SHIFT 12
581#define NOOFGROUPS_MASK 0x00001000
582
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]583#define MC_ARB_DRAM_TIMING 0x2774
584#define MC_ARB_DRAM_TIMING2 0x2778
585
586#define MC_ARB_BURST_TIME 0x2808
587#define STATE0(x) ((x) << 0)
588#define STATE0_MASK (0x1f << 0)
589#define STATE0_SHIFT 0
590#define STATE1(x) ((x) << 5)
591#define STATE1_MASK (0x1f << 5)
592#define STATE1_SHIFT 5
593#define STATE2(x) ((x) << 10)
594#define STATE2_MASK (0x1f << 10)
595#define STATE2_SHIFT 10
596#define STATE3(x) ((x) << 15)
597#define STATE3_MASK (0x1f << 15)
598#define STATE3_SHIFT 15
599
600#define MC_SEQ_RAS_TIMING 0x28a0
601#define MC_SEQ_CAS_TIMING 0x28a4
602#define MC_SEQ_MISC_TIMING 0x28a8
603#define MC_SEQ_MISC_TIMING2 0x28ac
604#define MC_SEQ_PMG_TIMING 0x28b0
605#define MC_SEQ_RD_CTL_D0 0x28b4
606#define MC_SEQ_RD_CTL_D1 0x28b8
607#define MC_SEQ_WR_CTL_D0 0x28bc
608#define MC_SEQ_WR_CTL_D1 0x28c0
609
Alex Deucherbc8273f2012-06-29 19:44:04 -0400[diff] [blame]610#define MC_SEQ_SUP_CNTL 0x28c8
611#define RUN_MASK (1 << 0)
612#define MC_SEQ_SUP_PGM 0x28cc
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]613#define MC_PMG_AUTO_CMD 0x28d0
Alex Deucherbc8273f2012-06-29 19:44:04 -0400[diff] [blame]614
615#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8
616#define TRAIN_DONE_D0 (1 << 30)
617#define TRAIN_DONE_D1 (1 << 31)
618
619#define MC_IO_PAD_CNTL_D0 0x29d0
620#define MEM_FALL_OUT_CMD (1 << 8)
621
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]622#define MC_SEQ_MISC0 0x2a00
623#define MC_SEQ_MISC0_VEN_ID_SHIFT 8
624#define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
625#define MC_SEQ_MISC0_VEN_ID_VALUE 3
626#define MC_SEQ_MISC0_REV_ID_SHIFT 12
627#define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
628#define MC_SEQ_MISC0_REV_ID_VALUE 1
629#define MC_SEQ_MISC0_GDDR5_SHIFT 28
630#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
631#define MC_SEQ_MISC0_GDDR5_VALUE 5
632#define MC_SEQ_MISC1 0x2a04
633#define MC_SEQ_RESERVE_M 0x2a08
634#define MC_PMG_CMD_EMRS 0x2a0c
635
Alex Deucherbc8273f2012-06-29 19:44:04 -0400[diff] [blame]636#define MC_SEQ_IO_DEBUG_INDEX 0x2a44
637#define MC_SEQ_IO_DEBUG_DATA 0x2a48
638
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]639#define MC_SEQ_MISC5 0x2a54
640#define MC_SEQ_MISC6 0x2a58
641
642#define MC_SEQ_MISC7 0x2a64
643
644#define MC_SEQ_RAS_TIMING_LP 0x2a6c
645#define MC_SEQ_CAS_TIMING_LP 0x2a70
646#define MC_SEQ_MISC_TIMING_LP 0x2a74
647#define MC_SEQ_MISC_TIMING2_LP 0x2a78
648#define MC_SEQ_WR_CTL_D0_LP 0x2a7c
649#define MC_SEQ_WR_CTL_D1_LP 0x2a80
650#define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
651#define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
652
653#define MC_PMG_CMD_MRS 0x2aac
654
655#define MC_SEQ_RD_CTL_D0_LP 0x2b1c
656#define MC_SEQ_RD_CTL_D1_LP 0x2b20
657
658#define MC_PMG_CMD_MRS1 0x2b44
659#define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
660#define MC_SEQ_PMG_TIMING_LP 0x2b4c
661
662#define MC_SEQ_WR_CTL_2 0x2b54
663#define MC_SEQ_WR_CTL_2_LP 0x2b58
664#define MC_PMG_CMD_MRS2 0x2b5c
665#define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
666
667#define MCLK_PWRMGT_CNTL 0x2ba0
668# define DLL_SPEED(x) ((x) << 0)
669# define DLL_SPEED_MASK (0x1f << 0)
670# define DLL_READY (1 << 6)
671# define MC_INT_CNTL (1 << 7)
672# define MRDCK0_PDNB (1 << 8)
673# define MRDCK1_PDNB (1 << 9)
674# define MRDCK0_RESET (1 << 16)
675# define MRDCK1_RESET (1 << 17)
676# define DLL_READY_READ (1 << 24)
677#define DLL_CNTL 0x2ba4
678# define MRDCK0_BYPASS (1 << 24)
679# define MRDCK1_BYPASS (1 << 25)
680
681#define MPLL_FUNC_CNTL 0x2bb4
682#define BWCTRL(x) ((x) << 20)
683#define BWCTRL_MASK (0xff << 20)
684#define MPLL_FUNC_CNTL_1 0x2bb8
685#define VCO_MODE(x) ((x) << 0)
686#define VCO_MODE_MASK (3 << 0)
687#define CLKFRAC(x) ((x) << 4)
688#define CLKFRAC_MASK (0xfff << 4)
689#define CLKF(x) ((x) << 16)
690#define CLKF_MASK (0xfff << 16)
691#define MPLL_FUNC_CNTL_2 0x2bbc
692#define MPLL_AD_FUNC_CNTL 0x2bc0
693#define YCLK_POST_DIV(x) ((x) << 0)
694#define YCLK_POST_DIV_MASK (7 << 0)
695#define MPLL_DQ_FUNC_CNTL 0x2bc4
696#define YCLK_SEL(x) ((x) << 4)
697#define YCLK_SEL_MASK (1 << 4)
698
699#define MPLL_SS1 0x2bcc
700#define CLKV(x) ((x) << 0)
701#define CLKV_MASK (0x3ffffff << 0)
702#define MPLL_SS2 0x2bd0
703#define CLKS(x) ((x) << 0)
704#define CLKS_MASK (0xfff << 0)
705
Alex Deucher8cc1a532013-04-09 12:41:24 -0400[diff] [blame]706#define HDP_HOST_PATH_CNTL 0x2C00
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]707#define CLOCK_GATING_DIS (1 << 23)
Alex Deucher8cc1a532013-04-09 12:41:24 -0400[diff] [blame]708#define HDP_NONSURFACE_BASE 0x2C04
709#define HDP_NONSURFACE_INFO 0x2C08
710#define HDP_NONSURFACE_SIZE 0x2C0C
711
712#define HDP_ADDR_CONFIG 0x2F48
713#define HDP_MISC_CNTL 0x2F4C
714#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]715#define HDP_MEM_POWER_LS 0x2F50
716#define HDP_LS_ENABLE (1 << 0)
717
718#define ATC_MISC_CG 0x3350
Alex Deucher8cc1a532013-04-09 12:41:24 -0400[diff] [blame]719
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]720#define MC_SEQ_CNTL_3 0x3600
721# define CAC_EN (1 << 31)
722#define MC_SEQ_G5PDX_CTRL 0x3604
723#define MC_SEQ_G5PDX_CTRL_LP 0x3608
724#define MC_SEQ_G5PDX_CMD0 0x360c
725#define MC_SEQ_G5PDX_CMD0_LP 0x3610
726#define MC_SEQ_G5PDX_CMD1 0x3614
727#define MC_SEQ_G5PDX_CMD1_LP 0x3618
728
729#define MC_SEQ_PMG_DVS_CTL 0x3628
730#define MC_SEQ_PMG_DVS_CTL_LP 0x362c
731#define MC_SEQ_PMG_DVS_CMD 0x3630
732#define MC_SEQ_PMG_DVS_CMD_LP 0x3634
733#define MC_SEQ_DLL_STBY 0x3638
734#define MC_SEQ_DLL_STBY_LP 0x363c
735
Alex Deuchera59781b2012-11-09 10:45:57 -0500[diff] [blame]736#define IH_RB_CNTL 0x3e00
737# define IH_RB_ENABLE (1 << 0)
738# define IH_RB_SIZE(x) ((x) << 1) /* log2 */
739# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
740# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
741# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
742# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
743# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
744#define IH_RB_BASE 0x3e04
745#define IH_RB_RPTR 0x3e08
746#define IH_RB_WPTR 0x3e0c
747# define RB_OVERFLOW (1 << 0)
748# define WPTR_OFFSET_MASK 0x3fffc
749#define IH_RB_WPTR_ADDR_HI 0x3e10
750#define IH_RB_WPTR_ADDR_LO 0x3e14
751#define IH_CNTL 0x3e18
752# define ENABLE_INTR (1 << 0)
753# define IH_MC_SWAP(x) ((x) << 1)
754# define IH_MC_SWAP_NONE 0
755# define IH_MC_SWAP_16BIT 1
756# define IH_MC_SWAP_32BIT 2
757# define IH_MC_SWAP_64BIT 3
758# define RPTR_REARM (1 << 4)
759# define MC_WRREQ_CREDIT(x) ((x) << 15)
760# define MC_WR_CLEAN_CNT(x) ((x) << 20)
761# define MC_VMID(x) ((x) << 25)
762
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]763#define BIF_LNCNT_RESET 0x5220
764# define RESET_LNCNT_EN (1 << 0)
765
Alex Deucher1c491652013-04-09 12:45:26 -0400[diff] [blame]766#define CONFIG_MEMSIZE 0x5428
767
Alex Deuchera59781b2012-11-09 10:45:57 -0500[diff] [blame]768#define INTERRUPT_CNTL 0x5468
769# define IH_DUMMY_RD_OVERRIDE (1 << 0)
770# define IH_DUMMY_RD_EN (1 << 1)
771# define IH_REQ_NONSNOOP_EN (1 << 3)
772# define GEN_IH_INT_EN (1 << 8)
773#define INTERRUPT_CNTL2 0x546c
774
Alex Deucher1c491652013-04-09 12:45:26 -0400[diff] [blame]775#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
776
Alex Deucher8cc1a532013-04-09 12:41:24 -0400[diff] [blame]777#define BIF_FB_EN 0x5490
778#define FB_READ_EN (1 << 0)
779#define FB_WRITE_EN (1 << 1)
780
Alex Deucher1c491652013-04-09 12:45:26 -0400[diff] [blame]781#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
782
Alex Deucher2cae3bc2012-07-05 11:45:40 -0400[diff] [blame]783#define GPU_HDP_FLUSH_REQ 0x54DC
784#define GPU_HDP_FLUSH_DONE 0x54E0
785#define CP0 (1 << 0)
786#define CP1 (1 << 1)
787#define CP2 (1 << 2)
788#define CP3 (1 << 3)
789#define CP4 (1 << 4)
790#define CP5 (1 << 5)
791#define CP6 (1 << 6)
792#define CP7 (1 << 7)
793#define CP8 (1 << 8)
794#define CP9 (1 << 9)
795#define SDMA0 (1 << 10)
796#define SDMA1 (1 << 11)
797
Alex Deuchercd84a272012-07-20 17:13:13 -0400[diff] [blame]798/* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */
799#define LB_MEMORY_CTRL 0x6b04
800#define LB_MEMORY_SIZE(x) ((x) << 0)
801#define LB_MEMORY_CONFIG(x) ((x) << 20)
802
803#define DPG_WATERMARK_MASK_CONTROL 0x6cc8
804# define LATENCY_WATERMARK_MASK(x) ((x) << 8)
805#define DPG_PIPE_LATENCY_CONTROL 0x6ccc
806# define LATENCY_LOW_WATERMARK(x) ((x) << 0)
807# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
808
Alex Deuchera59781b2012-11-09 10:45:57 -0500[diff] [blame]809/* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */
810#define LB_VLINE_STATUS 0x6b24
811# define VLINE_OCCURRED (1 << 0)
812# define VLINE_ACK (1 << 4)
813# define VLINE_STAT (1 << 12)
814# define VLINE_INTERRUPT (1 << 16)
815# define VLINE_INTERRUPT_TYPE (1 << 17)
816/* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */
817#define LB_VBLANK_STATUS 0x6b2c
818# define VBLANK_OCCURRED (1 << 0)
819# define VBLANK_ACK (1 << 4)
820# define VBLANK_STAT (1 << 12)
821# define VBLANK_INTERRUPT (1 << 16)
822# define VBLANK_INTERRUPT_TYPE (1 << 17)
823
824/* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */
825#define LB_INTERRUPT_MASK 0x6b20
826# define VBLANK_INTERRUPT_MASK (1 << 0)
827# define VLINE_INTERRUPT_MASK (1 << 4)
828# define VLINE2_INTERRUPT_MASK (1 << 8)
829
830#define DISP_INTERRUPT_STATUS 0x60f4
831# define LB_D1_VLINE_INTERRUPT (1 << 2)
832# define LB_D1_VBLANK_INTERRUPT (1 << 3)
833# define DC_HPD1_INTERRUPT (1 << 17)
834# define DC_HPD1_RX_INTERRUPT (1 << 18)
835# define DACA_AUTODETECT_INTERRUPT (1 << 22)
836# define DACB_AUTODETECT_INTERRUPT (1 << 23)
837# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
838# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
839#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
840# define LB_D2_VLINE_INTERRUPT (1 << 2)
841# define LB_D2_VBLANK_INTERRUPT (1 << 3)
842# define DC_HPD2_INTERRUPT (1 << 17)
843# define DC_HPD2_RX_INTERRUPT (1 << 18)
844# define DISP_TIMER_INTERRUPT (1 << 24)
845#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
846# define LB_D3_VLINE_INTERRUPT (1 << 2)
847# define LB_D3_VBLANK_INTERRUPT (1 << 3)
848# define DC_HPD3_INTERRUPT (1 << 17)
849# define DC_HPD3_RX_INTERRUPT (1 << 18)
850#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
851# define LB_D4_VLINE_INTERRUPT (1 << 2)
852# define LB_D4_VBLANK_INTERRUPT (1 << 3)
853# define DC_HPD4_INTERRUPT (1 << 17)
854# define DC_HPD4_RX_INTERRUPT (1 << 18)
855#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
856# define LB_D5_VLINE_INTERRUPT (1 << 2)
857# define LB_D5_VBLANK_INTERRUPT (1 << 3)
858# define DC_HPD5_INTERRUPT (1 << 17)
859# define DC_HPD5_RX_INTERRUPT (1 << 18)
860#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
861# define LB_D6_VLINE_INTERRUPT (1 << 2)
862# define LB_D6_VBLANK_INTERRUPT (1 << 3)
863# define DC_HPD6_INTERRUPT (1 << 17)
864# define DC_HPD6_RX_INTERRUPT (1 << 18)
865#define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780
866
867#define DAC_AUTODETECT_INT_CONTROL 0x67c8
868
869#define DC_HPD1_INT_STATUS 0x601c
870#define DC_HPD2_INT_STATUS 0x6028
871#define DC_HPD3_INT_STATUS 0x6034
872#define DC_HPD4_INT_STATUS 0x6040
873#define DC_HPD5_INT_STATUS 0x604c
874#define DC_HPD6_INT_STATUS 0x6058
875# define DC_HPDx_INT_STATUS (1 << 0)
876# define DC_HPDx_SENSE (1 << 1)
877# define DC_HPDx_SENSE_DELAYED (1 << 4)
878# define DC_HPDx_RX_INT_STATUS (1 << 8)
879
880#define DC_HPD1_INT_CONTROL 0x6020
881#define DC_HPD2_INT_CONTROL 0x602c
882#define DC_HPD3_INT_CONTROL 0x6038
883#define DC_HPD4_INT_CONTROL 0x6044
884#define DC_HPD5_INT_CONTROL 0x6050
885#define DC_HPD6_INT_CONTROL 0x605c
886# define DC_HPDx_INT_ACK (1 << 0)
887# define DC_HPDx_INT_POLARITY (1 << 8)
888# define DC_HPDx_INT_EN (1 << 16)
889# define DC_HPDx_RX_INT_ACK (1 << 20)
890# define DC_HPDx_RX_INT_EN (1 << 24)
891
892#define DC_HPD1_CONTROL 0x6024
893#define DC_HPD2_CONTROL 0x6030
894#define DC_HPD3_CONTROL 0x603c
895#define DC_HPD4_CONTROL 0x6048
896#define DC_HPD5_CONTROL 0x6054
897#define DC_HPD6_CONTROL 0x6060
898# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
899# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
900# define DC_HPDx_EN (1 << 28)
901
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]902#define DPG_PIPE_STUTTER_CONTROL 0x6cd4
903# define STUTTER_ENABLE (1 << 0)
904
Alex Deucher8cc1a532013-04-09 12:41:24 -0400[diff] [blame]905#define GRBM_CNTL 0x8000
906#define GRBM_READ_TIMEOUT(x) ((x) << 0)
907
Alex Deucher6f2043c2013-04-09 12:43:41 -0400[diff] [blame]908#define GRBM_STATUS2 0x8008
909#define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F
910#define ME0PIPE1_CF_RQ_PENDING (1 << 4)
911#define ME0PIPE1_PF_RQ_PENDING (1 << 5)
912#define ME1PIPE0_RQ_PENDING (1 << 6)
913#define ME1PIPE1_RQ_PENDING (1 << 7)
914#define ME1PIPE2_RQ_PENDING (1 << 8)
915#define ME1PIPE3_RQ_PENDING (1 << 9)
916#define ME2PIPE0_RQ_PENDING (1 << 10)
917#define ME2PIPE1_RQ_PENDING (1 << 11)
918#define ME2PIPE2_RQ_PENDING (1 << 12)
919#define ME2PIPE3_RQ_PENDING (1 << 13)
920#define RLC_RQ_PENDING (1 << 14)
921#define RLC_BUSY (1 << 24)
922#define TC_BUSY (1 << 25)
923#define CPF_BUSY (1 << 28)
924#define CPC_BUSY (1 << 29)
925#define CPG_BUSY (1 << 30)
926
927#define GRBM_STATUS 0x8010
928#define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F
929#define SRBM_RQ_PENDING (1 << 5)
930#define ME0PIPE0_CF_RQ_PENDING (1 << 7)
931#define ME0PIPE0_PF_RQ_PENDING (1 << 8)
932#define GDS_DMA_RQ_PENDING (1 << 9)
933#define DB_CLEAN (1 << 12)
934#define CB_CLEAN (1 << 13)
935#define TA_BUSY (1 << 14)
936#define GDS_BUSY (1 << 15)
937#define WD_BUSY_NO_DMA (1 << 16)
938#define VGT_BUSY (1 << 17)
939#define IA_BUSY_NO_DMA (1 << 18)
940#define IA_BUSY (1 << 19)
941#define SX_BUSY (1 << 20)
942#define WD_BUSY (1 << 21)
943#define SPI_BUSY (1 << 22)
944#define BCI_BUSY (1 << 23)
945#define SC_BUSY (1 << 24)
946#define PA_BUSY (1 << 25)
947#define DB_BUSY (1 << 26)
948#define CP_COHERENCY_BUSY (1 << 28)
949#define CP_BUSY (1 << 29)
950#define CB_BUSY (1 << 30)
951#define GUI_ACTIVE (1 << 31)
952#define GRBM_STATUS_SE0 0x8014
953#define GRBM_STATUS_SE1 0x8018
954#define GRBM_STATUS_SE2 0x8038
955#define GRBM_STATUS_SE3 0x803C
956#define SE_DB_CLEAN (1 << 1)
957#define SE_CB_CLEAN (1 << 2)
958#define SE_BCI_BUSY (1 << 22)
959#define SE_VGT_BUSY (1 << 23)
960#define SE_PA_BUSY (1 << 24)
961#define SE_TA_BUSY (1 << 25)
962#define SE_SX_BUSY (1 << 26)
963#define SE_SPI_BUSY (1 << 27)
964#define SE_SC_BUSY (1 << 29)
965#define SE_DB_BUSY (1 << 30)
966#define SE_CB_BUSY (1 << 31)
967
968#define GRBM_SOFT_RESET 0x8020
969#define SOFT_RESET_CP (1 << 0) /* All CP blocks */
970#define SOFT_RESET_RLC (1 << 2) /* RLC */
971#define SOFT_RESET_GFX (1 << 16) /* GFX */
972#define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */
973#define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */
974#define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */
975
Alex Deuchera59781b2012-11-09 10:45:57 -0500[diff] [blame]976#define GRBM_INT_CNTL 0x8060
977# define RDERR_INT_ENABLE (1 << 0)
978# define GUI_IDLE_INT_ENABLE (1 << 19)
979
Alex Deucher963e81f2013-06-26 17:37:11 -0400[diff] [blame]980#define CP_CPC_STATUS 0x8210
981#define CP_CPC_BUSY_STAT 0x8214
982#define CP_CPC_STALLED_STAT1 0x8218
983#define CP_CPF_STATUS 0x821c
984#define CP_CPF_BUSY_STAT 0x8220
985#define CP_CPF_STALLED_STAT1 0x8224
986
Alex Deucher6f2043c2013-04-09 12:43:41 -0400[diff] [blame]987#define CP_MEC_CNTL 0x8234
988#define MEC_ME2_HALT (1 << 28)
989#define MEC_ME1_HALT (1 << 30)
990
Alex Deucher841cf442012-12-18 21:47:44 -0500[diff] [blame]991#define CP_MEC_CNTL 0x8234
992#define MEC_ME2_HALT (1 << 28)
993#define MEC_ME1_HALT (1 << 30)
994
Alex Deucher963e81f2013-06-26 17:37:11 -0400[diff] [blame]995#define CP_STALLED_STAT3 0x8670
996#define CP_STALLED_STAT1 0x8674
997#define CP_STALLED_STAT2 0x8678
998
999#define CP_STAT 0x8680
1000
Alex Deucher6f2043c2013-04-09 12:43:41 -0400[diff] [blame]1001#define CP_ME_CNTL 0x86D8
1002#define CP_CE_HALT (1 << 24)
1003#define CP_PFP_HALT (1 << 26)
1004#define CP_ME_HALT (1 << 28)
1005
Alex Deucher841cf442012-12-18 21:47:44 -0500[diff] [blame]1006#define CP_RB0_RPTR 0x8700
1007#define CP_RB_WPTR_DELAY 0x8704
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]1008#define CP_RB_WPTR_POLL_CNTL 0x8708
1009#define IDLE_POLL_COUNT(x) ((x) << 16)
1010#define IDLE_POLL_COUNT_MASK (0xffff << 16)
Alex Deucher841cf442012-12-18 21:47:44 -0500[diff] [blame]1011
Alex Deucher8cc1a532013-04-09 12:41:24 -0400[diff] [blame]1012#define CP_MEQ_THRESHOLDS 0x8764
1013#define MEQ1_START(x) ((x) << 0)
1014#define MEQ2_START(x) ((x) << 8)
1015
1016#define VGT_VTX_VECT_EJECT_REG 0x88B0
1017
1018#define VGT_CACHE_INVALIDATION 0x88C4
1019#define CACHE_INVALIDATION(x) ((x) << 0)
1020#define VC_ONLY 0
1021#define TC_ONLY 1
1022#define VC_AND_TC 2
1023#define AUTO_INVLD_EN(x) ((x) << 6)
1024#define NO_AUTO 0
1025#define ES_AUTO 1
1026#define GS_AUTO 2
1027#define ES_AND_GS_AUTO 3
1028
1029#define VGT_GS_VERTEX_REUSE 0x88D4
1030
1031#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
1032#define INACTIVE_CUS_MASK 0xFFFF0000
1033#define INACTIVE_CUS_SHIFT 16
1034#define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
1035
1036#define PA_CL_ENHANCE 0x8A14
1037#define CLIP_VTX_REORDER_ENA (1 << 0)
1038#define NUM_CLIP_SEQ(x) ((x) << 1)
1039
1040#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
1041#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1042#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1043
1044#define PA_SC_FIFO_SIZE 0x8BCC
1045#define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
1046#define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
1047#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
1048#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
1049
1050#define PA_SC_ENHANCE 0x8BF0
1051#define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0)
1052#define DISABLE_PA_SC_GUIDANCE (1 << 13)
1053
1054#define SQ_CONFIG 0x8C00
1055
Alex Deucher1c491652013-04-09 12:45:26 -0400[diff] [blame]1056#define SH_MEM_BASES 0x8C28
1057/* if PTR32, these are the bases for scratch and lds */
1058#define PRIVATE_BASE(x) ((x) << 0) /* scratch */
1059#define SHARED_BASE(x) ((x) << 16) /* LDS */
1060#define SH_MEM_APE1_BASE 0x8C2C
1061/* if PTR32, this is the base location of GPUVM */
1062#define SH_MEM_APE1_LIMIT 0x8C30
1063/* if PTR32, this is the upper limit of GPUVM */
1064#define SH_MEM_CONFIG 0x8C34
1065#define PTR32 (1 << 0)
1066#define ALIGNMENT_MODE(x) ((x) << 2)
1067#define SH_MEM_ALIGNMENT_MODE_DWORD 0
1068#define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1
1069#define SH_MEM_ALIGNMENT_MODE_STRICT 2
1070#define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3
1071#define DEFAULT_MTYPE(x) ((x) << 4)
1072#define APE1_MTYPE(x) ((x) << 7)
1073
Alex Deucher8cc1a532013-04-09 12:41:24 -0400[diff] [blame]1074#define SX_DEBUG_1 0x9060
1075
1076#define SPI_CONFIG_CNTL 0x9100
1077
1078#define SPI_CONFIG_CNTL_1 0x913C
1079#define VTX_DONE_DELAY(x) ((x) << 0)
1080#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
1081
1082#define TA_CNTL_AUX 0x9508
1083
1084#define DB_DEBUG 0x9830
1085#define DB_DEBUG2 0x9834
1086#define DB_DEBUG3 0x9838
1087
1088#define CC_RB_BACKEND_DISABLE 0x98F4
1089#define BACKEND_DISABLE(x) ((x) << 16)
1090#define GB_ADDR_CONFIG 0x98F8
1091#define NUM_PIPES(x) ((x) << 0)
1092#define NUM_PIPES_MASK 0x00000007
1093#define NUM_PIPES_SHIFT 0
1094#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
1095#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
1096#define PIPE_INTERLEAVE_SIZE_SHIFT 4
1097#define NUM_SHADER_ENGINES(x) ((x) << 12)
1098#define NUM_SHADER_ENGINES_MASK 0x00003000
1099#define NUM_SHADER_ENGINES_SHIFT 12
1100#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
1101#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
1102#define SHADER_ENGINE_TILE_SIZE_SHIFT 16
1103#define ROW_SIZE(x) ((x) << 28)
1104#define ROW_SIZE_MASK 0x30000000
1105#define ROW_SIZE_SHIFT 28
1106
1107#define GB_TILE_MODE0 0x9910
1108# define ARRAY_MODE(x) ((x) << 2)
1109# define ARRAY_LINEAR_GENERAL 0
1110# define ARRAY_LINEAR_ALIGNED 1
1111# define ARRAY_1D_TILED_THIN1 2
1112# define ARRAY_2D_TILED_THIN1 4
1113# define ARRAY_PRT_TILED_THIN1 5
1114# define ARRAY_PRT_2D_TILED_THIN1 6
1115# define PIPE_CONFIG(x) ((x) << 6)
1116# define ADDR_SURF_P2 0
1117# define ADDR_SURF_P4_8x16 4
1118# define ADDR_SURF_P4_16x16 5
1119# define ADDR_SURF_P4_16x32 6
1120# define ADDR_SURF_P4_32x32 7
1121# define ADDR_SURF_P8_16x16_8x16 8
1122# define ADDR_SURF_P8_16x32_8x16 9
1123# define ADDR_SURF_P8_32x32_8x16 10
1124# define ADDR_SURF_P8_16x32_16x16 11
1125# define ADDR_SURF_P8_32x32_16x16 12
1126# define ADDR_SURF_P8_32x32_16x32 13
1127# define ADDR_SURF_P8_32x64_32x32 14
1128# define TILE_SPLIT(x) ((x) << 11)
1129# define ADDR_SURF_TILE_SPLIT_64B 0
1130# define ADDR_SURF_TILE_SPLIT_128B 1
1131# define ADDR_SURF_TILE_SPLIT_256B 2
1132# define ADDR_SURF_TILE_SPLIT_512B 3
1133# define ADDR_SURF_TILE_SPLIT_1KB 4
1134# define ADDR_SURF_TILE_SPLIT_2KB 5
1135# define ADDR_SURF_TILE_SPLIT_4KB 6
1136# define MICRO_TILE_MODE_NEW(x) ((x) << 22)
1137# define ADDR_SURF_DISPLAY_MICRO_TILING 0
1138# define ADDR_SURF_THIN_MICRO_TILING 1
1139# define ADDR_SURF_DEPTH_MICRO_TILING 2
1140# define ADDR_SURF_ROTATED_MICRO_TILING 3
1141# define SAMPLE_SPLIT(x) ((x) << 25)
1142# define ADDR_SURF_SAMPLE_SPLIT_1 0
1143# define ADDR_SURF_SAMPLE_SPLIT_2 1
1144# define ADDR_SURF_SAMPLE_SPLIT_4 2
1145# define ADDR_SURF_SAMPLE_SPLIT_8 3
1146
1147#define GB_MACROTILE_MODE0 0x9990
1148# define BANK_WIDTH(x) ((x) << 0)
1149# define ADDR_SURF_BANK_WIDTH_1 0
1150# define ADDR_SURF_BANK_WIDTH_2 1
1151# define ADDR_SURF_BANK_WIDTH_4 2
1152# define ADDR_SURF_BANK_WIDTH_8 3
1153# define BANK_HEIGHT(x) ((x) << 2)
1154# define ADDR_SURF_BANK_HEIGHT_1 0
1155# define ADDR_SURF_BANK_HEIGHT_2 1
1156# define ADDR_SURF_BANK_HEIGHT_4 2
1157# define ADDR_SURF_BANK_HEIGHT_8 3
1158# define MACRO_TILE_ASPECT(x) ((x) << 4)
1159# define ADDR_SURF_MACRO_ASPECT_1 0
1160# define ADDR_SURF_MACRO_ASPECT_2 1
1161# define ADDR_SURF_MACRO_ASPECT_4 2
1162# define ADDR_SURF_MACRO_ASPECT_8 3
1163# define NUM_BANKS(x) ((x) << 6)
1164# define ADDR_SURF_2_BANK 0
1165# define ADDR_SURF_4_BANK 1
1166# define ADDR_SURF_8_BANK 2
1167# define ADDR_SURF_16_BANK 3
1168
1169#define CB_HW_CONTROL 0x9A10
1170
1171#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
1172#define BACKEND_DISABLE_MASK 0x00FF0000
1173#define BACKEND_DISABLE_SHIFT 16
1174
1175#define TCP_CHAN_STEER_LO 0xac0c
1176#define TCP_CHAN_STEER_HI 0xac10
1177
Alex Deucher1c491652013-04-09 12:45:26 -0400[diff] [blame]1178#define TC_CFG_L1_LOAD_POLICY0 0xAC68
1179#define TC_CFG_L1_LOAD_POLICY1 0xAC6C
1180#define TC_CFG_L1_STORE_POLICY 0xAC70
1181#define TC_CFG_L2_LOAD_POLICY0 0xAC74
1182#define TC_CFG_L2_LOAD_POLICY1 0xAC78
1183#define TC_CFG_L2_STORE_POLICY0 0xAC7C
1184#define TC_CFG_L2_STORE_POLICY1 0xAC80
1185#define TC_CFG_L2_ATOMIC_POLICY 0xAC84
1186#define TC_CFG_L1_VOLATILE 0xAC88
1187#define TC_CFG_L2_VOLATILE 0xAC8C
1188
Alex Deucher841cf442012-12-18 21:47:44 -0500[diff] [blame]1189#define CP_RB0_BASE 0xC100
1190#define CP_RB0_CNTL 0xC104
1191#define RB_BUFSZ(x) ((x) << 0)
1192#define RB_BLKSZ(x) ((x) << 8)
1193#define BUF_SWAP_32BIT (2 << 16)
1194#define RB_NO_UPDATE (1 << 27)
1195#define RB_RPTR_WR_ENA (1 << 31)
1196
1197#define CP_RB0_RPTR_ADDR 0xC10C
1198#define RB_RPTR_SWAP_32BIT (2 << 0)
1199#define CP_RB0_RPTR_ADDR_HI 0xC110
1200#define CP_RB0_WPTR 0xC114
1201
1202#define CP_DEVICE_ID 0xC12C
1203#define CP_ENDIAN_SWAP 0xC140
1204#define CP_RB_VMID 0xC144
1205
1206#define CP_PFP_UCODE_ADDR 0xC150
1207#define CP_PFP_UCODE_DATA 0xC154
1208#define CP_ME_RAM_RADDR 0xC158
1209#define CP_ME_RAM_WADDR 0xC15C
1210#define CP_ME_RAM_DATA 0xC160
1211
1212#define CP_CE_UCODE_ADDR 0xC168
1213#define CP_CE_UCODE_DATA 0xC16C
1214#define CP_MEC_ME1_UCODE_ADDR 0xC170
1215#define CP_MEC_ME1_UCODE_DATA 0xC174
1216#define CP_MEC_ME2_UCODE_ADDR 0xC178
1217#define CP_MEC_ME2_UCODE_DATA 0xC17C
1218
Alex Deucherf6796ca2012-11-09 10:44:08 -0500[diff] [blame]1219#define CP_INT_CNTL_RING0 0xC1A8
1220# define CNTX_BUSY_INT_ENABLE (1 << 19)
1221# define CNTX_EMPTY_INT_ENABLE (1 << 20)
1222# define PRIV_INSTR_INT_ENABLE (1 << 22)
1223# define PRIV_REG_INT_ENABLE (1 << 23)
1224# define TIME_STAMP_INT_ENABLE (1 << 26)
1225# define CP_RINGID2_INT_ENABLE (1 << 29)
1226# define CP_RINGID1_INT_ENABLE (1 << 30)
1227# define CP_RINGID0_INT_ENABLE (1 << 31)
1228
Alex Deuchera59781b2012-11-09 10:45:57 -0500[diff] [blame]1229#define CP_INT_STATUS_RING0 0xC1B4
1230# define PRIV_INSTR_INT_STAT (1 << 22)
1231# define PRIV_REG_INT_STAT (1 << 23)
1232# define TIME_STAMP_INT_STAT (1 << 26)
1233# define CP_RINGID2_INT_STAT (1 << 29)
1234# define CP_RINGID1_INT_STAT (1 << 30)
1235# define CP_RINGID0_INT_STAT (1 << 31)
1236
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]1237#define CP_MEM_SLP_CNTL 0xC1E4
1238# define CP_MEM_LS_EN (1 << 0)
1239
Alex Deucher963e81f2013-06-26 17:37:11 -0400[diff] [blame]1240#define CP_CPF_DEBUG 0xC200
1241
1242#define CP_PQ_WPTR_POLL_CNTL 0xC20C
1243#define WPTR_POLL_EN (1 << 31)
1244
Alex Deuchera59781b2012-11-09 10:45:57 -0500[diff] [blame]1245#define CP_ME1_PIPE0_INT_CNTL 0xC214
1246#define CP_ME1_PIPE1_INT_CNTL 0xC218
1247#define CP_ME1_PIPE2_INT_CNTL 0xC21C
1248#define CP_ME1_PIPE3_INT_CNTL 0xC220
1249#define CP_ME2_PIPE0_INT_CNTL 0xC224
1250#define CP_ME2_PIPE1_INT_CNTL 0xC228
1251#define CP_ME2_PIPE2_INT_CNTL 0xC22C
1252#define CP_ME2_PIPE3_INT_CNTL 0xC230
1253# define DEQUEUE_REQUEST_INT_ENABLE (1 << 13)
1254# define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17)
1255# define PRIV_REG_INT_ENABLE (1 << 23)
1256# define TIME_STAMP_INT_ENABLE (1 << 26)
1257# define GENERIC2_INT_ENABLE (1 << 29)
1258# define GENERIC1_INT_ENABLE (1 << 30)
1259# define GENERIC0_INT_ENABLE (1 << 31)
1260#define CP_ME1_PIPE0_INT_STATUS 0xC214
1261#define CP_ME1_PIPE1_INT_STATUS 0xC218
1262#define CP_ME1_PIPE2_INT_STATUS 0xC21C
1263#define CP_ME1_PIPE3_INT_STATUS 0xC220
1264#define CP_ME2_PIPE0_INT_STATUS 0xC224
1265#define CP_ME2_PIPE1_INT_STATUS 0xC228
1266#define CP_ME2_PIPE2_INT_STATUS 0xC22C
1267#define CP_ME2_PIPE3_INT_STATUS 0xC230
1268# define DEQUEUE_REQUEST_INT_STATUS (1 << 13)
1269# define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17)
1270# define PRIV_REG_INT_STATUS (1 << 23)
1271# define TIME_STAMP_INT_STATUS (1 << 26)
1272# define GENERIC2_INT_STATUS (1 << 29)
1273# define GENERIC1_INT_STATUS (1 << 30)
1274# define GENERIC0_INT_STATUS (1 << 31)
1275
Alex Deucher841cf442012-12-18 21:47:44 -0500[diff] [blame]1276#define CP_MAX_CONTEXT 0xC2B8
1277
1278#define CP_RB0_BASE_HI 0xC2C4
1279
Alex Deucherf6796ca2012-11-09 10:44:08 -0500[diff] [blame]1280#define RLC_CNTL 0xC300
1281# define RLC_ENABLE (1 << 0)
1282
1283#define RLC_MC_CNTL 0xC30C
1284
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]1285#define RLC_MEM_SLP_CNTL 0xC318
1286# define RLC_MEM_LS_EN (1 << 0)
1287
Alex Deucherf6796ca2012-11-09 10:44:08 -0500[diff] [blame]1288#define RLC_LB_CNTR_MAX 0xC348
1289
1290#define RLC_LB_CNTL 0xC364
Alex Deucher866d83d2013-04-15 17:13:29 -0400[diff] [blame]1291# define LOAD_BALANCE_ENABLE (1 << 0)
Alex Deucherf6796ca2012-11-09 10:44:08 -0500[diff] [blame]1292
1293#define RLC_LB_CNTR_INIT 0xC36C
1294
1295#define RLC_SAVE_AND_RESTORE_BASE 0xC374
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]1296#define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */
1297#define RLC_CP_TABLE_RESTORE 0xC378 /* APU */
1298#define RLC_PG_DELAY_2 0xC37C
Alex Deucherf6796ca2012-11-09 10:44:08 -0500[diff] [blame]1299
1300#define RLC_GPM_UCODE_ADDR 0xC388
1301#define RLC_GPM_UCODE_DATA 0xC38C
Alex Deucher44fa3462012-12-18 22:17:00 -0500[diff] [blame]1302#define RLC_GPU_CLOCK_COUNT_LSB 0xC390
1303#define RLC_GPU_CLOCK_COUNT_MSB 0xC394
1304#define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398
Alex Deucherf6796ca2012-11-09 10:44:08 -0500[diff] [blame]1305#define RLC_UCODE_CNTL 0xC39C
1306
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]1307#define RLC_GPM_STAT 0xC400
1308# define RLC_GPM_BUSY (1 << 0)
Alex Deuchera412fce2013-04-22 20:23:31 -0400[diff] [blame]1309# define GFX_POWER_STATUS (1 << 1)
1310# define GFX_CLOCK_STATUS (1 << 2)
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]1311
1312#define RLC_PG_CNTL 0xC40C
1313# define GFX_PG_ENABLE (1 << 0)
1314# define GFX_PG_SRC (1 << 1)
1315# define DYN_PER_CU_PG_ENABLE (1 << 2)
1316# define STATIC_PER_CU_PG_ENABLE (1 << 3)
1317# define DISABLE_GDS_PG (1 << 13)
1318# define DISABLE_CP_PG (1 << 15)
1319# define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17)
1320# define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18)
1321
1322#define RLC_CGTT_MGCG_OVERRIDE 0xC420
Alex Deucherf6796ca2012-11-09 10:44:08 -0500[diff] [blame]1323#define RLC_CGCG_CGLS_CTRL 0xC424
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]1324# define CGCG_EN (1 << 0)
1325# define CGLS_EN (1 << 1)
1326
1327#define RLC_PG_DELAY 0xC434
Alex Deucherf6796ca2012-11-09 10:44:08 -0500[diff] [blame]1328
1329#define RLC_LB_INIT_CU_MASK 0xC43C
1330
1331#define RLC_LB_PARAMS 0xC444
1332
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]1333#define RLC_PG_AO_CU_MASK 0xC44C
1334
1335#define RLC_MAX_PG_CU 0xC450
1336# define MAX_PU_CU(x) ((x) << 0)
1337# define MAX_PU_CU_MASK (0xff << 0)
1338#define RLC_AUTO_PG_CTRL 0xC454
1339# define AUTO_PG_EN (1 << 0)
1340# define GRBM_REG_SGIT(x) ((x) << 3)
1341# define GRBM_REG_SGIT_MASK (0xffff << 3)
1342
1343#define RLC_SERDES_WR_CU_MASTER_MASK 0xC474
1344#define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478
1345#define RLC_SERDES_WR_CTRL 0xC47C
1346#define BPM_ADDR(x) ((x) << 0)
1347#define BPM_ADDR_MASK (0xff << 0)
1348#define CGLS_ENABLE (1 << 16)
1349#define CGCG_OVERRIDE_0 (1 << 20)
1350#define MGCG_OVERRIDE_0 (1 << 22)
1351#define MGCG_OVERRIDE_1 (1 << 23)
1352
Alex Deucherf6796ca2012-11-09 10:44:08 -0500[diff] [blame]1353#define RLC_SERDES_CU_MASTER_BUSY 0xC484
1354#define RLC_SERDES_NONCU_MASTER_BUSY 0xC488
1355# define SE_MASTER_BUSY_MASK 0x0000ffff
1356# define GC_MASTER_BUSY (1 << 16)
1357# define TC0_MASTER_BUSY (1 << 17)
1358# define TC1_MASTER_BUSY (1 << 18)
1359
1360#define RLC_GPM_SCRATCH_ADDR 0xC4B0
1361#define RLC_GPM_SCRATCH_DATA 0xC4B4
1362
Alex Deuchera412fce2013-04-22 20:23:31 -0400[diff] [blame]1363#define RLC_GPR_REG2 0xC4E8
1364#define REQ 0x00000001
1365#define MESSAGE(x) ((x) << 1)
1366#define MESSAGE_MASK 0x0000001e
1367#define MSG_ENTER_RLC_SAFE_MODE 1
1368#define MSG_EXIT_RLC_SAFE_MODE 0
1369
Alex Deucher963e81f2013-06-26 17:37:11 -0400[diff] [blame]1370#define CP_HPD_EOP_BASE_ADDR 0xC904
1371#define CP_HPD_EOP_BASE_ADDR_HI 0xC908
1372#define CP_HPD_EOP_VMID 0xC90C
1373#define CP_HPD_EOP_CONTROL 0xC910
1374#define EOP_SIZE(x) ((x) << 0)
1375#define EOP_SIZE_MASK (0x3f << 0)
1376#define CP_MQD_BASE_ADDR 0xC914
1377#define CP_MQD_BASE_ADDR_HI 0xC918
1378#define CP_HQD_ACTIVE 0xC91C
1379#define CP_HQD_VMID 0xC920
1380
1381#define CP_HQD_PQ_BASE 0xC934
1382#define CP_HQD_PQ_BASE_HI 0xC938
1383#define CP_HQD_PQ_RPTR 0xC93C
1384#define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940
1385#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944
1386#define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948
1387#define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C
1388#define CP_HQD_PQ_DOORBELL_CONTROL 0xC950
1389#define DOORBELL_OFFSET(x) ((x) << 2)
1390#define DOORBELL_OFFSET_MASK (0x1fffff << 2)
1391#define DOORBELL_SOURCE (1 << 28)
1392#define DOORBELL_SCHD_HIT (1 << 29)
1393#define DOORBELL_EN (1 << 30)
1394#define DOORBELL_HIT (1 << 31)
1395#define CP_HQD_PQ_WPTR 0xC954
1396#define CP_HQD_PQ_CONTROL 0xC958
1397#define QUEUE_SIZE(x) ((x) << 0)
1398#define QUEUE_SIZE_MASK (0x3f << 0)
1399#define RPTR_BLOCK_SIZE(x) ((x) << 8)
1400#define RPTR_BLOCK_SIZE_MASK (0x3f << 8)
1401#define PQ_VOLATILE (1 << 26)
1402#define NO_UPDATE_RPTR (1 << 27)
1403#define UNORD_DISPATCH (1 << 28)
1404#define ROQ_PQ_IB_FLIP (1 << 29)
1405#define PRIV_STATE (1 << 30)
1406#define KMD_QUEUE (1 << 31)
1407
1408#define CP_HQD_DEQUEUE_REQUEST 0xC974
1409
1410#define CP_MQD_CONTROL 0xC99C
1411#define MQD_VMID(x) ((x) << 0)
1412#define MQD_VMID_MASK (0xf << 0)
1413
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]1414#define DB_RENDER_CONTROL 0x28000
1415
Alex Deucher8cc1a532013-04-09 12:41:24 -0400[diff] [blame]1416#define PA_SC_RASTER_CONFIG 0x28350
1417# define RASTER_CONFIG_RB_MAP_0 0
1418# define RASTER_CONFIG_RB_MAP_1 1
1419# define RASTER_CONFIG_RB_MAP_2 2
1420# define RASTER_CONFIG_RB_MAP_3 3
1421
Alex Deucher2cae3bc2012-07-05 11:45:40 -0400[diff] [blame]1422#define VGT_EVENT_INITIATOR 0x28a90
1423# define SAMPLE_STREAMOUTSTATS1 (1 << 0)
1424# define SAMPLE_STREAMOUTSTATS2 (2 << 0)
1425# define SAMPLE_STREAMOUTSTATS3 (3 << 0)
1426# define CACHE_FLUSH_TS (4 << 0)
1427# define CACHE_FLUSH (6 << 0)
1428# define CS_PARTIAL_FLUSH (7 << 0)
1429# define VGT_STREAMOUT_RESET (10 << 0)
1430# define END_OF_PIPE_INCR_DE (11 << 0)
1431# define END_OF_PIPE_IB_END (12 << 0)
1432# define RST_PIX_CNT (13 << 0)
1433# define VS_PARTIAL_FLUSH (15 << 0)
1434# define PS_PARTIAL_FLUSH (16 << 0)
1435# define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
1436# define ZPASS_DONE (21 << 0)
1437# define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
1438# define PERFCOUNTER_START (23 << 0)
1439# define PERFCOUNTER_STOP (24 << 0)
1440# define PIPELINESTAT_START (25 << 0)
1441# define PIPELINESTAT_STOP (26 << 0)
1442# define PERFCOUNTER_SAMPLE (27 << 0)
1443# define SAMPLE_PIPELINESTAT (30 << 0)
1444# define SO_VGT_STREAMOUT_FLUSH (31 << 0)
1445# define SAMPLE_STREAMOUTSTATS (32 << 0)
1446# define RESET_VTX_CNT (33 << 0)
1447# define VGT_FLUSH (36 << 0)
1448# define BOTTOM_OF_PIPE_TS (40 << 0)
1449# define DB_CACHE_FLUSH_AND_INV (42 << 0)
1450# define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
1451# define FLUSH_AND_INV_DB_META (44 << 0)
1452# define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
1453# define FLUSH_AND_INV_CB_META (46 << 0)
1454# define CS_DONE (47 << 0)
1455# define PS_DONE (48 << 0)
1456# define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
1457# define THREAD_TRACE_START (51 << 0)
1458# define THREAD_TRACE_STOP (52 << 0)
1459# define THREAD_TRACE_FLUSH (54 << 0)
1460# define THREAD_TRACE_FINISH (55 << 0)
1461# define PIXEL_PIPE_STAT_CONTROL (56 << 0)
1462# define PIXEL_PIPE_STAT_DUMP (57 << 0)
1463# define PIXEL_PIPE_STAT_RESET (58 << 0)
1464
Alex Deucher841cf442012-12-18 21:47:44 -0500[diff] [blame]1465#define SCRATCH_REG0 0x30100
1466#define SCRATCH_REG1 0x30104
1467#define SCRATCH_REG2 0x30108
1468#define SCRATCH_REG3 0x3010C
1469#define SCRATCH_REG4 0x30110
1470#define SCRATCH_REG5 0x30114
1471#define SCRATCH_REG6 0x30118
1472#define SCRATCH_REG7 0x3011C
1473
1474#define SCRATCH_UMSK 0x30140
1475#define SCRATCH_ADDR 0x30144
1476
1477#define CP_SEM_WAIT_TIMER 0x301BC
1478
1479#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8
1480
Alex Deucher2cae3bc2012-07-05 11:45:40 -0400[diff] [blame]1481#define CP_WAIT_REG_MEM_TIMEOUT 0x301D0
1482
Alex Deucher8cc1a532013-04-09 12:41:24 -0400[diff] [blame]1483#define GRBM_GFX_INDEX 0x30800
1484#define INSTANCE_INDEX(x) ((x) << 0)
1485#define SH_INDEX(x) ((x) << 8)
1486#define SE_INDEX(x) ((x) << 16)
1487#define SH_BROADCAST_WRITES (1 << 29)
1488#define INSTANCE_BROADCAST_WRITES (1 << 30)
1489#define SE_BROADCAST_WRITES (1 << 31)
1490
1491#define VGT_ESGS_RING_SIZE 0x30900
1492#define VGT_GSVS_RING_SIZE 0x30904
1493#define VGT_PRIMITIVE_TYPE 0x30908
1494#define VGT_INDEX_TYPE 0x3090C
1495
1496#define VGT_NUM_INDICES 0x30930
1497#define VGT_NUM_INSTANCES 0x30934
1498#define VGT_TF_RING_SIZE 0x30938
1499#define VGT_HS_OFFCHIP_PARAM 0x3093C
1500#define VGT_TF_MEMORY_BASE 0x30940
1501
1502#define PA_SU_LINE_STIPPLE_VALUE 0x30a00
1503#define PA_SC_LINE_STIPPLE_STATE 0x30a04
1504
1505#define SQC_CACHES 0x30d20
1506
1507#define CP_PERFMON_CNTL 0x36020
1508
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]1509#define CGTS_SM_CTRL_REG 0x3c000
1510#define SM_MODE(x) ((x) << 17)
1511#define SM_MODE_MASK (0x7 << 17)
1512#define SM_MODE_ENABLE (1 << 20)
1513#define CGTS_OVERRIDE (1 << 21)
1514#define CGTS_LS_OVERRIDE (1 << 22)
1515#define ON_MONITOR_ADD_EN (1 << 23)
1516#define ON_MONITOR_ADD(x) ((x) << 24)
1517#define ON_MONITOR_ADD_MASK (0xff << 24)
1518
Alex Deucher8cc1a532013-04-09 12:41:24 -0400[diff] [blame]1519#define CGTS_TCC_DISABLE 0x3c00c
1520#define CGTS_USER_TCC_DISABLE 0x3c010
1521#define TCC_DISABLE_MASK 0xFFFF0000
1522#define TCC_DISABLE_SHIFT 16
1523
Alex Deucherf6796ca2012-11-09 10:44:08 -0500[diff] [blame]1524#define CB_CGTT_SCLK_CTRL 0x3c2a0
1525
Alex Deucher841cf442012-12-18 21:47:44 -0500[diff] [blame]1526/*
1527 * PM4
1528 */
1529#define PACKET_TYPE0 0
1530#define PACKET_TYPE1 1
1531#define PACKET_TYPE2 2
1532#define PACKET_TYPE3 3
1533
1534#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
1535#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
1536#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
1537#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
1538#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
1539 (((reg) >> 2) & 0xFFFF) | \
1540 ((n) & 0x3FFF) << 16)
1541#define CP_PACKET2 0x80000000
1542#define PACKET2_PAD_SHIFT 0
1543#define PACKET2_PAD_MASK (0x3fffffff << 0)
1544
1545#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1546
1547#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
1548 (((op) & 0xFF) << 8) | \
1549 ((n) & 0x3FFF) << 16)
1550
1551#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1552
1553/* Packet 3 types */
1554#define PACKET3_NOP 0x10
1555#define PACKET3_SET_BASE 0x11
1556#define PACKET3_BASE_INDEX(x) ((x) << 0)
1557#define CE_PARTITION_BASE 3
1558#define PACKET3_CLEAR_STATE 0x12
1559#define PACKET3_INDEX_BUFFER_SIZE 0x13
1560#define PACKET3_DISPATCH_DIRECT 0x15
1561#define PACKET3_DISPATCH_INDIRECT 0x16
1562#define PACKET3_ATOMIC_GDS 0x1D
1563#define PACKET3_ATOMIC_MEM 0x1E
1564#define PACKET3_OCCLUSION_QUERY 0x1F
1565#define PACKET3_SET_PREDICATION 0x20
1566#define PACKET3_REG_RMW 0x21
1567#define PACKET3_COND_EXEC 0x22
1568#define PACKET3_PRED_EXEC 0x23
1569#define PACKET3_DRAW_INDIRECT 0x24
1570#define PACKET3_DRAW_INDEX_INDIRECT 0x25
1571#define PACKET3_INDEX_BASE 0x26
1572#define PACKET3_DRAW_INDEX_2 0x27
1573#define PACKET3_CONTEXT_CONTROL 0x28
1574#define PACKET3_INDEX_TYPE 0x2A
1575#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
1576#define PACKET3_DRAW_INDEX_AUTO 0x2D
1577#define PACKET3_NUM_INSTANCES 0x2F
1578#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1579#define PACKET3_INDIRECT_BUFFER_CONST 0x33
1580#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1581#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1582#define PACKET3_DRAW_PREAMBLE 0x36
1583#define PACKET3_WRITE_DATA 0x37
Alex Deucher2cae3bc2012-07-05 11:45:40 -0400[diff] [blame]1584#define WRITE_DATA_DST_SEL(x) ((x) << 8)
1585 /* 0 - register
1586 * 1 - memory (sync - via GRBM)
1587 * 2 - gl2
1588 * 3 - gds
1589 * 4 - reserved
1590 * 5 - memory (async - direct)
1591 */
1592#define WR_ONE_ADDR (1 << 16)
1593#define WR_CONFIRM (1 << 20)
1594#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
1595 /* 0 - LRU
1596 * 1 - Stream
1597 */
1598#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
1599 /* 0 - me
1600 * 1 - pfp
1601 * 2 - ce
1602 */
Alex Deucher841cf442012-12-18 21:47:44 -0500[diff] [blame]1603#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
1604#define PACKET3_MEM_SEMAPHORE 0x39
Alex Deucher2cae3bc2012-07-05 11:45:40 -0400[diff] [blame]1605# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
1606# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
1607# define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
1608# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
1609# define PACKET3_SEM_SEL_WAIT (0x7 << 29)
Alex Deucher841cf442012-12-18 21:47:44 -0500[diff] [blame]1610#define PACKET3_COPY_DW 0x3B
1611#define PACKET3_WAIT_REG_MEM 0x3C
Alex Deucher2cae3bc2012-07-05 11:45:40 -0400[diff] [blame]1612#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
1613 /* 0 - always
1614 * 1 - <
1615 * 2 - <=
1616 * 3 - ==
1617 * 4 - !=
1618 * 5 - >=
1619 * 6 - >
1620 */
1621#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
1622 /* 0 - reg
1623 * 1 - mem
1624 */
1625#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
1626 /* 0 - wait_reg_mem
1627 * 1 - wr_wait_wr_reg
1628 */
1629#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
1630 /* 0 - me
1631 * 1 - pfp
1632 */
Alex Deucher841cf442012-12-18 21:47:44 -0500[diff] [blame]1633#define PACKET3_INDIRECT_BUFFER 0x3F
Alex Deucher2cae3bc2012-07-05 11:45:40 -0400[diff] [blame]1634#define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
1635#define INDIRECT_BUFFER_VALID (1 << 23)
1636#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
1637 /* 0 - LRU
1638 * 1 - Stream
1639 * 2 - Bypass
1640 */
Alex Deucher841cf442012-12-18 21:47:44 -0500[diff] [blame]1641#define PACKET3_COPY_DATA 0x40
1642#define PACKET3_PFP_SYNC_ME 0x42
1643#define PACKET3_SURFACE_SYNC 0x43
1644# define PACKET3_DEST_BASE_0_ENA (1 << 0)
1645# define PACKET3_DEST_BASE_1_ENA (1 << 1)
1646# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1647# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1648# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1649# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1650# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1651# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1652# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1653# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1654# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1655# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
1656# define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */
1657# define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */
1658# define PACKET3_DEST_BASE_2_ENA (1 << 19)
1659# define PACKET3_DEST_BASE_3_ENA (1 << 21)
1660# define PACKET3_TCL1_ACTION_ENA (1 << 22)
1661# define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */
1662# define PACKET3_CB_ACTION_ENA (1 << 25)
1663# define PACKET3_DB_ACTION_ENA (1 << 26)
1664# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1665# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
1666# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1667#define PACKET3_COND_WRITE 0x45
1668#define PACKET3_EVENT_WRITE 0x46
1669#define EVENT_TYPE(x) ((x) << 0)
1670#define EVENT_INDEX(x) ((x) << 8)
1671 /* 0 - any non-TS event
1672 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
1673 * 2 - SAMPLE_PIPELINESTAT
1674 * 3 - SAMPLE_STREAMOUTSTAT*
1675 * 4 - *S_PARTIAL_FLUSH
1676 * 5 - EOP events
1677 * 6 - EOS events
1678 */
1679#define PACKET3_EVENT_WRITE_EOP 0x47
1680#define EOP_TCL1_VOL_ACTION_EN (1 << 12)
1681#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
1682#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
1683#define EOP_TCL1_ACTION_EN (1 << 16)
1684#define EOP_TC_ACTION_EN (1 << 17) /* L2 */
Alex Deucher2cae3bc2012-07-05 11:45:40 -0400[diff] [blame]1685#define EOP_CACHE_POLICY(x) ((x) << 25)
Alex Deucher841cf442012-12-18 21:47:44 -0500[diff] [blame]1686 /* 0 - LRU
1687 * 1 - Stream
1688 * 2 - Bypass
1689 */
Alex Deucher2cae3bc2012-07-05 11:45:40 -0400[diff] [blame]1690#define EOP_TCL2_VOLATILE (1 << 27)
Alex Deucher841cf442012-12-18 21:47:44 -0500[diff] [blame]1691#define DATA_SEL(x) ((x) << 29)
1692 /* 0 - discard
1693 * 1 - send low 32bit data
1694 * 2 - send 64bit data
1695 * 3 - send 64bit GPU counter value
1696 * 4 - send 64bit sys counter value
1697 */
1698#define INT_SEL(x) ((x) << 24)
1699 /* 0 - none
1700 * 1 - interrupt only (DATA_SEL = 0)
1701 * 2 - interrupt when data write is confirmed
1702 */
1703#define DST_SEL(x) ((x) << 16)
1704 /* 0 - MC
1705 * 1 - TC/L2
1706 */
1707#define PACKET3_EVENT_WRITE_EOS 0x48
1708#define PACKET3_RELEASE_MEM 0x49
1709#define PACKET3_PREAMBLE_CNTL 0x4A
1710# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
1711# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
1712#define PACKET3_DMA_DATA 0x50
1713#define PACKET3_AQUIRE_MEM 0x58
1714#define PACKET3_REWIND 0x59
1715#define PACKET3_LOAD_UCONFIG_REG 0x5E
1716#define PACKET3_LOAD_SH_REG 0x5F
1717#define PACKET3_LOAD_CONFIG_REG 0x60
1718#define PACKET3_LOAD_CONTEXT_REG 0x61
1719#define PACKET3_SET_CONFIG_REG 0x68
1720#define PACKET3_SET_CONFIG_REG_START 0x00008000
1721#define PACKET3_SET_CONFIG_REG_END 0x0000b000
1722#define PACKET3_SET_CONTEXT_REG 0x69
1723#define PACKET3_SET_CONTEXT_REG_START 0x00028000
1724#define PACKET3_SET_CONTEXT_REG_END 0x00029000
1725#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1726#define PACKET3_SET_SH_REG 0x76
1727#define PACKET3_SET_SH_REG_START 0x0000b000
1728#define PACKET3_SET_SH_REG_END 0x0000c000
1729#define PACKET3_SET_SH_REG_OFFSET 0x77
1730#define PACKET3_SET_QUEUE_REG 0x78
1731#define PACKET3_SET_UCONFIG_REG 0x79
Alex Deucher2cae3bc2012-07-05 11:45:40 -0400[diff] [blame]1732#define PACKET3_SET_UCONFIG_REG_START 0x00030000
1733#define PACKET3_SET_UCONFIG_REG_END 0x00031000
Alex Deucher841cf442012-12-18 21:47:44 -0500[diff] [blame]1734#define PACKET3_SCRATCH_RAM_WRITE 0x7D
1735#define PACKET3_SCRATCH_RAM_READ 0x7E
1736#define PACKET3_LOAD_CONST_RAM 0x80
1737#define PACKET3_WRITE_CONST_RAM 0x81
1738#define PACKET3_DUMP_CONST_RAM 0x83
1739#define PACKET3_INCREMENT_CE_COUNTER 0x84
1740#define PACKET3_INCREMENT_DE_COUNTER 0x85
1741#define PACKET3_WAIT_ON_CE_COUNTER 0x86
1742#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
Alex Deucher2cae3bc2012-07-05 11:45:40 -0400[diff] [blame]1743#define PACKET3_SWITCH_BUFFER 0x8B
Alex Deucher841cf442012-12-18 21:47:44 -0500[diff] [blame]1744
Alex Deucher21a93e12013-04-09 12:47:11 -0400[diff] [blame]1745/* SDMA - first instance at 0xd000, second at 0xd800 */
1746#define SDMA0_REGISTER_OFFSET 0x0 /* not a register */
1747#define SDMA1_REGISTER_OFFSET 0x800 /* not a register */
1748
1749#define SDMA0_UCODE_ADDR 0xD000
1750#define SDMA0_UCODE_DATA 0xD004
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]1751#define SDMA0_POWER_CNTL 0xD008
1752#define SDMA0_CLK_CTRL 0xD00C
Alex Deucher21a93e12013-04-09 12:47:11 -0400[diff] [blame]1753
1754#define SDMA0_CNTL 0xD010
1755# define TRAP_ENABLE (1 << 0)
1756# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1757# define SEM_WAIT_INT_ENABLE (1 << 2)
1758# define DATA_SWAP_ENABLE (1 << 3)
1759# define FENCE_SWAP_ENABLE (1 << 4)
1760# define AUTO_CTXSW_ENABLE (1 << 18)
1761# define CTXEMPTY_INT_ENABLE (1 << 28)
1762
1763#define SDMA0_TILING_CONFIG 0xD018
1764
1765#define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020
1766#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024
1767
1768#define SDMA0_STATUS_REG 0xd034
1769# define SDMA_IDLE (1 << 0)
1770
1771#define SDMA0_ME_CNTL 0xD048
1772# define SDMA_HALT (1 << 0)
1773
1774#define SDMA0_GFX_RB_CNTL 0xD200
1775# define SDMA_RB_ENABLE (1 << 0)
1776# define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */
1777# define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
1778# define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1779# define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
1780# define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
1781#define SDMA0_GFX_RB_BASE 0xD204
1782#define SDMA0_GFX_RB_BASE_HI 0xD208
1783#define SDMA0_GFX_RB_RPTR 0xD20C
1784#define SDMA0_GFX_RB_WPTR 0xD210
1785
1786#define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220
1787#define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224
1788#define SDMA0_GFX_IB_CNTL 0xD228
1789# define SDMA_IB_ENABLE (1 << 0)
1790# define SDMA_IB_SWAP_ENABLE (1 << 4)
1791# define SDMA_SWITCH_INSIDE_IB (1 << 8)
1792# define SDMA_CMD_VMID(x) ((x) << 16)
1793
1794#define SDMA0_GFX_VIRTUAL_ADDR 0xD29C
1795#define SDMA0_GFX_APE1_CNTL 0xD2A0
1796
1797#define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \
1798 (((sub_op) & 0xFF) << 8) | \
1799 (((op) & 0xFF) << 0))
1800/* sDMA opcodes */
1801#define SDMA_OPCODE_NOP 0
1802#define SDMA_OPCODE_COPY 1
1803# define SDMA_COPY_SUB_OPCODE_LINEAR 0
1804# define SDMA_COPY_SUB_OPCODE_TILED 1
1805# define SDMA_COPY_SUB_OPCODE_SOA 3
1806# define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4
1807# define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5
1808# define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6
1809#define SDMA_OPCODE_WRITE 2
1810# define SDMA_WRITE_SUB_OPCODE_LINEAR 0
1811# define SDMA_WRTIE_SUB_OPCODE_TILED 1
1812#define SDMA_OPCODE_INDIRECT_BUFFER 4
1813#define SDMA_OPCODE_FENCE 5
1814#define SDMA_OPCODE_TRAP 6
1815#define SDMA_OPCODE_SEMAPHORE 7
1816# define SDMA_SEMAPHORE_EXTRA_O (1 << 13)
1817 /* 0 - increment
1818 * 1 - write 1
1819 */
1820# define SDMA_SEMAPHORE_EXTRA_S (1 << 14)
1821 /* 0 - wait
1822 * 1 - signal
1823 */
1824# define SDMA_SEMAPHORE_EXTRA_M (1 << 15)
1825 /* mailbox */
1826#define SDMA_OPCODE_POLL_REG_MEM 8
1827# define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10)
1828 /* 0 - wait_reg_mem
1829 * 1 - wr_wait_wr_reg
1830 */
1831# define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12)
1832 /* 0 - always
1833 * 1 - <
1834 * 2 - <=
1835 * 3 - ==
1836 * 4 - !=
1837 * 5 - >=
1838 * 6 - >
1839 */
1840# define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15)
1841 /* 0 = register
1842 * 1 = memory
1843 */
1844#define SDMA_OPCODE_COND_EXEC 9
1845#define SDMA_OPCODE_CONSTANT_FILL 11
1846# define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14)
1847 /* 0 = byte fill
1848 * 2 = DW fill
1849 */
1850#define SDMA_OPCODE_GENERATE_PTE_PDE 12
1851#define SDMA_OPCODE_TIMESTAMP 13
1852# define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0
1853# define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1
1854# define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2
1855#define SDMA_OPCODE_SRBM_WRITE 14
1856# define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12)
1857 /* byte mask */
1858
Christian König87167bb2013-04-09 13:39:21 -0400[diff] [blame]1859/* UVD */
1860
1861#define UVD_UDEC_ADDR_CONFIG 0xef4c
1862#define UVD_UDEC_DB_ADDR_CONFIG 0xef50
1863#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
1864
1865#define UVD_LMI_EXT40_ADDR 0xf498
1866#define UVD_LMI_ADDR_EXT 0xf594
1867#define UVD_VCPU_CACHE_OFFSET0 0xf608
1868#define UVD_VCPU_CACHE_SIZE0 0xf60c
1869#define UVD_VCPU_CACHE_OFFSET1 0xf610
1870#define UVD_VCPU_CACHE_SIZE1 0xf614
1871#define UVD_VCPU_CACHE_OFFSET2 0xf618
1872#define UVD_VCPU_CACHE_SIZE2 0xf61c
1873
1874#define UVD_RBC_RB_RPTR 0xf690
1875#define UVD_RBC_RB_WPTR 0xf694
1876
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]1877#define UVD_CGC_CTRL 0xF4B0
1878# define DCM (1 << 0)
1879# define CG_DT(x) ((x) << 2)
1880# define CG_DT_MASK (0xf << 2)
1881# define CLK_OD(x) ((x) << 6)
1882# define CLK_OD_MASK (0x1f << 6)
1883
Christian König87167bb2013-04-09 13:39:21 -0400[diff] [blame]1884/* UVD clocks */
1885
1886#define CG_DCLK_CNTL 0xC050009C
1887# define DCLK_DIVIDER_MASK 0x7f
1888# define DCLK_DIR_CNTL_EN (1 << 8)
1889#define CG_DCLK_STATUS 0xC05000A0
1890# define DCLK_STATUS (1 << 0)
1891#define CG_VCLK_CNTL 0xC05000A4
1892#define CG_VCLK_STATUS 0xC05000A8
1893
Alex Deucher22c775c2013-07-23 09:41:05 -0400[diff] [blame]1894/* UVD CTX indirect */
1895#define UVD_CGC_MEM_CTRL 0xC0
1896
Alex Deucher8cc1a532013-04-09 12:41:24 -0400[diff] [blame]1897#endif