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johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001/*
2 * rt5631.c -- RT5631 ALSA Soc Audio driver
3 *
4 * Copyright 2011 Realtek Microelectronics
5 *
6 * Author: flove <flove@realtek.com>
7 *
8 * Based on WM8753.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
Mark Brown01476802012-05-08 15:52:55 +010021#include <linux/regmap.h>
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +080022#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29
30#include "rt5631.h"
31
32struct rt5631_priv {
Mark Brown01476802012-05-08 15:52:55 +010033 struct regmap *regmap;
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +080034 int codec_version;
35 int master;
36 int sysclk;
37 int rx_rate;
38 int bclk_rate;
39 int dmic_used_flag;
40};
41
Mark Brown01476802012-05-08 15:52:55 +010042static const struct reg_default rt5631_reg[] = {
43 { RT5631_SPK_OUT_VOL, 0x8888 },
44 { RT5631_HP_OUT_VOL, 0x8080 },
45 { RT5631_MONO_AXO_1_2_VOL, 0xa080 },
46 { RT5631_AUX_IN_VOL, 0x0808 },
47 { RT5631_ADC_REC_MIXER, 0xf0f0 },
48 { RT5631_VDAC_DIG_VOL, 0x0010 },
49 { RT5631_OUTMIXER_L_CTRL, 0xffc0 },
50 { RT5631_OUTMIXER_R_CTRL, 0xffc0 },
51 { RT5631_AXO1MIXER_CTRL, 0x88c0 },
52 { RT5631_AXO2MIXER_CTRL, 0x88c0 },
53 { RT5631_DIG_MIC_CTRL, 0x3000 },
54 { RT5631_MONO_INPUT_VOL, 0x8808 },
55 { RT5631_SPK_MIXER_CTRL, 0xf8f8 },
56 { RT5631_SPK_MONO_OUT_CTRL, 0xfc00 },
57 { RT5631_SPK_MONO_HP_OUT_CTRL, 0x4440 },
58 { RT5631_SDP_CTRL, 0x8000 },
59 { RT5631_MONO_SDP_CTRL, 0x8000 },
60 { RT5631_STEREO_AD_DA_CLK_CTRL, 0x2010 },
61 { RT5631_GEN_PUR_CTRL_REG, 0x0e00 },
62 { RT5631_INT_ST_IRQ_CTRL_2, 0x071a },
63 { RT5631_MISC_CTRL, 0x2040 },
64 { RT5631_DEPOP_FUN_CTRL_2, 0x8000 },
65 { RT5631_SOFT_VOL_CTRL, 0x07e0 },
66 { RT5631_ALC_CTRL_1, 0x0206 },
67 { RT5631_ALC_CTRL_3, 0x2000 },
68 { RT5631_PSEUDO_SPATL_CTRL, 0x0553 },
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +080069};
70
71/**
72 * rt5631_write_index - write index register of 2nd layer
73 */
74static void rt5631_write_index(struct snd_soc_codec *codec,
75 unsigned int reg, unsigned int value)
76{
77 snd_soc_write(codec, RT5631_INDEX_ADD, reg);
78 snd_soc_write(codec, RT5631_INDEX_DATA, value);
79}
80
81/**
82 * rt5631_read_index - read index register of 2nd layer
83 */
84static unsigned int rt5631_read_index(struct snd_soc_codec *codec,
85 unsigned int reg)
86{
87 unsigned int value;
88
89 snd_soc_write(codec, RT5631_INDEX_ADD, reg);
90 value = snd_soc_read(codec, RT5631_INDEX_DATA);
91
92 return value;
93}
94
95static int rt5631_reset(struct snd_soc_codec *codec)
96{
97 return snd_soc_write(codec, RT5631_RESET, 0);
98}
99
Mark Brown01476802012-05-08 15:52:55 +0100100static bool rt5631_volatile_register(struct device *dev, unsigned int reg)
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +0800101{
102 switch (reg) {
103 case RT5631_RESET:
104 case RT5631_INT_ST_IRQ_CTRL_2:
105 case RT5631_INDEX_ADD:
106 case RT5631_INDEX_DATA:
107 case RT5631_EQ_CTRL:
108 return 1;
109 default:
110 return 0;
111 }
112}
113
Mark Brown01476802012-05-08 15:52:55 +0100114static bool rt5631_readable_register(struct device *dev, unsigned int reg)
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +0800115{
116 switch (reg) {
117 case RT5631_RESET:
118 case RT5631_SPK_OUT_VOL:
119 case RT5631_HP_OUT_VOL:
120 case RT5631_MONO_AXO_1_2_VOL:
121 case RT5631_AUX_IN_VOL:
122 case RT5631_STEREO_DAC_VOL_1:
123 case RT5631_MIC_CTRL_1:
124 case RT5631_STEREO_DAC_VOL_2:
125 case RT5631_ADC_CTRL_1:
126 case RT5631_ADC_REC_MIXER:
127 case RT5631_ADC_CTRL_2:
128 case RT5631_VDAC_DIG_VOL:
129 case RT5631_OUTMIXER_L_CTRL:
130 case RT5631_OUTMIXER_R_CTRL:
131 case RT5631_AXO1MIXER_CTRL:
132 case RT5631_AXO2MIXER_CTRL:
133 case RT5631_MIC_CTRL_2:
134 case RT5631_DIG_MIC_CTRL:
135 case RT5631_MONO_INPUT_VOL:
136 case RT5631_SPK_MIXER_CTRL:
137 case RT5631_SPK_MONO_OUT_CTRL:
138 case RT5631_SPK_MONO_HP_OUT_CTRL:
139 case RT5631_SDP_CTRL:
140 case RT5631_MONO_SDP_CTRL:
141 case RT5631_STEREO_AD_DA_CLK_CTRL:
142 case RT5631_PWR_MANAG_ADD1:
143 case RT5631_PWR_MANAG_ADD2:
144 case RT5631_PWR_MANAG_ADD3:
145 case RT5631_PWR_MANAG_ADD4:
146 case RT5631_GEN_PUR_CTRL_REG:
147 case RT5631_GLOBAL_CLK_CTRL:
148 case RT5631_PLL_CTRL:
149 case RT5631_INT_ST_IRQ_CTRL_1:
150 case RT5631_INT_ST_IRQ_CTRL_2:
151 case RT5631_GPIO_CTRL:
152 case RT5631_MISC_CTRL:
153 case RT5631_DEPOP_FUN_CTRL_1:
154 case RT5631_DEPOP_FUN_CTRL_2:
155 case RT5631_JACK_DET_CTRL:
156 case RT5631_SOFT_VOL_CTRL:
157 case RT5631_ALC_CTRL_1:
158 case RT5631_ALC_CTRL_2:
159 case RT5631_ALC_CTRL_3:
160 case RT5631_PSEUDO_SPATL_CTRL:
161 case RT5631_INDEX_ADD:
162 case RT5631_INDEX_DATA:
163 case RT5631_EQ_CTRL:
164 case RT5631_VENDOR_ID:
165 case RT5631_VENDOR_ID1:
166 case RT5631_VENDOR_ID2:
167 return 1;
168 default:
169 return 0;
170 }
171}
172
173static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
174static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -95625, 375, 0);
175static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
176/* {0, +20, +24, +30, +35, +40, +44, +50, +52}dB */
177static unsigned int mic_bst_tlv[] = {
Clemens Ladischa19ea0b2011-11-20 15:11:54 +0100178 TLV_DB_RANGE_HEAD(7),
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +0800179 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
180 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
181 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
182 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
183 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
184 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
185 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
186};
187
188static int rt5631_dmic_get(struct snd_kcontrol *kcontrol,
189 struct snd_ctl_elem_value *ucontrol)
190{
191 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
192 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
193
194 ucontrol->value.integer.value[0] = rt5631->dmic_used_flag;
195
196 return 0;
197}
198
199static int rt5631_dmic_put(struct snd_kcontrol *kcontrol,
200 struct snd_ctl_elem_value *ucontrol)
201{
202 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
203 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
204
205 rt5631->dmic_used_flag = ucontrol->value.integer.value[0];
206 return 0;
207}
208
209/* MIC Input Type */
210static const char *rt5631_input_mode[] = {
211 "Single ended", "Differential"};
212
213static const SOC_ENUM_SINGLE_DECL(
214 rt5631_mic1_mode_enum, RT5631_MIC_CTRL_1,
215 RT5631_MIC1_DIFF_INPUT_SHIFT, rt5631_input_mode);
216
217static const SOC_ENUM_SINGLE_DECL(
218 rt5631_mic2_mode_enum, RT5631_MIC_CTRL_1,
219 RT5631_MIC2_DIFF_INPUT_SHIFT, rt5631_input_mode);
220
221/* MONO Input Type */
222static const SOC_ENUM_SINGLE_DECL(
223 rt5631_monoin_mode_enum, RT5631_MONO_INPUT_VOL,
224 RT5631_MONO_DIFF_INPUT_SHIFT, rt5631_input_mode);
225
226/* SPK Ratio Gain Control */
227static const char *rt5631_spk_ratio[] = {"1.00x", "1.09x", "1.27x", "1.44x",
228 "1.56x", "1.68x", "1.99x", "2.34x"};
229
230static const SOC_ENUM_SINGLE_DECL(
231 rt5631_spk_ratio_enum, RT5631_GEN_PUR_CTRL_REG,
232 RT5631_SPK_AMP_RATIO_CTRL_SHIFT, rt5631_spk_ratio);
233
234static const struct snd_kcontrol_new rt5631_snd_controls[] = {
235 /* MIC */
236 SOC_ENUM("MIC1 Mode Control", rt5631_mic1_mode_enum),
237 SOC_SINGLE_TLV("MIC1 Boost", RT5631_MIC_CTRL_2,
238 RT5631_MIC1_BOOST_SHIFT, 8, 0, mic_bst_tlv),
239 SOC_ENUM("MIC2 Mode Control", rt5631_mic2_mode_enum),
240 SOC_SINGLE_TLV("MIC2 Boost", RT5631_MIC_CTRL_2,
241 RT5631_MIC2_BOOST_SHIFT, 8, 0, mic_bst_tlv),
242 /* MONO IN */
243 SOC_ENUM("MONOIN Mode Control", rt5631_monoin_mode_enum),
244 SOC_DOUBLE_TLV("MONOIN_RX Capture Volume", RT5631_MONO_INPUT_VOL,
245 RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT,
246 RT5631_VOL_MASK, 1, in_vol_tlv),
247 /* AXI */
248 SOC_DOUBLE_TLV("AXI Capture Volume", RT5631_AUX_IN_VOL,
249 RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT,
250 RT5631_VOL_MASK, 1, in_vol_tlv),
251 /* DAC */
252 SOC_DOUBLE_TLV("PCM Playback Volume", RT5631_STEREO_DAC_VOL_2,
253 RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT,
254 RT5631_DAC_VOL_MASK, 1, dac_vol_tlv),
255 SOC_DOUBLE("PCM Playback Switch", RT5631_STEREO_DAC_VOL_1,
256 RT5631_L_MUTE_SHIFT, RT5631_R_MUTE_SHIFT, 1, 1),
257 /* AXO */
258 SOC_SINGLE("AXO1 Playback Switch", RT5631_MONO_AXO_1_2_VOL,
259 RT5631_L_MUTE_SHIFT, 1, 1),
260 SOC_SINGLE("AXO2 Playback Switch", RT5631_MONO_AXO_1_2_VOL,
261 RT5631_R_VOL_SHIFT, 1, 1),
262 /* OUTVOL */
263 SOC_DOUBLE("OUTVOL Channel Switch", RT5631_SPK_OUT_VOL,
264 RT5631_L_EN_SHIFT, RT5631_R_EN_SHIFT, 1, 0),
265
266 /* SPK */
267 SOC_DOUBLE("Speaker Playback Switch", RT5631_SPK_OUT_VOL,
268 RT5631_L_MUTE_SHIFT, RT5631_R_MUTE_SHIFT, 1, 1),
269 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5631_SPK_OUT_VOL,
270 RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT, 39, 1, out_vol_tlv),
271 /* MONO OUT */
272 SOC_SINGLE("MONO Playback Switch", RT5631_MONO_AXO_1_2_VOL,
273 RT5631_MUTE_MONO_SHIFT, 1, 1),
274 /* HP */
275 SOC_DOUBLE("HP Playback Switch", RT5631_HP_OUT_VOL,
276 RT5631_L_MUTE_SHIFT, RT5631_R_MUTE_SHIFT, 1, 1),
277 SOC_DOUBLE_TLV("HP Playback Volume", RT5631_HP_OUT_VOL,
278 RT5631_L_VOL_SHIFT, RT5631_R_VOL_SHIFT,
279 RT5631_VOL_MASK, 1, out_vol_tlv),
280 /* DMIC */
281 SOC_SINGLE_EXT("DMIC Switch", 0, 0, 1, 0,
282 rt5631_dmic_get, rt5631_dmic_put),
283 SOC_DOUBLE("DMIC Capture Switch", RT5631_DIG_MIC_CTRL,
284 RT5631_DMIC_L_CH_MUTE_SHIFT,
285 RT5631_DMIC_R_CH_MUTE_SHIFT, 1, 1),
286
287 /* SPK Ratio Gain Control */
288 SOC_ENUM("SPK Ratio Control", rt5631_spk_ratio_enum),
289};
290
291static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
292 struct snd_soc_dapm_widget *sink)
293{
294 unsigned int reg;
295
296 reg = snd_soc_read(source->codec, RT5631_GLOBAL_CLK_CTRL);
297 return reg & RT5631_SYSCLK_SOUR_SEL_PLL;
298}
299
300static int check_dmic_used(struct snd_soc_dapm_widget *source,
301 struct snd_soc_dapm_widget *sink)
302{
303 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(source->codec);
304 return rt5631->dmic_used_flag;
305}
306
307static int check_dacl_to_outmixl(struct snd_soc_dapm_widget *source,
308 struct snd_soc_dapm_widget *sink)
309{
310 unsigned int reg;
311
312 reg = snd_soc_read(source->codec, RT5631_OUTMIXER_L_CTRL);
313 return !(reg & RT5631_M_DAC_L_TO_OUTMIXER_L);
314}
315
316static int check_dacr_to_outmixr(struct snd_soc_dapm_widget *source,
317 struct snd_soc_dapm_widget *sink)
318{
319 unsigned int reg;
320
321 reg = snd_soc_read(source->codec, RT5631_OUTMIXER_R_CTRL);
322 return !(reg & RT5631_M_DAC_R_TO_OUTMIXER_R);
323}
324
325static int check_dacl_to_spkmixl(struct snd_soc_dapm_widget *source,
326 struct snd_soc_dapm_widget *sink)
327{
328 unsigned int reg;
329
330 reg = snd_soc_read(source->codec, RT5631_SPK_MIXER_CTRL);
331 return !(reg & RT5631_M_DAC_L_TO_SPKMIXER_L);
332}
333
334static int check_dacr_to_spkmixr(struct snd_soc_dapm_widget *source,
335 struct snd_soc_dapm_widget *sink)
336{
337 unsigned int reg;
338
339 reg = snd_soc_read(source->codec, RT5631_SPK_MIXER_CTRL);
340 return !(reg & RT5631_M_DAC_R_TO_SPKMIXER_R);
341}
342
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +0800343static int check_adcl_select(struct snd_soc_dapm_widget *source,
344 struct snd_soc_dapm_widget *sink)
345{
346 unsigned int reg;
347
348 reg = snd_soc_read(source->codec, RT5631_ADC_REC_MIXER);
349 return !(reg & RT5631_M_MIC1_TO_RECMIXER_L);
350}
351
352static int check_adcr_select(struct snd_soc_dapm_widget *source,
353 struct snd_soc_dapm_widget *sink)
354{
355 unsigned int reg;
356
357 reg = snd_soc_read(source->codec, RT5631_ADC_REC_MIXER);
358 return !(reg & RT5631_M_MIC2_TO_RECMIXER_R);
359}
360
361/**
362 * onebit_depop_power_stage - auto depop in power stage.
363 * @enable: power on/off
364 *
365 * When power on/off headphone, the depop sequence is done by hardware.
366 */
367static void onebit_depop_power_stage(struct snd_soc_codec *codec, int enable)
368{
369 unsigned int soft_vol, hp_zc;
370
371 /* enable one-bit depop function */
372 snd_soc_update_bits(codec, RT5631_DEPOP_FUN_CTRL_2,
373 RT5631_EN_ONE_BIT_DEPOP, 0);
374
375 /* keep soft volume and zero crossing setting */
376 soft_vol = snd_soc_read(codec, RT5631_SOFT_VOL_CTRL);
377 snd_soc_write(codec, RT5631_SOFT_VOL_CTRL, 0);
378 hp_zc = snd_soc_read(codec, RT5631_INT_ST_IRQ_CTRL_2);
379 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, hp_zc & 0xf7ff);
380 if (enable) {
381 /* config one-bit depop parameter */
382 rt5631_write_index(codec, RT5631_TEST_MODE_CTRL, 0x84c0);
383 rt5631_write_index(codec, RT5631_SPK_INTL_CTRL, 0x309f);
384 rt5631_write_index(codec, RT5631_CP_INTL_REG2, 0x6530);
385 /* power on capless block */
386 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_2,
387 RT5631_EN_CAP_FREE_DEPOP);
388 } else {
389 /* power off capless block */
390 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_2, 0);
391 msleep(100);
392 }
393
394 /* recover soft volume and zero crossing setting */
395 snd_soc_write(codec, RT5631_SOFT_VOL_CTRL, soft_vol);
396 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, hp_zc);
397}
398
399/**
400 * onebit_depop_mute_stage - auto depop in mute stage.
401 * @enable: mute/unmute
402 *
403 * When mute/unmute headphone, the depop sequence is done by hardware.
404 */
405static void onebit_depop_mute_stage(struct snd_soc_codec *codec, int enable)
406{
407 unsigned int soft_vol, hp_zc;
408
409 /* enable one-bit depop function */
410 snd_soc_update_bits(codec, RT5631_DEPOP_FUN_CTRL_2,
411 RT5631_EN_ONE_BIT_DEPOP, 0);
412
413 /* keep soft volume and zero crossing setting */
414 soft_vol = snd_soc_read(codec, RT5631_SOFT_VOL_CTRL);
415 snd_soc_write(codec, RT5631_SOFT_VOL_CTRL, 0);
416 hp_zc = snd_soc_read(codec, RT5631_INT_ST_IRQ_CTRL_2);
417 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, hp_zc & 0xf7ff);
418 if (enable) {
419 schedule_timeout_uninterruptible(msecs_to_jiffies(10));
420 /* config one-bit depop parameter */
421 rt5631_write_index(codec, RT5631_SPK_INTL_CTRL, 0x307f);
422 snd_soc_update_bits(codec, RT5631_HP_OUT_VOL,
423 RT5631_L_MUTE | RT5631_R_MUTE, 0);
424 msleep(300);
425 } else {
426 snd_soc_update_bits(codec, RT5631_HP_OUT_VOL,
427 RT5631_L_MUTE | RT5631_R_MUTE,
428 RT5631_L_MUTE | RT5631_R_MUTE);
429 msleep(100);
430 }
431
432 /* recover soft volume and zero crossing setting */
433 snd_soc_write(codec, RT5631_SOFT_VOL_CTRL, soft_vol);
434 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, hp_zc);
435}
436
437/**
438 * onebit_depop_power_stage - step by step depop sequence in power stage.
439 * @enable: power on/off
440 *
441 * When power on/off headphone, the depop sequence is done in step by step.
442 */
443static void depop_seq_power_stage(struct snd_soc_codec *codec, int enable)
444{
445 unsigned int soft_vol, hp_zc;
446
447 /* depop control by register */
448 snd_soc_update_bits(codec, RT5631_DEPOP_FUN_CTRL_2,
449 RT5631_EN_ONE_BIT_DEPOP, RT5631_EN_ONE_BIT_DEPOP);
450
451 /* keep soft volume and zero crossing setting */
452 soft_vol = snd_soc_read(codec, RT5631_SOFT_VOL_CTRL);
453 snd_soc_write(codec, RT5631_SOFT_VOL_CTRL, 0);
454 hp_zc = snd_soc_read(codec, RT5631_INT_ST_IRQ_CTRL_2);
455 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, hp_zc & 0xf7ff);
456 if (enable) {
457 /* config depop sequence parameter */
458 rt5631_write_index(codec, RT5631_SPK_INTL_CTRL, 0x303e);
459
460 /* power on headphone and charge pump */
461 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
462 RT5631_PWR_CHARGE_PUMP | RT5631_PWR_HP_L_AMP |
463 RT5631_PWR_HP_R_AMP,
464 RT5631_PWR_CHARGE_PUMP | RT5631_PWR_HP_L_AMP |
465 RT5631_PWR_HP_R_AMP);
466
467 /* power on soft generator and depop mode2 */
468 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_1,
469 RT5631_POW_ON_SOFT_GEN | RT5631_EN_DEPOP2_FOR_HP);
470 msleep(100);
471
472 /* stop depop mode */
473 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
474 RT5631_PWR_HP_DEPOP_DIS, RT5631_PWR_HP_DEPOP_DIS);
475 } else {
476 /* config depop sequence parameter */
477 rt5631_write_index(codec, RT5631_SPK_INTL_CTRL, 0x303F);
478 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_1,
479 RT5631_POW_ON_SOFT_GEN | RT5631_EN_MUTE_UNMUTE_DEPOP |
480 RT5631_PD_HPAMP_L_ST_UP | RT5631_PD_HPAMP_R_ST_UP);
481 msleep(75);
482 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_1,
483 RT5631_POW_ON_SOFT_GEN | RT5631_PD_HPAMP_L_ST_UP |
484 RT5631_PD_HPAMP_R_ST_UP);
485
486 /* start depop mode */
487 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
488 RT5631_PWR_HP_DEPOP_DIS, 0);
489
490 /* config depop sequence parameter */
491 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_1,
492 RT5631_POW_ON_SOFT_GEN | RT5631_EN_DEPOP2_FOR_HP |
493 RT5631_PD_HPAMP_L_ST_UP | RT5631_PD_HPAMP_R_ST_UP);
494 msleep(80);
495 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_1,
496 RT5631_POW_ON_SOFT_GEN);
497
498 /* power down headphone and charge pump */
499 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
500 RT5631_PWR_CHARGE_PUMP | RT5631_PWR_HP_L_AMP |
501 RT5631_PWR_HP_R_AMP, 0);
502 }
503
504 /* recover soft volume and zero crossing setting */
505 snd_soc_write(codec, RT5631_SOFT_VOL_CTRL, soft_vol);
506 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, hp_zc);
507}
508
509/**
510 * depop_seq_mute_stage - step by step depop sequence in mute stage.
511 * @enable: mute/unmute
512 *
513 * When mute/unmute headphone, the depop sequence is done in step by step.
514 */
515static void depop_seq_mute_stage(struct snd_soc_codec *codec, int enable)
516{
517 unsigned int soft_vol, hp_zc;
518
519 /* depop control by register */
520 snd_soc_update_bits(codec, RT5631_DEPOP_FUN_CTRL_2,
521 RT5631_EN_ONE_BIT_DEPOP, RT5631_EN_ONE_BIT_DEPOP);
522
523 /* keep soft volume and zero crossing setting */
524 soft_vol = snd_soc_read(codec, RT5631_SOFT_VOL_CTRL);
525 snd_soc_write(codec, RT5631_SOFT_VOL_CTRL, 0);
526 hp_zc = snd_soc_read(codec, RT5631_INT_ST_IRQ_CTRL_2);
527 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, hp_zc & 0xf7ff);
528 if (enable) {
529 schedule_timeout_uninterruptible(msecs_to_jiffies(10));
530
531 /* config depop sequence parameter */
532 rt5631_write_index(codec, RT5631_SPK_INTL_CTRL, 0x302f);
533 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_1,
534 RT5631_POW_ON_SOFT_GEN | RT5631_EN_MUTE_UNMUTE_DEPOP |
535 RT5631_EN_HP_R_M_UN_MUTE_DEPOP |
536 RT5631_EN_HP_L_M_UN_MUTE_DEPOP);
537
538 snd_soc_update_bits(codec, RT5631_HP_OUT_VOL,
539 RT5631_L_MUTE | RT5631_R_MUTE, 0);
540 msleep(160);
541 } else {
542 /* config depop sequence parameter */
543 rt5631_write_index(codec, RT5631_SPK_INTL_CTRL, 0x302f);
544 snd_soc_write(codec, RT5631_DEPOP_FUN_CTRL_1,
545 RT5631_POW_ON_SOFT_GEN | RT5631_EN_MUTE_UNMUTE_DEPOP |
546 RT5631_EN_HP_R_M_UN_MUTE_DEPOP |
547 RT5631_EN_HP_L_M_UN_MUTE_DEPOP);
548
549 snd_soc_update_bits(codec, RT5631_HP_OUT_VOL,
550 RT5631_L_MUTE | RT5631_R_MUTE,
551 RT5631_L_MUTE | RT5631_R_MUTE);
552 msleep(150);
553 }
554
555 /* recover soft volume and zero crossing setting */
556 snd_soc_write(codec, RT5631_SOFT_VOL_CTRL, soft_vol);
557 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, hp_zc);
558}
559
560static int hp_event(struct snd_soc_dapm_widget *w,
561 struct snd_kcontrol *kcontrol, int event)
562{
563 struct snd_soc_codec *codec = w->codec;
564 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
565
566 switch (event) {
567 case SND_SOC_DAPM_PRE_PMD:
568 if (rt5631->codec_version) {
569 onebit_depop_mute_stage(codec, 0);
570 onebit_depop_power_stage(codec, 0);
571 } else {
572 depop_seq_mute_stage(codec, 0);
573 depop_seq_power_stage(codec, 0);
574 }
575 break;
576
577 case SND_SOC_DAPM_POST_PMU:
578 if (rt5631->codec_version) {
579 onebit_depop_power_stage(codec, 1);
580 onebit_depop_mute_stage(codec, 1);
581 } else {
582 depop_seq_power_stage(codec, 1);
583 depop_seq_mute_stage(codec, 1);
584 }
585 break;
586
587 default:
588 break;
589 }
590
591 return 0;
592}
593
594static int set_dmic_params(struct snd_soc_dapm_widget *w,
595 struct snd_kcontrol *kcontrol, int event)
596{
597 struct snd_soc_codec *codec = w->codec;
598 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
599
600 switch (rt5631->rx_rate) {
601 case 44100:
602 case 48000:
603 snd_soc_update_bits(codec, RT5631_DIG_MIC_CTRL,
604 RT5631_DMIC_CLK_CTRL_MASK,
605 RT5631_DMIC_CLK_CTRL_TO_32FS);
606 break;
607
608 case 32000:
609 case 22050:
610 snd_soc_update_bits(codec, RT5631_DIG_MIC_CTRL,
611 RT5631_DMIC_CLK_CTRL_MASK,
612 RT5631_DMIC_CLK_CTRL_TO_64FS);
613 break;
614
615 case 16000:
616 case 11025:
617 case 8000:
618 snd_soc_update_bits(codec, RT5631_DIG_MIC_CTRL,
619 RT5631_DMIC_CLK_CTRL_MASK,
620 RT5631_DMIC_CLK_CTRL_TO_128FS);
621 break;
622
623 default:
624 return -EINVAL;
625 }
626
627 return 0;
628}
629
630static const struct snd_kcontrol_new rt5631_recmixl_mixer_controls[] = {
631 SOC_DAPM_SINGLE("OUTMIXL Capture Switch", RT5631_ADC_REC_MIXER,
632 RT5631_M_OUTMIXL_RECMIXL_BIT, 1, 1),
633 SOC_DAPM_SINGLE("MIC1_BST1 Capture Switch", RT5631_ADC_REC_MIXER,
634 RT5631_M_MIC1_RECMIXL_BIT, 1, 1),
635 SOC_DAPM_SINGLE("AXILVOL Capture Switch", RT5631_ADC_REC_MIXER,
636 RT5631_M_AXIL_RECMIXL_BIT, 1, 1),
637 SOC_DAPM_SINGLE("MONOIN_RX Capture Switch", RT5631_ADC_REC_MIXER,
638 RT5631_M_MONO_IN_RECMIXL_BIT, 1, 1),
639};
640
641static const struct snd_kcontrol_new rt5631_recmixr_mixer_controls[] = {
642 SOC_DAPM_SINGLE("MONOIN_RX Capture Switch", RT5631_ADC_REC_MIXER,
643 RT5631_M_MONO_IN_RECMIXR_BIT, 1, 1),
644 SOC_DAPM_SINGLE("AXIRVOL Capture Switch", RT5631_ADC_REC_MIXER,
645 RT5631_M_AXIR_RECMIXR_BIT, 1, 1),
646 SOC_DAPM_SINGLE("MIC2_BST2 Capture Switch", RT5631_ADC_REC_MIXER,
647 RT5631_M_MIC2_RECMIXR_BIT, 1, 1),
648 SOC_DAPM_SINGLE("OUTMIXR Capture Switch", RT5631_ADC_REC_MIXER,
649 RT5631_M_OUTMIXR_RECMIXR_BIT, 1, 1),
650};
651
652static const struct snd_kcontrol_new rt5631_spkmixl_mixer_controls[] = {
653 SOC_DAPM_SINGLE("RECMIXL Playback Switch", RT5631_SPK_MIXER_CTRL,
654 RT5631_M_RECMIXL_SPKMIXL_BIT, 1, 1),
655 SOC_DAPM_SINGLE("MIC1_P Playback Switch", RT5631_SPK_MIXER_CTRL,
656 RT5631_M_MIC1P_SPKMIXL_BIT, 1, 1),
657 SOC_DAPM_SINGLE("DACL Playback Switch", RT5631_SPK_MIXER_CTRL,
658 RT5631_M_DACL_SPKMIXL_BIT, 1, 1),
659 SOC_DAPM_SINGLE("OUTMIXL Playback Switch", RT5631_SPK_MIXER_CTRL,
660 RT5631_M_OUTMIXL_SPKMIXL_BIT, 1, 1),
661};
662
663static const struct snd_kcontrol_new rt5631_spkmixr_mixer_controls[] = {
664 SOC_DAPM_SINGLE("OUTMIXR Playback Switch", RT5631_SPK_MIXER_CTRL,
665 RT5631_M_OUTMIXR_SPKMIXR_BIT, 1, 1),
666 SOC_DAPM_SINGLE("DACR Playback Switch", RT5631_SPK_MIXER_CTRL,
667 RT5631_M_DACR_SPKMIXR_BIT, 1, 1),
668 SOC_DAPM_SINGLE("MIC2_P Playback Switch", RT5631_SPK_MIXER_CTRL,
669 RT5631_M_MIC2P_SPKMIXR_BIT, 1, 1),
670 SOC_DAPM_SINGLE("RECMIXR Playback Switch", RT5631_SPK_MIXER_CTRL,
671 RT5631_M_RECMIXR_SPKMIXR_BIT, 1, 1),
672};
673
674static const struct snd_kcontrol_new rt5631_outmixl_mixer_controls[] = {
675 SOC_DAPM_SINGLE("RECMIXL Playback Switch", RT5631_OUTMIXER_L_CTRL,
676 RT5631_M_RECMIXL_OUTMIXL_BIT, 1, 1),
677 SOC_DAPM_SINGLE("RECMIXR Playback Switch", RT5631_OUTMIXER_L_CTRL,
678 RT5631_M_RECMIXR_OUTMIXL_BIT, 1, 1),
679 SOC_DAPM_SINGLE("DACL Playback Switch", RT5631_OUTMIXER_L_CTRL,
680 RT5631_M_DACL_OUTMIXL_BIT, 1, 1),
681 SOC_DAPM_SINGLE("MIC1_BST1 Playback Switch", RT5631_OUTMIXER_L_CTRL,
682 RT5631_M_MIC1_OUTMIXL_BIT, 1, 1),
683 SOC_DAPM_SINGLE("MIC2_BST2 Playback Switch", RT5631_OUTMIXER_L_CTRL,
684 RT5631_M_MIC2_OUTMIXL_BIT, 1, 1),
685 SOC_DAPM_SINGLE("MONOIN_RXP Playback Switch", RT5631_OUTMIXER_L_CTRL,
686 RT5631_M_MONO_INP_OUTMIXL_BIT, 1, 1),
687 SOC_DAPM_SINGLE("AXILVOL Playback Switch", RT5631_OUTMIXER_L_CTRL,
688 RT5631_M_AXIL_OUTMIXL_BIT, 1, 1),
689 SOC_DAPM_SINGLE("AXIRVOL Playback Switch", RT5631_OUTMIXER_L_CTRL,
690 RT5631_M_AXIR_OUTMIXL_BIT, 1, 1),
691 SOC_DAPM_SINGLE("VDAC Playback Switch", RT5631_OUTMIXER_L_CTRL,
692 RT5631_M_VDAC_OUTMIXL_BIT, 1, 1),
693};
694
695static const struct snd_kcontrol_new rt5631_outmixr_mixer_controls[] = {
696 SOC_DAPM_SINGLE("VDAC Playback Switch", RT5631_OUTMIXER_R_CTRL,
697 RT5631_M_VDAC_OUTMIXR_BIT, 1, 1),
698 SOC_DAPM_SINGLE("AXIRVOL Playback Switch", RT5631_OUTMIXER_R_CTRL,
699 RT5631_M_AXIR_OUTMIXR_BIT, 1, 1),
700 SOC_DAPM_SINGLE("AXILVOL Playback Switch", RT5631_OUTMIXER_R_CTRL,
701 RT5631_M_AXIL_OUTMIXR_BIT, 1, 1),
702 SOC_DAPM_SINGLE("MONOIN_RXN Playback Switch", RT5631_OUTMIXER_R_CTRL,
703 RT5631_M_MONO_INN_OUTMIXR_BIT, 1, 1),
704 SOC_DAPM_SINGLE("MIC2_BST2 Playback Switch", RT5631_OUTMIXER_R_CTRL,
705 RT5631_M_MIC2_OUTMIXR_BIT, 1, 1),
706 SOC_DAPM_SINGLE("MIC1_BST1 Playback Switch", RT5631_OUTMIXER_R_CTRL,
707 RT5631_M_MIC1_OUTMIXR_BIT, 1, 1),
708 SOC_DAPM_SINGLE("DACR Playback Switch", RT5631_OUTMIXER_R_CTRL,
709 RT5631_M_DACR_OUTMIXR_BIT, 1, 1),
710 SOC_DAPM_SINGLE("RECMIXR Playback Switch", RT5631_OUTMIXER_R_CTRL,
711 RT5631_M_RECMIXR_OUTMIXR_BIT, 1, 1),
712 SOC_DAPM_SINGLE("RECMIXL Playback Switch", RT5631_OUTMIXER_R_CTRL,
713 RT5631_M_RECMIXL_OUTMIXR_BIT, 1, 1),
714};
715
716static const struct snd_kcontrol_new rt5631_AXO1MIX_mixer_controls[] = {
717 SOC_DAPM_SINGLE("MIC1_BST1 Playback Switch", RT5631_AXO1MIXER_CTRL,
718 RT5631_M_MIC1_AXO1MIX_BIT , 1, 1),
719 SOC_DAPM_SINGLE("MIC2_BST2 Playback Switch", RT5631_AXO1MIXER_CTRL,
720 RT5631_M_MIC2_AXO1MIX_BIT, 1, 1),
721 SOC_DAPM_SINGLE("OUTVOLL Playback Switch", RT5631_AXO1MIXER_CTRL,
722 RT5631_M_OUTMIXL_AXO1MIX_BIT , 1 , 1),
723 SOC_DAPM_SINGLE("OUTVOLR Playback Switch", RT5631_AXO1MIXER_CTRL,
724 RT5631_M_OUTMIXR_AXO1MIX_BIT, 1, 1),
725};
726
727static const struct snd_kcontrol_new rt5631_AXO2MIX_mixer_controls[] = {
728 SOC_DAPM_SINGLE("MIC1_BST1 Playback Switch", RT5631_AXO2MIXER_CTRL,
729 RT5631_M_MIC1_AXO2MIX_BIT, 1, 1),
730 SOC_DAPM_SINGLE("MIC2_BST2 Playback Switch", RT5631_AXO2MIXER_CTRL,
731 RT5631_M_MIC2_AXO2MIX_BIT, 1, 1),
732 SOC_DAPM_SINGLE("OUTVOLL Playback Switch", RT5631_AXO2MIXER_CTRL,
733 RT5631_M_OUTMIXL_AXO2MIX_BIT, 1, 1),
734 SOC_DAPM_SINGLE("OUTVOLR Playback Switch", RT5631_AXO2MIXER_CTRL,
735 RT5631_M_OUTMIXR_AXO2MIX_BIT, 1 , 1),
736};
737
738static const struct snd_kcontrol_new rt5631_spolmix_mixer_controls[] = {
739 SOC_DAPM_SINGLE("SPKVOLL Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
740 RT5631_M_SPKVOLL_SPOLMIX_BIT, 1, 1),
741 SOC_DAPM_SINGLE("SPKVOLR Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
742 RT5631_M_SPKVOLR_SPOLMIX_BIT, 1, 1),
743};
744
745static const struct snd_kcontrol_new rt5631_spormix_mixer_controls[] = {
746 SOC_DAPM_SINGLE("SPKVOLL Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
747 RT5631_M_SPKVOLL_SPORMIX_BIT, 1, 1),
748 SOC_DAPM_SINGLE("SPKVOLR Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
749 RT5631_M_SPKVOLR_SPORMIX_BIT, 1, 1),
750};
751
752static const struct snd_kcontrol_new rt5631_monomix_mixer_controls[] = {
753 SOC_DAPM_SINGLE("OUTVOLL Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
754 RT5631_M_OUTVOLL_MONOMIX_BIT, 1, 1),
755 SOC_DAPM_SINGLE("OUTVOLR Playback Switch", RT5631_SPK_MONO_OUT_CTRL,
756 RT5631_M_OUTVOLR_MONOMIX_BIT, 1, 1),
757};
758
759/* Left SPK Volume Input */
760static const char *rt5631_spkvoll_sel[] = {"Vmid", "SPKMIXL"};
761
762static const SOC_ENUM_SINGLE_DECL(
763 rt5631_spkvoll_enum, RT5631_SPK_OUT_VOL,
764 RT5631_L_EN_SHIFT, rt5631_spkvoll_sel);
765
766static const struct snd_kcontrol_new rt5631_spkvoll_mux_control =
767 SOC_DAPM_ENUM("Left SPKVOL SRC", rt5631_spkvoll_enum);
768
769/* Left HP Volume Input */
770static const char *rt5631_hpvoll_sel[] = {"Vmid", "OUTMIXL"};
771
772static const SOC_ENUM_SINGLE_DECL(
773 rt5631_hpvoll_enum, RT5631_HP_OUT_VOL,
774 RT5631_L_EN_SHIFT, rt5631_hpvoll_sel);
775
776static const struct snd_kcontrol_new rt5631_hpvoll_mux_control =
777 SOC_DAPM_ENUM("Left HPVOL SRC", rt5631_hpvoll_enum);
778
779/* Left Out Volume Input */
780static const char *rt5631_outvoll_sel[] = {"Vmid", "OUTMIXL"};
781
782static const SOC_ENUM_SINGLE_DECL(
783 rt5631_outvoll_enum, RT5631_MONO_AXO_1_2_VOL,
784 RT5631_L_EN_SHIFT, rt5631_outvoll_sel);
785
786static const struct snd_kcontrol_new rt5631_outvoll_mux_control =
787 SOC_DAPM_ENUM("Left OUTVOL SRC", rt5631_outvoll_enum);
788
789/* Right Out Volume Input */
790static const char *rt5631_outvolr_sel[] = {"Vmid", "OUTMIXR"};
791
792static const SOC_ENUM_SINGLE_DECL(
793 rt5631_outvolr_enum, RT5631_MONO_AXO_1_2_VOL,
794 RT5631_R_EN_SHIFT, rt5631_outvolr_sel);
795
796static const struct snd_kcontrol_new rt5631_outvolr_mux_control =
797 SOC_DAPM_ENUM("Right OUTVOL SRC", rt5631_outvolr_enum);
798
799/* Right HP Volume Input */
800static const char *rt5631_hpvolr_sel[] = {"Vmid", "OUTMIXR"};
801
802static const SOC_ENUM_SINGLE_DECL(
803 rt5631_hpvolr_enum, RT5631_HP_OUT_VOL,
804 RT5631_R_EN_SHIFT, rt5631_hpvolr_sel);
805
806static const struct snd_kcontrol_new rt5631_hpvolr_mux_control =
807 SOC_DAPM_ENUM("Right HPVOL SRC", rt5631_hpvolr_enum);
808
809/* Right SPK Volume Input */
810static const char *rt5631_spkvolr_sel[] = {"Vmid", "SPKMIXR"};
811
812static const SOC_ENUM_SINGLE_DECL(
813 rt5631_spkvolr_enum, RT5631_SPK_OUT_VOL,
814 RT5631_R_EN_SHIFT, rt5631_spkvolr_sel);
815
816static const struct snd_kcontrol_new rt5631_spkvolr_mux_control =
817 SOC_DAPM_ENUM("Right SPKVOL SRC", rt5631_spkvolr_enum);
818
819/* SPO Left Channel Input */
820static const char *rt5631_spol_src_sel[] = {
821 "SPOLMIX", "MONOIN_RX", "VDAC", "DACL"};
822
823static const SOC_ENUM_SINGLE_DECL(
824 rt5631_spol_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
825 RT5631_SPK_L_MUX_SEL_SHIFT, rt5631_spol_src_sel);
826
827static const struct snd_kcontrol_new rt5631_spol_mux_control =
828 SOC_DAPM_ENUM("SPOL SRC", rt5631_spol_src_enum);
829
830/* SPO Right Channel Input */
831static const char *rt5631_spor_src_sel[] = {
832 "SPORMIX", "MONOIN_RX", "VDAC", "DACR"};
833
834static const SOC_ENUM_SINGLE_DECL(
835 rt5631_spor_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
836 RT5631_SPK_R_MUX_SEL_SHIFT, rt5631_spor_src_sel);
837
838static const struct snd_kcontrol_new rt5631_spor_mux_control =
839 SOC_DAPM_ENUM("SPOR SRC", rt5631_spor_src_enum);
840
841/* MONO Input */
842static const char *rt5631_mono_src_sel[] = {"MONOMIX", "MONOIN_RX", "VDAC"};
843
844static const SOC_ENUM_SINGLE_DECL(
845 rt5631_mono_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
846 RT5631_MONO_MUX_SEL_SHIFT, rt5631_mono_src_sel);
847
848static const struct snd_kcontrol_new rt5631_mono_mux_control =
849 SOC_DAPM_ENUM("MONO SRC", rt5631_mono_src_enum);
850
851/* Left HPO Input */
852static const char *rt5631_hpl_src_sel[] = {"Left HPVOL", "Left DAC"};
853
854static const SOC_ENUM_SINGLE_DECL(
855 rt5631_hpl_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
856 RT5631_HP_L_MUX_SEL_SHIFT, rt5631_hpl_src_sel);
857
858static const struct snd_kcontrol_new rt5631_hpl_mux_control =
859 SOC_DAPM_ENUM("HPL SRC", rt5631_hpl_src_enum);
860
861/* Right HPO Input */
862static const char *rt5631_hpr_src_sel[] = {"Right HPVOL", "Right DAC"};
863
864static const SOC_ENUM_SINGLE_DECL(
865 rt5631_hpr_src_enum, RT5631_SPK_MONO_HP_OUT_CTRL,
866 RT5631_HP_R_MUX_SEL_SHIFT, rt5631_hpr_src_sel);
867
868static const struct snd_kcontrol_new rt5631_hpr_mux_control =
869 SOC_DAPM_ENUM("HPR SRC", rt5631_hpr_src_enum);
870
871static const struct snd_soc_dapm_widget rt5631_dapm_widgets[] = {
872 /* Vmid */
873 SND_SOC_DAPM_VMID("Vmid"),
874 /* PLL1 */
875 SND_SOC_DAPM_SUPPLY("PLL1", RT5631_PWR_MANAG_ADD2,
876 RT5631_PWR_PLL1_BIT, 0, NULL, 0),
877
878 /* Input Side */
879 /* Input Lines */
880 SND_SOC_DAPM_INPUT("MIC1"),
881 SND_SOC_DAPM_INPUT("MIC2"),
882 SND_SOC_DAPM_INPUT("AXIL"),
883 SND_SOC_DAPM_INPUT("AXIR"),
884 SND_SOC_DAPM_INPUT("MONOIN_RXN"),
885 SND_SOC_DAPM_INPUT("MONOIN_RXP"),
886 SND_SOC_DAPM_INPUT("DMIC"),
887
888 /* MICBIAS */
889 SND_SOC_DAPM_MICBIAS("MIC Bias1", RT5631_PWR_MANAG_ADD2,
890 RT5631_PWR_MICBIAS1_VOL_BIT, 0),
891 SND_SOC_DAPM_MICBIAS("MIC Bias2", RT5631_PWR_MANAG_ADD2,
892 RT5631_PWR_MICBIAS2_VOL_BIT, 0),
893
894 /* Boost */
895 SND_SOC_DAPM_PGA("MIC1 Boost", RT5631_PWR_MANAG_ADD2,
896 RT5631_PWR_MIC1_BOOT_GAIN_BIT, 0, NULL, 0),
897 SND_SOC_DAPM_PGA("MIC2 Boost", RT5631_PWR_MANAG_ADD2,
898 RT5631_PWR_MIC2_BOOT_GAIN_BIT, 0, NULL, 0),
899 SND_SOC_DAPM_PGA("MONOIN_RXP Boost", RT5631_PWR_MANAG_ADD4,
900 RT5631_PWR_MONO_IN_P_VOL_BIT, 0, NULL, 0),
901 SND_SOC_DAPM_PGA("MONOIN_RXN Boost", RT5631_PWR_MANAG_ADD4,
902 RT5631_PWR_MONO_IN_N_VOL_BIT, 0, NULL, 0),
903 SND_SOC_DAPM_PGA("AXIL Boost", RT5631_PWR_MANAG_ADD4,
904 RT5631_PWR_AXIL_IN_VOL_BIT, 0, NULL, 0),
905 SND_SOC_DAPM_PGA("AXIR Boost", RT5631_PWR_MANAG_ADD4,
906 RT5631_PWR_AXIR_IN_VOL_BIT, 0, NULL, 0),
907
908 /* MONO In */
909 SND_SOC_DAPM_MIXER("MONO_IN", SND_SOC_NOPM, 0, 0, NULL, 0),
910
911 /* REC Mixer */
912 SND_SOC_DAPM_MIXER("RECMIXL Mixer", RT5631_PWR_MANAG_ADD2,
913 RT5631_PWR_RECMIXER_L_BIT, 0,
914 &rt5631_recmixl_mixer_controls[0],
915 ARRAY_SIZE(rt5631_recmixl_mixer_controls)),
916 SND_SOC_DAPM_MIXER("RECMIXR Mixer", RT5631_PWR_MANAG_ADD2,
917 RT5631_PWR_RECMIXER_R_BIT, 0,
918 &rt5631_recmixr_mixer_controls[0],
919 ARRAY_SIZE(rt5631_recmixr_mixer_controls)),
920 /* Because of record duplication for L/R channel,
921 * L/R ADCs need power up at the same time */
922 SND_SOC_DAPM_MIXER("ADC Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
923
924 /* DMIC */
925 SND_SOC_DAPM_SUPPLY("DMIC Supply", RT5631_DIG_MIC_CTRL,
926 RT5631_DMIC_ENA_SHIFT, 0,
927 set_dmic_params, SND_SOC_DAPM_PRE_PMU),
928 /* ADC Data Srouce */
929 SND_SOC_DAPM_SUPPLY("Left ADC Select", RT5631_INT_ST_IRQ_CTRL_2,
930 RT5631_ADC_DATA_SEL_MIC1_SHIFT, 0, NULL, 0),
931 SND_SOC_DAPM_SUPPLY("Right ADC Select", RT5631_INT_ST_IRQ_CTRL_2,
932 RT5631_ADC_DATA_SEL_MIC2_SHIFT, 0, NULL, 0),
933
934 /* ADCs */
935 SND_SOC_DAPM_ADC("Left ADC", "HIFI Capture",
936 RT5631_PWR_MANAG_ADD1, RT5631_PWR_ADC_L_CLK_BIT, 0),
937 SND_SOC_DAPM_ADC("Right ADC", "HIFI Capture",
938 RT5631_PWR_MANAG_ADD1, RT5631_PWR_ADC_R_CLK_BIT, 0),
939
940 /* DAC and ADC supply power */
941 SND_SOC_DAPM_SUPPLY("I2S", RT5631_PWR_MANAG_ADD1,
942 RT5631_PWR_MAIN_I2S_BIT, 0, NULL, 0),
943 SND_SOC_DAPM_SUPPLY("DAC REF", RT5631_PWR_MANAG_ADD1,
944 RT5631_PWR_DAC_REF_BIT, 0, NULL, 0),
945
946 /* Output Side */
947 /* DACs */
948 SND_SOC_DAPM_DAC("Left DAC", "HIFI Playback",
949 RT5631_PWR_MANAG_ADD1, RT5631_PWR_DAC_L_CLK_BIT, 0),
950 SND_SOC_DAPM_DAC("Right DAC", "HIFI Playback",
951 RT5631_PWR_MANAG_ADD1, RT5631_PWR_DAC_R_CLK_BIT, 0),
952 SND_SOC_DAPM_DAC("Voice DAC", "Voice DAC Mono Playback",
953 SND_SOC_NOPM, 0, 0),
954 SND_SOC_DAPM_PGA("Voice DAC Boost", SND_SOC_NOPM, 0, 0, NULL, 0),
955 /* DAC supply power */
956 SND_SOC_DAPM_SUPPLY("Left DAC To Mixer", RT5631_PWR_MANAG_ADD1,
957 RT5631_PWR_DAC_L_TO_MIXER_BIT, 0, NULL, 0),
958 SND_SOC_DAPM_SUPPLY("Right DAC To Mixer", RT5631_PWR_MANAG_ADD1,
959 RT5631_PWR_DAC_R_TO_MIXER_BIT, 0, NULL, 0),
960
961 /* Left SPK Mixer */
962 SND_SOC_DAPM_MIXER("SPKMIXL Mixer", RT5631_PWR_MANAG_ADD2,
963 RT5631_PWR_SPKMIXER_L_BIT, 0,
964 &rt5631_spkmixl_mixer_controls[0],
965 ARRAY_SIZE(rt5631_spkmixl_mixer_controls)),
966 /* Left Out Mixer */
967 SND_SOC_DAPM_MIXER("OUTMIXL Mixer", RT5631_PWR_MANAG_ADD2,
968 RT5631_PWR_OUTMIXER_L_BIT, 0,
969 &rt5631_outmixl_mixer_controls[0],
970 ARRAY_SIZE(rt5631_outmixl_mixer_controls)),
971 /* Right Out Mixer */
972 SND_SOC_DAPM_MIXER("OUTMIXR Mixer", RT5631_PWR_MANAG_ADD2,
973 RT5631_PWR_OUTMIXER_R_BIT, 0,
974 &rt5631_outmixr_mixer_controls[0],
975 ARRAY_SIZE(rt5631_outmixr_mixer_controls)),
976 /* Right SPK Mixer */
977 SND_SOC_DAPM_MIXER("SPKMIXR Mixer", RT5631_PWR_MANAG_ADD2,
978 RT5631_PWR_SPKMIXER_R_BIT, 0,
979 &rt5631_spkmixr_mixer_controls[0],
980 ARRAY_SIZE(rt5631_spkmixr_mixer_controls)),
981
982 /* Volume Mux */
983 SND_SOC_DAPM_MUX("Left SPKVOL Mux", RT5631_PWR_MANAG_ADD4,
984 RT5631_PWR_SPK_L_VOL_BIT, 0,
985 &rt5631_spkvoll_mux_control),
986 SND_SOC_DAPM_MUX("Left HPVOL Mux", RT5631_PWR_MANAG_ADD4,
987 RT5631_PWR_HP_L_OUT_VOL_BIT, 0,
988 &rt5631_hpvoll_mux_control),
989 SND_SOC_DAPM_MUX("Left OUTVOL Mux", RT5631_PWR_MANAG_ADD4,
990 RT5631_PWR_LOUT_VOL_BIT, 0,
991 &rt5631_outvoll_mux_control),
992 SND_SOC_DAPM_MUX("Right OUTVOL Mux", RT5631_PWR_MANAG_ADD4,
993 RT5631_PWR_ROUT_VOL_BIT, 0,
994 &rt5631_outvolr_mux_control),
995 SND_SOC_DAPM_MUX("Right HPVOL Mux", RT5631_PWR_MANAG_ADD4,
996 RT5631_PWR_HP_R_OUT_VOL_BIT, 0,
997 &rt5631_hpvolr_mux_control),
998 SND_SOC_DAPM_MUX("Right SPKVOL Mux", RT5631_PWR_MANAG_ADD4,
999 RT5631_PWR_SPK_R_VOL_BIT, 0,
1000 &rt5631_spkvolr_mux_control),
1001
1002 /* DAC To HP */
1003 SND_SOC_DAPM_PGA_S("Left DAC_HP", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
1004 SND_SOC_DAPM_PGA_S("Right DAC_HP", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
1005
1006 /* HP Depop */
1007 SND_SOC_DAPM_PGA_S("HP Depop", 1, SND_SOC_NOPM, 0, 0,
1008 hp_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1009
1010 /* AXO1 Mixer */
1011 SND_SOC_DAPM_MIXER("AXO1MIX Mixer", RT5631_PWR_MANAG_ADD3,
1012 RT5631_PWR_AXO1MIXER_BIT, 0,
1013 &rt5631_AXO1MIX_mixer_controls[0],
1014 ARRAY_SIZE(rt5631_AXO1MIX_mixer_controls)),
1015 /* SPOL Mixer */
1016 SND_SOC_DAPM_MIXER("SPOLMIX Mixer", SND_SOC_NOPM, 0, 0,
1017 &rt5631_spolmix_mixer_controls[0],
1018 ARRAY_SIZE(rt5631_spolmix_mixer_controls)),
1019 /* MONO Mixer */
1020 SND_SOC_DAPM_MIXER("MONOMIX Mixer", RT5631_PWR_MANAG_ADD3,
1021 RT5631_PWR_MONOMIXER_BIT, 0,
1022 &rt5631_monomix_mixer_controls[0],
1023 ARRAY_SIZE(rt5631_monomix_mixer_controls)),
1024 /* SPOR Mixer */
1025 SND_SOC_DAPM_MIXER("SPORMIX Mixer", SND_SOC_NOPM, 0, 0,
1026 &rt5631_spormix_mixer_controls[0],
1027 ARRAY_SIZE(rt5631_spormix_mixer_controls)),
1028 /* AXO2 Mixer */
1029 SND_SOC_DAPM_MIXER("AXO2MIX Mixer", RT5631_PWR_MANAG_ADD3,
1030 RT5631_PWR_AXO2MIXER_BIT, 0,
1031 &rt5631_AXO2MIX_mixer_controls[0],
1032 ARRAY_SIZE(rt5631_AXO2MIX_mixer_controls)),
1033
1034 /* Mux */
1035 SND_SOC_DAPM_MUX("SPOL Mux", SND_SOC_NOPM, 0, 0,
1036 &rt5631_spol_mux_control),
1037 SND_SOC_DAPM_MUX("SPOR Mux", SND_SOC_NOPM, 0, 0,
1038 &rt5631_spor_mux_control),
1039 SND_SOC_DAPM_MUX("MONO Mux", SND_SOC_NOPM, 0, 0,
1040 &rt5631_mono_mux_control),
1041 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0,
1042 &rt5631_hpl_mux_control),
1043 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0,
1044 &rt5631_hpr_mux_control),
1045
1046 /* AMP supply */
1047 SND_SOC_DAPM_SUPPLY("MONO Depop", RT5631_PWR_MANAG_ADD3,
1048 RT5631_PWR_MONO_DEPOP_DIS_BIT, 0, NULL, 0),
1049 SND_SOC_DAPM_SUPPLY("Class D", RT5631_PWR_MANAG_ADD1,
1050 RT5631_PWR_CLASS_D_BIT, 0, NULL, 0),
1051
1052 /* Output Lines */
1053 SND_SOC_DAPM_OUTPUT("AUXO1"),
1054 SND_SOC_DAPM_OUTPUT("AUXO2"),
1055 SND_SOC_DAPM_OUTPUT("SPOL"),
1056 SND_SOC_DAPM_OUTPUT("SPOR"),
1057 SND_SOC_DAPM_OUTPUT("HPOL"),
1058 SND_SOC_DAPM_OUTPUT("HPOR"),
1059 SND_SOC_DAPM_OUTPUT("MONO"),
1060};
1061
1062static const struct snd_soc_dapm_route rt5631_dapm_routes[] = {
1063 {"MIC1 Boost", NULL, "MIC1"},
1064 {"MIC2 Boost", NULL, "MIC2"},
1065 {"MONOIN_RXP Boost", NULL, "MONOIN_RXP"},
1066 {"MONOIN_RXN Boost", NULL, "MONOIN_RXN"},
1067 {"AXIL Boost", NULL, "AXIL"},
1068 {"AXIR Boost", NULL, "AXIR"},
1069
1070 {"MONO_IN", NULL, "MONOIN_RXP Boost"},
1071 {"MONO_IN", NULL, "MONOIN_RXN Boost"},
1072
1073 {"RECMIXL Mixer", "OUTMIXL Capture Switch", "OUTMIXL Mixer"},
1074 {"RECMIXL Mixer", "MIC1_BST1 Capture Switch", "MIC1 Boost"},
1075 {"RECMIXL Mixer", "AXILVOL Capture Switch", "AXIL Boost"},
1076 {"RECMIXL Mixer", "MONOIN_RX Capture Switch", "MONO_IN"},
1077
1078 {"RECMIXR Mixer", "OUTMIXR Capture Switch", "OUTMIXR Mixer"},
1079 {"RECMIXR Mixer", "MIC2_BST2 Capture Switch", "MIC2 Boost"},
1080 {"RECMIXR Mixer", "AXIRVOL Capture Switch", "AXIR Boost"},
1081 {"RECMIXR Mixer", "MONOIN_RX Capture Switch", "MONO_IN"},
1082
1083 {"ADC Mixer", NULL, "RECMIXL Mixer"},
1084 {"ADC Mixer", NULL, "RECMIXR Mixer"},
1085
1086 {"Left ADC", NULL, "ADC Mixer"},
1087 {"Left ADC", NULL, "Left ADC Select", check_adcl_select},
1088 {"Left ADC", NULL, "PLL1", check_sysclk1_source},
1089 {"Left ADC", NULL, "I2S"},
1090 {"Left ADC", NULL, "DAC REF"},
1091
1092 {"Right ADC", NULL, "ADC Mixer"},
1093 {"Right ADC", NULL, "Right ADC Select", check_adcr_select},
1094 {"Right ADC", NULL, "PLL1", check_sysclk1_source},
1095 {"Right ADC", NULL, "I2S"},
1096 {"Right ADC", NULL, "DAC REF"},
1097
1098 {"DMIC", NULL, "DMIC Supply", check_dmic_used},
1099 {"Left ADC", NULL, "DMIC"},
1100 {"Right ADC", NULL, "DMIC"},
1101
1102 {"Left DAC", NULL, "PLL1", check_sysclk1_source},
1103 {"Left DAC", NULL, "I2S"},
1104 {"Left DAC", NULL, "DAC REF"},
1105 {"Right DAC", NULL, "PLL1", check_sysclk1_source},
1106 {"Right DAC", NULL, "I2S"},
1107 {"Right DAC", NULL, "DAC REF"},
1108
1109 {"Voice DAC Boost", NULL, "Voice DAC"},
1110
1111 {"SPKMIXL Mixer", NULL, "Left DAC To Mixer", check_dacl_to_spkmixl},
1112 {"SPKMIXL Mixer", "RECMIXL Playback Switch", "RECMIXL Mixer"},
1113 {"SPKMIXL Mixer", "MIC1_P Playback Switch", "MIC1"},
1114 {"SPKMIXL Mixer", "DACL Playback Switch", "Left DAC"},
1115 {"SPKMIXL Mixer", "OUTMIXL Playback Switch", "OUTMIXL Mixer"},
1116
1117 {"SPKMIXR Mixer", NULL, "Right DAC To Mixer", check_dacr_to_spkmixr},
1118 {"SPKMIXR Mixer", "OUTMIXR Playback Switch", "OUTMIXR Mixer"},
1119 {"SPKMIXR Mixer", "DACR Playback Switch", "Right DAC"},
1120 {"SPKMIXR Mixer", "MIC2_P Playback Switch", "MIC2"},
1121 {"SPKMIXR Mixer", "RECMIXR Playback Switch", "RECMIXR Mixer"},
1122
1123 {"OUTMIXL Mixer", NULL, "Left DAC To Mixer", check_dacl_to_outmixl},
1124 {"OUTMIXL Mixer", "RECMIXL Playback Switch", "RECMIXL Mixer"},
1125 {"OUTMIXL Mixer", "RECMIXR Playback Switch", "RECMIXR Mixer"},
1126 {"OUTMIXL Mixer", "DACL Playback Switch", "Left DAC"},
1127 {"OUTMIXL Mixer", "MIC1_BST1 Playback Switch", "MIC1 Boost"},
1128 {"OUTMIXL Mixer", "MIC2_BST2 Playback Switch", "MIC2 Boost"},
1129 {"OUTMIXL Mixer", "MONOIN_RXP Playback Switch", "MONOIN_RXP Boost"},
1130 {"OUTMIXL Mixer", "AXILVOL Playback Switch", "AXIL Boost"},
1131 {"OUTMIXL Mixer", "AXIRVOL Playback Switch", "AXIR Boost"},
1132 {"OUTMIXL Mixer", "VDAC Playback Switch", "Voice DAC Boost"},
1133
1134 {"OUTMIXR Mixer", NULL, "Right DAC To Mixer", check_dacr_to_outmixr},
1135 {"OUTMIXR Mixer", "RECMIXL Playback Switch", "RECMIXL Mixer"},
1136 {"OUTMIXR Mixer", "RECMIXR Playback Switch", "RECMIXR Mixer"},
1137 {"OUTMIXR Mixer", "DACR Playback Switch", "Right DAC"},
1138 {"OUTMIXR Mixer", "MIC1_BST1 Playback Switch", "MIC1 Boost"},
1139 {"OUTMIXR Mixer", "MIC2_BST2 Playback Switch", "MIC2 Boost"},
1140 {"OUTMIXR Mixer", "MONOIN_RXN Playback Switch", "MONOIN_RXN Boost"},
1141 {"OUTMIXR Mixer", "AXILVOL Playback Switch", "AXIL Boost"},
1142 {"OUTMIXR Mixer", "AXIRVOL Playback Switch", "AXIR Boost"},
1143 {"OUTMIXR Mixer", "VDAC Playback Switch", "Voice DAC Boost"},
1144
1145 {"Left SPKVOL Mux", "SPKMIXL", "SPKMIXL Mixer"},
1146 {"Left SPKVOL Mux", "Vmid", "Vmid"},
1147 {"Left HPVOL Mux", "OUTMIXL", "OUTMIXL Mixer"},
1148 {"Left HPVOL Mux", "Vmid", "Vmid"},
1149 {"Left OUTVOL Mux", "OUTMIXL", "OUTMIXL Mixer"},
1150 {"Left OUTVOL Mux", "Vmid", "Vmid"},
1151 {"Right OUTVOL Mux", "OUTMIXR", "OUTMIXR Mixer"},
1152 {"Right OUTVOL Mux", "Vmid", "Vmid"},
1153 {"Right HPVOL Mux", "OUTMIXR", "OUTMIXR Mixer"},
1154 {"Right HPVOL Mux", "Vmid", "Vmid"},
1155 {"Right SPKVOL Mux", "SPKMIXR", "SPKMIXR Mixer"},
1156 {"Right SPKVOL Mux", "Vmid", "Vmid"},
1157
1158 {"AXO1MIX Mixer", "MIC1_BST1 Playback Switch", "MIC1 Boost"},
1159 {"AXO1MIX Mixer", "OUTVOLL Playback Switch", "Left OUTVOL Mux"},
1160 {"AXO1MIX Mixer", "OUTVOLR Playback Switch", "Right OUTVOL Mux"},
1161 {"AXO1MIX Mixer", "MIC2_BST2 Playback Switch", "MIC2 Boost"},
1162
1163 {"AXO2MIX Mixer", "MIC1_BST1 Playback Switch", "MIC1 Boost"},
1164 {"AXO2MIX Mixer", "OUTVOLL Playback Switch", "Left OUTVOL Mux"},
1165 {"AXO2MIX Mixer", "OUTVOLR Playback Switch", "Right OUTVOL Mux"},
1166 {"AXO2MIX Mixer", "MIC2_BST2 Playback Switch", "MIC2 Boost"},
1167
1168 {"SPOLMIX Mixer", "SPKVOLL Playback Switch", "Left SPKVOL Mux"},
1169 {"SPOLMIX Mixer", "SPKVOLR Playback Switch", "Right SPKVOL Mux"},
1170
1171 {"SPORMIX Mixer", "SPKVOLL Playback Switch", "Left SPKVOL Mux"},
1172 {"SPORMIX Mixer", "SPKVOLR Playback Switch", "Right SPKVOL Mux"},
1173
1174 {"MONOMIX Mixer", "OUTVOLL Playback Switch", "Left OUTVOL Mux"},
1175 {"MONOMIX Mixer", "OUTVOLR Playback Switch", "Right OUTVOL Mux"},
1176
1177 {"SPOL Mux", "SPOLMIX", "SPOLMIX Mixer"},
1178 {"SPOL Mux", "MONOIN_RX", "MONO_IN"},
1179 {"SPOL Mux", "VDAC", "Voice DAC Boost"},
1180 {"SPOL Mux", "DACL", "Left DAC"},
1181
1182 {"SPOR Mux", "SPORMIX", "SPORMIX Mixer"},
1183 {"SPOR Mux", "MONOIN_RX", "MONO_IN"},
1184 {"SPOR Mux", "VDAC", "Voice DAC Boost"},
1185 {"SPOR Mux", "DACR", "Right DAC"},
1186
1187 {"MONO Mux", "MONOMIX", "MONOMIX Mixer"},
1188 {"MONO Mux", "MONOIN_RX", "MONO_IN"},
1189 {"MONO Mux", "VDAC", "Voice DAC Boost"},
1190
1191 {"Right DAC_HP", NULL, "Right DAC"},
1192 {"Left DAC_HP", NULL, "Left DAC"},
1193
1194 {"HPL Mux", "Left HPVOL", "Left HPVOL Mux"},
1195 {"HPL Mux", "Left DAC", "Left DAC_HP"},
1196 {"HPR Mux", "Right HPVOL", "Right HPVOL Mux"},
1197 {"HPR Mux", "Right DAC", "Right DAC_HP"},
1198
1199 {"HP Depop", NULL, "HPL Mux"},
1200 {"HP Depop", NULL, "HPR Mux"},
1201
1202 {"AUXO1", NULL, "AXO1MIX Mixer"},
1203 {"AUXO2", NULL, "AXO2MIX Mixer"},
1204
1205 {"SPOL", NULL, "Class D"},
1206 {"SPOL", NULL, "SPOL Mux"},
1207 {"SPOR", NULL, "Class D"},
1208 {"SPOR", NULL, "SPOR Mux"},
1209
1210 {"HPOL", NULL, "HP Depop"},
1211 {"HPOR", NULL, "HP Depop"},
1212
1213 {"MONO", NULL, "MONO Depop"},
1214 {"MONO", NULL, "MONO Mux"},
1215};
1216
1217struct coeff_clk_div {
1218 u32 mclk;
1219 u32 bclk;
1220 u32 rate;
1221 u16 reg_val;
1222};
1223
1224/* PLL divisors */
1225struct pll_div {
1226 u32 pll_in;
1227 u32 pll_out;
1228 u16 reg_val;
1229};
1230
1231static const struct pll_div codec_master_pll_div[] = {
1232 {2048000, 8192000, 0x0ea0},
1233 {3686400, 8192000, 0x4e27},
1234 {12000000, 8192000, 0x456b},
1235 {13000000, 8192000, 0x495f},
1236 {13100000, 8192000, 0x0320},
1237 {2048000, 11289600, 0xf637},
1238 {3686400, 11289600, 0x2f22},
1239 {12000000, 11289600, 0x3e2f},
1240 {13000000, 11289600, 0x4d5b},
1241 {13100000, 11289600, 0x363b},
1242 {2048000, 16384000, 0x1ea0},
1243 {3686400, 16384000, 0x9e27},
1244 {12000000, 16384000, 0x452b},
1245 {13000000, 16384000, 0x542f},
1246 {13100000, 16384000, 0x03a0},
1247 {2048000, 16934400, 0xe625},
1248 {3686400, 16934400, 0x9126},
1249 {12000000, 16934400, 0x4d2c},
1250 {13000000, 16934400, 0x742f},
1251 {13100000, 16934400, 0x3c27},
1252 {2048000, 22579200, 0x2aa0},
1253 {3686400, 22579200, 0x2f20},
1254 {12000000, 22579200, 0x7e2f},
1255 {13000000, 22579200, 0x742f},
1256 {13100000, 22579200, 0x3c27},
1257 {2048000, 24576000, 0x2ea0},
1258 {3686400, 24576000, 0xee27},
1259 {12000000, 24576000, 0x2915},
1260 {13000000, 24576000, 0x772e},
1261 {13100000, 24576000, 0x0d20},
1262 {26000000, 24576000, 0x2027},
1263 {26000000, 22579200, 0x392f},
1264 {24576000, 22579200, 0x0921},
1265 {24576000, 24576000, 0x02a0},
1266};
1267
1268static const struct pll_div codec_slave_pll_div[] = {
1269 {256000, 2048000, 0x46f0},
1270 {256000, 4096000, 0x3ea0},
1271 {352800, 5644800, 0x3ea0},
1272 {512000, 8192000, 0x3ea0},
1273 {1024000, 8192000, 0x46f0},
1274 {705600, 11289600, 0x3ea0},
1275 {1024000, 16384000, 0x3ea0},
1276 {1411200, 22579200, 0x3ea0},
1277 {1536000, 24576000, 0x3ea0},
1278 {2048000, 16384000, 0x1ea0},
1279 {2822400, 22579200, 0x1ea0},
1280 {2822400, 45158400, 0x5ec0},
1281 {5644800, 45158400, 0x46f0},
1282 {3072000, 24576000, 0x1ea0},
1283 {3072000, 49152000, 0x5ec0},
1284 {6144000, 49152000, 0x46f0},
1285 {705600, 11289600, 0x3ea0},
1286 {705600, 8467200, 0x3ab0},
1287 {24576000, 24576000, 0x02a0},
1288 {1411200, 11289600, 0x1690},
1289 {2822400, 11289600, 0x0a90},
1290 {1536000, 12288000, 0x1690},
1291 {3072000, 12288000, 0x0a90},
1292};
1293
Mark Brownf79e5e82011-09-29 17:30:06 +01001294static struct coeff_clk_div coeff_div[] = {
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001295 /* sysclk is 256fs */
1296 {2048000, 8000 * 32, 8000, 0x1000},
1297 {2048000, 8000 * 64, 8000, 0x0000},
1298 {2822400, 11025 * 32, 11025, 0x1000},
1299 {2822400, 11025 * 64, 11025, 0x0000},
1300 {4096000, 16000 * 32, 16000, 0x1000},
1301 {4096000, 16000 * 64, 16000, 0x0000},
1302 {5644800, 22050 * 32, 22050, 0x1000},
1303 {5644800, 22050 * 64, 22050, 0x0000},
1304 {8192000, 32000 * 32, 32000, 0x1000},
1305 {8192000, 32000 * 64, 32000, 0x0000},
1306 {11289600, 44100 * 32, 44100, 0x1000},
1307 {11289600, 44100 * 64, 44100, 0x0000},
1308 {12288000, 48000 * 32, 48000, 0x1000},
1309 {12288000, 48000 * 64, 48000, 0x0000},
1310 {22579200, 88200 * 32, 88200, 0x1000},
1311 {22579200, 88200 * 64, 88200, 0x0000},
1312 {24576000, 96000 * 32, 96000, 0x1000},
1313 {24576000, 96000 * 64, 96000, 0x0000},
1314 /* sysclk is 512fs */
1315 {4096000, 8000 * 32, 8000, 0x3000},
1316 {4096000, 8000 * 64, 8000, 0x2000},
1317 {5644800, 11025 * 32, 11025, 0x3000},
1318 {5644800, 11025 * 64, 11025, 0x2000},
1319 {8192000, 16000 * 32, 16000, 0x3000},
1320 {8192000, 16000 * 64, 16000, 0x2000},
1321 {11289600, 22050 * 32, 22050, 0x3000},
1322 {11289600, 22050 * 64, 22050, 0x2000},
1323 {16384000, 32000 * 32, 32000, 0x3000},
1324 {16384000, 32000 * 64, 32000, 0x2000},
1325 {22579200, 44100 * 32, 44100, 0x3000},
1326 {22579200, 44100 * 64, 44100, 0x2000},
1327 {24576000, 48000 * 32, 48000, 0x3000},
1328 {24576000, 48000 * 64, 48000, 0x2000},
1329 {45158400, 88200 * 32, 88200, 0x3000},
1330 {45158400, 88200 * 64, 88200, 0x2000},
1331 {49152000, 96000 * 32, 96000, 0x3000},
1332 {49152000, 96000 * 64, 96000, 0x2000},
1333 /* sysclk is 24.576Mhz or 22.5792Mhz */
1334 {24576000, 8000 * 32, 8000, 0x7080},
1335 {24576000, 8000 * 64, 8000, 0x6080},
1336 {24576000, 16000 * 32, 16000, 0x5080},
1337 {24576000, 16000 * 64, 16000, 0x4080},
1338 {24576000, 24000 * 32, 24000, 0x5000},
1339 {24576000, 24000 * 64, 24000, 0x4000},
1340 {24576000, 32000 * 32, 32000, 0x3080},
1341 {24576000, 32000 * 64, 32000, 0x2080},
1342 {22579200, 11025 * 32, 11025, 0x7000},
1343 {22579200, 11025 * 64, 11025, 0x6000},
1344 {22579200, 22050 * 32, 22050, 0x5000},
1345 {22579200, 22050 * 64, 22050, 0x4000},
1346};
1347
1348static int get_coeff(int mclk, int rate, int timesofbclk)
1349{
1350 int i;
1351
1352 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
1353 if (coeff_div[i].mclk == mclk && coeff_div[i].rate == rate &&
1354 (coeff_div[i].bclk / coeff_div[i].rate) == timesofbclk)
1355 return i;
1356 }
1357 return -EINVAL;
1358}
1359
1360static int rt5631_hifi_pcm_params(struct snd_pcm_substream *substream,
1361 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1362{
Mark Browne6968a12012-04-04 15:58:16 +01001363 struct snd_soc_codec *codec = dai->codec;
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001364 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
1365 int timesofbclk = 32, coeff;
1366 unsigned int iface = 0;
1367
1368 dev_dbg(codec->dev, "enter %s\n", __func__);
1369
1370 rt5631->bclk_rate = snd_soc_params_to_bclk(params);
1371 if (rt5631->bclk_rate < 0) {
1372 dev_err(codec->dev, "Fail to get BCLK rate\n");
1373 return rt5631->bclk_rate;
1374 }
1375 rt5631->rx_rate = params_rate(params);
1376
1377 if (rt5631->master)
1378 coeff = get_coeff(rt5631->sysclk, rt5631->rx_rate,
1379 rt5631->bclk_rate / rt5631->rx_rate);
1380 else
1381 coeff = get_coeff(rt5631->sysclk, rt5631->rx_rate,
1382 timesofbclk);
1383 if (coeff < 0) {
1384 dev_err(codec->dev, "Fail to get coeff\n");
1385 return -EINVAL;
1386 }
1387
1388 switch (params_format(params)) {
1389 case SNDRV_PCM_FORMAT_S16_LE:
1390 break;
1391 case SNDRV_PCM_FORMAT_S20_3LE:
1392 iface |= RT5631_SDP_I2S_DL_20;
1393 break;
1394 case SNDRV_PCM_FORMAT_S24_LE:
1395 iface |= RT5631_SDP_I2S_DL_24;
1396 break;
1397 case SNDRV_PCM_FORMAT_S8:
1398 iface |= RT5631_SDP_I2S_DL_8;
1399 break;
1400 default:
1401 return -EINVAL;
1402 }
1403
1404 snd_soc_update_bits(codec, RT5631_SDP_CTRL,
1405 RT5631_SDP_I2S_DL_MASK, iface);
1406 snd_soc_write(codec, RT5631_STEREO_AD_DA_CLK_CTRL,
1407 coeff_div[coeff].reg_val);
1408
1409 return 0;
1410}
1411
1412static int rt5631_hifi_codec_set_dai_fmt(struct snd_soc_dai *codec_dai,
1413 unsigned int fmt)
1414{
1415 struct snd_soc_codec *codec = codec_dai->codec;
1416 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
1417 unsigned int iface = 0;
1418
1419 dev_dbg(codec->dev, "enter %s\n", __func__);
1420
1421 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1422 case SND_SOC_DAIFMT_CBM_CFM:
1423 rt5631->master = 1;
1424 break;
1425 case SND_SOC_DAIFMT_CBS_CFS:
1426 iface |= RT5631_SDP_MODE_SEL_SLAVE;
1427 rt5631->master = 0;
1428 break;
1429 default:
1430 return -EINVAL;
1431 }
1432
1433 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1434 case SND_SOC_DAIFMT_I2S:
1435 break;
1436 case SND_SOC_DAIFMT_LEFT_J:
1437 iface |= RT5631_SDP_I2S_DF_LEFT;
1438 break;
1439 case SND_SOC_DAIFMT_DSP_A:
1440 iface |= RT5631_SDP_I2S_DF_PCM_A;
1441 break;
1442 case SND_SOC_DAIFMT_DSP_B:
1443 iface |= RT5631_SDP_I2S_DF_PCM_B;
1444 break;
1445 default:
1446 return -EINVAL;
1447 }
1448
1449 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1450 case SND_SOC_DAIFMT_NB_NF:
1451 break;
1452 case SND_SOC_DAIFMT_IB_NF:
1453 iface |= RT5631_SDP_I2S_BCLK_POL_CTRL;
1454 break;
1455 default:
1456 return -EINVAL;
1457 }
1458
1459 snd_soc_write(codec, RT5631_SDP_CTRL, iface);
1460
1461 return 0;
1462}
1463
1464static int rt5631_hifi_codec_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1465 int clk_id, unsigned int freq, int dir)
1466{
1467 struct snd_soc_codec *codec = codec_dai->codec;
1468 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
1469
1470 dev_dbg(codec->dev, "enter %s, syclk=%d\n", __func__, freq);
1471
1472 if ((freq >= (256 * 8000)) && (freq <= (512 * 96000))) {
1473 rt5631->sysclk = freq;
1474 return 0;
1475 }
1476
1477 return -EINVAL;
1478}
1479
1480static int rt5631_codec_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1481 int source, unsigned int freq_in, unsigned int freq_out)
1482{
1483 struct snd_soc_codec *codec = codec_dai->codec;
1484 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
1485 int i, ret = -EINVAL;
1486
1487 dev_dbg(codec->dev, "enter %s\n", __func__);
1488
1489 if (!freq_in || !freq_out) {
1490 dev_dbg(codec->dev, "PLL disabled\n");
1491
1492 snd_soc_update_bits(codec, RT5631_GLOBAL_CLK_CTRL,
1493 RT5631_SYSCLK_SOUR_SEL_MASK,
1494 RT5631_SYSCLK_SOUR_SEL_MCLK);
1495
1496 return 0;
1497 }
1498
1499 if (rt5631->master) {
1500 for (i = 0; i < ARRAY_SIZE(codec_master_pll_div); i++)
1501 if (freq_in == codec_master_pll_div[i].pll_in &&
1502 freq_out == codec_master_pll_div[i].pll_out) {
1503 dev_info(codec->dev,
1504 "change PLL in master mode\n");
1505 snd_soc_write(codec, RT5631_PLL_CTRL,
1506 codec_master_pll_div[i].reg_val);
1507 schedule_timeout_uninterruptible(
1508 msecs_to_jiffies(20));
1509 snd_soc_update_bits(codec,
1510 RT5631_GLOBAL_CLK_CTRL,
1511 RT5631_SYSCLK_SOUR_SEL_MASK |
1512 RT5631_PLLCLK_SOUR_SEL_MASK,
1513 RT5631_SYSCLK_SOUR_SEL_PLL |
1514 RT5631_PLLCLK_SOUR_SEL_MCLK);
1515 ret = 0;
1516 break;
1517 }
1518 } else {
1519 for (i = 0; i < ARRAY_SIZE(codec_slave_pll_div); i++)
1520 if (freq_in == codec_slave_pll_div[i].pll_in &&
1521 freq_out == codec_slave_pll_div[i].pll_out) {
1522 dev_info(codec->dev,
1523 "change PLL in slave mode\n");
1524 snd_soc_write(codec, RT5631_PLL_CTRL,
1525 codec_slave_pll_div[i].reg_val);
1526 schedule_timeout_uninterruptible(
1527 msecs_to_jiffies(20));
1528 snd_soc_update_bits(codec,
1529 RT5631_GLOBAL_CLK_CTRL,
1530 RT5631_SYSCLK_SOUR_SEL_MASK |
1531 RT5631_PLLCLK_SOUR_SEL_MASK,
1532 RT5631_SYSCLK_SOUR_SEL_PLL |
1533 RT5631_PLLCLK_SOUR_SEL_BCLK);
1534 ret = 0;
1535 break;
1536 }
1537 }
1538
1539 return ret;
1540}
1541
1542static int rt5631_set_bias_level(struct snd_soc_codec *codec,
1543 enum snd_soc_bias_level level)
1544{
Mark Brown01476802012-05-08 15:52:55 +01001545 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
1546
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001547 switch (level) {
1548 case SND_SOC_BIAS_ON:
1549 case SND_SOC_BIAS_PREPARE:
1550 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD2,
1551 RT5631_PWR_MICBIAS1_VOL | RT5631_PWR_MICBIAS2_VOL,
1552 RT5631_PWR_MICBIAS1_VOL | RT5631_PWR_MICBIAS2_VOL);
1553 break;
1554
1555 case SND_SOC_BIAS_STANDBY:
1556 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1557 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
1558 RT5631_PWR_VREF | RT5631_PWR_MAIN_BIAS,
1559 RT5631_PWR_VREF | RT5631_PWR_MAIN_BIAS);
1560 msleep(80);
1561 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
1562 RT5631_PWR_FAST_VREF_CTRL,
1563 RT5631_PWR_FAST_VREF_CTRL);
Mark Brown01476802012-05-08 15:52:55 +01001564 regcache_cache_only(rt5631->regmap, false);
1565 regcache_sync(rt5631->regmap);
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001566 }
1567 break;
1568
1569 case SND_SOC_BIAS_OFF:
1570 snd_soc_write(codec, RT5631_PWR_MANAG_ADD1, 0x0000);
1571 snd_soc_write(codec, RT5631_PWR_MANAG_ADD2, 0x0000);
1572 snd_soc_write(codec, RT5631_PWR_MANAG_ADD3, 0x0000);
1573 snd_soc_write(codec, RT5631_PWR_MANAG_ADD4, 0x0000);
1574 break;
1575
1576 default:
1577 break;
1578 }
1579 codec->dapm.bias_level = level;
1580
1581 return 0;
1582}
1583
1584static int rt5631_probe(struct snd_soc_codec *codec)
1585{
1586 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
1587 unsigned int val;
1588 int ret;
1589
Mark Brown01476802012-05-08 15:52:55 +01001590 codec->control_data = rt5631->regmap;
1591
1592 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001593 if (ret != 0) {
1594 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1595 return ret;
1596 }
1597
1598 val = rt5631_read_index(codec, RT5631_ADDA_MIXER_INTL_REG3);
1599 if (val & 0x0002)
1600 rt5631->codec_version = 1;
1601 else
1602 rt5631->codec_version = 0;
1603
1604 rt5631_reset(codec);
1605 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
1606 RT5631_PWR_VREF | RT5631_PWR_MAIN_BIAS,
1607 RT5631_PWR_VREF | RT5631_PWR_MAIN_BIAS);
1608 msleep(80);
1609 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
1610 RT5631_PWR_FAST_VREF_CTRL, RT5631_PWR_FAST_VREF_CTRL);
1611 /* enable HP zero cross */
1612 snd_soc_write(codec, RT5631_INT_ST_IRQ_CTRL_2, 0x0f18);
1613 /* power off ClassD auto Recovery */
1614 if (rt5631->codec_version)
1615 snd_soc_update_bits(codec, RT5631_INT_ST_IRQ_CTRL_2,
1616 0x2000, 0x2000);
1617 else
1618 snd_soc_update_bits(codec, RT5631_INT_ST_IRQ_CTRL_2,
1619 0x2000, 0);
1620 /* DMIC */
1621 if (rt5631->dmic_used_flag) {
1622 snd_soc_update_bits(codec, RT5631_GPIO_CTRL,
1623 RT5631_GPIO_PIN_FUN_SEL_MASK |
1624 RT5631_GPIO_DMIC_FUN_SEL_MASK,
1625 RT5631_GPIO_PIN_FUN_SEL_GPIO_DIMC |
1626 RT5631_GPIO_DMIC_FUN_SEL_DIMC);
1627 snd_soc_update_bits(codec, RT5631_DIG_MIC_CTRL,
1628 RT5631_DMIC_L_CH_LATCH_MASK |
1629 RT5631_DMIC_R_CH_LATCH_MASK,
1630 RT5631_DMIC_L_CH_LATCH_FALLING |
1631 RT5631_DMIC_R_CH_LATCH_RISING);
1632 }
1633
1634 codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001635
1636 return 0;
1637}
1638
1639static int rt5631_remove(struct snd_soc_codec *codec)
1640{
1641 rt5631_set_bias_level(codec, SND_SOC_BIAS_OFF);
1642 return 0;
1643}
1644
1645#ifdef CONFIG_PM
Lars-Peter Clausen84b315e2011-12-02 10:18:28 +01001646static int rt5631_suspend(struct snd_soc_codec *codec)
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001647{
1648 rt5631_set_bias_level(codec, SND_SOC_BIAS_OFF);
1649 return 0;
1650}
1651
1652static int rt5631_resume(struct snd_soc_codec *codec)
1653{
1654 rt5631_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1655 return 0;
1656}
1657#else
1658#define rt5631_suspend NULL
1659#define rt5631_resume NULL
1660#endif
1661
1662#define RT5631_STEREO_RATES SNDRV_PCM_RATE_8000_96000
1663#define RT5631_FORMAT (SNDRV_PCM_FMTBIT_S16_LE | \
1664 SNDRV_PCM_FMTBIT_S20_3LE | \
1665 SNDRV_PCM_FMTBIT_S24_LE | \
1666 SNDRV_PCM_FMTBIT_S8)
1667
Lars-Peter Clausen85e76522011-11-23 11:40:40 +01001668static const struct snd_soc_dai_ops rt5631_ops = {
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001669 .hw_params = rt5631_hifi_pcm_params,
1670 .set_fmt = rt5631_hifi_codec_set_dai_fmt,
1671 .set_sysclk = rt5631_hifi_codec_set_dai_sysclk,
1672 .set_pll = rt5631_codec_set_dai_pll,
1673};
1674
Axel Lin51e19fb2011-09-23 16:22:07 +08001675static struct snd_soc_dai_driver rt5631_dai[] = {
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001676 {
1677 .name = "rt5631-hifi",
1678 .id = 1,
1679 .playback = {
1680 .stream_name = "HIFI Playback",
1681 .channels_min = 1,
1682 .channels_max = 2,
1683 .rates = RT5631_STEREO_RATES,
1684 .formats = RT5631_FORMAT,
1685 },
1686 .capture = {
1687 .stream_name = "HIFI Capture",
1688 .channels_min = 1,
1689 .channels_max = 2,
1690 .rates = RT5631_STEREO_RATES,
1691 .formats = RT5631_FORMAT,
1692 },
1693 .ops = &rt5631_ops,
1694 },
1695};
1696
1697static struct snd_soc_codec_driver soc_codec_dev_rt5631 = {
1698 .probe = rt5631_probe,
1699 .remove = rt5631_remove,
1700 .suspend = rt5631_suspend,
1701 .resume = rt5631_resume,
1702 .set_bias_level = rt5631_set_bias_level,
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001703 .controls = rt5631_snd_controls,
1704 .num_controls = ARRAY_SIZE(rt5631_snd_controls),
1705 .dapm_widgets = rt5631_dapm_widgets,
1706 .num_dapm_widgets = ARRAY_SIZE(rt5631_dapm_widgets),
1707 .dapm_routes = rt5631_dapm_routes,
1708 .num_dapm_routes = ARRAY_SIZE(rt5631_dapm_routes),
1709};
1710
1711static const struct i2c_device_id rt5631_i2c_id[] = {
1712 { "rt5631", 0 },
1713 { }
1714};
1715MODULE_DEVICE_TABLE(i2c, rt5631_i2c_id);
1716
Mark Brown01476802012-05-08 15:52:55 +01001717static const struct regmap_config rt5631_regmap_config = {
1718 .reg_bits = 8,
1719 .val_bits = 16,
1720
1721 .readable_reg = rt5631_readable_register,
1722 .volatile_reg = rt5631_volatile_register,
1723 .max_register = RT5631_VENDOR_ID2,
1724 .reg_defaults = rt5631_reg,
1725 .num_reg_defaults = ARRAY_SIZE(rt5631_reg),
1726 .cache_type = REGCACHE_RBTREE,
1727};
1728
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001729static int rt5631_i2c_probe(struct i2c_client *i2c,
1730 const struct i2c_device_id *id)
1731{
1732 struct rt5631_priv *rt5631;
1733 int ret;
1734
Axel Lina92b0a02011-12-29 12:04:15 +08001735 rt5631 = devm_kzalloc(&i2c->dev, sizeof(struct rt5631_priv),
1736 GFP_KERNEL);
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001737 if (NULL == rt5631)
1738 return -ENOMEM;
1739
1740 i2c_set_clientdata(i2c, rt5631);
1741
Mark Brown01476802012-05-08 15:52:55 +01001742 rt5631->regmap = devm_regmap_init_i2c(i2c, &rt5631_regmap_config);
1743 if (IS_ERR(rt5631->regmap))
1744 return PTR_ERR(rt5631->regmap);
1745
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001746 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5631,
1747 rt5631_dai, ARRAY_SIZE(rt5631_dai));
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001748 return ret;
1749}
1750
1751static __devexit int rt5631_i2c_remove(struct i2c_client *client)
1752{
1753 snd_soc_unregister_codec(&client->dev);
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001754 return 0;
1755}
1756
Mark Brownf79e5e82011-09-29 17:30:06 +01001757static struct i2c_driver rt5631_i2c_driver = {
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001758 .driver = {
1759 .name = "rt5631",
1760 .owner = THIS_MODULE,
1761 },
1762 .probe = rt5631_i2c_probe,
1763 .remove = __devexit_p(rt5631_i2c_remove),
1764 .id_table = rt5631_i2c_id,
1765};
1766
Mark Brown03730b82012-05-08 15:35:57 +01001767module_i2c_driver(rt5631_i2c_driver);
johnnyhsu@realtek.comd8085222011-09-07 11:16:35 +08001768
1769MODULE_DESCRIPTION("ASoC RT5631 driver");
1770MODULE_AUTHOR("flove <flove@realtek.com>");
1771MODULE_LICENSE("GPL");