Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2005 Stephane Marchesin |
| 3 | * Copyright 2008 Stuart Bennett |
| 4 | * All Rights Reserved. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 21 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 22 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 23 | * DEALINGS IN THE SOFTWARE. |
| 24 | */ |
| 25 | |
| 26 | #include <linux/swab.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 27 | #include <linux/slab.h> |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "drm_sarea.h" |
| 31 | #include "drm_crtc_helper.h" |
| 32 | #include <linux/vgaarb.h> |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 33 | #include <linux/vga_switcheroo.h> |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 34 | |
| 35 | #include "nouveau_drv.h" |
| 36 | #include "nouveau_drm.h" |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 37 | #include "nouveau_fbcon.h" |
Ben Skeggs | a8eaebc | 2010-09-01 15:24:31 +1000 | [diff] [blame] | 38 | #include "nouveau_ramht.h" |
Ben Skeggs | 330c598 | 2010-09-16 15:39:49 +1000 | [diff] [blame] | 39 | #include "nouveau_pm.h" |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 40 | #include "nv50_display.h" |
| 41 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 42 | static void nouveau_stub_takedown(struct drm_device *dev) {} |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 43 | static int nouveau_stub_init(struct drm_device *dev) { return 0; } |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 44 | |
| 45 | static int nouveau_init_engine_ptrs(struct drm_device *dev) |
| 46 | { |
| 47 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 48 | struct nouveau_engine *engine = &dev_priv->engine; |
| 49 | |
| 50 | switch (dev_priv->chipset & 0xf0) { |
| 51 | case 0x00: |
| 52 | engine->instmem.init = nv04_instmem_init; |
| 53 | engine->instmem.takedown = nv04_instmem_takedown; |
| 54 | engine->instmem.suspend = nv04_instmem_suspend; |
| 55 | engine->instmem.resume = nv04_instmem_resume; |
Ben Skeggs | e41115d | 2010-11-01 11:45:02 +1000 | [diff] [blame] | 56 | engine->instmem.get = nv04_instmem_get; |
| 57 | engine->instmem.put = nv04_instmem_put; |
| 58 | engine->instmem.map = nv04_instmem_map; |
| 59 | engine->instmem.unmap = nv04_instmem_unmap; |
Ben Skeggs | f56cb86 | 2010-07-08 11:29:10 +1000 | [diff] [blame] | 60 | engine->instmem.flush = nv04_instmem_flush; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 61 | engine->mc.init = nv04_mc_init; |
| 62 | engine->mc.takedown = nv04_mc_takedown; |
| 63 | engine->timer.init = nv04_timer_init; |
| 64 | engine->timer.read = nv04_timer_read; |
| 65 | engine->timer.takedown = nv04_timer_takedown; |
| 66 | engine->fb.init = nv04_fb_init; |
| 67 | engine->fb.takedown = nv04_fb_takedown; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 68 | engine->fifo.channels = 16; |
| 69 | engine->fifo.init = nv04_fifo_init; |
Ben Skeggs | 5178d40 | 2010-11-03 10:56:05 +1000 | [diff] [blame] | 70 | engine->fifo.takedown = nv04_fifo_fini; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 71 | engine->fifo.disable = nv04_fifo_disable; |
| 72 | engine->fifo.enable = nv04_fifo_enable; |
| 73 | engine->fifo.reassign = nv04_fifo_reassign; |
Francisco Jerez | 588d7d1 | 2009-12-13 20:07:42 +0100 | [diff] [blame] | 74 | engine->fifo.cache_pull = nv04_fifo_cache_pull; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 75 | engine->fifo.channel_id = nv04_fifo_channel_id; |
| 76 | engine->fifo.create_context = nv04_fifo_create_context; |
| 77 | engine->fifo.destroy_context = nv04_fifo_destroy_context; |
| 78 | engine->fifo.load_context = nv04_fifo_load_context; |
| 79 | engine->fifo.unload_context = nv04_fifo_unload_context; |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 80 | engine->display.early_init = nv04_display_early_init; |
| 81 | engine->display.late_takedown = nv04_display_late_takedown; |
| 82 | engine->display.create = nv04_display_create; |
| 83 | engine->display.init = nv04_display_init; |
| 84 | engine->display.destroy = nv04_display_destroy; |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 85 | engine->gpio.init = nouveau_stub_init; |
| 86 | engine->gpio.takedown = nouveau_stub_takedown; |
| 87 | engine->gpio.get = NULL; |
| 88 | engine->gpio.set = NULL; |
| 89 | engine->gpio.irq_enable = NULL; |
Ben Skeggs | 442b626 | 2010-09-16 16:25:26 +1000 | [diff] [blame] | 90 | engine->pm.clock_get = nv04_pm_clock_get; |
| 91 | engine->pm.clock_pre = nv04_pm_clock_pre; |
| 92 | engine->pm.clock_set = nv04_pm_clock_set; |
Ben Skeggs | 60d2a88 | 2010-12-06 15:28:54 +1000 | [diff] [blame] | 93 | engine->vram.init = nouveau_mem_detect; |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 94 | engine->vram.takedown = nouveau_stub_takedown; |
Ben Skeggs | 60d2a88 | 2010-12-06 15:28:54 +1000 | [diff] [blame] | 95 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 96 | break; |
| 97 | case 0x10: |
| 98 | engine->instmem.init = nv04_instmem_init; |
| 99 | engine->instmem.takedown = nv04_instmem_takedown; |
| 100 | engine->instmem.suspend = nv04_instmem_suspend; |
| 101 | engine->instmem.resume = nv04_instmem_resume; |
Ben Skeggs | e41115d | 2010-11-01 11:45:02 +1000 | [diff] [blame] | 102 | engine->instmem.get = nv04_instmem_get; |
| 103 | engine->instmem.put = nv04_instmem_put; |
| 104 | engine->instmem.map = nv04_instmem_map; |
| 105 | engine->instmem.unmap = nv04_instmem_unmap; |
Ben Skeggs | f56cb86 | 2010-07-08 11:29:10 +1000 | [diff] [blame] | 106 | engine->instmem.flush = nv04_instmem_flush; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 107 | engine->mc.init = nv04_mc_init; |
| 108 | engine->mc.takedown = nv04_mc_takedown; |
| 109 | engine->timer.init = nv04_timer_init; |
| 110 | engine->timer.read = nv04_timer_read; |
| 111 | engine->timer.takedown = nv04_timer_takedown; |
| 112 | engine->fb.init = nv10_fb_init; |
| 113 | engine->fb.takedown = nv10_fb_takedown; |
Francisco Jerez | a5cf68b | 2010-10-24 16:14:41 +0200 | [diff] [blame] | 114 | engine->fb.init_tile_region = nv10_fb_init_tile_region; |
| 115 | engine->fb.set_tile_region = nv10_fb_set_tile_region; |
| 116 | engine->fb.free_tile_region = nv10_fb_free_tile_region; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 117 | engine->fifo.channels = 32; |
| 118 | engine->fifo.init = nv10_fifo_init; |
Ben Skeggs | 5178d40 | 2010-11-03 10:56:05 +1000 | [diff] [blame] | 119 | engine->fifo.takedown = nv04_fifo_fini; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 120 | engine->fifo.disable = nv04_fifo_disable; |
| 121 | engine->fifo.enable = nv04_fifo_enable; |
| 122 | engine->fifo.reassign = nv04_fifo_reassign; |
Francisco Jerez | 588d7d1 | 2009-12-13 20:07:42 +0100 | [diff] [blame] | 123 | engine->fifo.cache_pull = nv04_fifo_cache_pull; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 124 | engine->fifo.channel_id = nv10_fifo_channel_id; |
| 125 | engine->fifo.create_context = nv10_fifo_create_context; |
Francisco Jerez | 3945e47 | 2010-10-18 03:53:39 +0200 | [diff] [blame] | 126 | engine->fifo.destroy_context = nv04_fifo_destroy_context; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 127 | engine->fifo.load_context = nv10_fifo_load_context; |
| 128 | engine->fifo.unload_context = nv10_fifo_unload_context; |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 129 | engine->display.early_init = nv04_display_early_init; |
| 130 | engine->display.late_takedown = nv04_display_late_takedown; |
| 131 | engine->display.create = nv04_display_create; |
| 132 | engine->display.init = nv04_display_init; |
| 133 | engine->display.destroy = nv04_display_destroy; |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 134 | engine->gpio.init = nouveau_stub_init; |
| 135 | engine->gpio.takedown = nouveau_stub_takedown; |
| 136 | engine->gpio.get = nv10_gpio_get; |
| 137 | engine->gpio.set = nv10_gpio_set; |
| 138 | engine->gpio.irq_enable = NULL; |
Ben Skeggs | 442b626 | 2010-09-16 16:25:26 +1000 | [diff] [blame] | 139 | engine->pm.clock_get = nv04_pm_clock_get; |
| 140 | engine->pm.clock_pre = nv04_pm_clock_pre; |
| 141 | engine->pm.clock_set = nv04_pm_clock_set; |
Ben Skeggs | 60d2a88 | 2010-12-06 15:28:54 +1000 | [diff] [blame] | 142 | engine->vram.init = nouveau_mem_detect; |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 143 | engine->vram.takedown = nouveau_stub_takedown; |
Ben Skeggs | 60d2a88 | 2010-12-06 15:28:54 +1000 | [diff] [blame] | 144 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 145 | break; |
| 146 | case 0x20: |
| 147 | engine->instmem.init = nv04_instmem_init; |
| 148 | engine->instmem.takedown = nv04_instmem_takedown; |
| 149 | engine->instmem.suspend = nv04_instmem_suspend; |
| 150 | engine->instmem.resume = nv04_instmem_resume; |
Ben Skeggs | e41115d | 2010-11-01 11:45:02 +1000 | [diff] [blame] | 151 | engine->instmem.get = nv04_instmem_get; |
| 152 | engine->instmem.put = nv04_instmem_put; |
| 153 | engine->instmem.map = nv04_instmem_map; |
| 154 | engine->instmem.unmap = nv04_instmem_unmap; |
Ben Skeggs | f56cb86 | 2010-07-08 11:29:10 +1000 | [diff] [blame] | 155 | engine->instmem.flush = nv04_instmem_flush; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 156 | engine->mc.init = nv04_mc_init; |
| 157 | engine->mc.takedown = nv04_mc_takedown; |
| 158 | engine->timer.init = nv04_timer_init; |
| 159 | engine->timer.read = nv04_timer_read; |
| 160 | engine->timer.takedown = nv04_timer_takedown; |
| 161 | engine->fb.init = nv10_fb_init; |
| 162 | engine->fb.takedown = nv10_fb_takedown; |
Francisco Jerez | a5cf68b | 2010-10-24 16:14:41 +0200 | [diff] [blame] | 163 | engine->fb.init_tile_region = nv10_fb_init_tile_region; |
| 164 | engine->fb.set_tile_region = nv10_fb_set_tile_region; |
| 165 | engine->fb.free_tile_region = nv10_fb_free_tile_region; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 166 | engine->fifo.channels = 32; |
| 167 | engine->fifo.init = nv10_fifo_init; |
Ben Skeggs | 5178d40 | 2010-11-03 10:56:05 +1000 | [diff] [blame] | 168 | engine->fifo.takedown = nv04_fifo_fini; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 169 | engine->fifo.disable = nv04_fifo_disable; |
| 170 | engine->fifo.enable = nv04_fifo_enable; |
| 171 | engine->fifo.reassign = nv04_fifo_reassign; |
Francisco Jerez | 588d7d1 | 2009-12-13 20:07:42 +0100 | [diff] [blame] | 172 | engine->fifo.cache_pull = nv04_fifo_cache_pull; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 173 | engine->fifo.channel_id = nv10_fifo_channel_id; |
| 174 | engine->fifo.create_context = nv10_fifo_create_context; |
Francisco Jerez | 3945e47 | 2010-10-18 03:53:39 +0200 | [diff] [blame] | 175 | engine->fifo.destroy_context = nv04_fifo_destroy_context; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 176 | engine->fifo.load_context = nv10_fifo_load_context; |
| 177 | engine->fifo.unload_context = nv10_fifo_unload_context; |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 178 | engine->display.early_init = nv04_display_early_init; |
| 179 | engine->display.late_takedown = nv04_display_late_takedown; |
| 180 | engine->display.create = nv04_display_create; |
| 181 | engine->display.init = nv04_display_init; |
| 182 | engine->display.destroy = nv04_display_destroy; |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 183 | engine->gpio.init = nouveau_stub_init; |
| 184 | engine->gpio.takedown = nouveau_stub_takedown; |
| 185 | engine->gpio.get = nv10_gpio_get; |
| 186 | engine->gpio.set = nv10_gpio_set; |
| 187 | engine->gpio.irq_enable = NULL; |
Ben Skeggs | 442b626 | 2010-09-16 16:25:26 +1000 | [diff] [blame] | 188 | engine->pm.clock_get = nv04_pm_clock_get; |
| 189 | engine->pm.clock_pre = nv04_pm_clock_pre; |
| 190 | engine->pm.clock_set = nv04_pm_clock_set; |
Ben Skeggs | 60d2a88 | 2010-12-06 15:28:54 +1000 | [diff] [blame] | 191 | engine->vram.init = nouveau_mem_detect; |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 192 | engine->vram.takedown = nouveau_stub_takedown; |
Ben Skeggs | 60d2a88 | 2010-12-06 15:28:54 +1000 | [diff] [blame] | 193 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 194 | break; |
| 195 | case 0x30: |
| 196 | engine->instmem.init = nv04_instmem_init; |
| 197 | engine->instmem.takedown = nv04_instmem_takedown; |
| 198 | engine->instmem.suspend = nv04_instmem_suspend; |
| 199 | engine->instmem.resume = nv04_instmem_resume; |
Ben Skeggs | e41115d | 2010-11-01 11:45:02 +1000 | [diff] [blame] | 200 | engine->instmem.get = nv04_instmem_get; |
| 201 | engine->instmem.put = nv04_instmem_put; |
| 202 | engine->instmem.map = nv04_instmem_map; |
| 203 | engine->instmem.unmap = nv04_instmem_unmap; |
Ben Skeggs | f56cb86 | 2010-07-08 11:29:10 +1000 | [diff] [blame] | 204 | engine->instmem.flush = nv04_instmem_flush; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 205 | engine->mc.init = nv04_mc_init; |
| 206 | engine->mc.takedown = nv04_mc_takedown; |
| 207 | engine->timer.init = nv04_timer_init; |
| 208 | engine->timer.read = nv04_timer_read; |
| 209 | engine->timer.takedown = nv04_timer_takedown; |
Francisco Jerez | 8bded18 | 2010-07-21 21:08:11 +0200 | [diff] [blame] | 210 | engine->fb.init = nv30_fb_init; |
| 211 | engine->fb.takedown = nv30_fb_takedown; |
Francisco Jerez | a5cf68b | 2010-10-24 16:14:41 +0200 | [diff] [blame] | 212 | engine->fb.init_tile_region = nv30_fb_init_tile_region; |
| 213 | engine->fb.set_tile_region = nv10_fb_set_tile_region; |
| 214 | engine->fb.free_tile_region = nv30_fb_free_tile_region; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 215 | engine->fifo.channels = 32; |
| 216 | engine->fifo.init = nv10_fifo_init; |
Ben Skeggs | 5178d40 | 2010-11-03 10:56:05 +1000 | [diff] [blame] | 217 | engine->fifo.takedown = nv04_fifo_fini; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 218 | engine->fifo.disable = nv04_fifo_disable; |
| 219 | engine->fifo.enable = nv04_fifo_enable; |
| 220 | engine->fifo.reassign = nv04_fifo_reassign; |
Francisco Jerez | 588d7d1 | 2009-12-13 20:07:42 +0100 | [diff] [blame] | 221 | engine->fifo.cache_pull = nv04_fifo_cache_pull; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 222 | engine->fifo.channel_id = nv10_fifo_channel_id; |
| 223 | engine->fifo.create_context = nv10_fifo_create_context; |
Francisco Jerez | 3945e47 | 2010-10-18 03:53:39 +0200 | [diff] [blame] | 224 | engine->fifo.destroy_context = nv04_fifo_destroy_context; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 225 | engine->fifo.load_context = nv10_fifo_load_context; |
| 226 | engine->fifo.unload_context = nv10_fifo_unload_context; |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 227 | engine->display.early_init = nv04_display_early_init; |
| 228 | engine->display.late_takedown = nv04_display_late_takedown; |
| 229 | engine->display.create = nv04_display_create; |
| 230 | engine->display.init = nv04_display_init; |
| 231 | engine->display.destroy = nv04_display_destroy; |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 232 | engine->gpio.init = nouveau_stub_init; |
| 233 | engine->gpio.takedown = nouveau_stub_takedown; |
| 234 | engine->gpio.get = nv10_gpio_get; |
| 235 | engine->gpio.set = nv10_gpio_set; |
| 236 | engine->gpio.irq_enable = NULL; |
Ben Skeggs | 442b626 | 2010-09-16 16:25:26 +1000 | [diff] [blame] | 237 | engine->pm.clock_get = nv04_pm_clock_get; |
| 238 | engine->pm.clock_pre = nv04_pm_clock_pre; |
| 239 | engine->pm.clock_set = nv04_pm_clock_set; |
| 240 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
| 241 | engine->pm.voltage_set = nouveau_voltage_gpio_set; |
Ben Skeggs | 60d2a88 | 2010-12-06 15:28:54 +1000 | [diff] [blame] | 242 | engine->vram.init = nouveau_mem_detect; |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 243 | engine->vram.takedown = nouveau_stub_takedown; |
Ben Skeggs | 60d2a88 | 2010-12-06 15:28:54 +1000 | [diff] [blame] | 244 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 245 | break; |
| 246 | case 0x40: |
| 247 | case 0x60: |
| 248 | engine->instmem.init = nv04_instmem_init; |
| 249 | engine->instmem.takedown = nv04_instmem_takedown; |
| 250 | engine->instmem.suspend = nv04_instmem_suspend; |
| 251 | engine->instmem.resume = nv04_instmem_resume; |
Ben Skeggs | e41115d | 2010-11-01 11:45:02 +1000 | [diff] [blame] | 252 | engine->instmem.get = nv04_instmem_get; |
| 253 | engine->instmem.put = nv04_instmem_put; |
| 254 | engine->instmem.map = nv04_instmem_map; |
| 255 | engine->instmem.unmap = nv04_instmem_unmap; |
Ben Skeggs | f56cb86 | 2010-07-08 11:29:10 +1000 | [diff] [blame] | 256 | engine->instmem.flush = nv04_instmem_flush; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 257 | engine->mc.init = nv40_mc_init; |
| 258 | engine->mc.takedown = nv40_mc_takedown; |
| 259 | engine->timer.init = nv04_timer_init; |
| 260 | engine->timer.read = nv04_timer_read; |
| 261 | engine->timer.takedown = nv04_timer_takedown; |
| 262 | engine->fb.init = nv40_fb_init; |
| 263 | engine->fb.takedown = nv40_fb_takedown; |
Francisco Jerez | a5cf68b | 2010-10-24 16:14:41 +0200 | [diff] [blame] | 264 | engine->fb.init_tile_region = nv30_fb_init_tile_region; |
| 265 | engine->fb.set_tile_region = nv40_fb_set_tile_region; |
| 266 | engine->fb.free_tile_region = nv30_fb_free_tile_region; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 267 | engine->fifo.channels = 32; |
| 268 | engine->fifo.init = nv40_fifo_init; |
Ben Skeggs | 5178d40 | 2010-11-03 10:56:05 +1000 | [diff] [blame] | 269 | engine->fifo.takedown = nv04_fifo_fini; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 270 | engine->fifo.disable = nv04_fifo_disable; |
| 271 | engine->fifo.enable = nv04_fifo_enable; |
| 272 | engine->fifo.reassign = nv04_fifo_reassign; |
Francisco Jerez | 588d7d1 | 2009-12-13 20:07:42 +0100 | [diff] [blame] | 273 | engine->fifo.cache_pull = nv04_fifo_cache_pull; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 274 | engine->fifo.channel_id = nv10_fifo_channel_id; |
| 275 | engine->fifo.create_context = nv40_fifo_create_context; |
Francisco Jerez | 3945e47 | 2010-10-18 03:53:39 +0200 | [diff] [blame] | 276 | engine->fifo.destroy_context = nv04_fifo_destroy_context; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 277 | engine->fifo.load_context = nv40_fifo_load_context; |
| 278 | engine->fifo.unload_context = nv40_fifo_unload_context; |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 279 | engine->display.early_init = nv04_display_early_init; |
| 280 | engine->display.late_takedown = nv04_display_late_takedown; |
| 281 | engine->display.create = nv04_display_create; |
| 282 | engine->display.init = nv04_display_init; |
| 283 | engine->display.destroy = nv04_display_destroy; |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 284 | engine->gpio.init = nouveau_stub_init; |
| 285 | engine->gpio.takedown = nouveau_stub_takedown; |
| 286 | engine->gpio.get = nv10_gpio_get; |
| 287 | engine->gpio.set = nv10_gpio_set; |
| 288 | engine->gpio.irq_enable = NULL; |
Ben Skeggs | 442b626 | 2010-09-16 16:25:26 +1000 | [diff] [blame] | 289 | engine->pm.clock_get = nv04_pm_clock_get; |
| 290 | engine->pm.clock_pre = nv04_pm_clock_pre; |
| 291 | engine->pm.clock_set = nv04_pm_clock_set; |
| 292 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
| 293 | engine->pm.voltage_set = nouveau_voltage_gpio_set; |
Francisco Jerez | 8155cac | 2010-09-23 20:58:38 +0200 | [diff] [blame] | 294 | engine->pm.temp_get = nv40_temp_get; |
Ben Skeggs | 60d2a88 | 2010-12-06 15:28:54 +1000 | [diff] [blame] | 295 | engine->vram.init = nouveau_mem_detect; |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 296 | engine->vram.takedown = nouveau_stub_takedown; |
Ben Skeggs | 60d2a88 | 2010-12-06 15:28:54 +1000 | [diff] [blame] | 297 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 298 | break; |
| 299 | case 0x50: |
| 300 | case 0x80: /* gotta love NVIDIA's consistency.. */ |
| 301 | case 0x90: |
Ben Skeggs | d9f61c2 | 2011-07-04 13:25:17 +1000 | [diff] [blame] | 302 | case 0xa0: |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 303 | engine->instmem.init = nv50_instmem_init; |
| 304 | engine->instmem.takedown = nv50_instmem_takedown; |
| 305 | engine->instmem.suspend = nv50_instmem_suspend; |
| 306 | engine->instmem.resume = nv50_instmem_resume; |
Ben Skeggs | e41115d | 2010-11-01 11:45:02 +1000 | [diff] [blame] | 307 | engine->instmem.get = nv50_instmem_get; |
| 308 | engine->instmem.put = nv50_instmem_put; |
| 309 | engine->instmem.map = nv50_instmem_map; |
| 310 | engine->instmem.unmap = nv50_instmem_unmap; |
Ben Skeggs | 734ee83 | 2010-07-15 11:02:54 +1000 | [diff] [blame] | 311 | if (dev_priv->chipset == 0x50) |
| 312 | engine->instmem.flush = nv50_instmem_flush; |
| 313 | else |
| 314 | engine->instmem.flush = nv84_instmem_flush; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 315 | engine->mc.init = nv50_mc_init; |
| 316 | engine->mc.takedown = nv50_mc_takedown; |
| 317 | engine->timer.init = nv04_timer_init; |
| 318 | engine->timer.read = nv04_timer_read; |
| 319 | engine->timer.takedown = nv04_timer_takedown; |
Marcin KoĆcielnicki | 304424e | 2010-03-01 00:18:39 +0000 | [diff] [blame] | 320 | engine->fb.init = nv50_fb_init; |
| 321 | engine->fb.takedown = nv50_fb_takedown; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 322 | engine->fifo.channels = 128; |
| 323 | engine->fifo.init = nv50_fifo_init; |
| 324 | engine->fifo.takedown = nv50_fifo_takedown; |
| 325 | engine->fifo.disable = nv04_fifo_disable; |
| 326 | engine->fifo.enable = nv04_fifo_enable; |
| 327 | engine->fifo.reassign = nv04_fifo_reassign; |
| 328 | engine->fifo.channel_id = nv50_fifo_channel_id; |
| 329 | engine->fifo.create_context = nv50_fifo_create_context; |
| 330 | engine->fifo.destroy_context = nv50_fifo_destroy_context; |
| 331 | engine->fifo.load_context = nv50_fifo_load_context; |
| 332 | engine->fifo.unload_context = nv50_fifo_unload_context; |
Ben Skeggs | 56ac747 | 2010-10-22 10:26:24 +1000 | [diff] [blame] | 333 | engine->fifo.tlb_flush = nv50_fifo_tlb_flush; |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 334 | engine->display.early_init = nv50_display_early_init; |
| 335 | engine->display.late_takedown = nv50_display_late_takedown; |
| 336 | engine->display.create = nv50_display_create; |
| 337 | engine->display.init = nv50_display_init; |
| 338 | engine->display.destroy = nv50_display_destroy; |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 339 | engine->gpio.init = nv50_gpio_init; |
Ben Skeggs | 2cbd4c8 | 2010-11-03 10:18:04 +1000 | [diff] [blame] | 340 | engine->gpio.takedown = nv50_gpio_fini; |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 341 | engine->gpio.get = nv50_gpio_get; |
| 342 | engine->gpio.set = nv50_gpio_set; |
Ben Skeggs | fce2bad | 2010-11-11 16:14:56 +1000 | [diff] [blame] | 343 | engine->gpio.irq_register = nv50_gpio_irq_register; |
| 344 | engine->gpio.irq_unregister = nv50_gpio_irq_unregister; |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 345 | engine->gpio.irq_enable = nv50_gpio_irq_enable; |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 346 | switch (dev_priv->chipset) { |
Ben Skeggs | bd2e597 | 2010-10-19 20:06:01 +1000 | [diff] [blame] | 347 | case 0x84: |
| 348 | case 0x86: |
| 349 | case 0x92: |
| 350 | case 0x94: |
| 351 | case 0x96: |
| 352 | case 0x98: |
| 353 | case 0xa0: |
Ben Skeggs | 5f80198 | 2010-10-22 08:44:09 +1000 | [diff] [blame] | 354 | case 0xaa: |
| 355 | case 0xac: |
Ben Skeggs | bd2e597 | 2010-10-19 20:06:01 +1000 | [diff] [blame] | 356 | case 0x50: |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 357 | engine->pm.clock_get = nv50_pm_clock_get; |
| 358 | engine->pm.clock_pre = nv50_pm_clock_pre; |
| 359 | engine->pm.clock_set = nv50_pm_clock_set; |
| 360 | break; |
Ben Skeggs | bd2e597 | 2010-10-19 20:06:01 +1000 | [diff] [blame] | 361 | default: |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 362 | engine->pm.clocks_get = nva3_pm_clocks_get; |
| 363 | engine->pm.clocks_pre = nva3_pm_clocks_pre; |
| 364 | engine->pm.clocks_set = nva3_pm_clocks_set; |
Ben Skeggs | bd2e597 | 2010-10-19 20:06:01 +1000 | [diff] [blame] | 365 | break; |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 366 | } |
Ben Skeggs | 02c30ca | 2010-09-16 16:17:35 +1000 | [diff] [blame] | 367 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
| 368 | engine->pm.voltage_set = nouveau_voltage_gpio_set; |
Francisco Jerez | 8155cac | 2010-09-23 20:58:38 +0200 | [diff] [blame] | 369 | if (dev_priv->chipset >= 0x84) |
| 370 | engine->pm.temp_get = nv84_temp_get; |
| 371 | else |
| 372 | engine->pm.temp_get = nv40_temp_get; |
Ben Skeggs | 60d2a88 | 2010-12-06 15:28:54 +1000 | [diff] [blame] | 373 | engine->vram.init = nv50_vram_init; |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 374 | engine->vram.takedown = nv50_vram_fini; |
Ben Skeggs | 60d2a88 | 2010-12-06 15:28:54 +1000 | [diff] [blame] | 375 | engine->vram.get = nv50_vram_new; |
| 376 | engine->vram.put = nv50_vram_del; |
| 377 | engine->vram.flags_valid = nv50_vram_flags_valid; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 378 | break; |
Ben Skeggs | d9f61c2 | 2011-07-04 13:25:17 +1000 | [diff] [blame] | 379 | case 0xc0: |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 380 | engine->instmem.init = nvc0_instmem_init; |
| 381 | engine->instmem.takedown = nvc0_instmem_takedown; |
| 382 | engine->instmem.suspend = nvc0_instmem_suspend; |
| 383 | engine->instmem.resume = nvc0_instmem_resume; |
Ben Skeggs | 8984e04 | 2010-11-15 11:48:33 +1000 | [diff] [blame] | 384 | engine->instmem.get = nv50_instmem_get; |
| 385 | engine->instmem.put = nv50_instmem_put; |
| 386 | engine->instmem.map = nv50_instmem_map; |
| 387 | engine->instmem.unmap = nv50_instmem_unmap; |
| 388 | engine->instmem.flush = nv84_instmem_flush; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 389 | engine->mc.init = nv50_mc_init; |
| 390 | engine->mc.takedown = nv50_mc_takedown; |
| 391 | engine->timer.init = nv04_timer_init; |
| 392 | engine->timer.read = nv04_timer_read; |
| 393 | engine->timer.takedown = nv04_timer_takedown; |
| 394 | engine->fb.init = nvc0_fb_init; |
| 395 | engine->fb.takedown = nvc0_fb_takedown; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 396 | engine->fifo.channels = 128; |
| 397 | engine->fifo.init = nvc0_fifo_init; |
| 398 | engine->fifo.takedown = nvc0_fifo_takedown; |
| 399 | engine->fifo.disable = nvc0_fifo_disable; |
| 400 | engine->fifo.enable = nvc0_fifo_enable; |
| 401 | engine->fifo.reassign = nvc0_fifo_reassign; |
| 402 | engine->fifo.channel_id = nvc0_fifo_channel_id; |
| 403 | engine->fifo.create_context = nvc0_fifo_create_context; |
| 404 | engine->fifo.destroy_context = nvc0_fifo_destroy_context; |
| 405 | engine->fifo.load_context = nvc0_fifo_load_context; |
| 406 | engine->fifo.unload_context = nvc0_fifo_unload_context; |
| 407 | engine->display.early_init = nv50_display_early_init; |
| 408 | engine->display.late_takedown = nv50_display_late_takedown; |
| 409 | engine->display.create = nv50_display_create; |
| 410 | engine->display.init = nv50_display_init; |
| 411 | engine->display.destroy = nv50_display_destroy; |
| 412 | engine->gpio.init = nv50_gpio_init; |
| 413 | engine->gpio.takedown = nouveau_stub_takedown; |
| 414 | engine->gpio.get = nv50_gpio_get; |
| 415 | engine->gpio.set = nv50_gpio_set; |
Ben Skeggs | fce2bad | 2010-11-11 16:14:56 +1000 | [diff] [blame] | 416 | engine->gpio.irq_register = nv50_gpio_irq_register; |
| 417 | engine->gpio.irq_unregister = nv50_gpio_irq_unregister; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 418 | engine->gpio.irq_enable = nv50_gpio_irq_enable; |
Ben Skeggs | 8984e04 | 2010-11-15 11:48:33 +1000 | [diff] [blame] | 419 | engine->vram.init = nvc0_vram_init; |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 420 | engine->vram.takedown = nv50_vram_fini; |
Ben Skeggs | 8984e04 | 2010-11-15 11:48:33 +1000 | [diff] [blame] | 421 | engine->vram.get = nvc0_vram_new; |
| 422 | engine->vram.put = nv50_vram_del; |
| 423 | engine->vram.flags_valid = nvc0_vram_flags_valid; |
Martin Peres | 74cfad1 | 2011-05-12 22:40:47 +0200 | [diff] [blame] | 424 | engine->pm.temp_get = nv84_temp_get; |
Ben Skeggs | 354d078 | 2011-06-19 01:44:36 +1000 | [diff] [blame] | 425 | engine->pm.clocks_get = nvc0_pm_clocks_get; |
Ben Skeggs | 3c71c23 | 2011-06-09 17:34:02 +1000 | [diff] [blame] | 426 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
Ben Skeggs | da1dc4c | 2011-06-10 12:07:09 +1000 | [diff] [blame] | 427 | engine->pm.voltage_set = nouveau_voltage_gpio_set; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 428 | break; |
Ben Skeggs | d9f61c2 | 2011-07-04 13:25:17 +1000 | [diff] [blame] | 429 | case 0xd0: |
| 430 | engine->instmem.init = nvc0_instmem_init; |
| 431 | engine->instmem.takedown = nvc0_instmem_takedown; |
| 432 | engine->instmem.suspend = nvc0_instmem_suspend; |
| 433 | engine->instmem.resume = nvc0_instmem_resume; |
| 434 | engine->instmem.get = nv50_instmem_get; |
| 435 | engine->instmem.put = nv50_instmem_put; |
| 436 | engine->instmem.map = nv50_instmem_map; |
| 437 | engine->instmem.unmap = nv50_instmem_unmap; |
| 438 | engine->instmem.flush = nv84_instmem_flush; |
| 439 | engine->mc.init = nv50_mc_init; |
| 440 | engine->mc.takedown = nv50_mc_takedown; |
| 441 | engine->timer.init = nv04_timer_init; |
| 442 | engine->timer.read = nv04_timer_read; |
| 443 | engine->timer.takedown = nv04_timer_takedown; |
| 444 | engine->fb.init = nvc0_fb_init; |
| 445 | engine->fb.takedown = nvc0_fb_takedown; |
| 446 | engine->fifo.channels = 128; |
| 447 | engine->fifo.init = nvc0_fifo_init; |
| 448 | engine->fifo.takedown = nvc0_fifo_takedown; |
| 449 | engine->fifo.disable = nvc0_fifo_disable; |
| 450 | engine->fifo.enable = nvc0_fifo_enable; |
| 451 | engine->fifo.reassign = nvc0_fifo_reassign; |
| 452 | engine->fifo.channel_id = nvc0_fifo_channel_id; |
| 453 | engine->fifo.create_context = nvc0_fifo_create_context; |
| 454 | engine->fifo.destroy_context = nvc0_fifo_destroy_context; |
| 455 | engine->fifo.load_context = nvc0_fifo_load_context; |
| 456 | engine->fifo.unload_context = nvc0_fifo_unload_context; |
| 457 | engine->display.early_init = nouveau_stub_init; |
| 458 | engine->display.late_takedown = nouveau_stub_takedown; |
| 459 | engine->display.create = nouveau_stub_init; |
| 460 | engine->display.init = nouveau_stub_init; |
| 461 | engine->display.destroy = nouveau_stub_takedown; |
Ben Skeggs | d7f8172 | 2011-07-03 02:57:35 +1000 | [diff] [blame] | 462 | engine->gpio.init = nv50_gpio_init; |
Ben Skeggs | d9f61c2 | 2011-07-04 13:25:17 +1000 | [diff] [blame] | 463 | engine->gpio.takedown = nouveau_stub_takedown; |
Ben Skeggs | d7f8172 | 2011-07-03 02:57:35 +1000 | [diff] [blame] | 464 | engine->gpio.get = nvd0_gpio_get; |
| 465 | engine->gpio.set = nvd0_gpio_set; |
| 466 | engine->gpio.irq_register = nv50_gpio_irq_register; |
| 467 | engine->gpio.irq_unregister = nv50_gpio_irq_unregister; |
| 468 | engine->gpio.irq_enable = nv50_gpio_irq_enable; |
Ben Skeggs | d9f61c2 | 2011-07-04 13:25:17 +1000 | [diff] [blame] | 469 | engine->vram.init = nvc0_vram_init; |
| 470 | engine->vram.takedown = nv50_vram_fini; |
| 471 | engine->vram.get = nvc0_vram_new; |
| 472 | engine->vram.put = nv50_vram_del; |
| 473 | engine->vram.flags_valid = nvc0_vram_flags_valid; |
Ben Skeggs | 4784e4a | 2011-07-04 14:06:07 +1000 | [diff] [blame^] | 474 | engine->pm.clocks_get = nvc0_pm_clocks_get; |
| 475 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
| 476 | engine->pm.voltage_set = nouveau_voltage_gpio_set; |
Ben Skeggs | d9f61c2 | 2011-07-04 13:25:17 +1000 | [diff] [blame] | 477 | break; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 478 | default: |
| 479 | NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset); |
| 480 | return 1; |
| 481 | } |
| 482 | |
Ben Skeggs | 03bc967 | 2011-07-04 13:14:05 +1000 | [diff] [blame] | 483 | /* headless mode */ |
| 484 | if (nouveau_modeset == 2) { |
| 485 | engine->display.early_init = nouveau_stub_init; |
| 486 | engine->display.late_takedown = nouveau_stub_takedown; |
| 487 | engine->display.create = nouveau_stub_init; |
| 488 | engine->display.init = nouveau_stub_init; |
| 489 | engine->display.destroy = nouveau_stub_takedown; |
| 490 | } |
| 491 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 492 | return 0; |
| 493 | } |
| 494 | |
| 495 | static unsigned int |
| 496 | nouveau_vga_set_decode(void *priv, bool state) |
| 497 | { |
Marcin KoĆcielnicki | 9967b94 | 2010-02-08 00:20:17 +0000 | [diff] [blame] | 498 | struct drm_device *dev = priv; |
| 499 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 500 | |
| 501 | if (dev_priv->chipset >= 0x40) |
| 502 | nv_wr32(dev, 0x88054, state); |
| 503 | else |
| 504 | nv_wr32(dev, 0x1854, state); |
| 505 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 506 | if (state) |
| 507 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
| 508 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 509 | else |
| 510 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 511 | } |
| 512 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 513 | static void nouveau_switcheroo_set_state(struct pci_dev *pdev, |
| 514 | enum vga_switcheroo_state state) |
| 515 | { |
Dave Airlie | fbf8176 | 2010-06-01 09:09:06 +1000 | [diff] [blame] | 516 | struct drm_device *dev = pci_get_drvdata(pdev); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 517 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; |
| 518 | if (state == VGA_SWITCHEROO_ON) { |
| 519 | printk(KERN_ERR "VGA switcheroo: switched nouveau on\n"); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 520 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 521 | nouveau_pci_resume(pdev); |
Dave Airlie | fbf8176 | 2010-06-01 09:09:06 +1000 | [diff] [blame] | 522 | drm_kms_helper_poll_enable(dev); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 523 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 524 | } else { |
| 525 | printk(KERN_ERR "VGA switcheroo: switched nouveau off\n"); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 526 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
Dave Airlie | fbf8176 | 2010-06-01 09:09:06 +1000 | [diff] [blame] | 527 | drm_kms_helper_poll_disable(dev); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 528 | nouveau_pci_suspend(pdev, pmm); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 529 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 530 | } |
| 531 | } |
| 532 | |
Dave Airlie | 8d608aa | 2010-12-07 08:57:57 +1000 | [diff] [blame] | 533 | static void nouveau_switcheroo_reprobe(struct pci_dev *pdev) |
| 534 | { |
| 535 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 536 | nouveau_fbcon_output_poll_changed(dev); |
| 537 | } |
| 538 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 539 | static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev) |
| 540 | { |
| 541 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 542 | bool can_switch; |
| 543 | |
| 544 | spin_lock(&dev->count_lock); |
| 545 | can_switch = (dev->open_count == 0); |
| 546 | spin_unlock(&dev->count_lock); |
| 547 | return can_switch; |
| 548 | } |
| 549 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 550 | int |
| 551 | nouveau_card_init(struct drm_device *dev) |
| 552 | { |
| 553 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 554 | struct nouveau_engine *engine; |
Ben Skeggs | eea55c8 | 2011-04-18 08:57:51 +1000 | [diff] [blame] | 555 | int ret, e = 0; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 556 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 557 | vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 558 | vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state, |
Dave Airlie | 8d608aa | 2010-12-07 08:57:57 +1000 | [diff] [blame] | 559 | nouveau_switcheroo_reprobe, |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 560 | nouveau_switcheroo_can_switch); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 561 | |
| 562 | /* Initialise internal driver API hooks */ |
| 563 | ret = nouveau_init_engine_ptrs(dev); |
| 564 | if (ret) |
Marcin KoĆcielnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 565 | goto out; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 566 | engine = &dev_priv->engine; |
Ben Skeggs | cff5c13 | 2010-10-06 16:16:59 +1000 | [diff] [blame] | 567 | spin_lock_init(&dev_priv->channels.lock); |
Francisco Jerez | a5cf68b | 2010-10-24 16:14:41 +0200 | [diff] [blame] | 568 | spin_lock_init(&dev_priv->tile.lock); |
Maarten Maathuis | ff9e527 | 2010-02-01 20:58:27 +0100 | [diff] [blame] | 569 | spin_lock_init(&dev_priv->context_switch_lock); |
Ben Skeggs | 04eb34a | 2011-04-06 13:28:35 +1000 | [diff] [blame] | 570 | spin_lock_init(&dev_priv->vm_lock); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 571 | |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 572 | /* Make the CRTCs and I2C buses accessible */ |
| 573 | ret = engine->display.early_init(dev); |
| 574 | if (ret) |
| 575 | goto out; |
| 576 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 577 | /* Parse BIOS tables / Run init tables if card not POSTed */ |
Ben Skeggs | cd0b072 | 2010-06-01 15:56:22 +1000 | [diff] [blame] | 578 | ret = nouveau_bios_init(dev); |
| 579 | if (ret) |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 580 | goto out_display_early; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 581 | |
Ben Skeggs | 330c598 | 2010-09-16 15:39:49 +1000 | [diff] [blame] | 582 | nouveau_pm_init(dev); |
| 583 | |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 584 | ret = engine->vram.init(dev); |
Ben Skeggs | a76fb4e | 2010-03-18 09:45:20 +1000 | [diff] [blame] | 585 | if (ret) |
| 586 | goto out_bios; |
| 587 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 588 | ret = nouveau_gpuobj_init(dev); |
| 589 | if (ret) |
Ben Skeggs | fbd2895 | 2010-09-01 15:24:34 +1000 | [diff] [blame] | 590 | goto out_vram; |
| 591 | |
| 592 | ret = engine->instmem.init(dev); |
| 593 | if (ret) |
| 594 | goto out_gpuobj; |
| 595 | |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 596 | ret = nouveau_mem_vram_init(dev); |
Ben Skeggs | fbd2895 | 2010-09-01 15:24:34 +1000 | [diff] [blame] | 597 | if (ret) |
| 598 | goto out_instmem; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 599 | |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 600 | ret = nouveau_mem_gart_init(dev); |
| 601 | if (ret) |
| 602 | goto out_ttmvram; |
| 603 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 604 | /* PMC */ |
| 605 | ret = engine->mc.init(dev); |
| 606 | if (ret) |
Ben Skeggs | fbd2895 | 2010-09-01 15:24:34 +1000 | [diff] [blame] | 607 | goto out_gart; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 608 | |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 609 | /* PGPIO */ |
| 610 | ret = engine->gpio.init(dev); |
| 611 | if (ret) |
| 612 | goto out_mc; |
| 613 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 614 | /* PTIMER */ |
| 615 | ret = engine->timer.init(dev); |
| 616 | if (ret) |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 617 | goto out_gpio; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 618 | |
| 619 | /* PFB */ |
| 620 | ret = engine->fb.init(dev); |
| 621 | if (ret) |
Marcin KoĆcielnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 622 | goto out_timer; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 623 | |
Ben Skeggs | aba99a8 | 2011-05-25 14:48:50 +1000 | [diff] [blame] | 624 | if (!dev_priv->noaccel) { |
Ben Skeggs | 18b54c4 | 2011-05-25 15:22:33 +1000 | [diff] [blame] | 625 | switch (dev_priv->card_type) { |
| 626 | case NV_04: |
| 627 | nv04_graph_create(dev); |
| 628 | break; |
| 629 | case NV_10: |
| 630 | nv10_graph_create(dev); |
| 631 | break; |
| 632 | case NV_20: |
| 633 | case NV_30: |
| 634 | nv20_graph_create(dev); |
| 635 | break; |
| 636 | case NV_40: |
| 637 | nv40_graph_create(dev); |
| 638 | break; |
| 639 | case NV_50: |
| 640 | nv50_graph_create(dev); |
| 641 | break; |
| 642 | case NV_C0: |
| 643 | nvc0_graph_create(dev); |
| 644 | break; |
| 645 | default: |
Ben Skeggs | 7ff5441 | 2011-03-18 10:25:59 +1000 | [diff] [blame] | 646 | break; |
| 647 | } |
Ben Skeggs | 7ff5441 | 2011-03-18 10:25:59 +1000 | [diff] [blame] | 648 | |
Ben Skeggs | 18b54c4 | 2011-05-25 15:22:33 +1000 | [diff] [blame] | 649 | switch (dev_priv->chipset) { |
| 650 | case 0x84: |
| 651 | case 0x86: |
| 652 | case 0x92: |
| 653 | case 0x94: |
| 654 | case 0x96: |
| 655 | case 0xa0: |
| 656 | nv84_crypt_create(dev); |
| 657 | break; |
| 658 | } |
Ben Skeggs | a02ccc7 | 2011-04-04 16:08:24 +1000 | [diff] [blame] | 659 | |
Ben Skeggs | 18b54c4 | 2011-05-25 15:22:33 +1000 | [diff] [blame] | 660 | switch (dev_priv->card_type) { |
| 661 | case NV_50: |
| 662 | switch (dev_priv->chipset) { |
| 663 | case 0xa3: |
| 664 | case 0xa5: |
| 665 | case 0xa8: |
| 666 | case 0xaf: |
| 667 | nva3_copy_create(dev); |
| 668 | break; |
| 669 | } |
| 670 | break; |
| 671 | case NV_C0: |
| 672 | nvc0_copy_create(dev, 0); |
| 673 | nvc0_copy_create(dev, 1); |
| 674 | break; |
| 675 | default: |
| 676 | break; |
| 677 | } |
| 678 | |
Ben Skeggs | 52d0733 | 2011-06-23 16:44:05 +1000 | [diff] [blame] | 679 | if (dev_priv->card_type == NV_40 || |
| 680 | dev_priv->chipset == 0x31 || |
| 681 | dev_priv->chipset == 0x34 || |
| 682 | dev_priv->chipset == 0x36) |
Ben Skeggs | 323dcac | 2011-06-23 16:21:21 +1000 | [diff] [blame] | 683 | nv31_mpeg_create(dev); |
Ben Skeggs | 18b54c4 | 2011-05-25 15:22:33 +1000 | [diff] [blame] | 684 | else |
| 685 | if (dev_priv->card_type == NV_50 && |
| 686 | (dev_priv->chipset < 0x98 || dev_priv->chipset == 0xa0)) |
| 687 | nv50_mpeg_create(dev); |
| 688 | |
Ben Skeggs | 6dfdd7a | 2011-03-31 15:40:43 +1000 | [diff] [blame] | 689 | for (e = 0; e < NVOBJ_ENGINE_NR; e++) { |
| 690 | if (dev_priv->eng[e]) { |
| 691 | ret = dev_priv->eng[e]->init(dev, e); |
| 692 | if (ret) |
| 693 | goto out_engine; |
| 694 | } |
| 695 | } |
| 696 | |
Marcin KoĆcielnicki | a32ed69 | 2010-01-26 14:00:42 +0000 | [diff] [blame] | 697 | /* PFIFO */ |
| 698 | ret = engine->fifo.init(dev); |
| 699 | if (ret) |
Ben Skeggs | a82dd49 | 2011-04-01 13:56:05 +1000 | [diff] [blame] | 700 | goto out_engine; |
Marcin KoĆcielnicki | a32ed69 | 2010-01-26 14:00:42 +0000 | [diff] [blame] | 701 | } |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 702 | |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 703 | ret = nouveau_irq_init(dev); |
| 704 | if (ret) |
| 705 | goto out_fifo; |
| 706 | |
Ben Skeggs | 048a885 | 2011-07-04 10:47:19 +1000 | [diff] [blame] | 707 | /* initialise general modesetting */ |
| 708 | drm_mode_config_init(dev); |
| 709 | drm_mode_create_scaling_mode_property(dev); |
| 710 | drm_mode_create_dithering_property(dev); |
| 711 | dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs; |
| 712 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 1); |
| 713 | dev->mode_config.min_width = 0; |
| 714 | dev->mode_config.min_height = 0; |
| 715 | if (dev_priv->card_type < NV_10) { |
| 716 | dev->mode_config.max_width = 2048; |
| 717 | dev->mode_config.max_height = 2048; |
| 718 | } else |
| 719 | if (dev_priv->card_type < NV_50) { |
| 720 | dev->mode_config.max_width = 4096; |
| 721 | dev->mode_config.max_height = 4096; |
| 722 | } else { |
| 723 | dev->mode_config.max_width = 8192; |
| 724 | dev->mode_config.max_height = 8192; |
| 725 | } |
| 726 | |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 727 | ret = engine->display.create(dev); |
Ben Skeggs | e88efe0 | 2010-07-09 10:56:08 +1000 | [diff] [blame] | 728 | if (ret) |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 729 | goto out_irq; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 730 | |
Ben Skeggs | a82dd49 | 2011-04-01 13:56:05 +1000 | [diff] [blame] | 731 | if (dev_priv->eng[NVOBJ_ENGINE_GR]) { |
Francisco Jerez | 0c6c1c2 | 2010-09-22 00:58:54 +0200 | [diff] [blame] | 732 | ret = nouveau_fence_init(dev); |
Ben Skeggs | 0735f62 | 2009-12-16 14:28:55 +1000 | [diff] [blame] | 733 | if (ret) |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 734 | goto out_disp; |
Francisco Jerez | 0c6c1c2 | 2010-09-22 00:58:54 +0200 | [diff] [blame] | 735 | |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 736 | ret = nouveau_channel_alloc(dev, &dev_priv->channel, NULL, |
| 737 | NvDmaFB, NvDmaTT); |
Francisco Jerez | 0c6c1c2 | 2010-09-22 00:58:54 +0200 | [diff] [blame] | 738 | if (ret) |
| 739 | goto out_fence; |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 740 | |
| 741 | mutex_unlock(&dev_priv->channel->mutex); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 742 | } |
| 743 | |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 744 | if (dev->mode_config.num_crtc) { |
| 745 | ret = drm_vblank_init(dev, dev->mode_config.num_crtc); |
| 746 | if (ret) |
| 747 | goto out_chan; |
| 748 | |
| 749 | nouveau_fbcon_init(dev); |
| 750 | drm_kms_helper_poll_init(dev); |
| 751 | } |
| 752 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 753 | return 0; |
Marcin KoĆcielnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 754 | |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 755 | out_chan: |
| 756 | nouveau_channel_put_unlocked(&dev_priv->channel); |
Francisco Jerez | 0c6c1c2 | 2010-09-22 00:58:54 +0200 | [diff] [blame] | 757 | out_fence: |
| 758 | nouveau_fence_fini(dev); |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 759 | out_disp: |
| 760 | engine->display.destroy(dev); |
Marcin KoĆcielnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 761 | out_irq: |
Ben Skeggs | 35fa2f2 | 2010-10-21 14:07:03 +1000 | [diff] [blame] | 762 | nouveau_irq_fini(dev); |
Marcin KoĆcielnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 763 | out_fifo: |
Ben Skeggs | aba99a8 | 2011-05-25 14:48:50 +1000 | [diff] [blame] | 764 | if (!dev_priv->noaccel) |
Marcin KoĆcielnicki | a32ed69 | 2010-01-26 14:00:42 +0000 | [diff] [blame] | 765 | engine->fifo.takedown(dev); |
Ben Skeggs | 6dfdd7a | 2011-03-31 15:40:43 +1000 | [diff] [blame] | 766 | out_engine: |
Ben Skeggs | aba99a8 | 2011-05-25 14:48:50 +1000 | [diff] [blame] | 767 | if (!dev_priv->noaccel) { |
Ben Skeggs | 6dfdd7a | 2011-03-31 15:40:43 +1000 | [diff] [blame] | 768 | for (e = e - 1; e >= 0; e--) { |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 769 | if (!dev_priv->eng[e]) |
| 770 | continue; |
Ben Skeggs | 6c320fe | 2011-07-20 11:22:33 +1000 | [diff] [blame] | 771 | dev_priv->eng[e]->fini(dev, e, false); |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 772 | dev_priv->eng[e]->destroy(dev,e ); |
Ben Skeggs | 6dfdd7a | 2011-03-31 15:40:43 +1000 | [diff] [blame] | 773 | } |
| 774 | } |
| 775 | |
Marcin KoĆcielnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 776 | engine->fb.takedown(dev); |
| 777 | out_timer: |
| 778 | engine->timer.takedown(dev); |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 779 | out_gpio: |
| 780 | engine->gpio.takedown(dev); |
Marcin KoĆcielnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 781 | out_mc: |
| 782 | engine->mc.takedown(dev); |
Ben Skeggs | fbd2895 | 2010-09-01 15:24:34 +1000 | [diff] [blame] | 783 | out_gart: |
| 784 | nouveau_mem_gart_fini(dev); |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 785 | out_ttmvram: |
| 786 | nouveau_mem_vram_fini(dev); |
Marcin KoĆcielnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 787 | out_instmem: |
| 788 | engine->instmem.takedown(dev); |
Ben Skeggs | fbd2895 | 2010-09-01 15:24:34 +1000 | [diff] [blame] | 789 | out_gpuobj: |
| 790 | nouveau_gpuobj_takedown(dev); |
| 791 | out_vram: |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 792 | engine->vram.takedown(dev); |
Marcin KoĆcielnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 793 | out_bios: |
Ben Skeggs | 330c598 | 2010-09-16 15:39:49 +1000 | [diff] [blame] | 794 | nouveau_pm_fini(dev); |
Marcin KoĆcielnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 795 | nouveau_bios_takedown(dev); |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 796 | out_display_early: |
| 797 | engine->display.late_takedown(dev); |
Marcin KoĆcielnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 798 | out: |
| 799 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
| 800 | return ret; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 801 | } |
| 802 | |
| 803 | static void nouveau_card_takedown(struct drm_device *dev) |
| 804 | { |
| 805 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 806 | struct nouveau_engine *engine = &dev_priv->engine; |
Ben Skeggs | 6dfdd7a | 2011-03-31 15:40:43 +1000 | [diff] [blame] | 807 | int e; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 808 | |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 809 | if (dev->mode_config.num_crtc) { |
| 810 | drm_kms_helper_poll_fini(dev); |
| 811 | nouveau_fbcon_fini(dev); |
| 812 | drm_vblank_cleanup(dev); |
| 813 | } |
Ben Skeggs | 06b75e3 | 2011-06-08 18:29:12 +1000 | [diff] [blame] | 814 | |
Ben Skeggs | a82dd49 | 2011-04-01 13:56:05 +1000 | [diff] [blame] | 815 | if (dev_priv->channel) { |
Francisco Jerez | 36c952e | 2010-10-18 03:01:34 +0200 | [diff] [blame] | 816 | nouveau_channel_put_unlocked(&dev_priv->channel); |
Ben Skeggs | 06b75e3 | 2011-06-08 18:29:12 +1000 | [diff] [blame] | 817 | nouveau_fence_fini(dev); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 818 | } |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 819 | |
Ben Skeggs | 06b75e3 | 2011-06-08 18:29:12 +1000 | [diff] [blame] | 820 | engine->display.destroy(dev); |
Ben Skeggs | 048a885 | 2011-07-04 10:47:19 +1000 | [diff] [blame] | 821 | drm_mode_config_cleanup(dev); |
Ben Skeggs | 06b75e3 | 2011-06-08 18:29:12 +1000 | [diff] [blame] | 822 | |
Ben Skeggs | aba99a8 | 2011-05-25 14:48:50 +1000 | [diff] [blame] | 823 | if (!dev_priv->noaccel) { |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 824 | engine->fifo.takedown(dev); |
Ben Skeggs | 6dfdd7a | 2011-03-31 15:40:43 +1000 | [diff] [blame] | 825 | for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) { |
| 826 | if (dev_priv->eng[e]) { |
Ben Skeggs | 6c320fe | 2011-07-20 11:22:33 +1000 | [diff] [blame] | 827 | dev_priv->eng[e]->fini(dev, e, false); |
Ben Skeggs | 6dfdd7a | 2011-03-31 15:40:43 +1000 | [diff] [blame] | 828 | dev_priv->eng[e]->destroy(dev,e ); |
| 829 | } |
| 830 | } |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 831 | } |
| 832 | engine->fb.takedown(dev); |
| 833 | engine->timer.takedown(dev); |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 834 | engine->gpio.takedown(dev); |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 835 | engine->mc.takedown(dev); |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 836 | engine->display.late_takedown(dev); |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 837 | |
Jimmy Rentz | 9766610 | 2011-04-17 16:15:09 -0400 | [diff] [blame] | 838 | if (dev_priv->vga_ram) { |
| 839 | nouveau_bo_unpin(dev_priv->vga_ram); |
| 840 | nouveau_bo_ref(NULL, &dev_priv->vga_ram); |
| 841 | } |
| 842 | |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 843 | mutex_lock(&dev->struct_mutex); |
| 844 | ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM); |
| 845 | ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT); |
| 846 | mutex_unlock(&dev->struct_mutex); |
Ben Skeggs | fbd2895 | 2010-09-01 15:24:34 +1000 | [diff] [blame] | 847 | nouveau_mem_gart_fini(dev); |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 848 | nouveau_mem_vram_fini(dev); |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 849 | |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 850 | engine->instmem.takedown(dev); |
Ben Skeggs | fbd2895 | 2010-09-01 15:24:34 +1000 | [diff] [blame] | 851 | nouveau_gpuobj_takedown(dev); |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 852 | engine->vram.takedown(dev); |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 853 | |
Ben Skeggs | 35fa2f2 | 2010-10-21 14:07:03 +1000 | [diff] [blame] | 854 | nouveau_irq_fini(dev); |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 855 | |
Ben Skeggs | 330c598 | 2010-09-16 15:39:49 +1000 | [diff] [blame] | 856 | nouveau_pm_fini(dev); |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 857 | nouveau_bios_takedown(dev); |
| 858 | |
| 859 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 860 | } |
| 861 | |
Ben Skeggs | 3f0a68d | 2011-05-31 11:11:28 +1000 | [diff] [blame] | 862 | int |
| 863 | nouveau_open(struct drm_device *dev, struct drm_file *file_priv) |
| 864 | { |
Ben Skeggs | fe32b16 | 2011-06-03 10:07:08 +1000 | [diff] [blame] | 865 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
Ben Skeggs | 3f0a68d | 2011-05-31 11:11:28 +1000 | [diff] [blame] | 866 | struct nouveau_fpriv *fpriv; |
Ben Skeggs | e41f26e | 2011-06-07 15:35:37 +1000 | [diff] [blame] | 867 | int ret; |
Ben Skeggs | 3f0a68d | 2011-05-31 11:11:28 +1000 | [diff] [blame] | 868 | |
| 869 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); |
| 870 | if (unlikely(!fpriv)) |
| 871 | return -ENOMEM; |
| 872 | |
| 873 | spin_lock_init(&fpriv->lock); |
Ben Skeggs | e8a863c | 2011-06-01 19:18:48 +1000 | [diff] [blame] | 874 | INIT_LIST_HEAD(&fpriv->channels); |
| 875 | |
Ben Skeggs | e41f26e | 2011-06-07 15:35:37 +1000 | [diff] [blame] | 876 | if (dev_priv->card_type == NV_50) { |
| 877 | ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL, |
| 878 | &fpriv->vm); |
| 879 | if (ret) { |
| 880 | kfree(fpriv); |
| 881 | return ret; |
| 882 | } |
| 883 | } else |
| 884 | if (dev_priv->card_type >= NV_C0) { |
Ben Skeggs | 5de8037 | 2011-06-08 18:17:41 +1000 | [diff] [blame] | 885 | ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL, |
| 886 | &fpriv->vm); |
| 887 | if (ret) { |
| 888 | kfree(fpriv); |
| 889 | return ret; |
| 890 | } |
Ben Skeggs | e41f26e | 2011-06-07 15:35:37 +1000 | [diff] [blame] | 891 | } |
Ben Skeggs | fe32b16 | 2011-06-03 10:07:08 +1000 | [diff] [blame] | 892 | |
Ben Skeggs | 3f0a68d | 2011-05-31 11:11:28 +1000 | [diff] [blame] | 893 | file_priv->driver_priv = fpriv; |
| 894 | return 0; |
| 895 | } |
| 896 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 897 | /* here a client dies, release the stuff that was allocated for its |
| 898 | * file_priv */ |
| 899 | void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv) |
| 900 | { |
| 901 | nouveau_channel_cleanup(dev, file_priv); |
| 902 | } |
| 903 | |
Ben Skeggs | 3f0a68d | 2011-05-31 11:11:28 +1000 | [diff] [blame] | 904 | void |
| 905 | nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv) |
| 906 | { |
| 907 | struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv); |
Ben Skeggs | fe32b16 | 2011-06-03 10:07:08 +1000 | [diff] [blame] | 908 | nouveau_vm_ref(NULL, &fpriv->vm, NULL); |
Ben Skeggs | 3f0a68d | 2011-05-31 11:11:28 +1000 | [diff] [blame] | 909 | kfree(fpriv); |
| 910 | } |
| 911 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 912 | /* first module load, setup the mmio/fb mapping */ |
| 913 | /* KMS: we need mmio at load time, not when the first drm client opens. */ |
| 914 | int nouveau_firstopen(struct drm_device *dev) |
| 915 | { |
| 916 | return 0; |
| 917 | } |
| 918 | |
| 919 | /* if we have an OF card, copy vbios to RAMIN */ |
| 920 | static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev) |
| 921 | { |
| 922 | #if defined(__powerpc__) |
| 923 | int size, i; |
| 924 | const uint32_t *bios; |
| 925 | struct device_node *dn = pci_device_to_OF_node(dev->pdev); |
| 926 | if (!dn) { |
| 927 | NV_INFO(dev, "Unable to get the OF node\n"); |
| 928 | return; |
| 929 | } |
| 930 | |
| 931 | bios = of_get_property(dn, "NVDA,BMP", &size); |
| 932 | if (bios) { |
| 933 | for (i = 0; i < size; i += 4) |
| 934 | nv_wi32(dev, i, bios[i/4]); |
| 935 | NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size); |
| 936 | } else { |
| 937 | NV_INFO(dev, "Unable to get the OF bios\n"); |
| 938 | } |
| 939 | #endif |
| 940 | } |
| 941 | |
Marcin Slusarz | 06415c5 | 2010-05-16 17:29:56 +0200 | [diff] [blame] | 942 | static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev) |
| 943 | { |
| 944 | struct pci_dev *pdev = dev->pdev; |
| 945 | struct apertures_struct *aper = alloc_apertures(3); |
| 946 | if (!aper) |
| 947 | return NULL; |
| 948 | |
| 949 | aper->ranges[0].base = pci_resource_start(pdev, 1); |
| 950 | aper->ranges[0].size = pci_resource_len(pdev, 1); |
| 951 | aper->count = 1; |
| 952 | |
| 953 | if (pci_resource_len(pdev, 2)) { |
| 954 | aper->ranges[aper->count].base = pci_resource_start(pdev, 2); |
| 955 | aper->ranges[aper->count].size = pci_resource_len(pdev, 2); |
| 956 | aper->count++; |
| 957 | } |
| 958 | |
| 959 | if (pci_resource_len(pdev, 3)) { |
| 960 | aper->ranges[aper->count].base = pci_resource_start(pdev, 3); |
| 961 | aper->ranges[aper->count].size = pci_resource_len(pdev, 3); |
| 962 | aper->count++; |
| 963 | } |
| 964 | |
| 965 | return aper; |
| 966 | } |
| 967 | |
| 968 | static int nouveau_remove_conflicting_drivers(struct drm_device *dev) |
| 969 | { |
| 970 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
Marcin Slusarz | 3b9676e | 2010-05-16 17:33:09 +0200 | [diff] [blame] | 971 | bool primary = false; |
Marcin Slusarz | 06415c5 | 2010-05-16 17:29:56 +0200 | [diff] [blame] | 972 | dev_priv->apertures = nouveau_get_apertures(dev); |
| 973 | if (!dev_priv->apertures) |
| 974 | return -ENOMEM; |
| 975 | |
Marcin Slusarz | 3b9676e | 2010-05-16 17:33:09 +0200 | [diff] [blame] | 976 | #ifdef CONFIG_X86 |
| 977 | primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; |
| 978 | #endif |
Emil Velikov | f212949 | 2011-03-19 23:31:52 +0000 | [diff] [blame] | 979 | |
Marcin Slusarz | 3b9676e | 2010-05-16 17:33:09 +0200 | [diff] [blame] | 980 | remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary); |
Marcin Slusarz | 06415c5 | 2010-05-16 17:29:56 +0200 | [diff] [blame] | 981 | return 0; |
| 982 | } |
| 983 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 984 | int nouveau_load(struct drm_device *dev, unsigned long flags) |
| 985 | { |
| 986 | struct drm_nouveau_private *dev_priv; |
| 987 | uint32_t reg0; |
| 988 | resource_size_t mmio_start_offs; |
Ben Skeggs | cd0b072 | 2010-06-01 15:56:22 +1000 | [diff] [blame] | 989 | int ret; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 990 | |
| 991 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
Dan Carpenter | a0d069e | 2010-07-30 17:04:32 +0200 | [diff] [blame] | 992 | if (!dev_priv) { |
| 993 | ret = -ENOMEM; |
| 994 | goto err_out; |
| 995 | } |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 996 | dev->dev_private = dev_priv; |
| 997 | dev_priv->dev = dev; |
| 998 | |
| 999 | dev_priv->flags = flags & NOUVEAU_FLAGS; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1000 | |
| 1001 | NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n", |
| 1002 | dev->pci_vendor, dev->pci_device, dev->pdev->class); |
| 1003 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1004 | /* resource 0 is mmio regs */ |
| 1005 | /* resource 1 is linear FB */ |
| 1006 | /* resource 2 is RAMIN (mmio regs + 0x1000000) */ |
| 1007 | /* resource 6 is bios */ |
| 1008 | |
| 1009 | /* map the mmio regs */ |
| 1010 | mmio_start_offs = pci_resource_start(dev->pdev, 0); |
| 1011 | dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000); |
| 1012 | if (!dev_priv->mmio) { |
| 1013 | NV_ERROR(dev, "Unable to initialize the mmio mapping. " |
| 1014 | "Please report your setup to " DRIVER_EMAIL "\n"); |
Dan Carpenter | a0d069e | 2010-07-30 17:04:32 +0200 | [diff] [blame] | 1015 | ret = -EINVAL; |
Tejun Heo | d82f8e6 | 2011-01-26 17:49:18 +0100 | [diff] [blame] | 1016 | goto err_priv; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1017 | } |
| 1018 | NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", |
| 1019 | (unsigned long long)mmio_start_offs); |
| 1020 | |
| 1021 | #ifdef __BIG_ENDIAN |
| 1022 | /* Put the card in BE mode if it's not */ |
Ben Skeggs | 0897554 | 2011-06-14 10:16:17 +1000 | [diff] [blame] | 1023 | if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001) |
| 1024 | nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1025 | |
| 1026 | DRM_MEMORYBARRIER(); |
| 1027 | #endif |
| 1028 | |
| 1029 | /* Time to determine the card architecture */ |
| 1030 | reg0 = nv_rd32(dev, NV03_PMC_BOOT_0); |
Roy Spliet | 50066f8 | 2011-03-27 18:13:11 +0200 | [diff] [blame] | 1031 | dev_priv->stepping = 0; /* XXX: add stepping for pre-NV10? */ |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1032 | |
| 1033 | /* We're dealing with >=NV10 */ |
| 1034 | if ((reg0 & 0x0f000000) > 0) { |
| 1035 | /* Bit 27-20 contain the architecture in hex */ |
| 1036 | dev_priv->chipset = (reg0 & 0xff00000) >> 20; |
Roy Spliet | 50066f8 | 2011-03-27 18:13:11 +0200 | [diff] [blame] | 1037 | dev_priv->stepping = (reg0 & 0xff); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1038 | /* NV04 or NV05 */ |
| 1039 | } else if ((reg0 & 0xff00fff0) == 0x20004000) { |
Ben Skeggs | 1dee7a9 | 2010-01-07 13:47:57 +1000 | [diff] [blame] | 1040 | if (reg0 & 0x00f00000) |
| 1041 | dev_priv->chipset = 0x05; |
| 1042 | else |
| 1043 | dev_priv->chipset = 0x04; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1044 | } else |
| 1045 | dev_priv->chipset = 0xff; |
| 1046 | |
| 1047 | switch (dev_priv->chipset & 0xf0) { |
| 1048 | case 0x00: |
| 1049 | case 0x10: |
| 1050 | case 0x20: |
| 1051 | case 0x30: |
| 1052 | dev_priv->card_type = dev_priv->chipset & 0xf0; |
| 1053 | break; |
| 1054 | case 0x40: |
| 1055 | case 0x60: |
| 1056 | dev_priv->card_type = NV_40; |
| 1057 | break; |
| 1058 | case 0x50: |
| 1059 | case 0x80: |
| 1060 | case 0x90: |
| 1061 | case 0xa0: |
| 1062 | dev_priv->card_type = NV_50; |
| 1063 | break; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 1064 | case 0xc0: |
| 1065 | dev_priv->card_type = NV_C0; |
| 1066 | break; |
Ben Skeggs | d9f61c2 | 2011-07-04 13:25:17 +1000 | [diff] [blame] | 1067 | case 0xd0: |
| 1068 | dev_priv->card_type = NV_D0; |
| 1069 | break; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1070 | default: |
| 1071 | NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0); |
Dan Carpenter | a0d069e | 2010-07-30 17:04:32 +0200 | [diff] [blame] | 1072 | ret = -EINVAL; |
| 1073 | goto err_mmio; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1074 | } |
| 1075 | |
| 1076 | NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n", |
| 1077 | dev_priv->card_type, reg0); |
| 1078 | |
Ben Skeggs | aba99a8 | 2011-05-25 14:48:50 +1000 | [diff] [blame] | 1079 | /* Determine whether we'll attempt acceleration or not, some |
| 1080 | * cards are disabled by default here due to them being known |
| 1081 | * non-functional, or never been tested due to lack of hw. |
| 1082 | */ |
| 1083 | dev_priv->noaccel = !!nouveau_noaccel; |
| 1084 | if (nouveau_noaccel == -1) { |
| 1085 | switch (dev_priv->chipset) { |
| 1086 | case 0xc1: /* known broken */ |
| 1087 | case 0xc8: /* never tested */ |
Ben Skeggs | ad830d2 | 2011-05-27 16:18:10 +1000 | [diff] [blame] | 1088 | NV_INFO(dev, "acceleration disabled by default, pass " |
| 1089 | "noaccel=0 to force enable\n"); |
Ben Skeggs | aba99a8 | 2011-05-25 14:48:50 +1000 | [diff] [blame] | 1090 | dev_priv->noaccel = true; |
| 1091 | break; |
| 1092 | default: |
| 1093 | dev_priv->noaccel = false; |
| 1094 | break; |
| 1095 | } |
| 1096 | } |
| 1097 | |
Ben Skeggs | cd0b072 | 2010-06-01 15:56:22 +1000 | [diff] [blame] | 1098 | ret = nouveau_remove_conflicting_drivers(dev); |
| 1099 | if (ret) |
Dan Carpenter | a0d069e | 2010-07-30 17:04:32 +0200 | [diff] [blame] | 1100 | goto err_mmio; |
Marcin Slusarz | 06415c5 | 2010-05-16 17:29:56 +0200 | [diff] [blame] | 1101 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1102 | /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */ |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1103 | if (dev_priv->card_type >= NV_40) { |
| 1104 | int ramin_bar = 2; |
| 1105 | if (pci_resource_len(dev->pdev, ramin_bar) == 0) |
| 1106 | ramin_bar = 3; |
| 1107 | |
| 1108 | dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar); |
Ben Skeggs | 6d69630 | 2010-06-02 10:16:24 +1000 | [diff] [blame] | 1109 | dev_priv->ramin = |
| 1110 | ioremap(pci_resource_start(dev->pdev, ramin_bar), |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1111 | dev_priv->ramin_size); |
| 1112 | if (!dev_priv->ramin) { |
Ben Skeggs | 6d69630 | 2010-06-02 10:16:24 +1000 | [diff] [blame] | 1113 | NV_ERROR(dev, "Failed to PRAMIN BAR"); |
Dan Carpenter | a0d069e | 2010-07-30 17:04:32 +0200 | [diff] [blame] | 1114 | ret = -ENOMEM; |
| 1115 | goto err_mmio; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1116 | } |
Ben Skeggs | 6d69630 | 2010-06-02 10:16:24 +1000 | [diff] [blame] | 1117 | } else { |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1118 | dev_priv->ramin_size = 1 * 1024 * 1024; |
| 1119 | dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN, |
Ben Skeggs | 6d69630 | 2010-06-02 10:16:24 +1000 | [diff] [blame] | 1120 | dev_priv->ramin_size); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1121 | if (!dev_priv->ramin) { |
| 1122 | NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n"); |
Dan Carpenter | a0d069e | 2010-07-30 17:04:32 +0200 | [diff] [blame] | 1123 | ret = -ENOMEM; |
| 1124 | goto err_mmio; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1125 | } |
| 1126 | } |
| 1127 | |
| 1128 | nouveau_OF_copy_vbios_to_ramin(dev); |
| 1129 | |
| 1130 | /* Special flags */ |
| 1131 | if (dev->pci_device == 0x01a0) |
| 1132 | dev_priv->flags |= NV_NFORCE; |
| 1133 | else if (dev->pci_device == 0x01f0) |
| 1134 | dev_priv->flags |= NV_NFORCE2; |
| 1135 | |
| 1136 | /* For kernel modesetting, init card now and bring up fbcon */ |
Ben Skeggs | cd0b072 | 2010-06-01 15:56:22 +1000 | [diff] [blame] | 1137 | ret = nouveau_card_init(dev); |
| 1138 | if (ret) |
Dan Carpenter | a0d069e | 2010-07-30 17:04:32 +0200 | [diff] [blame] | 1139 | goto err_ramin; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1140 | |
| 1141 | return 0; |
Dan Carpenter | a0d069e | 2010-07-30 17:04:32 +0200 | [diff] [blame] | 1142 | |
| 1143 | err_ramin: |
| 1144 | iounmap(dev_priv->ramin); |
| 1145 | err_mmio: |
| 1146 | iounmap(dev_priv->mmio); |
Dan Carpenter | a0d069e | 2010-07-30 17:04:32 +0200 | [diff] [blame] | 1147 | err_priv: |
| 1148 | kfree(dev_priv); |
| 1149 | dev->dev_private = NULL; |
| 1150 | err_out: |
| 1151 | return ret; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1152 | } |
| 1153 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1154 | void nouveau_lastclose(struct drm_device *dev) |
| 1155 | { |
Dave Airlie | 5ccb377 | 2010-12-07 13:56:26 +1000 | [diff] [blame] | 1156 | vga_switcheroo_process_delayed_switch(); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1157 | } |
| 1158 | |
| 1159 | int nouveau_unload(struct drm_device *dev) |
| 1160 | { |
| 1161 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 1162 | |
Ben Skeggs | cd0b072 | 2010-06-01 15:56:22 +1000 | [diff] [blame] | 1163 | nouveau_card_takedown(dev); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1164 | |
| 1165 | iounmap(dev_priv->mmio); |
| 1166 | iounmap(dev_priv->ramin); |
| 1167 | |
| 1168 | kfree(dev_priv); |
| 1169 | dev->dev_private = NULL; |
| 1170 | return 0; |
| 1171 | } |
| 1172 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1173 | int nouveau_ioctl_getparam(struct drm_device *dev, void *data, |
| 1174 | struct drm_file *file_priv) |
| 1175 | { |
| 1176 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 1177 | struct drm_nouveau_getparam *getparam = data; |
| 1178 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1179 | switch (getparam->param) { |
| 1180 | case NOUVEAU_GETPARAM_CHIPSET_ID: |
| 1181 | getparam->value = dev_priv->chipset; |
| 1182 | break; |
| 1183 | case NOUVEAU_GETPARAM_PCI_VENDOR: |
| 1184 | getparam->value = dev->pci_vendor; |
| 1185 | break; |
| 1186 | case NOUVEAU_GETPARAM_PCI_DEVICE: |
| 1187 | getparam->value = dev->pci_device; |
| 1188 | break; |
| 1189 | case NOUVEAU_GETPARAM_BUS_TYPE: |
Dave Airlie | 8410ea3 | 2010-12-15 03:16:38 +1000 | [diff] [blame] | 1190 | if (drm_pci_device_is_agp(dev)) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1191 | getparam->value = NV_AGP; |
Jon Mason | 58b6542 | 2011-06-27 16:07:50 +0000 | [diff] [blame] | 1192 | else if (pci_is_pcie(dev->pdev)) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1193 | getparam->value = NV_PCIE; |
| 1194 | else |
| 1195 | getparam->value = NV_PCI; |
| 1196 | break; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1197 | case NOUVEAU_GETPARAM_FB_SIZE: |
| 1198 | getparam->value = dev_priv->fb_available_size; |
| 1199 | break; |
| 1200 | case NOUVEAU_GETPARAM_AGP_SIZE: |
| 1201 | getparam->value = dev_priv->gart_info.aper_size; |
| 1202 | break; |
| 1203 | case NOUVEAU_GETPARAM_VM_VRAM_BASE: |
Ben Skeggs | 6d6c5a1 | 2010-11-16 10:17:53 +1000 | [diff] [blame] | 1204 | getparam->value = 0; /* deprecated */ |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1205 | break; |
Marcin KoĆcielnicki | 7fc74f1 | 2010-05-23 11:36:04 +0000 | [diff] [blame] | 1206 | case NOUVEAU_GETPARAM_PTIMER_TIME: |
| 1207 | getparam->value = dev_priv->engine.timer.read(dev); |
| 1208 | break; |
Francisco Jerez | f13b326 | 2010-10-10 06:01:08 +0200 | [diff] [blame] | 1209 | case NOUVEAU_GETPARAM_HAS_BO_USAGE: |
| 1210 | getparam->value = 1; |
| 1211 | break; |
Francisco Jerez | 332b242 | 2010-10-20 23:35:40 +0200 | [diff] [blame] | 1212 | case NOUVEAU_GETPARAM_HAS_PAGEFLIP: |
Ben Skeggs | bd2f203 | 2011-02-08 15:16:23 +1000 | [diff] [blame] | 1213 | getparam->value = 1; |
Francisco Jerez | 332b242 | 2010-10-20 23:35:40 +0200 | [diff] [blame] | 1214 | break; |
Marcin KoĆcielnicki | 69c9700 | 2010-01-26 18:39:20 +0000 | [diff] [blame] | 1215 | case NOUVEAU_GETPARAM_GRAPH_UNITS: |
| 1216 | /* NV40 and NV50 versions are quite different, but register |
| 1217 | * address is the same. User is supposed to know the card |
| 1218 | * family anyway... */ |
| 1219 | if (dev_priv->chipset >= 0x40) { |
| 1220 | getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS); |
| 1221 | break; |
| 1222 | } |
| 1223 | /* FALLTHRU */ |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1224 | default: |
Francisco Jerez | 1397b42 | 2010-10-12 03:17:43 +0200 | [diff] [blame] | 1225 | NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1226 | return -EINVAL; |
| 1227 | } |
| 1228 | |
| 1229 | return 0; |
| 1230 | } |
| 1231 | |
| 1232 | int |
| 1233 | nouveau_ioctl_setparam(struct drm_device *dev, void *data, |
| 1234 | struct drm_file *file_priv) |
| 1235 | { |
| 1236 | struct drm_nouveau_setparam *setparam = data; |
| 1237 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1238 | switch (setparam->param) { |
| 1239 | default: |
Francisco Jerez | 1397b42 | 2010-10-12 03:17:43 +0200 | [diff] [blame] | 1240 | NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1241 | return -EINVAL; |
| 1242 | } |
| 1243 | |
| 1244 | return 0; |
| 1245 | } |
| 1246 | |
| 1247 | /* Wait until (value(reg) & mask) == val, up until timeout has hit */ |
Ben Skeggs | 12fb952 | 2010-11-19 14:32:56 +1000 | [diff] [blame] | 1248 | bool |
| 1249 | nouveau_wait_eq(struct drm_device *dev, uint64_t timeout, |
| 1250 | uint32_t reg, uint32_t mask, uint32_t val) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1251 | { |
| 1252 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 1253 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; |
| 1254 | uint64_t start = ptimer->read(dev); |
| 1255 | |
| 1256 | do { |
| 1257 | if ((nv_rd32(dev, reg) & mask) == val) |
| 1258 | return true; |
| 1259 | } while (ptimer->read(dev) - start < timeout); |
| 1260 | |
| 1261 | return false; |
| 1262 | } |
| 1263 | |
Ben Skeggs | 12fb952 | 2010-11-19 14:32:56 +1000 | [diff] [blame] | 1264 | /* Wait until (value(reg) & mask) != val, up until timeout has hit */ |
| 1265 | bool |
| 1266 | nouveau_wait_ne(struct drm_device *dev, uint64_t timeout, |
| 1267 | uint32_t reg, uint32_t mask, uint32_t val) |
| 1268 | { |
| 1269 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 1270 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; |
| 1271 | uint64_t start = ptimer->read(dev); |
| 1272 | |
| 1273 | do { |
| 1274 | if ((nv_rd32(dev, reg) & mask) != val) |
| 1275 | return true; |
| 1276 | } while (ptimer->read(dev) - start < timeout); |
| 1277 | |
| 1278 | return false; |
| 1279 | } |
| 1280 | |
Ben Skeggs | 78e2933 | 2011-06-18 16:27:24 +1000 | [diff] [blame] | 1281 | /* Wait until cond(data) == true, up until timeout has hit */ |
| 1282 | bool |
| 1283 | nouveau_wait_cb(struct drm_device *dev, u64 timeout, |
| 1284 | bool (*cond)(void *), void *data) |
| 1285 | { |
| 1286 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 1287 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; |
| 1288 | u64 start = ptimer->read(dev); |
| 1289 | |
| 1290 | do { |
| 1291 | if (cond(data) == true) |
| 1292 | return true; |
| 1293 | } while (ptimer->read(dev) - start < timeout); |
| 1294 | |
| 1295 | return false; |
| 1296 | } |
| 1297 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1298 | /* Waits for PGRAPH to go completely idle */ |
| 1299 | bool nouveau_wait_for_idle(struct drm_device *dev) |
| 1300 | { |
Francisco Jerez | 0541324a | 2010-10-18 16:15:15 +0200 | [diff] [blame] | 1301 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 1302 | uint32_t mask = ~0; |
| 1303 | |
| 1304 | if (dev_priv->card_type == NV_40) |
| 1305 | mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL; |
| 1306 | |
| 1307 | if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) { |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1308 | NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n", |
| 1309 | nv_rd32(dev, NV04_PGRAPH_STATUS)); |
| 1310 | return false; |
| 1311 | } |
| 1312 | |
| 1313 | return true; |
| 1314 | } |
| 1315 | |