| dmitry pervushin | a50808b | 2009-06-04 13:49:37 +0100 | [diff] [blame] | 1 | /* |
| 2 | * stmp378x: PXP register definitions |
| 3 | * |
| 4 | * Copyright (c) 2008 Freescale Semiconductor |
| 5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 20 | */ |
| 21 | #define REGS_PXP_BASE (STMP3XXX_REGS_BASE + 0x2A000) |
| 22 | #define REGS_PXP_PHYS 0x8002A000 |
| 23 | #define REGS_PXP_SIZE 0x2000 |
| 24 | |
| 25 | #define HW_PXP_CTRL 0x0 |
| 26 | #define BM_PXP_CTRL_ENABLE 0x00000001 |
| 27 | #define BP_PXP_CTRL_ENABLE 0 |
| 28 | #define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 |
| 29 | #define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0 |
| 30 | #define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4 |
| 31 | #define BM_PXP_CTRL_ROTATE 0x00000300 |
| 32 | #define BP_PXP_CTRL_ROTATE 8 |
| 33 | #define BM_PXP_CTRL_HFLIP 0x00000400 |
| 34 | #define BM_PXP_CTRL_VFLIP 0x00000800 |
| 35 | #define BM_PXP_CTRL_S0_FORMAT 0x0000F000 |
| 36 | #define BP_PXP_CTRL_S0_FORMAT 12 |
| 37 | #define BM_PXP_CTRL_SCALE 0x00040000 |
| 38 | #define BM_PXP_CTRL_CROP 0x00080000 |
| 39 | |
| 40 | #define HW_PXP_STAT 0x10 |
| 41 | #define BM_PXP_STAT_IRQ 0x00000001 |
| 42 | #define BP_PXP_STAT_IRQ 0 |
| 43 | |
| 44 | #define HW_PXP_RGBBUF 0x20 |
| 45 | |
| 46 | #define HW_PXP_RGBSIZE 0x40 |
| 47 | #define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF |
| 48 | #define BP_PXP_RGBSIZE_HEIGHT 0 |
| 49 | #define BM_PXP_RGBSIZE_WIDTH 0x00FFF000 |
| 50 | #define BP_PXP_RGBSIZE_WIDTH 12 |
| 51 | |
| 52 | #define HW_PXP_S0BUF 0x50 |
| 53 | |
| 54 | #define HW_PXP_S0UBUF 0x60 |
| 55 | |
| 56 | #define HW_PXP_S0VBUF 0x70 |
| 57 | |
| 58 | #define HW_PXP_S0PARAM 0x80 |
| 59 | #define BM_PXP_S0PARAM_HEIGHT 0x000000FF |
| 60 | #define BP_PXP_S0PARAM_HEIGHT 0 |
| 61 | #define BM_PXP_S0PARAM_WIDTH 0x0000FF00 |
| 62 | #define BP_PXP_S0PARAM_WIDTH 8 |
| 63 | #define BM_PXP_S0PARAM_YBASE 0x00FF0000 |
| 64 | #define BP_PXP_S0PARAM_YBASE 16 |
| 65 | #define BM_PXP_S0PARAM_XBASE 0xFF000000 |
| 66 | #define BP_PXP_S0PARAM_XBASE 24 |
| 67 | |
| 68 | #define HW_PXP_S0BACKGROUND 0x90 |
| 69 | |
| 70 | #define HW_PXP_S0CROP 0xA0 |
| 71 | #define BM_PXP_S0CROP_HEIGHT 0x000000FF |
| 72 | #define BP_PXP_S0CROP_HEIGHT 0 |
| 73 | #define BM_PXP_S0CROP_WIDTH 0x0000FF00 |
| 74 | #define BP_PXP_S0CROP_WIDTH 8 |
| 75 | #define BM_PXP_S0CROP_YBASE 0x00FF0000 |
| 76 | #define BP_PXP_S0CROP_YBASE 16 |
| 77 | #define BM_PXP_S0CROP_XBASE 0xFF000000 |
| 78 | #define BP_PXP_S0CROP_XBASE 24 |
| 79 | |
| 80 | #define HW_PXP_S0SCALE 0xB0 |
| 81 | #define BM_PXP_S0SCALE_XSCALE 0x00003FFF |
| 82 | #define BP_PXP_S0SCALE_XSCALE 0 |
| 83 | #define BM_PXP_S0SCALE_YSCALE 0x3FFF0000 |
| 84 | #define BP_PXP_S0SCALE_YSCALE 16 |
| 85 | |
| 86 | #define HW_PXP_CSCCOEFF0 0xD0 |
| 87 | |
| 88 | #define HW_PXP_CSCCOEFF1 0xE0 |
| 89 | |
| 90 | #define HW_PXP_CSCCOEFF2 0xF0 |
| 91 | |
| 92 | #define HW_PXP_S0COLORKEYLOW 0x180 |
| 93 | |
| 94 | #define HW_PXP_S0COLORKEYHIGH 0x190 |
| 95 | |
| 96 | #define HW_PXP_OL0 (0x200 + 0 * 0x40) |
| 97 | #define HW_PXP_OL1 (0x200 + 1 * 0x40) |
| 98 | #define HW_PXP_OL2 (0x200 + 2 * 0x40) |
| 99 | #define HW_PXP_OL3 (0x200 + 3 * 0x40) |
| 100 | #define HW_PXP_OL4 (0x200 + 4 * 0x40) |
| 101 | #define HW_PXP_OL5 (0x200 + 5 * 0x40) |
| 102 | #define HW_PXP_OL6 (0x200 + 6 * 0x40) |
| 103 | #define HW_PXP_OL7 (0x200 + 7 * 0x40) |
| 104 | |
| 105 | #define HW_PXP_OLn 0x200 |
| 106 | |
| 107 | #define HW_PXP_OL0SIZE (0x210 + 0 * 0x40) |
| 108 | #define HW_PXP_OL1SIZE (0x210 + 1 * 0x40) |
| 109 | #define HW_PXP_OL2SIZE (0x210 + 2 * 0x40) |
| 110 | #define HW_PXP_OL3SIZE (0x210 + 3 * 0x40) |
| 111 | #define HW_PXP_OL4SIZE (0x210 + 4 * 0x40) |
| 112 | #define HW_PXP_OL5SIZE (0x210 + 5 * 0x40) |
| 113 | #define HW_PXP_OL6SIZE (0x210 + 6 * 0x40) |
| 114 | #define HW_PXP_OL7SIZE (0x210 + 7 * 0x40) |
| 115 | |
| 116 | #define HW_PXP_OLnSIZE 0x210 |
| 117 | #define BM_PXP_OLnSIZE_HEIGHT 0x000000FF |
| 118 | #define BP_PXP_OLnSIZE_HEIGHT 0 |
| 119 | #define BM_PXP_OLnSIZE_WIDTH 0x0000FF00 |
| 120 | #define BP_PXP_OLnSIZE_WIDTH 8 |
| 121 | |
| 122 | #define HW_PXP_OL0PARAM (0x220 + 0 * 0x40) |
| 123 | #define HW_PXP_OL1PARAM (0x220 + 1 * 0x40) |
| 124 | #define HW_PXP_OL2PARAM (0x220 + 2 * 0x40) |
| 125 | #define HW_PXP_OL3PARAM (0x220 + 3 * 0x40) |
| 126 | #define HW_PXP_OL4PARAM (0x220 + 4 * 0x40) |
| 127 | #define HW_PXP_OL5PARAM (0x220 + 5 * 0x40) |
| 128 | #define HW_PXP_OL6PARAM (0x220 + 6 * 0x40) |
| 129 | #define HW_PXP_OL7PARAM (0x220 + 7 * 0x40) |
| 130 | |
| 131 | #define HW_PXP_OLnPARAM 0x220 |
| 132 | #define BM_PXP_OLnPARAM_ENABLE 0x00000001 |
| 133 | #define BP_PXP_OLnPARAM_ENABLE 0 |
| 134 | #define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006 |
| 135 | #define BP_PXP_OLnPARAM_ALPHA_CNTL 1 |
| 136 | #define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008 |
| 137 | #define BM_PXP_OLnPARAM_FORMAT 0x000000F0 |
| 138 | #define BP_PXP_OLnPARAM_FORMAT 4 |
| 139 | #define BM_PXP_OLnPARAM_ALPHA 0x0000FF00 |
| 140 | #define BP_PXP_OLnPARAM_ALPHA 8 |