Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1 | /* |
Dhananjay Phadke | 5d242f1 | 2009-02-25 15:57:56 +0000 | [diff] [blame] | 2 | * Copyright (C) 2003 - 2009 NetXen, Inc. |
Dhananjay Phadke | 13af7a6 | 2009-09-11 11:28:15 +0000 | [diff] [blame] | 3 | * Copyright (C) 2009 - QLogic Corporation. |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 4 | * All rights reserved. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 5 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 10 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 11 | * This program is distributed in the hope that it will be useful, but |
| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 15 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, |
| 19 | * MA 02111-1307, USA. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 20 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 21 | * The full GNU General Public License is included in this distribution |
| 22 | * in the file called LICENSE. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 23 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 24 | */ |
| 25 | |
| 26 | #ifndef _NETXEN_NIC_H_ |
| 27 | #define _NETXEN_NIC_H_ |
| 28 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 29 | #include <linux/module.h> |
| 30 | #include <linux/kernel.h> |
| 31 | #include <linux/types.h> |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 32 | #include <linux/ioport.h> |
| 33 | #include <linux/pci.h> |
| 34 | #include <linux/netdevice.h> |
| 35 | #include <linux/etherdevice.h> |
| 36 | #include <linux/ip.h> |
| 37 | #include <linux/in.h> |
| 38 | #include <linux/tcp.h> |
| 39 | #include <linux/skbuff.h> |
Dhananjay Phadke | f7185c7 | 2009-04-28 15:29:11 +0000 | [diff] [blame] | 40 | #include <linux/firmware.h> |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 41 | |
| 42 | #include <linux/ethtool.h> |
| 43 | #include <linux/mii.h> |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 44 | #include <linux/timer.h> |
| 45 | |
David S. Miller | 4255589 | 2008-07-22 18:29:10 -0700 | [diff] [blame] | 46 | #include <linux/vmalloc.h> |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 47 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 48 | #include <asm/io.h> |
| 49 | #include <asm/byteorder.h> |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 50 | |
Dhananjay Phadke | 7d6fd5e | 2009-08-23 08:35:13 +0000 | [diff] [blame] | 51 | #include "netxen_nic_hdr.h" |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 52 | #include "netxen_nic_hw.h" |
| 53 | |
Dhananjay Phadke | 5873556 | 2008-07-21 19:44:10 -0700 | [diff] [blame] | 54 | #define _NETXEN_NIC_LINUX_MAJOR 4 |
| 55 | #define _NETXEN_NIC_LINUX_MINOR 0 |
Dhananjay Phadke | 5877e55 | 2009-09-05 17:43:12 +0000 | [diff] [blame] | 56 | #define _NETXEN_NIC_LINUX_SUBVERSION 50 |
| 57 | #define NETXEN_NIC_LINUX_VERSIONID "4.0.50" |
Dhananjay Phadke | 5873556 | 2008-07-21 19:44:10 -0700 | [diff] [blame] | 58 | |
Dhananjay Phadke | 98e31bb | 2009-07-01 11:41:42 +0000 | [diff] [blame] | 59 | #define NETXEN_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) |
| 60 | #define _major(v) (((v) >> 24) & 0xff) |
| 61 | #define _minor(v) (((v) >> 16) & 0xff) |
| 62 | #define _build(v) ((v) & 0xffff) |
| 63 | |
| 64 | /* version in image has weird encoding: |
| 65 | * 7:0 - major |
| 66 | * 15:8 - minor |
| 67 | * 31:16 - build (little endian) |
| 68 | */ |
| 69 | #define NETXEN_DECODE_VERSION(v) \ |
| 70 | NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) |
Amit S. Kale | 27d2ab5 | 2007-02-05 07:40:49 -0800 | [diff] [blame] | 71 | |
Mithlesh Thukral | 0d04761 | 2007-06-07 04:36:36 -0700 | [diff] [blame] | 72 | #define NETXEN_NUM_FLASH_SECTORS (64) |
| 73 | #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024) |
| 74 | #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \ |
| 75 | * NETXEN_FLASH_SECTOR_SIZE) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 76 | |
Linsys Contractor Mithlesh Thukral | 0c25cfe | 2007-02-28 05:14:07 -0800 | [diff] [blame] | 77 | #define PHAN_VENDOR_ID 0x4040 |
| 78 | |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 79 | #define RCV_DESC_RINGSIZE(rds_ring) \ |
| 80 | (sizeof(struct rcv_desc) * (rds_ring)->num_desc) |
| 81 | #define RCV_BUFF_RINGSIZE(rds_ring) \ |
Dhananjay Phadke | 438627c | 2009-03-13 14:52:03 +0000 | [diff] [blame] | 82 | (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc) |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 83 | #define STATUS_DESC_RINGSIZE(sds_ring) \ |
| 84 | (sizeof(struct status_desc) * (sds_ring)->num_desc) |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 85 | #define TX_BUFF_RINGSIZE(tx_ring) \ |
| 86 | (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc) |
| 87 | #define TX_DESC_RINGSIZE(tx_ring) \ |
| 88 | (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 89 | |
Dhananjay Phadke | ba53e6b | 2008-03-17 19:59:50 -0700 | [diff] [blame] | 90 | #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a))) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 91 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 92 | #define NETXEN_RCV_PRODUCER_OFFSET 0 |
| 93 | #define NETXEN_RCV_PEG_DB_ID 2 |
| 94 | #define NETXEN_HOST_DUMMY_DMA_SIZE 1024 |
Amit S. Kale | 27d2ab5 | 2007-02-05 07:40:49 -0800 | [diff] [blame] | 95 | #define FLASH_SUCCESS 0 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 96 | |
| 97 | #define ADDR_IN_WINDOW1(off) \ |
| 98 | ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0 |
| 99 | |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 100 | /* |
| 101 | * normalize a 64MB crb address to 32MB PCI window |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 102 | * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1 |
| 103 | */ |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 104 | #define NETXEN_CRB_NORMAL(reg) \ |
| 105 | ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST) |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 106 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 107 | #define NETXEN_CRB_NORMALIZE(adapter, reg) \ |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 108 | pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg)) |
| 109 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 110 | #define DB_NORMALIZE(adapter, off) \ |
| 111 | (adapter->ahw.db_base + (off)) |
| 112 | |
| 113 | #define NX_P2_C0 0x24 |
| 114 | #define NX_P2_C1 0x25 |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 115 | #define NX_P3_A0 0x30 |
| 116 | #define NX_P3_A2 0x30 |
| 117 | #define NX_P3_B0 0x40 |
| 118 | #define NX_P3_B1 0x41 |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 119 | #define NX_P3_B2 0x42 |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 120 | |
| 121 | #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1) |
| 122 | #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 123 | |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 124 | #define FIRST_PAGE_GROUP_START 0 |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 125 | #define FIRST_PAGE_GROUP_END 0x100000 |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 126 | |
Mithlesh Thukral | 78403a9 | 2007-04-20 07:57:26 -0700 | [diff] [blame] | 127 | #define SECOND_PAGE_GROUP_START 0x6000000 |
| 128 | #define SECOND_PAGE_GROUP_END 0x68BC000 |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 129 | |
| 130 | #define THIRD_PAGE_GROUP_START 0x70E4000 |
| 131 | #define THIRD_PAGE_GROUP_END 0x8000000 |
| 132 | |
| 133 | #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START |
| 134 | #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START |
| 135 | #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 136 | |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 137 | #define P2_MAX_MTU (8000) |
| 138 | #define P3_MAX_MTU (9600) |
| 139 | #define NX_ETHERMTU 1500 |
| 140 | #define NX_MAX_ETHERHDR 32 /* This contains some padding */ |
| 141 | |
Dhananjay Phadke | 9b08beb | 2009-07-26 20:07:44 +0000 | [diff] [blame] | 142 | #define NX_P2_RX_BUF_MAX_LEN 1760 |
| 143 | #define NX_P3_RX_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU) |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 144 | #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU) |
| 145 | #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU) |
Dhananjay Phadke | d9e651b | 2008-07-21 19:44:08 -0700 | [diff] [blame] | 146 | #define NX_CT_DEFAULT_RX_BUF_LEN 2048 |
Dhananjay Phadke | bc75e5b | 2009-09-03 13:10:53 +0000 | [diff] [blame] | 147 | #define NX_LRO_BUFFER_EXTRA 2048 |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 148 | |
Dhananjay Phadke | 9b08beb | 2009-07-26 20:07:44 +0000 | [diff] [blame] | 149 | #define NX_RX_LRO_BUFFER_LENGTH (8060) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 150 | |
| 151 | /* |
| 152 | * Maximum number of ring contexts |
| 153 | */ |
| 154 | #define MAX_RING_CTX 1 |
| 155 | |
| 156 | /* Opcodes to be used with the commands */ |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 157 | #define TX_ETHER_PKT 0x01 |
| 158 | #define TX_TCP_PKT 0x02 |
| 159 | #define TX_UDP_PKT 0x03 |
| 160 | #define TX_IP_PKT 0x04 |
| 161 | #define TX_TCP_LSO 0x05 |
| 162 | #define TX_TCP_LSO6 0x06 |
| 163 | #define TX_IPSEC 0x07 |
| 164 | #define TX_IPSEC_CMD 0x0a |
| 165 | #define TX_TCPV6_PKT 0x0b |
| 166 | #define TX_UDPV6_PKT 0x0c |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 167 | |
| 168 | /* The following opcodes are for internal consumption. */ |
| 169 | #define NETXEN_CONTROL_OP 0x10 |
| 170 | #define PEGNET_REQUEST 0x11 |
| 171 | |
| 172 | #define MAX_NUM_CARDS 4 |
| 173 | |
| 174 | #define MAX_BUFFERS_PER_CMD 32 |
Dhananjay Phadke | cb2107b | 2009-06-17 17:27:25 +0000 | [diff] [blame] | 175 | #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + 4) |
Amit Kumar Salecha | 74c520d | 2009-09-11 11:28:14 +0000 | [diff] [blame] | 176 | #define NX_MAX_TX_TIMEOUTS 2 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 177 | |
| 178 | /* |
| 179 | * Following are the states of the Phantom. Phantom will set them and |
| 180 | * Host will read to check if the fields are correct. |
| 181 | */ |
| 182 | #define PHAN_INITIALIZE_START 0xff00 |
| 183 | #define PHAN_INITIALIZE_FAILED 0xffff |
| 184 | #define PHAN_INITIALIZE_COMPLETE 0xff01 |
| 185 | |
| 186 | /* Host writes the following to notify that it has done the init-handshake */ |
| 187 | #define PHAN_INITIALIZE_ACK 0xf00f |
| 188 | |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 189 | #define NUM_RCV_DESC_RINGS 3 |
| 190 | #define NUM_STS_DESC_RINGS 4 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 191 | |
Dhananjay Phadke | 438627c | 2009-03-13 14:52:03 +0000 | [diff] [blame] | 192 | #define RCV_RING_NORMAL 0 |
| 193 | #define RCV_RING_JUMBO 1 |
| 194 | #define RCV_RING_LRO 2 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 195 | |
Dhananjay Phadke | 24767ab | 2009-07-27 11:08:00 -0700 | [diff] [blame] | 196 | #define MIN_CMD_DESCRIPTORS 64 |
| 197 | #define MIN_RCV_DESCRIPTORS 64 |
| 198 | #define MIN_JUMBO_DESCRIPTORS 32 |
| 199 | |
| 200 | #define MAX_CMD_DESCRIPTORS 1024 |
| 201 | #define MAX_RCV_DESCRIPTORS_1G 4096 |
| 202 | #define MAX_RCV_DESCRIPTORS_10G 8192 |
| 203 | #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 |
| 204 | #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 |
Dhananjay Phadke | 32ec803 | 2009-01-26 12:35:19 -0800 | [diff] [blame] | 205 | #define MAX_LRO_RCV_DESCRIPTORS 8 |
Dhananjay Phadke | 24767ab | 2009-07-27 11:08:00 -0700 | [diff] [blame] | 206 | |
| 207 | #define DEFAULT_RCV_DESCRIPTORS_1G 2048 |
| 208 | #define DEFAULT_RCV_DESCRIPTORS_10G 4096 |
| 209 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 210 | #define NETXEN_CTX_SIGNATURE 0xdee0 |
Dhananjay Phadke | f6d21f4 | 2009-04-07 22:50:46 +0000 | [diff] [blame] | 211 | #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0 |
| 212 | #define NETXEN_CTX_RESET 0xbad0 |
Dhananjay Phadke | cf981ff | 2009-07-17 15:27:06 +0000 | [diff] [blame] | 213 | #define NETXEN_CTX_D3_RESET 0xacc0 |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 214 | #define NETXEN_RCV_PRODUCER(ringid) (ringid) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 215 | |
| 216 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 |
| 217 | #define PHAN_PEG_RCV_START_INITIALIZE 0xff00 |
| 218 | |
| 219 | #define get_next_index(index, length) \ |
| 220 | (((index) + 1) & ((length) - 1)) |
| 221 | |
| 222 | #define get_index_range(index,length,count) \ |
| 223 | (((index) + (count)) & ((length) - 1)) |
| 224 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 225 | #define MPORT_SINGLE_FUNCTION_MODE 0x1111 |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 226 | #define MPORT_MULTI_FUNCTION_MODE 0x2222 |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 227 | |
Dhananjay Phadke | 6a581e9 | 2009-09-05 17:43:08 +0000 | [diff] [blame] | 228 | #define NX_MAX_PCI_FUNC 8 |
| 229 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 230 | /* |
| 231 | * NetXen host-peg signal message structure |
| 232 | * |
| 233 | * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx |
| 234 | * Bit 2 : priv_id => must be 1 |
| 235 | * Bit 3-17 : count => for doorbell |
| 236 | * Bit 18-27 : ctx_id => Context id |
| 237 | * Bit 28-31 : opcode |
| 238 | */ |
| 239 | |
| 240 | typedef u32 netxen_ctx_msg; |
| 241 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 242 | #define netxen_set_msg_peg_id(config_word, val) \ |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 243 | ((config_word) &= ~3, (config_word) |= val & 3) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 244 | #define netxen_set_msg_privid(config_word) \ |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 245 | ((config_word) |= 1 << 2) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 246 | #define netxen_set_msg_count(config_word, val) \ |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 247 | ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 248 | #define netxen_set_msg_ctxid(config_word, val) \ |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 249 | ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 250 | #define netxen_set_msg_opcode(config_word, val) \ |
Amit S. Kale | 8258117 | 2007-02-12 04:33:38 -0800 | [diff] [blame] | 251 | ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 252 | |
Dhananjay Phadke | f6d21f4 | 2009-04-07 22:50:46 +0000 | [diff] [blame] | 253 | struct netxen_rcv_ring { |
| 254 | __le64 addr; |
| 255 | __le32 size; |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 256 | __le32 rsrvd; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 257 | }; |
| 258 | |
Dhananjay Phadke | f6d21f4 | 2009-04-07 22:50:46 +0000 | [diff] [blame] | 259 | struct netxen_sts_ring { |
| 260 | __le64 addr; |
| 261 | __le32 size; |
| 262 | __le16 msi_index; |
| 263 | __le16 rsvd; |
| 264 | } ; |
| 265 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 266 | struct netxen_ring_ctx { |
| 267 | |
| 268 | /* one command ring */ |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 269 | __le64 cmd_consumer_offset; |
| 270 | __le64 cmd_ring_addr; |
| 271 | __le32 cmd_ring_size; |
| 272 | __le32 rsrvd; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 273 | |
| 274 | /* three receive rings */ |
Dhananjay Phadke | f6d21f4 | 2009-04-07 22:50:46 +0000 | [diff] [blame] | 275 | struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS]; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 276 | |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 277 | __le64 sts_ring_addr; |
| 278 | __le32 sts_ring_size; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 279 | |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 280 | __le32 ctx_id; |
Dhananjay Phadke | f6d21f4 | 2009-04-07 22:50:46 +0000 | [diff] [blame] | 281 | |
| 282 | __le64 rsrvd_2[3]; |
| 283 | __le32 sts_ring_count; |
| 284 | __le32 rsrvd_3; |
| 285 | struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS]; |
| 286 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 287 | } __attribute__ ((aligned(64))); |
| 288 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 289 | /* |
| 290 | * Following data structures describe the descriptors that will be used. |
| 291 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when |
| 292 | * we are doing LSO (above the 1500 size packet) only. |
| 293 | */ |
| 294 | |
| 295 | /* |
| 296 | * The size of reference handle been changed to 16 bits to pass the MSS fields |
| 297 | * for the LSO packet |
| 298 | */ |
| 299 | |
| 300 | #define FLAGS_CHECKSUM_ENABLED 0x01 |
| 301 | #define FLAGS_LSO_ENABLED 0x02 |
| 302 | #define FLAGS_IPSEC_SA_ADD 0x04 |
| 303 | #define FLAGS_IPSEC_SA_DELETE 0x08 |
| 304 | #define FLAGS_VLAN_TAGGED 0x10 |
Dhananjay Phadke | 028afe7 | 2009-07-26 20:07:45 +0000 | [diff] [blame] | 305 | #define FLAGS_VLAN_OOB 0x40 |
| 306 | |
| 307 | #define netxen_set_tx_vlan_tci(cmd_desc, v) \ |
| 308 | (cmd_desc)->vlan_TCI = cpu_to_le16(v); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 309 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 310 | #define netxen_set_cmd_desc_port(cmd_desc, var) \ |
| 311 | ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) |
Mithlesh Thukral | 6c80b18 | 2007-04-20 07:55:26 -0700 | [diff] [blame] | 312 | #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 313 | ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0)) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 314 | |
Dhananjay Phadke | 391587c | 2009-01-14 20:48:11 -0800 | [diff] [blame] | 315 | #define netxen_set_tx_port(_desc, _port) \ |
| 316 | (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 317 | |
Dhananjay Phadke | 391587c | 2009-01-14 20:48:11 -0800 | [diff] [blame] | 318 | #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \ |
| 319 | (_desc)->flags_opcode = \ |
| 320 | cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 321 | |
Dhananjay Phadke | 391587c | 2009-01-14 20:48:11 -0800 | [diff] [blame] | 322 | #define netxen_set_tx_frags_len(_desc, _frags, _len) \ |
Dhananjay Phadke | 1bcfd79 | 2009-07-26 20:07:40 +0000 | [diff] [blame] | 323 | (_desc)->nfrags__length = \ |
Dhananjay Phadke | 391587c | 2009-01-14 20:48:11 -0800 | [diff] [blame] | 324 | cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 325 | |
| 326 | struct cmd_desc_type0 { |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 327 | u8 tcp_hdr_offset; /* For LSO only */ |
| 328 | u8 ip_hdr_offset; /* For LSO only */ |
Dhananjay Phadke | 1bcfd79 | 2009-07-26 20:07:40 +0000 | [diff] [blame] | 329 | __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ |
| 330 | __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 331 | |
Dhananjay Phadke | 1bcfd79 | 2009-07-26 20:07:40 +0000 | [diff] [blame] | 332 | __le64 addr_buffer2; |
| 333 | |
| 334 | __le16 reference_handle; |
| 335 | __le16 mss; |
| 336 | u8 port_ctxid; /* 7:4 ctxid 3:0 port */ |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 337 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 338 | __le16 conn_id; /* IPSec offoad only */ |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 339 | |
Dhananjay Phadke | 1bcfd79 | 2009-07-26 20:07:40 +0000 | [diff] [blame] | 340 | __le64 addr_buffer3; |
| 341 | __le64 addr_buffer1; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 342 | |
Dhananjay Phadke | d32cc3d | 2009-03-09 08:50:53 +0000 | [diff] [blame] | 343 | __le16 buffer_length[4]; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 344 | |
Dhananjay Phadke | 1bcfd79 | 2009-07-26 20:07:40 +0000 | [diff] [blame] | 345 | __le64 addr_buffer4; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 346 | |
Dhananjay Phadke | 028afe7 | 2009-07-26 20:07:45 +0000 | [diff] [blame] | 347 | __le32 reserved2; |
Amit Kumar Salecha | 58f2546 | 2009-09-09 18:12:59 -0700 | [diff] [blame] | 348 | __le16 reserved; |
| 349 | __le16 vlan_TCI; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 350 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 351 | } __attribute__ ((aligned(64))); |
| 352 | |
| 353 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ |
| 354 | struct rcv_desc { |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 355 | __le16 reference_handle; |
| 356 | __le16 reserved; |
| 357 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ |
| 358 | __le64 addr_buffer; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 359 | }; |
| 360 | |
| 361 | /* opcode field in status_desc */ |
Dhananjay Phadke | 6598b16 | 2009-07-26 20:07:37 +0000 | [diff] [blame] | 362 | #define NETXEN_NIC_SYN_OFFLOAD 0x03 |
Dhananjay Phadke | d9e651b | 2008-07-21 19:44:08 -0700 | [diff] [blame] | 363 | #define NETXEN_NIC_RXPKT_DESC 0x04 |
| 364 | #define NETXEN_OLD_RXPKT_DESC 0x3f |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 365 | #define NETXEN_NIC_RESPONSE_DESC 0x05 |
Dhananjay Phadke | c1c00ab | 2009-08-05 07:34:09 +0000 | [diff] [blame] | 366 | #define NETXEN_NIC_LRO_DESC 0x12 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 367 | |
| 368 | /* for status field in status_desc */ |
| 369 | #define STATUS_NEED_CKSUM (1) |
| 370 | #define STATUS_CKSUM_OK (2) |
| 371 | |
| 372 | /* owner bits of status_desc */ |
Dhananjay Phadke | 0ddc110 | 2009-03-09 08:50:52 +0000 | [diff] [blame] | 373 | #define STATUS_OWNER_HOST (0x1ULL << 56) |
| 374 | #define STATUS_OWNER_PHANTOM (0x2ULL << 56) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 375 | |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 376 | /* Status descriptor: |
| 377 | 0-3 port, 4-7 status, 8-11 type, 12-27 total_length |
| 378 | 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset |
| 379 | 53-55 desc_cnt, 56-57 owner, 58-63 opcode |
| 380 | */ |
Dhananjay Phadke | 5dc1626 | 2007-12-31 10:08:57 -0800 | [diff] [blame] | 381 | #define netxen_get_sts_port(sts_data) \ |
| 382 | ((sts_data) & 0x0F) |
| 383 | #define netxen_get_sts_status(sts_data) \ |
| 384 | (((sts_data) >> 4) & 0x0F) |
| 385 | #define netxen_get_sts_type(sts_data) \ |
| 386 | (((sts_data) >> 8) & 0x0F) |
| 387 | #define netxen_get_sts_totallength(sts_data) \ |
| 388 | (((sts_data) >> 12) & 0xFFFF) |
| 389 | #define netxen_get_sts_refhandle(sts_data) \ |
| 390 | (((sts_data) >> 28) & 0xFFFF) |
| 391 | #define netxen_get_sts_prot(sts_data) \ |
| 392 | (((sts_data) >> 44) & 0x0F) |
Dhananjay Phadke | d9e651b | 2008-07-21 19:44:08 -0700 | [diff] [blame] | 393 | #define netxen_get_sts_pkt_offset(sts_data) \ |
| 394 | (((sts_data) >> 48) & 0x1F) |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 395 | #define netxen_get_sts_desc_cnt(sts_data) \ |
| 396 | (((sts_data) >> 53) & 0x7) |
Dhananjay Phadke | 5dc1626 | 2007-12-31 10:08:57 -0800 | [diff] [blame] | 397 | #define netxen_get_sts_opcode(sts_data) \ |
| 398 | (((sts_data) >> 58) & 0x03F) |
| 399 | |
Dhananjay Phadke | c1c00ab | 2009-08-05 07:34:09 +0000 | [diff] [blame] | 400 | #define netxen_get_lro_sts_refhandle(sts_data) \ |
| 401 | ((sts_data) & 0x0FFFF) |
| 402 | #define netxen_get_lro_sts_length(sts_data) \ |
| 403 | (((sts_data) >> 16) & 0x0FFFF) |
| 404 | #define netxen_get_lro_sts_l2_hdr_offset(sts_data) \ |
| 405 | (((sts_data) >> 32) & 0x0FF) |
| 406 | #define netxen_get_lro_sts_l4_hdr_offset(sts_data) \ |
| 407 | (((sts_data) >> 40) & 0x0FF) |
| 408 | #define netxen_get_lro_sts_timestamp(sts_data) \ |
| 409 | (((sts_data) >> 48) & 0x1) |
| 410 | #define netxen_get_lro_sts_type(sts_data) \ |
| 411 | (((sts_data) >> 49) & 0x7) |
| 412 | #define netxen_get_lro_sts_push_flag(sts_data) \ |
| 413 | (((sts_data) >> 52) & 0x1) |
| 414 | #define netxen_get_lro_sts_seq_number(sts_data) \ |
| 415 | ((sts_data) & 0x0FFFFFFFF) |
| 416 | |
| 417 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 418 | struct status_desc { |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 419 | __le64 status_desc_data[2]; |
Mithlesh Thukral | 6c80b18 | 2007-04-20 07:55:26 -0700 | [diff] [blame] | 420 | } __attribute__ ((aligned(16))); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 421 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 422 | /* The version of the main data structure */ |
| 423 | #define NETXEN_BDINFO_VERSION 1 |
| 424 | |
| 425 | /* Magic number to let user know flash is programmed */ |
| 426 | #define NETXEN_BDINFO_MAGIC 0x12345678 |
| 427 | |
| 428 | /* Max number of Gig ports on a Phantom board */ |
| 429 | #define NETXEN_MAX_PORTS 4 |
| 430 | |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 431 | #define NETXEN_BRDTYPE_P1_BD 0x0000 |
| 432 | #define NETXEN_BRDTYPE_P1_SB 0x0001 |
| 433 | #define NETXEN_BRDTYPE_P1_SMAX 0x0002 |
| 434 | #define NETXEN_BRDTYPE_P1_SOCK 0x0003 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 435 | |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 436 | #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008 |
| 437 | #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009 |
| 438 | #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a |
| 439 | #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b |
| 440 | #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 441 | |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 442 | #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d |
| 443 | #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e |
| 444 | #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 445 | |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 446 | #define NETXEN_BRDTYPE_P3_REF_QG 0x0021 |
| 447 | #define NETXEN_BRDTYPE_P3_HMEZ 0x0022 |
| 448 | #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023 |
| 449 | #define NETXEN_BRDTYPE_P3_4_GB 0x0024 |
| 450 | #define NETXEN_BRDTYPE_P3_IMEZ 0x0025 |
| 451 | #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026 |
| 452 | #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027 |
| 453 | #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028 |
| 454 | #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029 |
| 455 | #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a |
| 456 | #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b |
| 457 | #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031 |
| 458 | #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032 |
| 459 | #define NETXEN_BRDTYPE_P3_10G_TP 0x0080 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 460 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 461 | /* Flash memory map */ |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 462 | #define NETXEN_CRBINIT_START 0 /* crbinit section */ |
| 463 | #define NETXEN_BRDCFG_START 0x4000 /* board config */ |
| 464 | #define NETXEN_INITCODE_START 0x6000 /* pegtune code */ |
| 465 | #define NETXEN_BOOTLD_START 0x10000 /* bootld */ |
| 466 | #define NETXEN_IMAGE_START 0x43000 /* compressed image */ |
| 467 | #define NETXEN_SECONDARY_START 0x200000 /* backup images */ |
| 468 | #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */ |
| 469 | #define NETXEN_USER_START 0x3E8000 /* Firmare info */ |
| 470 | #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */ |
Dhananjay Phadke | 06db58c | 2009-08-05 07:34:08 +0000 | [diff] [blame] | 471 | #define NETXEN_USER_START_OLD NETXEN_PXE_START /* very old flash */ |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 472 | |
Dhananjay Phadke | 06db58c | 2009-08-05 07:34:08 +0000 | [diff] [blame] | 473 | #define NX_OLD_MAC_ADDR_OFFSET (NETXEN_USER_START) |
Dhananjay Phadke | ba599d4 | 2009-02-24 16:38:22 -0800 | [diff] [blame] | 474 | #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408) |
| 475 | #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c) |
Dhananjay Phadke | 06db58c | 2009-08-05 07:34:08 +0000 | [diff] [blame] | 476 | #define NX_FW_MAC_ADDR_OFFSET (NETXEN_USER_START+0x418) |
| 477 | #define NX_FW_SERIAL_NUM_OFFSET (NETXEN_USER_START+0x81c) |
Dhananjay Phadke | ba599d4 | 2009-02-24 16:38:22 -0800 | [diff] [blame] | 478 | #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c) |
Dhananjay Phadke | 06db58c | 2009-08-05 07:34:08 +0000 | [diff] [blame] | 479 | |
| 480 | #define NX_HDR_VERSION_OFFSET (NETXEN_BRDCFG_START) |
| 481 | #define NX_BRDTYPE_OFFSET (NETXEN_BRDCFG_START+0x8) |
Dhananjay Phadke | ba599d4 | 2009-02-24 16:38:22 -0800 | [diff] [blame] | 482 | #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128) |
Dhananjay Phadke | 06db58c | 2009-08-05 07:34:08 +0000 | [diff] [blame] | 483 | |
Dhananjay Phadke | ba599d4 | 2009-02-24 16:38:22 -0800 | [diff] [blame] | 484 | #define NX_FW_MIN_SIZE (0x3fffff) |
Dhananjay Phadke | bd257ed | 2009-03-17 13:14:22 -0700 | [diff] [blame] | 485 | #define NX_P2_MN_ROMIMAGE 0 |
| 486 | #define NX_P3_CT_ROMIMAGE 1 |
| 487 | #define NX_P3_MN_ROMIMAGE 2 |
Dhananjay Phadke | 67c38fc | 2009-07-01 11:41:43 +0000 | [diff] [blame] | 488 | #define NX_FLASH_ROMIMAGE 3 |
Dhananjay Phadke | ba599d4 | 2009-02-24 16:38:22 -0800 | [diff] [blame] | 489 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 490 | extern char netxen_nic_driver_name[]; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 491 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 492 | /* Number of status descriptors to handle per interrupt */ |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 493 | #define MAX_STATUS_HANDLE (64) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 494 | |
| 495 | /* |
| 496 | * netxen_skb_frag{} is to contain mapping info for each SG list. This |
| 497 | * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}. |
| 498 | */ |
| 499 | struct netxen_skb_frag { |
| 500 | u64 dma; |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 501 | u64 length; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 502 | }; |
| 503 | |
Dhananjay Phadke | 7d6fd5e | 2009-08-23 08:35:13 +0000 | [diff] [blame] | 504 | struct netxen_recv_crb { |
| 505 | u32 crb_rcv_producer[NUM_RCV_DESC_RINGS]; |
| 506 | u32 crb_sts_consumer[NUM_STS_DESC_RINGS]; |
| 507 | u32 sw_int_mask[NUM_STS_DESC_RINGS]; |
| 508 | }; |
Mithlesh Thukral | 6c80b18 | 2007-04-20 07:55:26 -0700 | [diff] [blame] | 509 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 510 | /* Following defines are for the state of the buffers */ |
| 511 | #define NETXEN_BUFFER_FREE 0 |
| 512 | #define NETXEN_BUFFER_BUSY 1 |
| 513 | |
| 514 | /* |
| 515 | * There will be one netxen_buffer per skb packet. These will be |
| 516 | * used to save the dma info for pci_unmap_page() |
| 517 | */ |
| 518 | struct netxen_cmd_buffer { |
| 519 | struct sk_buff *skb; |
| 520 | struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1]; |
Dhananjay Phadke | 391587c | 2009-01-14 20:48:11 -0800 | [diff] [blame] | 521 | u32 frag_count; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 522 | }; |
| 523 | |
| 524 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ |
| 525 | struct netxen_rx_buffer { |
Dhananjay Phadke | d9e651b | 2008-07-21 19:44:08 -0700 | [diff] [blame] | 526 | struct list_head list; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 527 | struct sk_buff *skb; |
| 528 | u64 dma; |
| 529 | u16 ref_handle; |
| 530 | u16 state; |
| 531 | }; |
| 532 | |
| 533 | /* Board types */ |
| 534 | #define NETXEN_NIC_GBE 0x01 |
| 535 | #define NETXEN_NIC_XGBE 0x02 |
| 536 | |
| 537 | /* |
| 538 | * One hardware_context{} per adapter |
| 539 | * contains interrupt info as well shared hardware info. |
| 540 | */ |
| 541 | struct netxen_hardware_context { |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 542 | void __iomem *pci_base0; |
| 543 | void __iomem *pci_base1; |
| 544 | void __iomem *pci_base2; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 545 | void __iomem *db_base; |
Dhananjay Phadke | 47abe35 | 2009-10-13 05:31:42 +0000 | [diff] [blame^] | 546 | void __iomem *ocm_win_crb; |
| 547 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 548 | unsigned long db_len; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 549 | unsigned long pci_len0; |
| 550 | |
Dhananjay Phadke | 47abe35 | 2009-10-13 05:31:42 +0000 | [diff] [blame^] | 551 | u32 ocm_win; |
| 552 | u32 resv1; |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 553 | |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 554 | u8 cut_through; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 555 | u8 revision_id; |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 556 | u8 pci_func; |
| 557 | u8 linkup; |
Dhananjay Phadke | 1e2d005 | 2009-03-09 08:50:56 +0000 | [diff] [blame] | 558 | u16 port_type; |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 559 | u16 board_type; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 560 | }; |
| 561 | |
| 562 | #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ |
| 563 | #define ETHERNET_FCS_SIZE 4 |
| 564 | |
| 565 | struct netxen_adapter_stats { |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 566 | u64 xmitcalled; |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 567 | u64 xmitfinished; |
Dhananjay Phadke | d1847a7 | 2008-03-17 19:59:51 -0700 | [diff] [blame] | 568 | u64 rxdropped; |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 569 | u64 txdropped; |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 570 | u64 csummed; |
Narender Kumar | 1bb482f | 2009-08-23 08:35:09 +0000 | [diff] [blame] | 571 | u64 rx_pkts; |
| 572 | u64 lro_pkts; |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 573 | u64 rxbytes; |
| 574 | u64 txbytes; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 575 | }; |
| 576 | |
| 577 | /* |
| 578 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may |
| 579 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. |
| 580 | */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 581 | struct nx_host_rds_ring { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 582 | u32 producer; |
Dhananjay Phadke | 438627c | 2009-03-13 14:52:03 +0000 | [diff] [blame] | 583 | u32 num_desc; |
| 584 | u32 dma_size; |
| 585 | u32 skb_size; |
| 586 | u32 flags; |
Amit Kumar Salecha | 195c5f9 | 2009-09-05 17:43:10 +0000 | [diff] [blame] | 587 | void __iomem *crb_rcv_producer; |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 588 | struct rcv_desc *desc_head; |
| 589 | struct netxen_rx_buffer *rx_buf_arr; |
| 590 | struct list_head free_list; |
| 591 | spinlock_t lock; |
Dhananjay Phadke | 438627c | 2009-03-13 14:52:03 +0000 | [diff] [blame] | 592 | dma_addr_t phys_addr; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 593 | }; |
| 594 | |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 595 | struct nx_host_sds_ring { |
| 596 | u32 consumer; |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 597 | u32 num_desc; |
Amit Kumar Salecha | 195c5f9 | 2009-09-05 17:43:10 +0000 | [diff] [blame] | 598 | void __iomem *crb_sts_consumer; |
| 599 | void __iomem *crb_intr_mask; |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 600 | |
| 601 | struct status_desc *desc_head; |
| 602 | struct netxen_adapter *adapter; |
| 603 | struct napi_struct napi; |
| 604 | struct list_head free_list[NUM_RCV_DESC_RINGS]; |
| 605 | |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 606 | int irq; |
| 607 | |
| 608 | dma_addr_t phys_addr; |
| 609 | char name[IFNAMSIZ+4]; |
| 610 | }; |
| 611 | |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 612 | struct nx_host_tx_ring { |
| 613 | u32 producer; |
| 614 | __le32 *hw_consumer; |
| 615 | u32 sw_consumer; |
Amit Kumar Salecha | 195c5f9 | 2009-09-05 17:43:10 +0000 | [diff] [blame] | 616 | void __iomem *crb_cmd_producer; |
| 617 | void __iomem *crb_cmd_consumer; |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 618 | u32 num_desc; |
| 619 | |
Dhananjay Phadke | b2af9cb | 2009-07-17 15:27:07 +0000 | [diff] [blame] | 620 | struct netdev_queue *txq; |
| 621 | |
Dhananjay Phadke | d877f1e | 2009-04-07 22:50:40 +0000 | [diff] [blame] | 622 | struct netxen_cmd_buffer *cmd_buf_arr; |
| 623 | struct cmd_desc_type0 *desc_head; |
| 624 | dma_addr_t phys_addr; |
| 625 | }; |
| 626 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 627 | /* |
| 628 | * Receive context. There is one such structure per instance of the |
| 629 | * receive processing. Any state information that is relevant to |
| 630 | * the receive, and is must be in this structure. The global data may be |
| 631 | * present elsewhere. |
| 632 | */ |
| 633 | struct netxen_recv_context { |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 634 | u32 state; |
| 635 | u16 context_id; |
| 636 | u16 virt_port; |
| 637 | |
Dhananjay Phadke | 4ea528a | 2009-04-28 15:29:10 +0000 | [diff] [blame] | 638 | struct nx_host_rds_ring *rds_rings; |
Dhananjay Phadke | 71dcddb | 2009-04-07 22:50:43 +0000 | [diff] [blame] | 639 | struct nx_host_sds_ring *sds_rings; |
Dhananjay Phadke | 4ea528a | 2009-04-28 15:29:10 +0000 | [diff] [blame] | 640 | |
| 641 | struct netxen_ring_ctx *hwctx; |
| 642 | dma_addr_t phys_addr; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 643 | }; |
| 644 | |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 645 | /* New HW context creation */ |
| 646 | |
| 647 | #define NX_OS_CRB_RETRY_COUNT 4000 |
| 648 | #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \ |
| 649 | (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16)) |
| 650 | |
| 651 | #define NX_CDRP_CLEAR 0x00000000 |
| 652 | #define NX_CDRP_CMD_BIT 0x80000000 |
| 653 | |
| 654 | /* |
| 655 | * All responses must have the NX_CDRP_CMD_BIT cleared |
| 656 | * in the crb NX_CDRP_CRB_OFFSET. |
| 657 | */ |
| 658 | #define NX_CDRP_FORM_RSP(rsp) (rsp) |
| 659 | #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0) |
| 660 | |
| 661 | #define NX_CDRP_RSP_OK 0x00000001 |
| 662 | #define NX_CDRP_RSP_FAIL 0x00000002 |
| 663 | #define NX_CDRP_RSP_TIMEOUT 0x00000003 |
| 664 | |
| 665 | /* |
| 666 | * All commands must have the NX_CDRP_CMD_BIT set in |
| 667 | * the crb NX_CDRP_CRB_OFFSET. |
| 668 | */ |
| 669 | #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd)) |
| 670 | #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0) |
| 671 | |
| 672 | #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 |
| 673 | #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002 |
| 674 | #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003 |
| 675 | #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004 |
| 676 | #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 |
| 677 | #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 |
| 678 | #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007 |
| 679 | #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008 |
| 680 | #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009 |
| 681 | #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a |
| 682 | #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e |
| 683 | #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f |
| 684 | #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010 |
| 685 | #define NX_CDRP_CMD_SET_MTU 0x00000012 |
Dhananjay Phadke | 3ad4467 | 2009-08-24 19:23:27 +0000 | [diff] [blame] | 686 | #define NX_CDRP_CMD_READ_PHY 0x00000013 |
| 687 | #define NX_CDRP_CMD_WRITE_PHY 0x00000014 |
| 688 | #define NX_CDRP_CMD_READ_HW_REG 0x00000015 |
| 689 | #define NX_CDRP_CMD_GET_FLOW_CTL 0x00000016 |
| 690 | #define NX_CDRP_CMD_SET_FLOW_CTL 0x00000017 |
| 691 | #define NX_CDRP_CMD_READ_MAX_MTU 0x00000018 |
| 692 | #define NX_CDRP_CMD_READ_MAX_LRO 0x00000019 |
| 693 | #define NX_CDRP_CMD_CONFIGURE_TOE 0x0000001a |
| 694 | #define NX_CDRP_CMD_FUNC_ATTRIB 0x0000001b |
| 695 | #define NX_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c |
| 696 | #define NX_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d |
| 697 | #define NX_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e |
| 698 | #define NX_CDRP_CMD_MAX 0x0000001f |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 699 | |
| 700 | #define NX_RCODE_SUCCESS 0 |
| 701 | #define NX_RCODE_NO_HOST_MEM 1 |
| 702 | #define NX_RCODE_NO_HOST_RESOURCE 2 |
| 703 | #define NX_RCODE_NO_CARD_CRB 3 |
| 704 | #define NX_RCODE_NO_CARD_MEM 4 |
| 705 | #define NX_RCODE_NO_CARD_RESOURCE 5 |
| 706 | #define NX_RCODE_INVALID_ARGS 6 |
| 707 | #define NX_RCODE_INVALID_ACTION 7 |
| 708 | #define NX_RCODE_INVALID_STATE 8 |
| 709 | #define NX_RCODE_NOT_SUPPORTED 9 |
| 710 | #define NX_RCODE_NOT_PERMITTED 10 |
| 711 | #define NX_RCODE_NOT_READY 11 |
| 712 | #define NX_RCODE_DOES_NOT_EXIST 12 |
| 713 | #define NX_RCODE_ALREADY_EXISTS 13 |
| 714 | #define NX_RCODE_BAD_SIGNATURE 14 |
| 715 | #define NX_RCODE_CMD_NOT_IMPL 15 |
| 716 | #define NX_RCODE_CMD_INVALID 16 |
| 717 | #define NX_RCODE_TIMEOUT 17 |
| 718 | #define NX_RCODE_CMD_FAILED 18 |
| 719 | #define NX_RCODE_MAX_EXCEEDED 19 |
| 720 | #define NX_RCODE_MAX 20 |
| 721 | |
| 722 | #define NX_DESTROY_CTX_RESET 0 |
| 723 | #define NX_DESTROY_CTX_D3_RESET 1 |
| 724 | #define NX_DESTROY_CTX_MAX 2 |
| 725 | |
| 726 | /* |
| 727 | * Capabilities |
| 728 | */ |
| 729 | #define NX_CAP_BIT(class, bit) (1 << bit) |
| 730 | #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0) |
| 731 | #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1) |
| 732 | #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2) |
| 733 | #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3) |
| 734 | #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4) |
| 735 | #define NX_CAP0_LRO NX_CAP_BIT(0, 5) |
| 736 | #define NX_CAP0_LSO NX_CAP_BIT(0, 6) |
| 737 | #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7) |
| 738 | #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8) |
Dhananjay Phadke | c1c00ab | 2009-08-05 07:34:09 +0000 | [diff] [blame] | 739 | #define NX_CAP0_HW_LRO NX_CAP_BIT(0, 10) |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 740 | |
| 741 | /* |
| 742 | * Context state |
| 743 | */ |
| 744 | #define NX_HOST_CTX_STATE_FREED 0 |
| 745 | #define NX_HOST_CTX_STATE_ALLOCATED 1 |
| 746 | #define NX_HOST_CTX_STATE_ACTIVE 2 |
| 747 | #define NX_HOST_CTX_STATE_DISABLED 3 |
| 748 | #define NX_HOST_CTX_STATE_QUIESCED 4 |
| 749 | #define NX_HOST_CTX_STATE_MAX 5 |
| 750 | |
| 751 | /* |
| 752 | * Rx context |
| 753 | */ |
| 754 | |
| 755 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 756 | __le64 host_phys_addr; /* Ring base addr */ |
| 757 | __le32 ring_size; /* Ring entries */ |
| 758 | __le16 msi_index; |
| 759 | __le16 rsvd; /* Padding */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 760 | } nx_hostrq_sds_ring_t; |
| 761 | |
| 762 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 763 | __le64 host_phys_addr; /* Ring base addr */ |
| 764 | __le64 buff_size; /* Packet buffer size */ |
| 765 | __le32 ring_size; /* Ring entries */ |
| 766 | __le32 ring_kind; /* Class of ring */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 767 | } nx_hostrq_rds_ring_t; |
| 768 | |
| 769 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 770 | __le64 host_rsp_dma_addr; /* Response dma'd here */ |
| 771 | __le32 capabilities[4]; /* Flag bit vector */ |
| 772 | __le32 host_int_crb_mode; /* Interrupt crb usage */ |
| 773 | __le32 host_rds_crb_mode; /* RDS crb usage */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 774 | /* These ring offsets are relative to data[0] below */ |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 775 | __le32 rds_ring_offset; /* Offset to RDS config */ |
| 776 | __le32 sds_ring_offset; /* Offset to SDS config */ |
| 777 | __le16 num_rds_rings; /* Count of RDS rings */ |
| 778 | __le16 num_sds_rings; /* Count of SDS rings */ |
| 779 | __le16 rsvd1; /* Padding */ |
| 780 | __le16 rsvd2; /* Padding */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 781 | u8 reserved[128]; /* reserve space for future expansion*/ |
| 782 | /* MUST BE 64-bit aligned. |
| 783 | The following is packed: |
| 784 | - N hostrq_rds_rings |
| 785 | - N hostrq_sds_rings */ |
| 786 | char data[0]; |
| 787 | } nx_hostrq_rx_ctx_t; |
| 788 | |
| 789 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 790 | __le32 host_producer_crb; /* Crb to use */ |
| 791 | __le32 rsvd1; /* Padding */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 792 | } nx_cardrsp_rds_ring_t; |
| 793 | |
| 794 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 795 | __le32 host_consumer_crb; /* Crb to use */ |
| 796 | __le32 interrupt_crb; /* Crb to use */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 797 | } nx_cardrsp_sds_ring_t; |
| 798 | |
| 799 | typedef struct { |
| 800 | /* These ring offsets are relative to data[0] below */ |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 801 | __le32 rds_ring_offset; /* Offset to RDS config */ |
| 802 | __le32 sds_ring_offset; /* Offset to SDS config */ |
| 803 | __le32 host_ctx_state; /* Starting State */ |
| 804 | __le32 num_fn_per_port; /* How many PCI fn share the port */ |
| 805 | __le16 num_rds_rings; /* Count of RDS rings */ |
| 806 | __le16 num_sds_rings; /* Count of SDS rings */ |
| 807 | __le16 context_id; /* Handle for context */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 808 | u8 phys_port; /* Physical id of port */ |
| 809 | u8 virt_port; /* Virtual/Logical id of port */ |
| 810 | u8 reserved[128]; /* save space for future expansion */ |
| 811 | /* MUST BE 64-bit aligned. |
| 812 | The following is packed: |
| 813 | - N cardrsp_rds_rings |
| 814 | - N cardrs_sds_rings */ |
| 815 | char data[0]; |
| 816 | } nx_cardrsp_rx_ctx_t; |
| 817 | |
| 818 | #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ |
| 819 | (sizeof(HOSTRQ_RX) + \ |
| 820 | (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \ |
| 821 | (sds_rings)*(sizeof(nx_hostrq_sds_ring_t))) |
| 822 | |
| 823 | #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ |
| 824 | (sizeof(CARDRSP_RX) + \ |
| 825 | (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \ |
| 826 | (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t))) |
| 827 | |
| 828 | /* |
| 829 | * Tx context |
| 830 | */ |
| 831 | |
| 832 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 833 | __le64 host_phys_addr; /* Ring base addr */ |
| 834 | __le32 ring_size; /* Ring entries */ |
| 835 | __le32 rsvd; /* Padding */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 836 | } nx_hostrq_cds_ring_t; |
| 837 | |
| 838 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 839 | __le64 host_rsp_dma_addr; /* Response dma'd here */ |
| 840 | __le64 cmd_cons_dma_addr; /* */ |
| 841 | __le64 dummy_dma_addr; /* */ |
| 842 | __le32 capabilities[4]; /* Flag bit vector */ |
| 843 | __le32 host_int_crb_mode; /* Interrupt crb usage */ |
| 844 | __le32 rsvd1; /* Padding */ |
| 845 | __le16 rsvd2; /* Padding */ |
| 846 | __le16 interrupt_ctl; |
| 847 | __le16 msi_index; |
| 848 | __le16 rsvd3; /* Padding */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 849 | nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */ |
| 850 | u8 reserved[128]; /* future expansion */ |
| 851 | } nx_hostrq_tx_ctx_t; |
| 852 | |
| 853 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 854 | __le32 host_producer_crb; /* Crb to use */ |
| 855 | __le32 interrupt_crb; /* Crb to use */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 856 | } nx_cardrsp_cds_ring_t; |
| 857 | |
| 858 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 859 | __le32 host_ctx_state; /* Starting state */ |
| 860 | __le16 context_id; /* Handle for context */ |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 861 | u8 phys_port; /* Physical id of port */ |
| 862 | u8 virt_port; /* Virtual/Logical id of port */ |
| 863 | nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */ |
| 864 | u8 reserved[128]; /* future expansion */ |
| 865 | } nx_cardrsp_tx_ctx_t; |
| 866 | |
| 867 | #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) |
| 868 | #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) |
| 869 | |
| 870 | /* CRB */ |
| 871 | |
| 872 | #define NX_HOST_RDS_CRB_MODE_UNIQUE 0 |
| 873 | #define NX_HOST_RDS_CRB_MODE_SHARED 1 |
| 874 | #define NX_HOST_RDS_CRB_MODE_CUSTOM 2 |
| 875 | #define NX_HOST_RDS_CRB_MODE_MAX 3 |
| 876 | |
| 877 | #define NX_HOST_INT_CRB_MODE_UNIQUE 0 |
| 878 | #define NX_HOST_INT_CRB_MODE_SHARED 1 |
| 879 | #define NX_HOST_INT_CRB_MODE_NORX 2 |
| 880 | #define NX_HOST_INT_CRB_MODE_NOTX 3 |
| 881 | #define NX_HOST_INT_CRB_MODE_NORXTX 4 |
| 882 | |
| 883 | |
| 884 | /* MAC */ |
| 885 | |
| 886 | #define MC_COUNT_P2 16 |
| 887 | #define MC_COUNT_P3 38 |
| 888 | |
| 889 | #define NETXEN_MAC_NOOP 0 |
| 890 | #define NETXEN_MAC_ADD 1 |
| 891 | #define NETXEN_MAC_DEL 2 |
| 892 | |
| 893 | typedef struct nx_mac_list_s { |
Dhananjay Phadke | 5cf4d32 | 2009-05-05 19:05:07 +0000 | [diff] [blame] | 894 | struct list_head list; |
| 895 | uint8_t mac_addr[ETH_ALEN+2]; |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 896 | } nx_mac_list_t; |
| 897 | |
Dhananjay Phadke | cd1f816 | 2008-07-21 19:44:09 -0700 | [diff] [blame] | 898 | /* |
| 899 | * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is |
| 900 | * adjusted based on configured MTU. |
| 901 | */ |
| 902 | #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3 |
| 903 | #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256 |
| 904 | #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64 |
| 905 | #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4 |
| 906 | |
| 907 | #define NETXEN_NIC_INTR_DEFAULT 0x04 |
| 908 | |
| 909 | typedef union { |
| 910 | struct { |
| 911 | uint16_t rx_packets; |
| 912 | uint16_t rx_time_us; |
| 913 | uint16_t tx_packets; |
| 914 | uint16_t tx_time_us; |
| 915 | } data; |
| 916 | uint64_t word; |
| 917 | } nx_nic_intr_coalesce_data_t; |
| 918 | |
| 919 | typedef struct { |
| 920 | uint16_t stats_time_us; |
| 921 | uint16_t rate_sample_time; |
| 922 | uint16_t flags; |
| 923 | uint16_t rsvd_1; |
| 924 | uint32_t low_threshold; |
| 925 | uint32_t high_threshold; |
| 926 | nx_nic_intr_coalesce_data_t normal; |
| 927 | nx_nic_intr_coalesce_data_t low; |
| 928 | nx_nic_intr_coalesce_data_t high; |
| 929 | nx_nic_intr_coalesce_data_t irq; |
| 930 | } nx_nic_intr_coalesce_t; |
| 931 | |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 932 | #define NX_HOST_REQUEST 0x13 |
| 933 | #define NX_NIC_REQUEST 0x14 |
| 934 | |
| 935 | #define NX_MAC_EVENT 0x1 |
| 936 | |
Dhananjay Phadke | 6598b16 | 2009-07-26 20:07:37 +0000 | [diff] [blame] | 937 | #define NX_IP_UP 2 |
| 938 | #define NX_IP_DOWN 3 |
| 939 | |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 940 | /* |
| 941 | * Driver --> Firmware |
| 942 | */ |
| 943 | #define NX_NIC_H2C_OPCODE_START 0 |
| 944 | #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1 |
| 945 | #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2 |
| 946 | #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3 |
| 947 | #define NX_NIC_H2C_OPCODE_CONFIG_LED 4 |
| 948 | #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5 |
| 949 | #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6 |
| 950 | #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7 |
| 951 | #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8 |
| 952 | #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9 |
| 953 | #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10 |
| 954 | #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11 |
| 955 | #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12 |
| 956 | #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13 |
| 957 | #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14 |
| 958 | #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15 |
| 959 | #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16 |
| 960 | #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17 |
| 961 | #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18 |
| 962 | #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19 |
| 963 | #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20 |
| 964 | #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21 |
| 965 | #define NX_NIC_C2C_OPCODE 22 |
Narender Kumar | fa3ce35 | 2009-08-24 19:23:28 +0000 | [diff] [blame] | 966 | #define NX_NIC_H2C_OPCODE_CONFIG_BRIDGING 23 |
Narender Kumar | 1bb482f | 2009-08-23 08:35:09 +0000 | [diff] [blame] | 967 | #define NX_NIC_H2C_OPCODE_CONFIG_HW_LRO 24 |
| 968 | #define NX_NIC_H2C_OPCODE_LAST 25 |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 969 | |
| 970 | /* |
| 971 | * Firmware --> Driver |
| 972 | */ |
| 973 | |
| 974 | #define NX_NIC_C2H_OPCODE_START 128 |
| 975 | #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129 |
| 976 | #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130 |
| 977 | #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131 |
| 978 | #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132 |
| 979 | #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133 |
| 980 | #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134 |
| 981 | #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135 |
| 982 | #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136 |
| 983 | #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137 |
| 984 | #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138 |
| 985 | #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139 |
| 986 | #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140 |
| 987 | #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141 |
| 988 | #define NX_NIC_C2H_OPCODE_LAST 142 |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 989 | |
| 990 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ |
| 991 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ |
| 992 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ |
| 993 | |
Narender Kumar | 1bb482f | 2009-08-23 08:35:09 +0000 | [diff] [blame] | 994 | #define NX_NIC_LRO_REQUEST_FIRST 0 |
| 995 | #define NX_NIC_LRO_REQUEST_ADD_FLOW 1 |
| 996 | #define NX_NIC_LRO_REQUEST_DELETE_FLOW 2 |
| 997 | #define NX_NIC_LRO_REQUEST_TIMER 3 |
| 998 | #define NX_NIC_LRO_REQUEST_CLEANUP 4 |
| 999 | #define NX_NIC_LRO_REQUEST_ADD_FLOW_SCHEDULED 5 |
| 1000 | #define NX_TOE_LRO_REQUEST_ADD_FLOW 6 |
| 1001 | #define NX_TOE_LRO_REQUEST_ADD_FLOW_RESPONSE 7 |
| 1002 | #define NX_TOE_LRO_REQUEST_DELETE_FLOW 8 |
| 1003 | #define NX_TOE_LRO_REQUEST_DELETE_FLOW_RESPONSE 9 |
| 1004 | #define NX_TOE_LRO_REQUEST_TIMER 10 |
| 1005 | #define NX_NIC_LRO_REQUEST_LAST 11 |
| 1006 | |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 1007 | #define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5) |
| 1008 | #define NX_FW_CAPABILITY_SWITCHING (1 << 6) |
Dhananjay Phadke | 028afe7 | 2009-07-26 20:07:45 +0000 | [diff] [blame] | 1009 | #define NX_FW_CAPABILITY_PEXQ (1 << 7) |
| 1010 | #define NX_FW_CAPABILITY_BDG (1 << 8) |
| 1011 | #define NX_FW_CAPABILITY_FVLANTX (1 << 9) |
Dhananjay Phadke | c1c00ab | 2009-08-05 07:34:09 +0000 | [diff] [blame] | 1012 | #define NX_FW_CAPABILITY_HW_LRO (1 << 10) |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 1013 | |
| 1014 | /* module types */ |
| 1015 | #define LINKEVENT_MODULE_NOT_PRESENT 1 |
| 1016 | #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 |
| 1017 | #define LINKEVENT_MODULE_OPTICAL_SRLR 3 |
| 1018 | #define LINKEVENT_MODULE_OPTICAL_LRM 4 |
| 1019 | #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 |
| 1020 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 |
| 1021 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 |
| 1022 | #define LINKEVENT_MODULE_TWINAX 8 |
| 1023 | |
| 1024 | #define LINKSPEED_10GBPS 10000 |
| 1025 | #define LINKSPEED_1GBPS 1000 |
| 1026 | #define LINKSPEED_100MBPS 100 |
| 1027 | #define LINKSPEED_10MBPS 10 |
| 1028 | |
| 1029 | #define LINKSPEED_ENCODED_10MBPS 0 |
| 1030 | #define LINKSPEED_ENCODED_100MBPS 1 |
| 1031 | #define LINKSPEED_ENCODED_1GBPS 2 |
| 1032 | |
| 1033 | #define LINKEVENT_AUTONEG_DISABLED 0 |
| 1034 | #define LINKEVENT_AUTONEG_ENABLED 1 |
| 1035 | |
| 1036 | #define LINKEVENT_HALF_DUPLEX 0 |
| 1037 | #define LINKEVENT_FULL_DUPLEX 1 |
| 1038 | |
| 1039 | #define LINKEVENT_LINKSPEED_MBPS 0 |
| 1040 | #define LINKEVENT_LINKSPEED_ENCODED 1 |
| 1041 | |
| 1042 | /* firmware response header: |
| 1043 | * 63:58 - message type |
| 1044 | * 57:56 - owner |
| 1045 | * 55:53 - desc count |
| 1046 | * 52:48 - reserved |
| 1047 | * 47:40 - completion id |
| 1048 | * 39:32 - opcode |
| 1049 | * 31:16 - error code |
| 1050 | * 15:00 - reserved |
| 1051 | */ |
| 1052 | #define netxen_get_nic_msgtype(msg_hdr) \ |
| 1053 | ((msg_hdr >> 58) & 0x3F) |
| 1054 | #define netxen_get_nic_msg_compid(msg_hdr) \ |
| 1055 | ((msg_hdr >> 40) & 0xFF) |
| 1056 | #define netxen_get_nic_msg_opcode(msg_hdr) \ |
| 1057 | ((msg_hdr >> 32) & 0xFF) |
| 1058 | #define netxen_get_nic_msg_errcode(msg_hdr) \ |
| 1059 | ((msg_hdr >> 16) & 0xFFFF) |
| 1060 | |
| 1061 | typedef struct { |
| 1062 | union { |
| 1063 | struct { |
| 1064 | u64 hdr; |
| 1065 | u64 body[7]; |
| 1066 | }; |
| 1067 | u64 words[8]; |
| 1068 | }; |
| 1069 | } nx_fw_msg_t; |
| 1070 | |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 1071 | typedef struct { |
Dhananjay Phadke | 2edbb45 | 2009-01-14 20:47:30 -0800 | [diff] [blame] | 1072 | __le64 qhdr; |
| 1073 | __le64 req_hdr; |
| 1074 | __le64 words[6]; |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 1075 | } nx_nic_req_t; |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 1076 | |
| 1077 | typedef struct { |
| 1078 | u8 op; |
| 1079 | u8 tag; |
| 1080 | u8 mac_addr[6]; |
| 1081 | } nx_mac_req_t; |
| 1082 | |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 1083 | #define MAX_PENDING_DESC_BLOCK_SIZE 64 |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 1084 | |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 1085 | #define NETXEN_NIC_MSI_ENABLED 0x02 |
| 1086 | #define NETXEN_NIC_MSIX_ENABLED 0x04 |
Narender Kumar | 1bb482f | 2009-08-23 08:35:09 +0000 | [diff] [blame] | 1087 | #define NETXEN_NIC_LRO_ENABLED 0x08 |
Narender Kumar | fa3ce35 | 2009-08-24 19:23:28 +0000 | [diff] [blame] | 1088 | #define NETXEN_NIC_BRIDGE_ENABLED 0X10 |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 1089 | #define NETXEN_IS_MSI_FAMILY(adapter) \ |
| 1090 | ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED)) |
| 1091 | |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 1092 | #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 1093 | #define NETXEN_MSIX_TBL_SPACE 8192 |
| 1094 | #define NETXEN_PCI_REG_MSIX_TBL 0x44 |
| 1095 | |
| 1096 | #define NETXEN_DB_MAPSIZE_BYTES 0x1000 |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 1097 | |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 1098 | #define NETXEN_NETDEV_WEIGHT 128 |
Dhananjay Phadke | cd1f816 | 2008-07-21 19:44:09 -0700 | [diff] [blame] | 1099 | #define NETXEN_ADAPTER_UP_MAGIC 777 |
| 1100 | #define NETXEN_NIC_PEG_TUNE 0 |
| 1101 | |
Dhananjay Phadke | 6a581e9 | 2009-09-05 17:43:08 +0000 | [diff] [blame] | 1102 | #define __NX_FW_ATTACHED 0 |
| 1103 | #define __NX_DEV_UP 1 |
| 1104 | #define __NX_RESETTING 2 |
| 1105 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 1106 | struct netxen_dummy_dma { |
| 1107 | void *addr; |
| 1108 | dma_addr_t phys_addr; |
| 1109 | }; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1110 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1111 | struct netxen_adapter { |
| 1112 | struct netxen_hardware_context ahw; |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 1113 | |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1114 | struct net_device *netdev; |
| 1115 | struct pci_dev *pdev; |
Dhananjay Phadke | 5cf4d32 | 2009-05-05 19:05:07 +0000 | [diff] [blame] | 1116 | struct list_head mac_list; |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 1117 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1118 | u32 curr_window; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1119 | u32 crb_win; |
| 1120 | rwlock_t adapter_lock; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1121 | |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1122 | spinlock_t tx_clean_lock; |
Dhananjay Phadke | ba53e6b | 2008-03-17 19:59:50 -0700 | [diff] [blame] | 1123 | |
Dhananjay Phadke | 71dcddb | 2009-04-07 22:50:43 +0000 | [diff] [blame] | 1124 | u16 num_txd; |
| 1125 | u16 num_rxd; |
| 1126 | u16 num_jumbo_rxd; |
| 1127 | u16 num_lro_rxd; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1128 | |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1129 | u8 max_rds_rings; |
| 1130 | u8 max_sds_rings; |
| 1131 | u8 driver_mismatch; |
| 1132 | u8 msix_supported; |
| 1133 | u8 rx_csum; |
| 1134 | u8 pci_using_dac; |
| 1135 | u8 portnum; |
| 1136 | u8 physical_port; |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 1137 | |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1138 | u8 mc_enabled; |
| 1139 | u8 max_mc_count; |
Dhananjay Phadke | f6d21f4 | 2009-04-07 22:50:46 +0000 | [diff] [blame] | 1140 | u8 rss_supported; |
Amit Kumar Salecha | e424fa9 | 2009-08-13 07:03:00 +0000 | [diff] [blame] | 1141 | u8 link_changed; |
Dhananjay Phadke | 6a581e9 | 2009-09-05 17:43:08 +0000 | [diff] [blame] | 1142 | u8 fw_wait_cnt; |
| 1143 | u8 fw_fail_cnt; |
Amit Kumar Salecha | 74c520d | 2009-09-11 11:28:14 +0000 | [diff] [blame] | 1144 | u8 tx_timeo_cnt; |
| 1145 | u8 need_fw_reset; |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 1146 | |
| 1147 | u8 has_link_events; |
Dhananjay Phadke | 67c38fc | 2009-07-01 11:41:43 +0000 | [diff] [blame] | 1148 | u8 fw_type; |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1149 | u16 tx_context_id; |
| 1150 | u16 mtu; |
| 1151 | u16 is_up; |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 1152 | |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1153 | u16 link_speed; |
| 1154 | u16 link_duplex; |
| 1155 | u16 link_autoneg; |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 1156 | u16 module_type; |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1157 | |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 1158 | u32 capabilities; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1159 | u32 flags; |
| 1160 | u32 irq; |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1161 | u32 temp; |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 1162 | |
Amit Kumar Salecha | 195c5f9 | 2009-09-05 17:43:10 +0000 | [diff] [blame] | 1163 | u32 int_vec_bit; |
Dhananjay Phadke | 6a581e9 | 2009-09-05 17:43:08 +0000 | [diff] [blame] | 1164 | u32 heartbit; |
Dhananjay Phadke | 7a2469c | 2009-05-08 22:02:27 +0000 | [diff] [blame] | 1165 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1166 | struct netxen_adapter_stats stats; |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 1167 | |
Dhananjay Phadke | becf46a | 2009-03-09 08:50:55 +0000 | [diff] [blame] | 1168 | struct netxen_recv_context recv_ctx; |
Dhananjay Phadke | 4ea528a | 2009-04-28 15:29:10 +0000 | [diff] [blame] | 1169 | struct nx_host_tx_ring *tx_ring; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1170 | |
Dhananjay Phadke | 3d0a3cc | 2009-05-05 19:05:08 +0000 | [diff] [blame] | 1171 | int (*macaddr_set) (struct netxen_adapter *, u8 *); |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1172 | int (*set_mtu) (struct netxen_adapter *, int); |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 1173 | int (*set_promisc) (struct netxen_adapter *, u32); |
Dhananjay Phadke | 3d0a3cc | 2009-05-05 19:05:08 +0000 | [diff] [blame] | 1174 | void (*set_multi) (struct net_device *); |
Dhananjay Phadke | 3ad4467 | 2009-08-24 19:23:27 +0000 | [diff] [blame] | 1175 | int (*phy_read) (struct netxen_adapter *, u32 reg, u32 *); |
| 1176 | int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val); |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 1177 | int (*init_port) (struct netxen_adapter *, int); |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1178 | int (*stop_port) (struct netxen_adapter *); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1179 | |
Amit Kumar Salecha | 195c5f9 | 2009-09-05 17:43:10 +0000 | [diff] [blame] | 1180 | u32 (*crb_read)(struct netxen_adapter *, ulong); |
| 1181 | int (*crb_write)(struct netxen_adapter *, ulong, u32); |
| 1182 | |
Amit Kumar Salecha | 1f5e055 | 2009-10-13 05:31:41 +0000 | [diff] [blame] | 1183 | int (*pci_mem_read)(struct netxen_adapter *, u64, u64 *); |
| 1184 | int (*pci_mem_write)(struct netxen_adapter *, u64, u64); |
Amit Kumar Salecha | 195c5f9 | 2009-09-05 17:43:10 +0000 | [diff] [blame] | 1185 | |
Dhananjay Phadke | 47abe35 | 2009-10-13 05:31:42 +0000 | [diff] [blame^] | 1186 | int (*pci_set_window)(struct netxen_adapter *, u64, u32 *); |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1187 | |
Amit Kumar Salecha | 195c5f9 | 2009-09-05 17:43:10 +0000 | [diff] [blame] | 1188 | u32 (*io_read)(struct netxen_adapter *, void __iomem *); |
| 1189 | void (*io_write)(struct netxen_adapter *, void __iomem *, u32); |
| 1190 | |
| 1191 | void __iomem *tgt_mask_reg; |
| 1192 | void __iomem *pci_int_reg; |
| 1193 | void __iomem *tgt_status_reg; |
| 1194 | void __iomem *crb_int_state_reg; |
| 1195 | void __iomem *isr_int_vec; |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1196 | |
| 1197 | struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER]; |
| 1198 | |
| 1199 | struct netxen_dummy_dma dummy_dma; |
| 1200 | |
Dhananjay Phadke | 6a581e9 | 2009-09-05 17:43:08 +0000 | [diff] [blame] | 1201 | struct delayed_work fw_work; |
| 1202 | |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1203 | struct work_struct tx_timeout_task; |
| 1204 | |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1205 | nx_nic_intr_coalesce_t coal; |
Dhananjay Phadke | f7185c7 | 2009-04-28 15:29:11 +0000 | [diff] [blame] | 1206 | |
Dhananjay Phadke | 6a581e9 | 2009-09-05 17:43:08 +0000 | [diff] [blame] | 1207 | unsigned long state; |
Dhananjay Phadke | 4f96b98 | 2009-07-26 20:07:42 +0000 | [diff] [blame] | 1208 | u32 resv5; |
Dhananjay Phadke | f7185c7 | 2009-04-28 15:29:11 +0000 | [diff] [blame] | 1209 | u32 fw_version; |
| 1210 | const struct firmware *fw; |
Dhananjay Phadke | 1b1f789 | 2009-04-07 22:50:39 +0000 | [diff] [blame] | 1211 | }; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1212 | |
Dhananjay Phadke | 7d6fd5e | 2009-08-23 08:35:13 +0000 | [diff] [blame] | 1213 | int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port); |
Dhananjay Phadke | 7d6fd5e | 2009-08-23 08:35:13 +0000 | [diff] [blame] | 1214 | int netxen_niu_disable_xg_port(struct netxen_adapter *adapter); |
| 1215 | |
Dhananjay Phadke | 3ad4467 | 2009-08-24 19:23:27 +0000 | [diff] [blame] | 1216 | int nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val); |
| 1217 | int nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1218 | |
| 1219 | /* Functions available from netxen_nic_hw.c */ |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 1220 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu); |
| 1221 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu); |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1222 | |
Dhananjay Phadke | 3d0a3cc | 2009-05-05 19:05:08 +0000 | [diff] [blame] | 1223 | int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr); |
| 1224 | int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr); |
| 1225 | |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1226 | #define NXRD32(adapter, off) \ |
Amit Kumar Salecha | 195c5f9 | 2009-09-05 17:43:10 +0000 | [diff] [blame] | 1227 | (adapter->crb_read(adapter, off)) |
Dhananjay Phadke | f98a9f6 | 2009-04-07 22:50:45 +0000 | [diff] [blame] | 1228 | #define NXWR32(adapter, off, val) \ |
Amit Kumar Salecha | 195c5f9 | 2009-09-05 17:43:10 +0000 | [diff] [blame] | 1229 | (adapter->crb_write(adapter, off, val)) |
| 1230 | #define NXRDIO(adapter, addr) \ |
| 1231 | (adapter->io_read(adapter, addr)) |
| 1232 | #define NXWRIO(adapter, addr, val) \ |
| 1233 | (adapter->io_write(adapter, addr, val)) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1234 | |
Dhananjay Phadke | c9517e5 | 2009-08-24 19:23:26 +0000 | [diff] [blame] | 1235 | int netxen_pcie_sem_lock(struct netxen_adapter *, int, u32); |
| 1236 | void netxen_pcie_sem_unlock(struct netxen_adapter *, int); |
| 1237 | |
| 1238 | #define netxen_rom_lock(a) \ |
| 1239 | netxen_pcie_sem_lock((a), 2, NETXEN_ROM_LOCK_ID) |
| 1240 | #define netxen_rom_unlock(a) \ |
| 1241 | netxen_pcie_sem_unlock((a), 2) |
| 1242 | #define netxen_phy_lock(a) \ |
| 1243 | netxen_pcie_sem_lock((a), 3, NETXEN_PHY_LOCK_ID) |
| 1244 | #define netxen_phy_unlock(a) \ |
| 1245 | netxen_pcie_sem_unlock((a), 3) |
| 1246 | #define netxen_api_lock(a) \ |
| 1247 | netxen_pcie_sem_lock((a), 5, 0) |
| 1248 | #define netxen_api_unlock(a) \ |
| 1249 | netxen_pcie_sem_unlock((a), 5) |
| 1250 | #define netxen_sw_lock(a) \ |
| 1251 | netxen_pcie_sem_lock((a), 6, 0) |
| 1252 | #define netxen_sw_unlock(a) \ |
| 1253 | netxen_pcie_sem_unlock((a), 6) |
| 1254 | #define crb_win_lock(a) \ |
| 1255 | netxen_pcie_sem_lock((a), 7, NETXEN_CRB_WIN_LOCK_ID) |
| 1256 | #define crb_win_unlock(a) \ |
| 1257 | netxen_pcie_sem_unlock((a), 7) |
| 1258 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1259 | int netxen_nic_get_board_info(struct netxen_adapter *adapter); |
Dhananjay Phadke | 0b72e65 | 2009-03-13 14:52:02 +0000 | [diff] [blame] | 1260 | int netxen_nic_wol_supported(struct netxen_adapter *adapter); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame] | 1261 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1262 | /* Functions from netxen_nic_init.c */ |
Dhananjay Phadke | 83ac51f | 2009-07-26 20:07:39 +0000 | [diff] [blame] | 1263 | int netxen_init_dummy_dma(struct netxen_adapter *adapter); |
| 1264 | void netxen_free_dummy_dma(struct netxen_adapter *adapter); |
| 1265 | |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 1266 | int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val); |
| 1267 | int netxen_load_firmware(struct netxen_adapter *adapter); |
Dhananjay Phadke | 67c38fc | 2009-07-01 11:41:43 +0000 | [diff] [blame] | 1268 | int netxen_need_fw_reset(struct netxen_adapter *adapter); |
Dhananjay Phadke | f7185c7 | 2009-04-28 15:29:11 +0000 | [diff] [blame] | 1269 | void netxen_request_firmware(struct netxen_adapter *adapter); |
| 1270 | void netxen_release_firmware(struct netxen_adapter *adapter); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1271 | int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose); |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 1272 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1273 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp); |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 1274 | int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
Amit S. Kale | 27d2ab5 | 2007-02-05 07:40:49 -0800 | [diff] [blame] | 1275 | u8 *bytes, size_t size); |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 1276 | int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr, |
Amit S. Kale | 27d2ab5 | 2007-02-05 07:40:49 -0800 | [diff] [blame] | 1277 | u8 *bytes, size_t size); |
| 1278 | int netxen_flash_unlock(struct netxen_adapter *adapter); |
| 1279 | int netxen_backup_crbinit(struct netxen_adapter *adapter); |
| 1280 | int netxen_flash_erase_secondary(struct netxen_adapter *adapter); |
| 1281 | int netxen_flash_erase_primary(struct netxen_adapter *adapter); |
Amit S. Kale | e45d9ab | 2007-02-09 05:49:08 -0800 | [diff] [blame] | 1282 | void netxen_halt_pegs(struct netxen_adapter *adapter); |
Amit S. Kale | 27d2ab5 | 2007-02-05 07:40:49 -0800 | [diff] [blame] | 1283 | |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1284 | int netxen_rom_se(struct netxen_adapter *adapter, int addr); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1285 | |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 1286 | int netxen_alloc_sw_resources(struct netxen_adapter *adapter); |
| 1287 | void netxen_free_sw_resources(struct netxen_adapter *adapter); |
| 1288 | |
Amit Kumar Salecha | 195c5f9 | 2009-09-05 17:43:10 +0000 | [diff] [blame] | 1289 | void netxen_setup_hwops(struct netxen_adapter *adapter); |
| 1290 | void __iomem *netxen_get_ioaddr(struct netxen_adapter *, u32); |
| 1291 | |
Dhananjay Phadke | 2956640 | 2008-07-21 19:44:04 -0700 | [diff] [blame] | 1292 | int netxen_alloc_hw_resources(struct netxen_adapter *adapter); |
| 1293 | void netxen_free_hw_resources(struct netxen_adapter *adapter); |
| 1294 | |
| 1295 | void netxen_release_rx_buffers(struct netxen_adapter *adapter); |
| 1296 | void netxen_release_tx_buffers(struct netxen_adapter *adapter); |
| 1297 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1298 | int netxen_init_firmware(struct netxen_adapter *adapter); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1299 | void netxen_nic_clear_stats(struct netxen_adapter *adapter); |
David Howells | 6d5aefb | 2006-12-05 19:36:26 +0000 | [diff] [blame] | 1300 | void netxen_watchdog_task(struct work_struct *work); |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 1301 | void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid, |
| 1302 | struct nx_host_rds_ring *rds_ring); |
Dhananjay Phadke | 05aaa02 | 2008-03-17 19:59:49 -0700 | [diff] [blame] | 1303 | int netxen_process_cmd_ring(struct netxen_adapter *adapter); |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 1304 | int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max); |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 1305 | void netxen_p2_nic_set_multi(struct net_device *netdev); |
| 1306 | void netxen_p3_nic_set_multi(struct net_device *netdev); |
Dhananjay Phadke | 06e9d9f | 2009-01-14 20:49:22 -0800 | [diff] [blame] | 1307 | void netxen_p3_free_mac_list(struct netxen_adapter *adapter); |
Dhananjay Phadke | 3ad4467 | 2009-08-24 19:23:27 +0000 | [diff] [blame] | 1308 | int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode); |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 1309 | int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32); |
Dhananjay Phadke | cd1f816 | 2008-07-21 19:44:09 -0700 | [diff] [blame] | 1310 | int netxen_config_intr_coalesce(struct netxen_adapter *adapter); |
Dhananjay Phadke | d8b100c | 2009-03-13 14:52:05 +0000 | [diff] [blame] | 1311 | int netxen_config_rss(struct netxen_adapter *adapter, int enable); |
Dhananjay Phadke | 6598b16 | 2009-07-26 20:07:37 +0000 | [diff] [blame] | 1312 | int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd); |
Dhananjay Phadke | 3bf26ce | 2009-04-07 22:50:42 +0000 | [diff] [blame] | 1313 | int netxen_linkevent_request(struct netxen_adapter *adapter, int enable); |
| 1314 | void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup); |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 1315 | |
Dhananjay Phadke | 9ad2764 | 2008-08-01 03:14:59 -0700 | [diff] [blame] | 1316 | int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1317 | int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu); |
Narender Kumar | 1bb482f | 2009-08-23 08:35:09 +0000 | [diff] [blame] | 1318 | int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable); |
Narender Kumar | fa3ce35 | 2009-08-24 19:23:28 +0000 | [diff] [blame] | 1319 | int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable); |
Narender Kumar | 1bb482f | 2009-08-23 08:35:09 +0000 | [diff] [blame] | 1320 | int netxen_send_lro_cleanup(struct netxen_adapter *adapter); |
Dhananjay Phadke | 48bfd1e | 2008-07-21 19:44:06 -0700 | [diff] [blame] | 1321 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1322 | int netxen_nic_set_mac(struct net_device *netdev, void *p); |
| 1323 | struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev); |
| 1324 | |
Dhananjay Phadke | c9fc891 | 2008-07-21 19:44:07 -0700 | [diff] [blame] | 1325 | void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter, |
Dhananjay Phadke | cb2107b | 2009-06-17 17:27:25 +0000 | [diff] [blame] | 1326 | struct nx_host_tx_ring *tx_ring); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1327 | |
Amit Kumar Salecha | 7042cd8 | 2009-07-27 11:15:54 -0700 | [diff] [blame] | 1328 | /* Functions from netxen_nic_main.c */ |
| 1329 | int netxen_nic_reset_context(struct netxen_adapter *); |
| 1330 | |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1331 | /* |
| 1332 | * NetXen Board information |
| 1333 | */ |
| 1334 | |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1335 | #define NETXEN_MAX_SHORT_NAME 32 |
Amit S. Kale | 71bd787 | 2006-12-01 05:36:22 -0800 | [diff] [blame] | 1336 | struct netxen_brdinfo { |
Dhananjay Phadke | e98e335 | 2009-04-07 22:50:38 +0000 | [diff] [blame] | 1337 | int brdtype; /* type of board */ |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1338 | long ports; /* max no of physical ports */ |
| 1339 | char short_name[NETXEN_MAX_SHORT_NAME]; |
Amit S. Kale | 71bd787 | 2006-12-01 05:36:22 -0800 | [diff] [blame] | 1340 | }; |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1341 | |
Amit S. Kale | 71bd787 | 2006-12-01 05:36:22 -0800 | [diff] [blame] | 1342 | static const struct netxen_brdinfo netxen_boards[] = { |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1343 | {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"}, |
| 1344 | {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"}, |
| 1345 | {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"}, |
| 1346 | {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"}, |
| 1347 | {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"}, |
| 1348 | {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"}, |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1349 | {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "}, |
| 1350 | {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"}, |
| 1351 | {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"}, |
| 1352 | {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"}, |
| 1353 | {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"}, |
| 1354 | {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"}, |
| 1355 | {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"}, |
| 1356 | {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"}, |
Dhananjay Phadke | a70f939 | 2008-08-01 03:14:56 -0700 | [diff] [blame] | 1357 | {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"}, |
| 1358 | {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"}, |
| 1359 | {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"}, |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1360 | {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"}, |
| 1361 | {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"} |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1362 | }; |
| 1363 | |
Denis Cheng | ff8ac60 | 2007-09-02 18:30:18 +0800 | [diff] [blame] | 1364 | #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards) |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1365 | |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1366 | static inline void get_brd_name_by_type(u32 type, char *name) |
| 1367 | { |
| 1368 | int i, found = 0; |
| 1369 | for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) { |
| 1370 | if (netxen_boards[i].brdtype == type) { |
| 1371 | strcpy(name, netxen_boards[i].short_name); |
| 1372 | found = 1; |
| 1373 | break; |
| 1374 | } |
| 1375 | |
| 1376 | } |
| 1377 | if (!found) |
| 1378 | name = "Unknown"; |
| 1379 | } |
| 1380 | |
Dhananjay Phadke | cb2107b | 2009-06-17 17:27:25 +0000 | [diff] [blame] | 1381 | static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring) |
| 1382 | { |
| 1383 | smp_mb(); |
| 1384 | return find_diff_among(tx_ring->producer, |
| 1385 | tx_ring->sw_consumer, tx_ring->num_desc); |
| 1386 | |
| 1387 | } |
| 1388 | |
Dhananjay Phadke | 9dc28ef | 2008-08-08 00:08:39 -0700 | [diff] [blame] | 1389 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac); |
| 1390 | int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1391 | extern void netxen_change_ringparam(struct netxen_adapter *adapter); |
| 1392 | extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, |
| 1393 | int *valp); |
| 1394 | |
Stephen Hemminger | 0fc0b73 | 2009-09-02 01:03:33 -0700 | [diff] [blame] | 1395 | extern const struct ethtool_ops netxen_nic_ethtool_ops; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1396 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1397 | #endif /* __NETXEN_NIC_H_ */ |