Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2013 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Author: Jani Nikula <jani.nikula@intel.com> |
| 24 | */ |
| 25 | |
| 26 | #include <drm/drmP.h> |
Matt Roper | c6f95f2 | 2015-01-22 16:50:32 -0800 | [diff] [blame] | 27 | #include <drm/drm_atomic_helper.h> |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 28 | #include <drm/drm_crtc.h> |
| 29 | #include <drm/drm_edid.h> |
| 30 | #include <drm/i915_drm.h> |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 31 | #include <drm/drm_panel.h> |
Jani Nikula | 7e9804f | 2015-01-16 14:27:23 +0200 | [diff] [blame] | 32 | #include <drm/drm_mipi_dsi.h> |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 33 | #include <linux/slab.h> |
Shobhit Kumar | fc45e82 | 2015-06-26 14:32:09 +0530 | [diff] [blame] | 34 | #include <linux/gpio/consumer.h> |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 35 | #include "i915_drv.h" |
| 36 | #include "intel_drv.h" |
| 37 | #include "intel_dsi.h" |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 38 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 39 | static const struct { |
| 40 | u16 panel_id; |
| 41 | struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id); |
| 42 | } intel_dsi_drivers[] = { |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 43 | { |
| 44 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 45 | .init = vbt_panel_init, |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 46 | }, |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 47 | }; |
| 48 | |
Ramalingam C | 43367ec | 2016-04-07 14:36:06 +0530 | [diff] [blame] | 49 | enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) |
| 50 | { |
| 51 | /* It just so happens the VBT matches register contents. */ |
| 52 | switch (fmt) { |
| 53 | case VID_MODE_FORMAT_RGB888: |
| 54 | return MIPI_DSI_FMT_RGB888; |
| 55 | case VID_MODE_FORMAT_RGB666: |
| 56 | return MIPI_DSI_FMT_RGB666; |
| 57 | case VID_MODE_FORMAT_RGB666_PACKED: |
| 58 | return MIPI_DSI_FMT_RGB666_PACKED; |
| 59 | case VID_MODE_FORMAT_RGB565: |
| 60 | return MIPI_DSI_FMT_RGB565; |
| 61 | default: |
| 62 | MISSING_CASE(fmt); |
| 63 | return MIPI_DSI_FMT_RGB666; |
| 64 | } |
| 65 | } |
| 66 | |
Jani Nikula | 7f6a6a4 | 2015-01-16 14:27:19 +0200 | [diff] [blame] | 67 | static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
Jani Nikula | 3b1808b | 2015-01-16 14:27:18 +0200 | [diff] [blame] | 68 | { |
| 69 | struct drm_encoder *encoder = &intel_dsi->base.base; |
| 70 | struct drm_device *dev = encoder->dev; |
| 71 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | 3b1808b | 2015-01-16 14:27:18 +0200 | [diff] [blame] | 72 | u32 mask; |
| 73 | |
| 74 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | |
| 75 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; |
| 76 | |
| 77 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) |
| 78 | DRM_ERROR("DPI FIFOs are not empty\n"); |
| 79 | } |
| 80 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 81 | static void write_data(struct drm_i915_private *dev_priv, |
| 82 | i915_reg_t reg, |
Jani Nikula | 7e9804f | 2015-01-16 14:27:23 +0200 | [diff] [blame] | 83 | const u8 *data, u32 len) |
| 84 | { |
| 85 | u32 i, j; |
| 86 | |
| 87 | for (i = 0; i < len; i += 4) { |
| 88 | u32 val = 0; |
| 89 | |
| 90 | for (j = 0; j < min_t(u32, len - i, 4); j++) |
| 91 | val |= *data++ << 8 * j; |
| 92 | |
| 93 | I915_WRITE(reg, val); |
| 94 | } |
| 95 | } |
| 96 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 97 | static void read_data(struct drm_i915_private *dev_priv, |
| 98 | i915_reg_t reg, |
Jani Nikula | 7e9804f | 2015-01-16 14:27:23 +0200 | [diff] [blame] | 99 | u8 *data, u32 len) |
| 100 | { |
| 101 | u32 i, j; |
| 102 | |
| 103 | for (i = 0; i < len; i += 4) { |
| 104 | u32 val = I915_READ(reg); |
| 105 | |
| 106 | for (j = 0; j < min_t(u32, len - i, 4); j++) |
| 107 | *data++ = val >> 8 * j; |
| 108 | } |
| 109 | } |
| 110 | |
| 111 | static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, |
| 112 | const struct mipi_dsi_msg *msg) |
| 113 | { |
| 114 | struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); |
| 115 | struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; |
| 116 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 117 | enum port port = intel_dsi_host->port; |
| 118 | struct mipi_dsi_packet packet; |
| 119 | ssize_t ret; |
| 120 | const u8 *header, *data; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 121 | i915_reg_t data_reg, ctrl_reg; |
| 122 | u32 data_mask, ctrl_mask; |
Jani Nikula | 7e9804f | 2015-01-16 14:27:23 +0200 | [diff] [blame] | 123 | |
| 124 | ret = mipi_dsi_create_packet(&packet, msg); |
| 125 | if (ret < 0) |
| 126 | return ret; |
| 127 | |
| 128 | header = packet.header; |
| 129 | data = packet.payload; |
| 130 | |
| 131 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) { |
| 132 | data_reg = MIPI_LP_GEN_DATA(port); |
| 133 | data_mask = LP_DATA_FIFO_FULL; |
| 134 | ctrl_reg = MIPI_LP_GEN_CTRL(port); |
| 135 | ctrl_mask = LP_CTRL_FIFO_FULL; |
| 136 | } else { |
| 137 | data_reg = MIPI_HS_GEN_DATA(port); |
| 138 | data_mask = HS_DATA_FIFO_FULL; |
| 139 | ctrl_reg = MIPI_HS_GEN_CTRL(port); |
| 140 | ctrl_mask = HS_CTRL_FIFO_FULL; |
| 141 | } |
| 142 | |
| 143 | /* note: this is never true for reads */ |
| 144 | if (packet.payload_length) { |
| 145 | |
| 146 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50)) |
| 147 | DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); |
| 148 | |
| 149 | write_data(dev_priv, data_reg, packet.payload, |
| 150 | packet.payload_length); |
| 151 | } |
| 152 | |
| 153 | if (msg->rx_len) { |
| 154 | I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); |
| 155 | } |
| 156 | |
| 157 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) { |
| 158 | DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); |
| 159 | } |
| 160 | |
| 161 | I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); |
| 162 | |
| 163 | /* ->rx_len is set only for reads */ |
| 164 | if (msg->rx_len) { |
| 165 | data_mask = GEN_READ_DATA_AVAIL; |
| 166 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50)) |
| 167 | DRM_ERROR("Timeout waiting for read data.\n"); |
| 168 | |
| 169 | read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); |
| 170 | } |
| 171 | |
| 172 | /* XXX: fix for reads and writes */ |
| 173 | return 4 + packet.payload_length; |
| 174 | } |
| 175 | |
| 176 | static int intel_dsi_host_attach(struct mipi_dsi_host *host, |
| 177 | struct mipi_dsi_device *dsi) |
| 178 | { |
| 179 | return 0; |
| 180 | } |
| 181 | |
| 182 | static int intel_dsi_host_detach(struct mipi_dsi_host *host, |
| 183 | struct mipi_dsi_device *dsi) |
| 184 | { |
| 185 | return 0; |
| 186 | } |
| 187 | |
| 188 | static const struct mipi_dsi_host_ops intel_dsi_host_ops = { |
| 189 | .attach = intel_dsi_host_attach, |
| 190 | .detach = intel_dsi_host_detach, |
| 191 | .transfer = intel_dsi_host_transfer, |
| 192 | }; |
| 193 | |
| 194 | static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, |
| 195 | enum port port) |
| 196 | { |
| 197 | struct intel_dsi_host *host; |
| 198 | struct mipi_dsi_device *device; |
| 199 | |
| 200 | host = kzalloc(sizeof(*host), GFP_KERNEL); |
| 201 | if (!host) |
| 202 | return NULL; |
| 203 | |
| 204 | host->base.ops = &intel_dsi_host_ops; |
| 205 | host->intel_dsi = intel_dsi; |
| 206 | host->port = port; |
| 207 | |
| 208 | /* |
| 209 | * We should call mipi_dsi_host_register(&host->base) here, but we don't |
| 210 | * have a host->dev, and we don't have OF stuff either. So just use the |
| 211 | * dsi framework as a library and hope for the best. Create the dsi |
| 212 | * devices by ourselves here too. Need to be careful though, because we |
| 213 | * don't initialize any of the driver model devices here. |
| 214 | */ |
| 215 | device = kzalloc(sizeof(*device), GFP_KERNEL); |
| 216 | if (!device) { |
| 217 | kfree(host); |
| 218 | return NULL; |
| 219 | } |
| 220 | |
| 221 | device->host = &host->base; |
| 222 | host->device = device; |
| 223 | |
| 224 | return host; |
| 225 | } |
| 226 | |
Jani Nikula | a2581a9 | 2015-01-16 14:27:26 +0200 | [diff] [blame] | 227 | /* |
| 228 | * send a video mode command |
| 229 | * |
| 230 | * XXX: commands with data in MIPI_DPI_DATA? |
| 231 | */ |
| 232 | static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, |
| 233 | enum port port) |
| 234 | { |
| 235 | struct drm_encoder *encoder = &intel_dsi->base.base; |
| 236 | struct drm_device *dev = encoder->dev; |
| 237 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 238 | u32 mask; |
| 239 | |
| 240 | /* XXX: pipe, hs */ |
| 241 | if (hs) |
| 242 | cmd &= ~DPI_LP_MODE; |
| 243 | else |
| 244 | cmd |= DPI_LP_MODE; |
| 245 | |
| 246 | /* clear bit */ |
| 247 | I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); |
| 248 | |
| 249 | /* XXX: old code skips write if control unchanged */ |
| 250 | if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) |
| 251 | DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); |
| 252 | |
| 253 | I915_WRITE(MIPI_DPI_CONTROL(port), cmd); |
| 254 | |
| 255 | mask = SPL_PKT_SENT_INTERRUPT; |
| 256 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) |
| 257 | DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); |
| 258 | |
| 259 | return 0; |
| 260 | } |
| 261 | |
Shobhit Kumar | e9fe51c | 2013-12-10 12:14:55 +0530 | [diff] [blame] | 262 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
Shobhit Kumar | 4ce8c9a | 2013-08-27 15:12:24 +0300 | [diff] [blame] | 263 | { |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 264 | mutex_lock(&dev_priv->sb_lock); |
Shobhit Kumar | 4ce8c9a | 2013-08-27 15:12:24 +0300 | [diff] [blame] | 265 | |
Shobhit Kumar | e9fe51c | 2013-12-10 12:14:55 +0530 | [diff] [blame] | 266 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
| 267 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); |
| 268 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); |
| 269 | udelay(150); |
| 270 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); |
| 271 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); |
Shobhit Kumar | 4ce8c9a | 2013-08-27 15:12:24 +0300 | [diff] [blame] | 272 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 273 | mutex_unlock(&dev_priv->sb_lock); |
Shobhit Kumar | 4ce8c9a | 2013-08-27 15:12:24 +0300 | [diff] [blame] | 274 | } |
| 275 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 276 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
| 277 | { |
Shobhit Kumar | dfba2e2 | 2014-04-14 11:18:24 +0530 | [diff] [blame] | 278 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 279 | } |
| 280 | |
| 281 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) |
| 282 | { |
Shobhit Kumar | dfba2e2 | 2014-04-14 11:18:24 +0530 | [diff] [blame] | 283 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 284 | } |
| 285 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 286 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 287 | struct intel_crtc_state *pipe_config) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 288 | { |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 289 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 290 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
| 291 | base); |
| 292 | struct intel_connector *intel_connector = intel_dsi->attached_connector; |
| 293 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 294 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
Ville Syrjälä | 47eacba | 2016-04-12 22:14:35 +0300 | [diff] [blame^] | 295 | int ret; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 296 | |
| 297 | DRM_DEBUG_KMS("\n"); |
| 298 | |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 299 | pipe_config->has_dsi_encoder = true; |
| 300 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 301 | if (fixed_mode) |
| 302 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
| 303 | |
Shobhit Kumar | f573de5 | 2014-07-30 20:32:37 +0530 | [diff] [blame] | 304 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
| 305 | adjusted_mode->flags = 0; |
| 306 | |
Jani Nikula | 4d1de97 | 2016-03-18 17:05:42 +0200 | [diff] [blame] | 307 | if (IS_BROXTON(dev_priv)) { |
| 308 | /* Dual link goes to DSI transcoder A. */ |
| 309 | if (intel_dsi->ports == BIT(PORT_C)) |
| 310 | pipe_config->cpu_transcoder = TRANSCODER_DSI_C; |
| 311 | else |
| 312 | pipe_config->cpu_transcoder = TRANSCODER_DSI_A; |
| 313 | } |
| 314 | |
Ville Syrjälä | 47eacba | 2016-04-12 22:14:35 +0300 | [diff] [blame^] | 315 | ret = intel_compute_dsi_pll(encoder, pipe_config); |
| 316 | if (ret) |
| 317 | return false; |
| 318 | |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 319 | pipe_config->clock_set = true; |
| 320 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 321 | return true; |
| 322 | } |
| 323 | |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 324 | static void bxt_dsi_device_ready(struct intel_encoder *encoder) |
Gaurav K Singh | 5505a24 | 2014-12-04 10:58:47 +0530 | [diff] [blame] | 325 | { |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 326 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
Gaurav K Singh | 5505a24 | 2014-12-04 10:58:47 +0530 | [diff] [blame] | 327 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
Gaurav K Singh | 369602d | 2014-12-05 14:09:28 +0530 | [diff] [blame] | 328 | enum port port; |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 329 | u32 val; |
Gaurav K Singh | 5505a24 | 2014-12-04 10:58:47 +0530 | [diff] [blame] | 330 | |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 331 | DRM_DEBUG_KMS("\n"); |
Gaurav K Singh | a9da9bc | 2014-12-05 14:13:41 +0530 | [diff] [blame] | 332 | |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 333 | /* Exit Low power state in 4 steps*/ |
Gaurav K Singh | 369602d | 2014-12-05 14:09:28 +0530 | [diff] [blame] | 334 | for_each_dsi_port(port, intel_dsi->ports) { |
Gaurav K Singh | 369602d | 2014-12-05 14:09:28 +0530 | [diff] [blame] | 335 | |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 336 | /* 1. Enable MIPI PHY transparent latch */ |
| 337 | val = I915_READ(BXT_MIPI_PORT_CTRL(port)); |
| 338 | I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); |
| 339 | usleep_range(2000, 2500); |
| 340 | |
| 341 | /* 2. Enter ULPS */ |
| 342 | val = I915_READ(MIPI_DEVICE_READY(port)); |
| 343 | val &= ~ULPS_STATE_MASK; |
| 344 | val |= (ULPS_STATE_ENTER | DEVICE_READY); |
| 345 | I915_WRITE(MIPI_DEVICE_READY(port), val); |
| 346 | usleep_range(2, 3); |
| 347 | |
| 348 | /* 3. Exit ULPS */ |
| 349 | val = I915_READ(MIPI_DEVICE_READY(port)); |
| 350 | val &= ~ULPS_STATE_MASK; |
| 351 | val |= (ULPS_STATE_EXIT | DEVICE_READY); |
| 352 | I915_WRITE(MIPI_DEVICE_READY(port), val); |
| 353 | usleep_range(1000, 1500); |
| 354 | |
| 355 | /* Clear ULPS and set device ready */ |
| 356 | val = I915_READ(MIPI_DEVICE_READY(port)); |
| 357 | val &= ~ULPS_STATE_MASK; |
| 358 | val |= DEVICE_READY; |
| 359 | I915_WRITE(MIPI_DEVICE_READY(port), val); |
Gaurav K Singh | 369602d | 2014-12-05 14:09:28 +0530 | [diff] [blame] | 360 | } |
Gaurav K Singh | 5505a24 | 2014-12-04 10:58:47 +0530 | [diff] [blame] | 361 | } |
| 362 | |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 363 | static void vlv_dsi_device_ready(struct intel_encoder *encoder) |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 364 | { |
| 365 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 366 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
| 367 | enum port port; |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 368 | u32 val; |
| 369 | |
| 370 | DRM_DEBUG_KMS("\n"); |
| 371 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 372 | mutex_lock(&dev_priv->sb_lock); |
Shobhit Kumar | 2095f9f | 2014-04-09 13:59:30 +0530 | [diff] [blame] | 373 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
| 374 | * needed everytime after power gate */ |
| 375 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 376 | mutex_unlock(&dev_priv->sb_lock); |
Shobhit Kumar | 2095f9f | 2014-04-09 13:59:30 +0530 | [diff] [blame] | 377 | |
| 378 | /* bandgap reset is needed after everytime we do power gate */ |
| 379 | band_gap_reset(dev_priv); |
| 380 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 381 | for_each_dsi_port(port, intel_dsi->ports) { |
Shobhit Kumar | aceb365 | 2014-07-03 16:35:41 +0530 | [diff] [blame] | 382 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 383 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
| 384 | usleep_range(2500, 3000); |
Shobhit Kumar | aceb365 | 2014-07-03 16:35:41 +0530 | [diff] [blame] | 385 | |
Gaurav K Singh | bf344e8 | 2014-12-07 16:13:54 +0530 | [diff] [blame] | 386 | /* Enable MIPI PHY transparent latch |
| 387 | * Common bit for both MIPI Port A & MIPI Port C |
| 388 | * No similar bit in MIPI Port C reg |
| 389 | */ |
Shobhit Kumar | 4ba7d93 | 2015-02-05 17:08:45 +0530 | [diff] [blame] | 390 | val = I915_READ(MIPI_PORT_CTRL(PORT_A)); |
Gaurav K Singh | bf344e8 | 2014-12-07 16:13:54 +0530 | [diff] [blame] | 391 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 392 | usleep_range(1000, 1500); |
Shobhit Kumar | aceb365 | 2014-07-03 16:35:41 +0530 | [diff] [blame] | 393 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 394 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
| 395 | usleep_range(2500, 3000); |
| 396 | |
| 397 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); |
| 398 | usleep_range(2500, 3000); |
| 399 | } |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 400 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 401 | |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 402 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
| 403 | { |
| 404 | struct drm_device *dev = encoder->base.dev; |
| 405 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 406 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 407 | vlv_dsi_device_ready(encoder); |
| 408 | else if (IS_BROXTON(dev)) |
| 409 | bxt_dsi_device_ready(encoder); |
| 410 | } |
| 411 | |
| 412 | static void intel_dsi_port_enable(struct intel_encoder *encoder) |
| 413 | { |
| 414 | struct drm_device *dev = encoder->base.dev; |
| 415 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 416 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
| 417 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
| 418 | enum port port; |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 419 | |
| 420 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 421 | u32 temp; |
| 422 | |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 423 | temp = I915_READ(VLV_CHICKEN_3); |
| 424 | temp &= ~PIXEL_OVERLAP_CNT_MASK | |
| 425 | intel_dsi->pixel_overlap << |
| 426 | PIXEL_OVERLAP_CNT_SHIFT; |
| 427 | I915_WRITE(VLV_CHICKEN_3, temp); |
| 428 | } |
| 429 | |
| 430 | for_each_dsi_port(port, intel_dsi->ports) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 431 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
| 432 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
| 433 | u32 temp; |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 434 | |
| 435 | temp = I915_READ(port_ctrl); |
| 436 | |
| 437 | temp &= ~LANE_CONFIGURATION_MASK; |
| 438 | temp &= ~DUAL_LINK_MODE_MASK; |
| 439 | |
Jani Nikula | 701d25b | 2016-03-18 17:05:43 +0200 | [diff] [blame] | 440 | if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 441 | temp |= (intel_dsi->dual_link - 1) |
| 442 | << DUAL_LINK_MODE_SHIFT; |
| 443 | temp |= intel_crtc->pipe ? |
| 444 | LANE_CONFIGURATION_DUAL_LINK_B : |
| 445 | LANE_CONFIGURATION_DUAL_LINK_A; |
| 446 | } |
| 447 | /* assert ip_tg_enable signal */ |
| 448 | I915_WRITE(port_ctrl, temp | DPI_ENABLE); |
| 449 | POSTING_READ(port_ctrl); |
| 450 | } |
| 451 | } |
| 452 | |
| 453 | static void intel_dsi_port_disable(struct intel_encoder *encoder) |
| 454 | { |
| 455 | struct drm_device *dev = encoder->base.dev; |
| 456 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 457 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
| 458 | enum port port; |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 459 | |
| 460 | for_each_dsi_port(port, intel_dsi->ports) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 461 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
| 462 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
| 463 | u32 temp; |
| 464 | |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 465 | /* de-assert ip_tg_enable signal */ |
Shashank Sharma | b389a45 | 2015-09-01 19:41:44 +0530 | [diff] [blame] | 466 | temp = I915_READ(port_ctrl); |
| 467 | I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); |
| 468 | POSTING_READ(port_ctrl); |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 469 | } |
| 470 | } |
| 471 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 472 | static void intel_dsi_enable(struct intel_encoder *encoder) |
| 473 | { |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 474 | struct drm_device *dev = encoder->base.dev; |
| 475 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 476 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
Jani Nikula | 4934b65 | 2015-01-22 15:01:35 +0200 | [diff] [blame] | 477 | enum port port; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 478 | |
| 479 | DRM_DEBUG_KMS("\n"); |
| 480 | |
Jani Nikula | 4934b65 | 2015-01-22 15:01:35 +0200 | [diff] [blame] | 481 | if (is_cmd_mode(intel_dsi)) { |
| 482 | for_each_dsi_port(port, intel_dsi->ports) |
| 483 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); |
| 484 | } else { |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 485 | msleep(20); /* XXX */ |
Jani Nikula | f03e417 | 2015-01-16 14:27:16 +0200 | [diff] [blame] | 486 | for_each_dsi_port(port, intel_dsi->ports) |
Jani Nikula | a2581a9 | 2015-01-16 14:27:26 +0200 | [diff] [blame] | 487 | dpi_send_cmd(intel_dsi, TURN_ON, false, port); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 488 | msleep(100); |
| 489 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 490 | drm_panel_enable(intel_dsi->panel); |
Shobhit Kumar | 2634fd7 | 2014-04-09 13:59:31 +0530 | [diff] [blame] | 491 | |
Jani Nikula | 7f6a6a4 | 2015-01-16 14:27:19 +0200 | [diff] [blame] | 492 | for_each_dsi_port(port, intel_dsi->ports) |
| 493 | wait_for_dsi_fifo_empty(intel_dsi, port); |
Shobhit Kumar | 1381308 | 2014-07-12 17:17:22 +0530 | [diff] [blame] | 494 | |
Gaurav K Singh | 5505a24 | 2014-12-04 10:58:47 +0530 | [diff] [blame] | 495 | intel_dsi_port_enable(encoder); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 496 | } |
Shobhit Kumar | b029e66 | 2015-06-26 14:32:10 +0530 | [diff] [blame] | 497 | |
| 498 | intel_panel_enable_backlight(intel_dsi->attached_connector); |
Shobhit Kumar | 2634fd7 | 2014-04-09 13:59:31 +0530 | [diff] [blame] | 499 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 500 | |
Jani Nikula | e3488e7 | 2015-11-27 12:21:44 +0200 | [diff] [blame] | 501 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder); |
| 502 | |
Shobhit Kumar | 2634fd7 | 2014-04-09 13:59:31 +0530 | [diff] [blame] | 503 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) |
| 504 | { |
Shobhit Kumar | 20e5bf6 | 2014-04-09 13:59:32 +0530 | [diff] [blame] | 505 | struct drm_device *dev = encoder->base.dev; |
| 506 | struct drm_i915_private *dev_priv = dev->dev_private; |
Shobhit Kumar | 2634fd7 | 2014-04-09 13:59:31 +0530 | [diff] [blame] | 507 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
Ville Syrjälä | 47eacba | 2016-04-12 22:14:35 +0300 | [diff] [blame^] | 508 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Jani Nikula | 7f6a6a4 | 2015-01-16 14:27:19 +0200 | [diff] [blame] | 509 | enum port port; |
Shobhit Kumar | 20e5bf6 | 2014-04-09 13:59:32 +0530 | [diff] [blame] | 510 | u32 tmp; |
Shobhit Kumar | 2634fd7 | 2014-04-09 13:59:31 +0530 | [diff] [blame] | 511 | |
| 512 | DRM_DEBUG_KMS("\n"); |
| 513 | |
Ville Syrjälä | f00b568 | 2016-03-15 16:40:03 +0200 | [diff] [blame] | 514 | /* |
| 515 | * The BIOS may leave the PLL in a wonky state where it doesn't |
| 516 | * lock. It needs to be fully powered down to fix it. |
| 517 | */ |
| 518 | intel_disable_dsi_pll(encoder); |
Ville Syrjälä | 47eacba | 2016-04-12 22:14:35 +0300 | [diff] [blame^] | 519 | intel_enable_dsi_pll(encoder, crtc->config); |
Ville Syrjälä | f00b568 | 2016-03-15 16:40:03 +0200 | [diff] [blame] | 520 | |
Ramalingam C | 58d4d32 | 2016-02-03 18:20:46 +0530 | [diff] [blame] | 521 | intel_dsi_prepare(encoder); |
Jani Nikula | e3488e7 | 2015-11-27 12:21:44 +0200 | [diff] [blame] | 522 | |
Shobhit Kumar | fc45e82 | 2015-06-26 14:32:09 +0530 | [diff] [blame] | 523 | /* Panel Enable over CRC PMIC */ |
| 524 | if (intel_dsi->gpio_panel) |
| 525 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); |
| 526 | |
| 527 | msleep(intel_dsi->panel_on_delay); |
| 528 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 529 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | cd2d34d | 2016-04-12 22:14:34 +0300 | [diff] [blame] | 530 | /* Disable DPOunit clock gating, can stall pipe */ |
Shashank Sharma | 37ab081 | 2015-09-01 19:41:42 +0530 | [diff] [blame] | 531 | tmp = I915_READ(DSPCLK_GATE_D); |
| 532 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; |
| 533 | I915_WRITE(DSPCLK_GATE_D, tmp); |
| 534 | } |
Shobhit Kumar | 2634fd7 | 2014-04-09 13:59:31 +0530 | [diff] [blame] | 535 | |
| 536 | /* put device in ready state */ |
| 537 | intel_dsi_device_ready(encoder); |
| 538 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 539 | drm_panel_prepare(intel_dsi->panel); |
Shobhit Kumar | 20e5bf6 | 2014-04-09 13:59:32 +0530 | [diff] [blame] | 540 | |
Jani Nikula | 7f6a6a4 | 2015-01-16 14:27:19 +0200 | [diff] [blame] | 541 | for_each_dsi_port(port, intel_dsi->ports) |
| 542 | wait_for_dsi_fifo_empty(intel_dsi, port); |
Shobhit Kumar | 1381308 | 2014-07-12 17:17:22 +0530 | [diff] [blame] | 543 | |
Shobhit Kumar | 2634fd7 | 2014-04-09 13:59:31 +0530 | [diff] [blame] | 544 | /* Enable port in pre-enable phase itself because as per hw team |
| 545 | * recommendation, port should be enabled befor plane & pipe */ |
| 546 | intel_dsi_enable(encoder); |
| 547 | } |
| 548 | |
| 549 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) |
| 550 | { |
| 551 | DRM_DEBUG_KMS("\n"); |
| 552 | |
| 553 | /* for DSI port enable has to be done before pipe |
| 554 | * and plane enable, so port enable is done in |
| 555 | * pre_enable phase itself unlike other encoders |
| 556 | */ |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 557 | } |
| 558 | |
Imre Deak | c315faf | 2014-05-27 19:00:09 +0300 | [diff] [blame] | 559 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
| 560 | { |
| 561 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
Jani Nikula | f03e417 | 2015-01-16 14:27:16 +0200 | [diff] [blame] | 562 | enum port port; |
Imre Deak | c315faf | 2014-05-27 19:00:09 +0300 | [diff] [blame] | 563 | |
| 564 | DRM_DEBUG_KMS("\n"); |
| 565 | |
Shobhit Kumar | b029e66 | 2015-06-26 14:32:10 +0530 | [diff] [blame] | 566 | intel_panel_disable_backlight(intel_dsi->attached_connector); |
| 567 | |
Imre Deak | c315faf | 2014-05-27 19:00:09 +0300 | [diff] [blame] | 568 | if (is_vid_mode(intel_dsi)) { |
| 569 | /* Send Shutdown command to the panel in LP mode */ |
Jani Nikula | f03e417 | 2015-01-16 14:27:16 +0200 | [diff] [blame] | 570 | for_each_dsi_port(port, intel_dsi->ports) |
Jani Nikula | a2581a9 | 2015-01-16 14:27:26 +0200 | [diff] [blame] | 571 | dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); |
Imre Deak | c315faf | 2014-05-27 19:00:09 +0300 | [diff] [blame] | 572 | msleep(10); |
| 573 | } |
| 574 | } |
| 575 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 576 | static void intel_dsi_disable(struct intel_encoder *encoder) |
| 577 | { |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 578 | struct drm_device *dev = encoder->base.dev; |
| 579 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 580 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 581 | enum port port; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 582 | u32 temp; |
| 583 | |
| 584 | DRM_DEBUG_KMS("\n"); |
| 585 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 586 | if (is_vid_mode(intel_dsi)) { |
Jani Nikula | 7f6a6a4 | 2015-01-16 14:27:19 +0200 | [diff] [blame] | 587 | for_each_dsi_port(port, intel_dsi->ports) |
| 588 | wait_for_dsi_fifo_empty(intel_dsi, port); |
Shobhit Kumar | 1381308 | 2014-07-12 17:17:22 +0530 | [diff] [blame] | 589 | |
Gaurav K Singh | 5505a24 | 2014-12-04 10:58:47 +0530 | [diff] [blame] | 590 | intel_dsi_port_disable(encoder); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 591 | msleep(2); |
| 592 | } |
| 593 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 594 | for_each_dsi_port(port, intel_dsi->ports) { |
| 595 | /* Panel commands can be sent when clock is in LP11 */ |
| 596 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); |
Shobhit Kumar | 339023e | 2014-04-09 13:59:34 +0530 | [diff] [blame] | 597 | |
Shashank Sharma | b389a45 | 2015-09-01 19:41:44 +0530 | [diff] [blame] | 598 | intel_dsi_reset_clocks(encoder, port); |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 599 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
Shobhit Kumar | 339023e | 2014-04-09 13:59:34 +0530 | [diff] [blame] | 600 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 601 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
| 602 | temp &= ~VID_MODE_FORMAT_MASK; |
| 603 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); |
Shobhit Kumar | 339023e | 2014-04-09 13:59:34 +0530 | [diff] [blame] | 604 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 605 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
| 606 | } |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 607 | /* if disable packets are sent before sending shutdown packet then in |
| 608 | * some next enable sequence send turn on packet error is observed */ |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 609 | drm_panel_disable(intel_dsi->panel); |
Shobhit Kumar | 1381308 | 2014-07-12 17:17:22 +0530 | [diff] [blame] | 610 | |
Jani Nikula | 7f6a6a4 | 2015-01-16 14:27:19 +0200 | [diff] [blame] | 611 | for_each_dsi_port(port, intel_dsi->ports) |
| 612 | wait_for_dsi_fifo_empty(intel_dsi, port); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 613 | } |
| 614 | |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 615 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 616 | { |
Shashank Sharma | b389a45 | 2015-09-01 19:41:44 +0530 | [diff] [blame] | 617 | struct drm_device *dev = encoder->base.dev; |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 618 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 619 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
| 620 | enum port port; |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 621 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 622 | DRM_DEBUG_KMS("\n"); |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 623 | for_each_dsi_port(port, intel_dsi->ports) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 624 | /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ |
| 625 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
| 626 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); |
| 627 | u32 val; |
ymohanma | be4fc04 | 2013-08-27 23:40:56 +0300 | [diff] [blame] | 628 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 629 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
| 630 | ULPS_STATE_ENTER); |
| 631 | usleep_range(2000, 2500); |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 632 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 633 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
| 634 | ULPS_STATE_EXIT); |
| 635 | usleep_range(2000, 2500); |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 636 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 637 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
| 638 | ULPS_STATE_ENTER); |
| 639 | usleep_range(2000, 2500); |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 640 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 641 | /* Wait till Clock lanes are in LP-00 state for MIPI Port A |
| 642 | * only. MIPI Port C has no similar bit for checking |
| 643 | */ |
Shashank Sharma | b389a45 | 2015-09-01 19:41:44 +0530 | [diff] [blame] | 644 | if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT) |
| 645 | == 0x00000), 30)) |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 646 | DRM_ERROR("DSI LP not going Low\n"); |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 647 | |
Shashank Sharma | b389a45 | 2015-09-01 19:41:44 +0530 | [diff] [blame] | 648 | /* Disable MIPI PHY transparent latch */ |
| 649 | val = I915_READ(port_ctrl); |
| 650 | I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 651 | usleep_range(1000, 1500); |
Shobhit Kumar | aceb365 | 2014-07-03 16:35:41 +0530 | [diff] [blame] | 652 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 653 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); |
| 654 | usleep_range(2000, 2500); |
| 655 | } |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 656 | |
Shashank Sharma | fe88fc6 | 2015-09-01 19:41:39 +0530 | [diff] [blame] | 657 | intel_disable_dsi_pll(encoder); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 658 | } |
Shobhit Kumar | 20e5bf6 | 2014-04-09 13:59:32 +0530 | [diff] [blame] | 659 | |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 660 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
| 661 | { |
Shobhit Kumar | 20e5bf6 | 2014-04-09 13:59:32 +0530 | [diff] [blame] | 662 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 663 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
| 664 | |
| 665 | DRM_DEBUG_KMS("\n"); |
| 666 | |
Imre Deak | c315faf | 2014-05-27 19:00:09 +0300 | [diff] [blame] | 667 | intel_dsi_disable(encoder); |
| 668 | |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 669 | intel_dsi_clear_device_ready(encoder); |
| 670 | |
Uma Shankar | d6e3af5 | 2016-02-18 13:49:26 +0200 | [diff] [blame] | 671 | if (!IS_BROXTON(dev_priv)) { |
| 672 | u32 val; |
| 673 | |
| 674 | val = I915_READ(DSPCLK_GATE_D); |
| 675 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; |
| 676 | I915_WRITE(DSPCLK_GATE_D, val); |
| 677 | } |
Shobhit Kumar | 20e5bf6 | 2014-04-09 13:59:32 +0530 | [diff] [blame] | 678 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 679 | drm_panel_unprepare(intel_dsi->panel); |
Shobhit Kumar | df38e65 | 2014-04-14 11:18:26 +0530 | [diff] [blame] | 680 | |
| 681 | msleep(intel_dsi->panel_off_delay); |
| 682 | msleep(intel_dsi->panel_pwr_cycle_delay); |
Shobhit Kumar | fc45e82 | 2015-06-26 14:32:09 +0530 | [diff] [blame] | 683 | |
| 684 | /* Panel Disable over CRC PMIC */ |
| 685 | if (intel_dsi->gpio_panel) |
| 686 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 687 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 688 | |
| 689 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, |
| 690 | enum pipe *pipe) |
| 691 | { |
| 692 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
Gaurav K Singh | c0beefd | 2014-12-09 10:59:20 +0530 | [diff] [blame] | 693 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
| 694 | struct drm_device *dev = encoder->base.dev; |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 695 | enum intel_display_power_domain power_domain; |
Jani Nikula | e7d7cad | 2014-11-14 16:54:21 +0200 | [diff] [blame] | 696 | enum port port; |
Jani Nikula | 1dcec2f | 2016-03-15 21:51:11 +0200 | [diff] [blame] | 697 | bool active = false; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 698 | |
| 699 | DRM_DEBUG_KMS("\n"); |
| 700 | |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 701 | power_domain = intel_display_port_power_domain(encoder); |
Imre Deak | 3f3f42b | 2016-02-12 18:55:19 +0200 | [diff] [blame] | 702 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 703 | return false; |
| 704 | |
Imre Deak | db18b6a | 2016-03-24 12:41:40 +0200 | [diff] [blame] | 705 | /* |
| 706 | * On Broxton the PLL needs to be enabled with a valid divider |
| 707 | * configuration, otherwise accessing DSI registers will hang the |
| 708 | * machine. See BSpec North Display Engine registers/MIPI[BXT]. |
| 709 | */ |
| 710 | if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv)) |
| 711 | goto out_put_power; |
| 712 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 713 | /* XXX: this only works for one DSI output */ |
Gaurav K Singh | c0beefd | 2014-12-09 10:59:20 +0530 | [diff] [blame] | 714 | for_each_dsi_port(port, intel_dsi->ports) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 715 | i915_reg_t ctrl_reg = IS_BROXTON(dev) ? |
| 716 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
Jani Nikula | 1dcec2f | 2016-03-15 21:51:11 +0200 | [diff] [blame] | 717 | bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 718 | |
Gaurav K Singh | c0beefd | 2014-12-09 10:59:20 +0530 | [diff] [blame] | 719 | /* Due to some hardware limitations on BYT, MIPI Port C DPI |
| 720 | * Enable bit does not get set. To check whether DSI Port C |
| 721 | * was enabled in BIOS, check the Pipe B enable bit |
| 722 | */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 723 | if (IS_VALLEYVIEW(dev) && port == PORT_C) |
Jani Nikula | 1dcec2f | 2016-03-15 21:51:11 +0200 | [diff] [blame] | 724 | enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; |
Gaurav K Singh | c0beefd | 2014-12-09 10:59:20 +0530 | [diff] [blame] | 725 | |
Jani Nikula | 1dcec2f | 2016-03-15 21:51:11 +0200 | [diff] [blame] | 726 | /* Try command mode if video mode not enabled */ |
| 727 | if (!enabled) { |
| 728 | u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
| 729 | enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 730 | } |
Jani Nikula | 1dcec2f | 2016-03-15 21:51:11 +0200 | [diff] [blame] | 731 | |
| 732 | if (!enabled) |
| 733 | continue; |
| 734 | |
| 735 | if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) |
| 736 | continue; |
| 737 | |
Jani Nikula | 6b93e9c | 2016-03-15 21:51:12 +0200 | [diff] [blame] | 738 | if (IS_BROXTON(dev_priv)) { |
| 739 | u32 tmp = I915_READ(MIPI_CTRL(port)); |
| 740 | tmp &= BXT_PIPE_SELECT_MASK; |
| 741 | tmp >>= BXT_PIPE_SELECT_SHIFT; |
| 742 | |
| 743 | if (WARN_ON(tmp > PIPE_C)) |
| 744 | continue; |
| 745 | |
| 746 | *pipe = tmp; |
| 747 | } else { |
| 748 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; |
| 749 | } |
| 750 | |
Jani Nikula | 1dcec2f | 2016-03-15 21:51:11 +0200 | [diff] [blame] | 751 | active = true; |
| 752 | break; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 753 | } |
Jani Nikula | 1dcec2f | 2016-03-15 21:51:11 +0200 | [diff] [blame] | 754 | |
Imre Deak | db18b6a | 2016-03-24 12:41:40 +0200 | [diff] [blame] | 755 | out_put_power: |
Imre Deak | 3f3f42b | 2016-02-12 18:55:19 +0200 | [diff] [blame] | 756 | intel_display_power_put(dev_priv, power_domain); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 757 | |
Jani Nikula | 1dcec2f | 2016-03-15 21:51:11 +0200 | [diff] [blame] | 758 | return active; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 759 | } |
| 760 | |
Ramalingam C | 6f0e753 | 2016-04-07 14:36:07 +0530 | [diff] [blame] | 761 | static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, |
| 762 | struct intel_crtc_state *pipe_config) |
| 763 | { |
| 764 | struct drm_device *dev = encoder->base.dev; |
| 765 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 766 | struct drm_display_mode *adjusted_mode = |
| 767 | &pipe_config->base.adjusted_mode; |
| 768 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
| 769 | unsigned int bpp, fmt; |
| 770 | enum port port; |
| 771 | u16 vfp, vsync, vbp; |
| 772 | |
| 773 | /* |
| 774 | * Atleast one port is active as encoder->get_config called only if |
| 775 | * encoder->get_hw_state() returns true. |
| 776 | */ |
| 777 | for_each_dsi_port(port, intel_dsi->ports) { |
| 778 | if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) |
| 779 | break; |
| 780 | } |
| 781 | |
| 782 | fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; |
| 783 | pipe_config->pipe_bpp = |
| 784 | mipi_dsi_pixel_format_to_bpp( |
| 785 | pixel_format_from_register_bits(fmt)); |
| 786 | bpp = pipe_config->pipe_bpp; |
| 787 | |
| 788 | /* In terms of pixels */ |
| 789 | adjusted_mode->crtc_hdisplay = |
| 790 | I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); |
| 791 | adjusted_mode->crtc_vdisplay = |
| 792 | I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); |
| 793 | adjusted_mode->crtc_vtotal = |
| 794 | I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); |
| 795 | |
| 796 | /* |
| 797 | * TODO: Retrieve hfp, hsync and hbp. Adjust them for dual link and |
| 798 | * calculate hsync_start, hsync_end, htotal and hblank_end |
| 799 | */ |
| 800 | |
| 801 | /* vertical values are in terms of lines */ |
| 802 | vfp = I915_READ(MIPI_VFP_COUNT(port)); |
| 803 | vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); |
| 804 | vbp = I915_READ(MIPI_VBP_COUNT(port)); |
| 805 | |
| 806 | adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; |
| 807 | |
| 808 | adjusted_mode->crtc_vsync_start = |
| 809 | vfp + adjusted_mode->crtc_vdisplay; |
| 810 | adjusted_mode->crtc_vsync_end = |
| 811 | vsync + adjusted_mode->crtc_vsync_start; |
| 812 | adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; |
| 813 | adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; |
| 814 | } |
| 815 | |
| 816 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 817 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 818 | struct intel_crtc_state *pipe_config) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 819 | { |
Ramalingam C | 6f0e753 | 2016-04-07 14:36:07 +0530 | [diff] [blame] | 820 | struct drm_device *dev = encoder->base.dev; |
Jani Nikula | d7d85d8 | 2016-01-08 12:45:39 +0200 | [diff] [blame] | 821 | u32 pclk; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 822 | DRM_DEBUG_KMS("\n"); |
| 823 | |
Jani Nikula | a65347b | 2015-11-27 12:21:46 +0200 | [diff] [blame] | 824 | pipe_config->has_dsi_encoder = true; |
| 825 | |
Ramalingam C | 6f0e753 | 2016-04-07 14:36:07 +0530 | [diff] [blame] | 826 | if (IS_BROXTON(dev)) |
| 827 | bxt_dsi_get_pipe_config(encoder, pipe_config); |
| 828 | |
Ville Syrjälä | 47eacba | 2016-04-12 22:14:35 +0300 | [diff] [blame^] | 829 | pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp, |
| 830 | pipe_config); |
Shobhit Kumar | f573de5 | 2014-07-30 20:32:37 +0530 | [diff] [blame] | 831 | if (!pclk) |
| 832 | return; |
| 833 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 834 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
Shobhit Kumar | f573de5 | 2014-07-30 20:32:37 +0530 | [diff] [blame] | 835 | pipe_config->port_clock = pclk; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 836 | } |
| 837 | |
Damien Lespiau | c19de8e | 2013-11-28 15:29:18 +0000 | [diff] [blame] | 838 | static enum drm_mode_status |
| 839 | intel_dsi_mode_valid(struct drm_connector *connector, |
| 840 | struct drm_display_mode *mode) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 841 | { |
| 842 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 843 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
Mika Kahola | 759a1e9 | 2015-08-18 14:37:01 +0300 | [diff] [blame] | 844 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 845 | |
| 846 | DRM_DEBUG_KMS("\n"); |
| 847 | |
| 848 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { |
| 849 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); |
| 850 | return MODE_NO_DBLESCAN; |
| 851 | } |
| 852 | |
| 853 | if (fixed_mode) { |
| 854 | if (mode->hdisplay > fixed_mode->hdisplay) |
| 855 | return MODE_PANEL; |
| 856 | if (mode->vdisplay > fixed_mode->vdisplay) |
| 857 | return MODE_PANEL; |
Mika Kahola | 759a1e9 | 2015-08-18 14:37:01 +0300 | [diff] [blame] | 858 | if (fixed_mode->clock > max_dotclk) |
| 859 | return MODE_CLOCK_HIGH; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 860 | } |
| 861 | |
Jani Nikula | 36d21f4 | 2015-01-16 14:27:20 +0200 | [diff] [blame] | 862 | return MODE_OK; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 863 | } |
| 864 | |
| 865 | /* return txclkesc cycles in terms of divider and duration in us */ |
| 866 | static u16 txclkesc(u32 divider, unsigned int us) |
| 867 | { |
| 868 | switch (divider) { |
| 869 | case ESCAPE_CLOCK_DIVIDER_1: |
| 870 | default: |
| 871 | return 20 * us; |
| 872 | case ESCAPE_CLOCK_DIVIDER_2: |
| 873 | return 10 * us; |
| 874 | case ESCAPE_CLOCK_DIVIDER_4: |
| 875 | return 5 * us; |
| 876 | } |
| 877 | } |
| 878 | |
| 879 | /* return pixels in terms of txbyteclkhs */ |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 880 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, |
| 881 | u16 burst_mode_ratio) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 882 | { |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 883 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
Daniel Vetter | 7f3de83 | 2014-07-30 22:34:27 +0200 | [diff] [blame] | 884 | 8 * 100), lane_count); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 885 | } |
| 886 | |
| 887 | static void set_dsi_timings(struct drm_encoder *encoder, |
Ville Syrjälä | 5e7234c | 2015-09-25 16:37:43 +0300 | [diff] [blame] | 888 | const struct drm_display_mode *adjusted_mode) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 889 | { |
| 890 | struct drm_device *dev = encoder->dev; |
| 891 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 892 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
Gaurav K Singh | aa102d2 | 2014-12-04 10:58:54 +0530 | [diff] [blame] | 893 | enum port port; |
Jani Nikula | 1e78aa0 | 2016-03-16 12:21:40 +0200 | [diff] [blame] | 894 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 895 | unsigned int lane_count = intel_dsi->lane_count; |
| 896 | |
| 897 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
| 898 | |
Ville Syrjälä | aad941d | 2015-09-25 16:38:56 +0300 | [diff] [blame] | 899 | hactive = adjusted_mode->crtc_hdisplay; |
| 900 | hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; |
| 901 | hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; |
| 902 | hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 903 | |
Gaurav K Singh | aa102d2 | 2014-12-04 10:58:54 +0530 | [diff] [blame] | 904 | if (intel_dsi->dual_link) { |
| 905 | hactive /= 2; |
| 906 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) |
| 907 | hactive += intel_dsi->pixel_overlap; |
| 908 | hfp /= 2; |
| 909 | hsync /= 2; |
| 910 | hbp /= 2; |
| 911 | } |
| 912 | |
Ville Syrjälä | aad941d | 2015-09-25 16:38:56 +0300 | [diff] [blame] | 913 | vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; |
| 914 | vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; |
| 915 | vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 916 | |
| 917 | /* horizontal values are in terms of high speed byte clock */ |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 918 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
Daniel Vetter | 7f3de83 | 2014-07-30 22:34:27 +0200 | [diff] [blame] | 919 | intel_dsi->burst_mode_ratio); |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 920 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
| 921 | hsync = txbyteclkhs(hsync, bpp, lane_count, |
Daniel Vetter | 7f3de83 | 2014-07-30 22:34:27 +0200 | [diff] [blame] | 922 | intel_dsi->burst_mode_ratio); |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 923 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 924 | |
Gaurav K Singh | aa102d2 | 2014-12-04 10:58:54 +0530 | [diff] [blame] | 925 | for_each_dsi_port(port, intel_dsi->ports) { |
Shashank Sharma | d2e08c0 | 2015-09-01 19:41:40 +0530 | [diff] [blame] | 926 | if (IS_BROXTON(dev)) { |
| 927 | /* |
| 928 | * Program hdisplay and vdisplay on MIPI transcoder. |
| 929 | * This is different from calculated hactive and |
| 930 | * vactive, as they are calculated per channel basis, |
| 931 | * whereas these values should be based on resolution. |
| 932 | */ |
| 933 | I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), |
Ville Syrjälä | aad941d | 2015-09-25 16:38:56 +0300 | [diff] [blame] | 934 | adjusted_mode->crtc_hdisplay); |
Shashank Sharma | d2e08c0 | 2015-09-01 19:41:40 +0530 | [diff] [blame] | 935 | I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), |
Ville Syrjälä | aad941d | 2015-09-25 16:38:56 +0300 | [diff] [blame] | 936 | adjusted_mode->crtc_vdisplay); |
Shashank Sharma | d2e08c0 | 2015-09-01 19:41:40 +0530 | [diff] [blame] | 937 | I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), |
Ville Syrjälä | aad941d | 2015-09-25 16:38:56 +0300 | [diff] [blame] | 938 | adjusted_mode->crtc_vtotal); |
Shashank Sharma | d2e08c0 | 2015-09-01 19:41:40 +0530 | [diff] [blame] | 939 | } |
| 940 | |
Gaurav K Singh | aa102d2 | 2014-12-04 10:58:54 +0530 | [diff] [blame] | 941 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
| 942 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 943 | |
Gaurav K Singh | aa102d2 | 2014-12-04 10:58:54 +0530 | [diff] [blame] | 944 | /* meaningful for video mode non-burst sync pulse mode only, |
| 945 | * can be zero for non-burst sync events and burst modes */ |
| 946 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); |
| 947 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 948 | |
Gaurav K Singh | aa102d2 | 2014-12-04 10:58:54 +0530 | [diff] [blame] | 949 | /* vertical values are in terms of lines */ |
| 950 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); |
| 951 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); |
| 952 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); |
| 953 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 954 | } |
| 955 | |
Jani Nikula | 1e78aa0 | 2016-03-16 12:21:40 +0200 | [diff] [blame] | 956 | static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) |
| 957 | { |
| 958 | switch (fmt) { |
| 959 | case MIPI_DSI_FMT_RGB888: |
| 960 | return VID_MODE_FORMAT_RGB888; |
| 961 | case MIPI_DSI_FMT_RGB666: |
| 962 | return VID_MODE_FORMAT_RGB666; |
| 963 | case MIPI_DSI_FMT_RGB666_PACKED: |
| 964 | return VID_MODE_FORMAT_RGB666_PACKED; |
| 965 | case MIPI_DSI_FMT_RGB565: |
| 966 | return VID_MODE_FORMAT_RGB565; |
| 967 | default: |
| 968 | MISSING_CASE(fmt); |
| 969 | return VID_MODE_FORMAT_RGB666; |
| 970 | } |
| 971 | } |
| 972 | |
Daniel Vetter | 07e4fb9 | 2014-04-24 23:54:59 +0200 | [diff] [blame] | 973 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 974 | { |
| 975 | struct drm_encoder *encoder = &intel_encoder->base; |
| 976 | struct drm_device *dev = encoder->dev; |
| 977 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 978 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 979 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 980 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 981 | enum port port; |
Jani Nikula | 1e78aa0 | 2016-03-16 12:21:40 +0200 | [diff] [blame] | 982 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 983 | u32 val, tmp; |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 984 | u16 mode_hdisplay; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 985 | |
Jani Nikula | e7d7cad | 2014-11-14 16:54:21 +0200 | [diff] [blame] | 986 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 987 | |
Ville Syrjälä | aad941d | 2015-09-25 16:38:56 +0300 | [diff] [blame] | 988 | mode_hdisplay = adjusted_mode->crtc_hdisplay; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 989 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 990 | if (intel_dsi->dual_link) { |
| 991 | mode_hdisplay /= 2; |
| 992 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) |
| 993 | mode_hdisplay += intel_dsi->pixel_overlap; |
| 994 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 995 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 996 | for_each_dsi_port(port, intel_dsi->ports) { |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 997 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Shashank Sharma | d2e08c0 | 2015-09-01 19:41:40 +0530 | [diff] [blame] | 998 | /* |
| 999 | * escape clock divider, 20MHz, shared for A and C. |
| 1000 | * device ready must be off when doing this! txclkesc? |
| 1001 | */ |
| 1002 | tmp = I915_READ(MIPI_CTRL(PORT_A)); |
| 1003 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
| 1004 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | |
| 1005 | ESCAPE_CLOCK_DIVIDER_1); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1006 | |
Shashank Sharma | d2e08c0 | 2015-09-01 19:41:40 +0530 | [diff] [blame] | 1007 | /* read request priority is per pipe */ |
| 1008 | tmp = I915_READ(MIPI_CTRL(port)); |
| 1009 | tmp &= ~READ_REQUEST_PRIORITY_MASK; |
| 1010 | I915_WRITE(MIPI_CTRL(port), tmp | |
| 1011 | READ_REQUEST_PRIORITY_HIGH); |
| 1012 | } else if (IS_BROXTON(dev)) { |
Deepak M | 56c4897 | 2015-12-09 20:14:04 +0530 | [diff] [blame] | 1013 | enum pipe pipe = intel_crtc->pipe; |
| 1014 | |
Shashank Sharma | d2e08c0 | 2015-09-01 19:41:40 +0530 | [diff] [blame] | 1015 | tmp = I915_READ(MIPI_CTRL(port)); |
| 1016 | tmp &= ~BXT_PIPE_SELECT_MASK; |
| 1017 | |
Deepak M | 56c4897 | 2015-12-09 20:14:04 +0530 | [diff] [blame] | 1018 | tmp |= BXT_PIPE_SELECT(pipe); |
Shashank Sharma | d2e08c0 | 2015-09-01 19:41:40 +0530 | [diff] [blame] | 1019 | I915_WRITE(MIPI_CTRL(port), tmp); |
| 1020 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1021 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 1022 | /* XXX: why here, why like this? handling in irq handler?! */ |
| 1023 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); |
| 1024 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); |
| 1025 | |
| 1026 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); |
| 1027 | |
| 1028 | I915_WRITE(MIPI_DPI_RESOLUTION(port), |
Ville Syrjälä | aad941d | 2015-09-25 16:38:56 +0300 | [diff] [blame] | 1029 | adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 1030 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
| 1031 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1032 | |
| 1033 | set_dsi_timings(encoder, adjusted_mode); |
| 1034 | |
| 1035 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; |
| 1036 | if (is_cmd_mode(intel_dsi)) { |
| 1037 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; |
| 1038 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ |
| 1039 | } else { |
| 1040 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; |
Jani Nikula | 1e78aa0 | 2016-03-16 12:21:40 +0200 | [diff] [blame] | 1041 | val |= pixel_format_to_reg(intel_dsi->pixel_format); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1042 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1043 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 1044 | tmp = 0; |
Shobhit Kumar | f1c79f1 | 2014-04-09 13:59:33 +0530 | [diff] [blame] | 1045 | if (intel_dsi->eotp_pkt == 0) |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 1046 | tmp |= EOT_DISABLE; |
Shobhit Kumar | f1c79f1 | 2014-04-09 13:59:33 +0530 | [diff] [blame] | 1047 | if (intel_dsi->clock_stop) |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 1048 | tmp |= CLOCKSTOP; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1049 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 1050 | for_each_dsi_port(port, intel_dsi->ports) { |
| 1051 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1052 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 1053 | /* timeouts for recovery. one frame IIUC. if counter expires, |
| 1054 | * EOT and stop state. */ |
Shobhit Kumar | cf4dbd2 | 2014-04-14 11:18:25 +0530 | [diff] [blame] | 1055 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 1056 | /* |
| 1057 | * In burst mode, value greater than one DPI line Time in byte |
| 1058 | * clock (txbyteclkhs) To timeout this timer 1+ of the above |
| 1059 | * said value is recommended. |
| 1060 | * |
| 1061 | * In non-burst mode, Value greater than one DPI frame time in |
| 1062 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above |
| 1063 | * said value is recommended. |
| 1064 | * |
| 1065 | * In DBI only mode, value greater than one DBI frame time in |
| 1066 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above |
| 1067 | * said value is recommended. |
| 1068 | */ |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1069 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 1070 | if (is_vid_mode(intel_dsi) && |
| 1071 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { |
| 1072 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), |
Ville Syrjälä | aad941d | 2015-09-25 16:38:56 +0300 | [diff] [blame] | 1073 | txbyteclkhs(adjusted_mode->crtc_htotal, bpp, |
Ville Syrjälä | 124abe0 | 2015-09-08 13:40:45 +0300 | [diff] [blame] | 1074 | intel_dsi->lane_count, |
| 1075 | intel_dsi->burst_mode_ratio) + 1); |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 1076 | } else { |
| 1077 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), |
Ville Syrjälä | aad941d | 2015-09-25 16:38:56 +0300 | [diff] [blame] | 1078 | txbyteclkhs(adjusted_mode->crtc_vtotal * |
| 1079 | adjusted_mode->crtc_htotal, |
Ville Syrjälä | 124abe0 | 2015-09-08 13:40:45 +0300 | [diff] [blame] | 1080 | bpp, intel_dsi->lane_count, |
| 1081 | intel_dsi->burst_mode_ratio) + 1); |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 1082 | } |
| 1083 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); |
| 1084 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), |
| 1085 | intel_dsi->turn_arnd_val); |
| 1086 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), |
| 1087 | intel_dsi->rst_timer_val); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1088 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 1089 | /* dphy stuff */ |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1090 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 1091 | /* in terms of low power clock */ |
| 1092 | I915_WRITE(MIPI_INIT_COUNT(port), |
| 1093 | txclkesc(intel_dsi->escape_clk_div, 100)); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1094 | |
Shashank Sharma | d2e08c0 | 2015-09-01 19:41:40 +0530 | [diff] [blame] | 1095 | if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) { |
| 1096 | /* |
| 1097 | * BXT spec says write MIPI_INIT_COUNT for |
| 1098 | * both the ports, even if only one is |
| 1099 | * getting used. So write the other port |
| 1100 | * if not in dual link mode. |
| 1101 | */ |
| 1102 | I915_WRITE(MIPI_INIT_COUNT(port == |
| 1103 | PORT_A ? PORT_C : PORT_A), |
| 1104 | intel_dsi->init_count); |
| 1105 | } |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 1106 | |
| 1107 | /* recovery disables */ |
Shobhit Kumar | 87c54d0 | 2015-02-03 12:17:35 +0530 | [diff] [blame] | 1108 | I915_WRITE(MIPI_EOT_DISABLE(port), tmp); |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 1109 | |
| 1110 | /* in terms of low power clock */ |
| 1111 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); |
| 1112 | |
| 1113 | /* in terms of txbyteclkhs. actual high to low switch + |
| 1114 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. |
| 1115 | * |
| 1116 | * XXX: write MIPI_STOP_STATE_STALL? |
| 1117 | */ |
| 1118 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), |
| 1119 | intel_dsi->hs_to_lp_count); |
| 1120 | |
| 1121 | /* XXX: low power clock equivalence in terms of byte clock. |
| 1122 | * the number of byte clocks occupied in one low power clock. |
| 1123 | * based on txbyteclkhs and txclkesc. |
| 1124 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL |
| 1125 | * ) / 105.??? |
| 1126 | */ |
| 1127 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); |
| 1128 | |
| 1129 | /* the bw essential for transmitting 16 long packets containing |
| 1130 | * 252 bytes meant for dcs write memory command is programmed in |
| 1131 | * this register in terms of byte clocks. based on dsi transfer |
| 1132 | * rate and the number of lanes configured the time taken to |
| 1133 | * transmit 16 long packets in a dsi stream varies. */ |
| 1134 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); |
| 1135 | |
| 1136 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), |
| 1137 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | |
| 1138 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); |
| 1139 | |
| 1140 | if (is_vid_mode(intel_dsi)) |
| 1141 | /* Some panels might have resolution which is not a |
| 1142 | * multiple of 64 like 1366 x 768. Enable RANDOM |
| 1143 | * resolution support for such panels by default */ |
| 1144 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), |
| 1145 | intel_dsi->video_frmt_cfg_bits | |
| 1146 | intel_dsi->video_mode_format | |
| 1147 | IP_TG_CONFIG | |
| 1148 | RANDOM_DPI_DISPLAY_RESOLUTION); |
| 1149 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1150 | } |
| 1151 | |
| 1152 | static enum drm_connector_status |
| 1153 | intel_dsi_detect(struct drm_connector *connector, bool force) |
| 1154 | { |
Jani Nikula | 36d21f4 | 2015-01-16 14:27:20 +0200 | [diff] [blame] | 1155 | return connector_status_connected; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1156 | } |
| 1157 | |
| 1158 | static int intel_dsi_get_modes(struct drm_connector *connector) |
| 1159 | { |
| 1160 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 1161 | struct drm_display_mode *mode; |
| 1162 | |
| 1163 | DRM_DEBUG_KMS("\n"); |
| 1164 | |
| 1165 | if (!intel_connector->panel.fixed_mode) { |
| 1166 | DRM_DEBUG_KMS("no fixed mode\n"); |
| 1167 | return 0; |
| 1168 | } |
| 1169 | |
| 1170 | mode = drm_mode_duplicate(connector->dev, |
| 1171 | intel_connector->panel.fixed_mode); |
| 1172 | if (!mode) { |
| 1173 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); |
| 1174 | return 0; |
| 1175 | } |
| 1176 | |
| 1177 | drm_mode_probed_add(connector, mode); |
| 1178 | return 1; |
| 1179 | } |
| 1180 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 1181 | static void intel_dsi_connector_destroy(struct drm_connector *connector) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1182 | { |
| 1183 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 1184 | |
| 1185 | DRM_DEBUG_KMS("\n"); |
| 1186 | intel_panel_fini(&intel_connector->panel); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1187 | drm_connector_cleanup(connector); |
| 1188 | kfree(connector); |
| 1189 | } |
| 1190 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 1191 | static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) |
| 1192 | { |
| 1193 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
| 1194 | |
| 1195 | if (intel_dsi->panel) { |
| 1196 | drm_panel_detach(intel_dsi->panel); |
| 1197 | /* XXX: Logically this call belongs in the panel driver. */ |
| 1198 | drm_panel_remove(intel_dsi->panel); |
| 1199 | } |
Shobhit Kumar | fc45e82 | 2015-06-26 14:32:09 +0530 | [diff] [blame] | 1200 | |
| 1201 | /* dispose of the gpios */ |
| 1202 | if (intel_dsi->gpio_panel) |
| 1203 | gpiod_put(intel_dsi->gpio_panel); |
| 1204 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 1205 | intel_encoder_destroy(encoder); |
| 1206 | } |
| 1207 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1208 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 1209 | .destroy = intel_dsi_encoder_destroy, |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1210 | }; |
| 1211 | |
| 1212 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { |
| 1213 | .get_modes = intel_dsi_get_modes, |
| 1214 | .mode_valid = intel_dsi_mode_valid, |
| 1215 | .best_encoder = intel_best_encoder, |
| 1216 | }; |
| 1217 | |
| 1218 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { |
Maarten Lankhorst | 4d688a2 | 2015-08-05 12:37:06 +0200 | [diff] [blame] | 1219 | .dpms = drm_atomic_helper_connector_dpms, |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1220 | .detect = intel_dsi_detect, |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 1221 | .destroy = intel_dsi_connector_destroy, |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1222 | .fill_modes = drm_helper_probe_single_connector_modes, |
Matt Roper | 2545e4a | 2015-01-22 16:51:27 -0800 | [diff] [blame] | 1223 | .atomic_get_property = intel_connector_atomic_get_property, |
Matt Roper | c6f95f2 | 2015-01-22 16:50:32 -0800 | [diff] [blame] | 1224 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
Ander Conselvan de Oliveira | 9896972 | 2015-03-20 16:18:06 +0200 | [diff] [blame] | 1225 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1226 | }; |
| 1227 | |
Damien Lespiau | 4328633d | 2014-05-28 12:30:56 +0100 | [diff] [blame] | 1228 | void intel_dsi_init(struct drm_device *dev) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1229 | { |
| 1230 | struct intel_dsi *intel_dsi; |
| 1231 | struct intel_encoder *intel_encoder; |
| 1232 | struct drm_encoder *encoder; |
| 1233 | struct intel_connector *intel_connector; |
| 1234 | struct drm_connector *connector; |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 1235 | struct drm_display_mode *scan, *fixed_mode = NULL; |
Shashank Sharma | b6fdd0f | 2014-05-19 20:54:03 +0530 | [diff] [blame] | 1236 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | 7e9804f | 2015-01-16 14:27:23 +0200 | [diff] [blame] | 1237 | enum port port; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1238 | unsigned int i; |
| 1239 | |
| 1240 | DRM_DEBUG_KMS("\n"); |
| 1241 | |
Shobhit Kumar | 3e6bd01 | 2014-05-27 19:33:59 +0530 | [diff] [blame] | 1242 | /* There is no detection method for MIPI so rely on VBT */ |
Jani Nikula | 7137aec | 2016-03-16 12:43:32 +0200 | [diff] [blame] | 1243 | if (!intel_bios_is_dsi_present(dev_priv, &port)) |
Damien Lespiau | 4328633d | 2014-05-28 12:30:56 +0100 | [diff] [blame] | 1244 | return; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1245 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 1246 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Shashank Sharma | b6fdd0f | 2014-05-19 20:54:03 +0530 | [diff] [blame] | 1247 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; |
Shashank Sharma | c6c794a | 2016-03-22 12:01:50 +0200 | [diff] [blame] | 1248 | } else if (IS_BROXTON(dev)) { |
| 1249 | dev_priv->mipi_mmio_base = BXT_MIPI_BASE; |
Shashank Sharma | b6fdd0f | 2014-05-19 20:54:03 +0530 | [diff] [blame] | 1250 | } else { |
| 1251 | DRM_ERROR("Unsupported Mipi device to reg base"); |
Christoph Jaeger | 868d665 | 2014-06-13 21:51:22 +0200 | [diff] [blame] | 1252 | return; |
Shashank Sharma | b6fdd0f | 2014-05-19 20:54:03 +0530 | [diff] [blame] | 1253 | } |
| 1254 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1255 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
| 1256 | if (!intel_dsi) |
Damien Lespiau | 4328633d | 2014-05-28 12:30:56 +0100 | [diff] [blame] | 1257 | return; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1258 | |
Ander Conselvan de Oliveira | 08d9bc9 | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 1259 | intel_connector = intel_connector_alloc(); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1260 | if (!intel_connector) { |
| 1261 | kfree(intel_dsi); |
Damien Lespiau | 4328633d | 2014-05-28 12:30:56 +0100 | [diff] [blame] | 1262 | return; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1263 | } |
| 1264 | |
| 1265 | intel_encoder = &intel_dsi->base; |
| 1266 | encoder = &intel_encoder->base; |
| 1267 | intel_dsi->attached_connector = intel_connector; |
| 1268 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1269 | connector = &intel_connector->base; |
| 1270 | |
Ville Syrjälä | 13a3d91 | 2015-12-09 16:20:18 +0200 | [diff] [blame] | 1271 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, |
| 1272 | NULL); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1273 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1274 | intel_encoder->compute_config = intel_dsi_compute_config; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1275 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
Shobhit Kumar | 2634fd7 | 2014-04-09 13:59:31 +0530 | [diff] [blame] | 1276 | intel_encoder->enable = intel_dsi_enable_nop; |
Imre Deak | c315faf | 2014-05-27 19:00:09 +0300 | [diff] [blame] | 1277 | intel_encoder->disable = intel_dsi_pre_disable; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1278 | intel_encoder->post_disable = intel_dsi_post_disable; |
| 1279 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; |
| 1280 | intel_encoder->get_config = intel_dsi_get_config; |
| 1281 | |
| 1282 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 1283 | intel_connector->unregister = intel_connector_unregister; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1284 | |
Jani Nikula | 2e85ab4 | 2016-03-18 17:05:44 +0200 | [diff] [blame] | 1285 | /* |
| 1286 | * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI |
| 1287 | * port C. BXT isn't limited like this. |
| 1288 | */ |
| 1289 | if (IS_BROXTON(dev_priv)) |
| 1290 | intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); |
| 1291 | else if (port == PORT_A) |
Jani Nikula | 701d25b | 2016-03-18 17:05:43 +0200 | [diff] [blame] | 1292 | intel_encoder->crtc_mask = BIT(PIPE_A); |
Jani Nikula | 7137aec | 2016-03-16 12:43:32 +0200 | [diff] [blame] | 1293 | else |
Jani Nikula | 701d25b | 2016-03-18 17:05:43 +0200 | [diff] [blame] | 1294 | intel_encoder->crtc_mask = BIT(PIPE_B); |
Jani Nikula | e7d7cad | 2014-11-14 16:54:21 +0200 | [diff] [blame] | 1295 | |
Gaurav K Singh | 8242578 | 2015-08-03 15:45:32 +0530 | [diff] [blame] | 1296 | if (dev_priv->vbt.dsi.config->dual_link) |
Jani Nikula | 701d25b | 2016-03-18 17:05:43 +0200 | [diff] [blame] | 1297 | intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); |
Jani Nikula | 7137aec | 2016-03-16 12:43:32 +0200 | [diff] [blame] | 1298 | else |
Jani Nikula | 701d25b | 2016-03-18 17:05:43 +0200 | [diff] [blame] | 1299 | intel_dsi->ports = BIT(port); |
Gaurav K Singh | 8242578 | 2015-08-03 15:45:32 +0530 | [diff] [blame] | 1300 | |
Jani Nikula | 7e9804f | 2015-01-16 14:27:23 +0200 | [diff] [blame] | 1301 | /* Create a DSI host (and a device) for each port. */ |
| 1302 | for_each_dsi_port(port, intel_dsi->ports) { |
| 1303 | struct intel_dsi_host *host; |
| 1304 | |
| 1305 | host = intel_dsi_host_init(intel_dsi, port); |
| 1306 | if (!host) |
| 1307 | goto err; |
| 1308 | |
| 1309 | intel_dsi->dsi_hosts[port] = host; |
| 1310 | } |
| 1311 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 1312 | for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) { |
| 1313 | intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi, |
| 1314 | intel_dsi_drivers[i].panel_id); |
| 1315 | if (intel_dsi->panel) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1316 | break; |
| 1317 | } |
| 1318 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 1319 | if (!intel_dsi->panel) { |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1320 | DRM_DEBUG_KMS("no device found\n"); |
| 1321 | goto err; |
| 1322 | } |
| 1323 | |
Shobhit Kumar | fc45e82 | 2015-06-26 14:32:09 +0530 | [diff] [blame] | 1324 | /* |
| 1325 | * In case of BYT with CRC PMIC, we need to use GPIO for |
| 1326 | * Panel control. |
| 1327 | */ |
| 1328 | if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { |
| 1329 | intel_dsi->gpio_panel = |
| 1330 | gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); |
| 1331 | |
| 1332 | if (IS_ERR(intel_dsi->gpio_panel)) { |
| 1333 | DRM_ERROR("Failed to own gpio for panel control\n"); |
| 1334 | intel_dsi->gpio_panel = NULL; |
| 1335 | } |
| 1336 | } |
| 1337 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1338 | intel_encoder->type = INTEL_OUTPUT_DSI; |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 1339 | intel_encoder->cloneable = 0; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1340 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
| 1341 | DRM_MODE_CONNECTOR_DSI); |
| 1342 | |
| 1343 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); |
| 1344 | |
| 1345 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ |
| 1346 | connector->interlace_allowed = false; |
| 1347 | connector->doublescan_allowed = false; |
| 1348 | |
| 1349 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
| 1350 | |
Thomas Wood | 34ea3d3 | 2014-05-29 16:57:41 +0100 | [diff] [blame] | 1351 | drm_connector_register(connector); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1352 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 1353 | drm_panel_attach(intel_dsi->panel, connector); |
| 1354 | |
| 1355 | mutex_lock(&dev->mode_config.mutex); |
| 1356 | drm_panel_get_modes(intel_dsi->panel); |
| 1357 | list_for_each_entry(scan, &connector->probed_modes, head) { |
| 1358 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
| 1359 | fixed_mode = drm_mode_duplicate(dev, scan); |
| 1360 | break; |
| 1361 | } |
| 1362 | } |
| 1363 | mutex_unlock(&dev->mode_config.mutex); |
| 1364 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1365 | if (!fixed_mode) { |
| 1366 | DRM_DEBUG_KMS("no fixed mode\n"); |
| 1367 | goto err; |
| 1368 | } |
| 1369 | |
Vandana Kannan | 4b6ed68 | 2014-02-11 14:26:36 +0530 | [diff] [blame] | 1370 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
Shobhit Kumar | b029e66 | 2015-06-26 14:32:10 +0530 | [diff] [blame] | 1371 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1372 | |
Damien Lespiau | 4328633d | 2014-05-28 12:30:56 +0100 | [diff] [blame] | 1373 | return; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1374 | |
| 1375 | err: |
| 1376 | drm_encoder_cleanup(&intel_encoder->base); |
| 1377 | kfree(intel_dsi); |
| 1378 | kfree(intel_connector); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1379 | } |