blob: aa80313c922ef3913e5f85796c51921111505a45 [file] [log] [blame]
Divy Le Ray4d22de32007-01-18 22:04:14 -05001#define A_SG_CONTROL 0x0
2
3#define S_DROPPKT 20
4#define V_DROPPKT(x) ((x) << S_DROPPKT)
5#define F_DROPPKT V_DROPPKT(1U)
6
7#define S_EGRGENCTRL 19
8#define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL)
9#define F_EGRGENCTRL V_EGRGENCTRL(1U)
10
11#define S_USERSPACESIZE 14
12#define M_USERSPACESIZE 0x1f
13#define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE)
14
15#define S_HOSTPAGESIZE 11
16#define M_HOSTPAGESIZE 0x7
17#define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE)
18
19#define S_FLMODE 9
20#define V_FLMODE(x) ((x) << S_FLMODE)
21#define F_FLMODE V_FLMODE(1U)
22
23#define S_PKTSHIFT 6
24#define M_PKTSHIFT 0x7
25#define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
26
27#define S_ONEINTMULTQ 5
28#define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ)
29#define F_ONEINTMULTQ V_ONEINTMULTQ(1U)
30
31#define S_BIGENDIANINGRESS 2
32#define V_BIGENDIANINGRESS(x) ((x) << S_BIGENDIANINGRESS)
33#define F_BIGENDIANINGRESS V_BIGENDIANINGRESS(1U)
34
35#define S_ISCSICOALESCING 1
36#define V_ISCSICOALESCING(x) ((x) << S_ISCSICOALESCING)
37#define F_ISCSICOALESCING V_ISCSICOALESCING(1U)
38
39#define S_GLOBALENABLE 0
40#define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
41#define F_GLOBALENABLE V_GLOBALENABLE(1U)
42
43#define S_AVOIDCQOVFL 24
44#define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL)
45#define F_AVOIDCQOVFL V_AVOIDCQOVFL(1U)
46
47#define S_OPTONEINTMULTQ 23
48#define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ)
49#define F_OPTONEINTMULTQ V_OPTONEINTMULTQ(1U)
50
51#define S_CQCRDTCTRL 22
52#define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL)
53#define F_CQCRDTCTRL V_CQCRDTCTRL(1U)
54
55#define A_SG_KDOORBELL 0x4
56
57#define S_SELEGRCNTX 31
58#define V_SELEGRCNTX(x) ((x) << S_SELEGRCNTX)
59#define F_SELEGRCNTX V_SELEGRCNTX(1U)
60
61#define S_EGRCNTX 0
62#define M_EGRCNTX 0xffff
63#define V_EGRCNTX(x) ((x) << S_EGRCNTX)
64
65#define A_SG_GTS 0x8
66
67#define S_RSPQ 29
68#define M_RSPQ 0x7
69#define V_RSPQ(x) ((x) << S_RSPQ)
70#define G_RSPQ(x) (((x) >> S_RSPQ) & M_RSPQ)
71
72#define S_NEWTIMER 16
73#define M_NEWTIMER 0x1fff
74#define V_NEWTIMER(x) ((x) << S_NEWTIMER)
75
76#define S_NEWINDEX 0
77#define M_NEWINDEX 0xffff
78#define V_NEWINDEX(x) ((x) << S_NEWINDEX)
79
80#define A_SG_CONTEXT_CMD 0xc
81
82#define S_CONTEXT_CMD_OPCODE 28
83#define M_CONTEXT_CMD_OPCODE 0xf
84#define V_CONTEXT_CMD_OPCODE(x) ((x) << S_CONTEXT_CMD_OPCODE)
85
86#define S_CONTEXT_CMD_BUSY 27
87#define V_CONTEXT_CMD_BUSY(x) ((x) << S_CONTEXT_CMD_BUSY)
88#define F_CONTEXT_CMD_BUSY V_CONTEXT_CMD_BUSY(1U)
89
90#define S_CQ_CREDIT 20
91
92#define M_CQ_CREDIT 0x7f
93
94#define V_CQ_CREDIT(x) ((x) << S_CQ_CREDIT)
95
96#define G_CQ_CREDIT(x) (((x) >> S_CQ_CREDIT) & M_CQ_CREDIT)
97
98#define S_CQ 19
99
100#define V_CQ(x) ((x) << S_CQ)
101#define F_CQ V_CQ(1U)
102
103#define S_RESPONSEQ 18
104#define V_RESPONSEQ(x) ((x) << S_RESPONSEQ)
105#define F_RESPONSEQ V_RESPONSEQ(1U)
106
107#define S_EGRESS 17
108#define V_EGRESS(x) ((x) << S_EGRESS)
109#define F_EGRESS V_EGRESS(1U)
110
111#define S_FREELIST 16
112#define V_FREELIST(x) ((x) << S_FREELIST)
113#define F_FREELIST V_FREELIST(1U)
114
115#define S_CONTEXT 0
116#define M_CONTEXT 0xffff
117#define V_CONTEXT(x) ((x) << S_CONTEXT)
118
119#define G_CONTEXT(x) (((x) >> S_CONTEXT) & M_CONTEXT)
120
121#define A_SG_CONTEXT_DATA0 0x10
122
123#define A_SG_CONTEXT_DATA1 0x14
124
125#define A_SG_CONTEXT_DATA2 0x18
126
127#define A_SG_CONTEXT_DATA3 0x1c
128
129#define A_SG_CONTEXT_MASK0 0x20
130
131#define A_SG_CONTEXT_MASK1 0x24
132
133#define A_SG_CONTEXT_MASK2 0x28
134
135#define A_SG_CONTEXT_MASK3 0x2c
136
137#define A_SG_RSPQ_CREDIT_RETURN 0x30
138
139#define S_CREDITS 0
140#define M_CREDITS 0xffff
141#define V_CREDITS(x) ((x) << S_CREDITS)
142
143#define A_SG_DATA_INTR 0x34
144
145#define S_ERRINTR 31
146#define V_ERRINTR(x) ((x) << S_ERRINTR)
147#define F_ERRINTR V_ERRINTR(1U)
148
149#define A_SG_HI_DRB_HI_THRSH 0x38
150
151#define A_SG_HI_DRB_LO_THRSH 0x3c
152
153#define A_SG_LO_DRB_HI_THRSH 0x40
154
155#define A_SG_LO_DRB_LO_THRSH 0x44
156
157#define A_SG_RSPQ_FL_STATUS 0x4c
158
159#define S_RSPQ0DISABLED 8
160
161#define A_SG_EGR_RCQ_DRB_THRSH 0x54
162
163#define S_HIRCQDRBTHRSH 16
164#define M_HIRCQDRBTHRSH 0x7ff
165#define V_HIRCQDRBTHRSH(x) ((x) << S_HIRCQDRBTHRSH)
166
167#define S_LORCQDRBTHRSH 0
168#define M_LORCQDRBTHRSH 0x7ff
169#define V_LORCQDRBTHRSH(x) ((x) << S_LORCQDRBTHRSH)
170
171#define A_SG_EGR_CNTX_BADDR 0x58
172
173#define A_SG_INT_CAUSE 0x5c
174
175#define S_RSPQDISABLED 3
176#define V_RSPQDISABLED(x) ((x) << S_RSPQDISABLED)
177#define F_RSPQDISABLED V_RSPQDISABLED(1U)
178
179#define S_RSPQCREDITOVERFOW 2
180#define V_RSPQCREDITOVERFOW(x) ((x) << S_RSPQCREDITOVERFOW)
181#define F_RSPQCREDITOVERFOW V_RSPQCREDITOVERFOW(1U)
182
183#define A_SG_INT_ENABLE 0x60
184
185#define A_SG_CMDQ_CREDIT_TH 0x64
186
187#define S_TIMEOUT 8
188#define M_TIMEOUT 0xffffff
189#define V_TIMEOUT(x) ((x) << S_TIMEOUT)
190
191#define S_THRESHOLD 0
192#define M_THRESHOLD 0xff
193#define V_THRESHOLD(x) ((x) << S_THRESHOLD)
194
195#define A_SG_TIMER_TICK 0x68
196
197#define A_SG_CQ_CONTEXT_BADDR 0x6c
198
199#define A_SG_OCO_BASE 0x70
200
201#define S_BASE1 16
202#define M_BASE1 0xffff
203#define V_BASE1(x) ((x) << S_BASE1)
204
205#define A_SG_DRB_PRI_THRESH 0x74
206
207#define A_PCIX_INT_ENABLE 0x80
208
209#define S_MSIXPARERR 22
210#define M_MSIXPARERR 0x7
211
212#define V_MSIXPARERR(x) ((x) << S_MSIXPARERR)
213
214#define S_CFPARERR 18
215#define M_CFPARERR 0xf
216
217#define V_CFPARERR(x) ((x) << S_CFPARERR)
218
219#define S_RFPARERR 14
220#define M_RFPARERR 0xf
221
222#define V_RFPARERR(x) ((x) << S_RFPARERR)
223
224#define S_WFPARERR 12
225#define M_WFPARERR 0x3
226
227#define V_WFPARERR(x) ((x) << S_WFPARERR)
228
229#define S_PIOPARERR 11
230#define V_PIOPARERR(x) ((x) << S_PIOPARERR)
231#define F_PIOPARERR V_PIOPARERR(1U)
232
233#define S_DETUNCECCERR 10
234#define V_DETUNCECCERR(x) ((x) << S_DETUNCECCERR)
235#define F_DETUNCECCERR V_DETUNCECCERR(1U)
236
237#define S_DETCORECCERR 9
238#define V_DETCORECCERR(x) ((x) << S_DETCORECCERR)
239#define F_DETCORECCERR V_DETCORECCERR(1U)
240
241#define S_RCVSPLCMPERR 8
242#define V_RCVSPLCMPERR(x) ((x) << S_RCVSPLCMPERR)
243#define F_RCVSPLCMPERR V_RCVSPLCMPERR(1U)
244
245#define S_UNXSPLCMP 7
246#define V_UNXSPLCMP(x) ((x) << S_UNXSPLCMP)
247#define F_UNXSPLCMP V_UNXSPLCMP(1U)
248
249#define S_SPLCMPDIS 6
250#define V_SPLCMPDIS(x) ((x) << S_SPLCMPDIS)
251#define F_SPLCMPDIS V_SPLCMPDIS(1U)
252
253#define S_DETPARERR 5
254#define V_DETPARERR(x) ((x) << S_DETPARERR)
255#define F_DETPARERR V_DETPARERR(1U)
256
257#define S_SIGSYSERR 4
258#define V_SIGSYSERR(x) ((x) << S_SIGSYSERR)
259#define F_SIGSYSERR V_SIGSYSERR(1U)
260
261#define S_RCVMSTABT 3
262#define V_RCVMSTABT(x) ((x) << S_RCVMSTABT)
263#define F_RCVMSTABT V_RCVMSTABT(1U)
264
265#define S_RCVTARABT 2
266#define V_RCVTARABT(x) ((x) << S_RCVTARABT)
267#define F_RCVTARABT V_RCVTARABT(1U)
268
269#define S_SIGTARABT 1
270#define V_SIGTARABT(x) ((x) << S_SIGTARABT)
271#define F_SIGTARABT V_SIGTARABT(1U)
272
273#define S_MSTDETPARERR 0
274#define V_MSTDETPARERR(x) ((x) << S_MSTDETPARERR)
275#define F_MSTDETPARERR V_MSTDETPARERR(1U)
276
277#define A_PCIX_INT_CAUSE 0x84
278
279#define A_PCIX_CFG 0x88
280
281#define S_CLIDECEN 18
282#define V_CLIDECEN(x) ((x) << S_CLIDECEN)
283#define F_CLIDECEN V_CLIDECEN(1U)
284
285#define A_PCIX_MODE 0x8c
286
287#define S_PCLKRANGE 6
288#define M_PCLKRANGE 0x3
289#define V_PCLKRANGE(x) ((x) << S_PCLKRANGE)
290#define G_PCLKRANGE(x) (((x) >> S_PCLKRANGE) & M_PCLKRANGE)
291
292#define S_PCIXINITPAT 2
293#define M_PCIXINITPAT 0xf
294#define V_PCIXINITPAT(x) ((x) << S_PCIXINITPAT)
295#define G_PCIXINITPAT(x) (((x) >> S_PCIXINITPAT) & M_PCIXINITPAT)
296
297#define S_64BIT 0
298#define V_64BIT(x) ((x) << S_64BIT)
299#define F_64BIT V_64BIT(1U)
300
301#define A_PCIE_INT_ENABLE 0x80
302
303#define S_BISTERR 15
304#define M_BISTERR 0xff
305
306#define V_BISTERR(x) ((x) << S_BISTERR)
307
308#define S_PCIE_MSIXPARERR 12
309#define M_PCIE_MSIXPARERR 0x7
310
311#define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR)
312
313#define S_PCIE_CFPARERR 11
314#define V_PCIE_CFPARERR(x) ((x) << S_PCIE_CFPARERR)
315#define F_PCIE_CFPARERR V_PCIE_CFPARERR(1U)
316
317#define S_PCIE_RFPARERR 10
318#define V_PCIE_RFPARERR(x) ((x) << S_PCIE_RFPARERR)
319#define F_PCIE_RFPARERR V_PCIE_RFPARERR(1U)
320
321#define S_PCIE_WFPARERR 9
322#define V_PCIE_WFPARERR(x) ((x) << S_PCIE_WFPARERR)
323#define F_PCIE_WFPARERR V_PCIE_WFPARERR(1U)
324
325#define S_PCIE_PIOPARERR 8
326#define V_PCIE_PIOPARERR(x) ((x) << S_PCIE_PIOPARERR)
327#define F_PCIE_PIOPARERR V_PCIE_PIOPARERR(1U)
328
329#define S_UNXSPLCPLERRC 7
330#define V_UNXSPLCPLERRC(x) ((x) << S_UNXSPLCPLERRC)
331#define F_UNXSPLCPLERRC V_UNXSPLCPLERRC(1U)
332
333#define S_UNXSPLCPLERRR 6
334#define V_UNXSPLCPLERRR(x) ((x) << S_UNXSPLCPLERRR)
335#define F_UNXSPLCPLERRR V_UNXSPLCPLERRR(1U)
336
337#define S_PEXERR 0
338#define V_PEXERR(x) ((x) << S_PEXERR)
339#define F_PEXERR V_PEXERR(1U)
340
341#define A_PCIE_INT_CAUSE 0x84
342
343#define A_PCIE_CFG 0x88
344
345#define S_PCIE_CLIDECEN 16
346#define V_PCIE_CLIDECEN(x) ((x) << S_PCIE_CLIDECEN)
347#define F_PCIE_CLIDECEN V_PCIE_CLIDECEN(1U)
348
349#define S_CRSTWRMMODE 0
350#define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE)
351#define F_CRSTWRMMODE V_CRSTWRMMODE(1U)
352
353#define A_PCIE_MODE 0x8c
354
355#define S_NUMFSTTRNSEQRX 10
356#define M_NUMFSTTRNSEQRX 0xff
357#define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX)
358#define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX)
359
360#define A_PCIE_PEX_CTRL0 0x98
361
362#define S_NUMFSTTRNSEQ 22
363#define M_NUMFSTTRNSEQ 0xff
364#define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ)
365#define G_NUMFSTTRNSEQ(x) (((x) >> S_NUMFSTTRNSEQ) & M_NUMFSTTRNSEQ)
366
367#define S_REPLAYLMT 2
368#define M_REPLAYLMT 0xfffff
369
370#define V_REPLAYLMT(x) ((x) << S_REPLAYLMT)
371
372#define A_PCIE_PEX_CTRL1 0x9c
373
374#define S_T3A_ACKLAT 0
375#define M_T3A_ACKLAT 0x7ff
376
377#define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT)
378
379#define S_ACKLAT 0
380#define M_ACKLAT 0x1fff
381
382#define V_ACKLAT(x) ((x) << S_ACKLAT)
383
384#define A_PCIE_PEX_ERR 0xa4
385
386#define A_T3DBG_GPIO_EN 0xd0
387
388#define S_GPIO11_OEN 27
389#define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
390#define F_GPIO11_OEN V_GPIO11_OEN(1U)
391
392#define S_GPIO10_OEN 26
393#define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
394#define F_GPIO10_OEN V_GPIO10_OEN(1U)
395
396#define S_GPIO7_OEN 23
397#define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
398#define F_GPIO7_OEN V_GPIO7_OEN(1U)
399
400#define S_GPIO6_OEN 22
401#define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
402#define F_GPIO6_OEN V_GPIO6_OEN(1U)
403
404#define S_GPIO5_OEN 21
405#define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
406#define F_GPIO5_OEN V_GPIO5_OEN(1U)
407
408#define S_GPIO4_OEN 20
409#define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
410#define F_GPIO4_OEN V_GPIO4_OEN(1U)
411
412#define S_GPIO2_OEN 18
413#define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
414#define F_GPIO2_OEN V_GPIO2_OEN(1U)
415
416#define S_GPIO1_OEN 17
417#define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
418#define F_GPIO1_OEN V_GPIO1_OEN(1U)
419
420#define S_GPIO0_OEN 16
421#define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
422#define F_GPIO0_OEN V_GPIO0_OEN(1U)
423
424#define S_GPIO10_OUT_VAL 10
425#define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
426#define F_GPIO10_OUT_VAL V_GPIO10_OUT_VAL(1U)
427
428#define S_GPIO7_OUT_VAL 7
429#define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
430#define F_GPIO7_OUT_VAL V_GPIO7_OUT_VAL(1U)
431
432#define S_GPIO6_OUT_VAL 6
433#define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
434#define F_GPIO6_OUT_VAL V_GPIO6_OUT_VAL(1U)
435
436#define S_GPIO5_OUT_VAL 5
437#define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
438#define F_GPIO5_OUT_VAL V_GPIO5_OUT_VAL(1U)
439
440#define S_GPIO4_OUT_VAL 4
441#define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
442#define F_GPIO4_OUT_VAL V_GPIO4_OUT_VAL(1U)
443
444#define S_GPIO2_OUT_VAL 2
445#define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
446#define F_GPIO2_OUT_VAL V_GPIO2_OUT_VAL(1U)
447
448#define S_GPIO1_OUT_VAL 1
449#define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
450#define F_GPIO1_OUT_VAL V_GPIO1_OUT_VAL(1U)
451
452#define S_GPIO0_OUT_VAL 0
453#define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
454#define F_GPIO0_OUT_VAL V_GPIO0_OUT_VAL(1U)
455
456#define A_T3DBG_INT_ENABLE 0xd8
457
458#define S_GPIO11 11
459#define V_GPIO11(x) ((x) << S_GPIO11)
460#define F_GPIO11 V_GPIO11(1U)
461
462#define S_GPIO10 10
463#define V_GPIO10(x) ((x) << S_GPIO10)
464#define F_GPIO10 V_GPIO10(1U)
465
466#define S_GPIO7 7
467#define V_GPIO7(x) ((x) << S_GPIO7)
468#define F_GPIO7 V_GPIO7(1U)
469
470#define S_GPIO6 6
471#define V_GPIO6(x) ((x) << S_GPIO6)
472#define F_GPIO6 V_GPIO6(1U)
473
474#define S_GPIO5 5
475#define V_GPIO5(x) ((x) << S_GPIO5)
476#define F_GPIO5 V_GPIO5(1U)
477
478#define S_GPIO4 4
479#define V_GPIO4(x) ((x) << S_GPIO4)
480#define F_GPIO4 V_GPIO4(1U)
481
482#define S_GPIO3 3
483#define V_GPIO3(x) ((x) << S_GPIO3)
484#define F_GPIO3 V_GPIO3(1U)
485
486#define S_GPIO2 2
487#define V_GPIO2(x) ((x) << S_GPIO2)
488#define F_GPIO2 V_GPIO2(1U)
489
490#define S_GPIO1 1
491#define V_GPIO1(x) ((x) << S_GPIO1)
492#define F_GPIO1 V_GPIO1(1U)
493
494#define S_GPIO0 0
495#define V_GPIO0(x) ((x) << S_GPIO0)
496#define F_GPIO0 V_GPIO0(1U)
497
498#define A_T3DBG_INT_CAUSE 0xdc
499
500#define A_T3DBG_GPIO_ACT_LOW 0xf0
501
502#define MC7_PMRX_BASE_ADDR 0x100
503
504#define A_MC7_CFG 0x100
505
506#define S_IFEN 13
507#define V_IFEN(x) ((x) << S_IFEN)
508#define F_IFEN V_IFEN(1U)
509
510#define S_TERM150 11
511#define V_TERM150(x) ((x) << S_TERM150)
512#define F_TERM150 V_TERM150(1U)
513
514#define S_SLOW 10
515#define V_SLOW(x) ((x) << S_SLOW)
516#define F_SLOW V_SLOW(1U)
517
518#define S_WIDTH 8
519#define M_WIDTH 0x3
520#define V_WIDTH(x) ((x) << S_WIDTH)
521#define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH)
522
523#define S_BKS 6
524#define V_BKS(x) ((x) << S_BKS)
525#define F_BKS V_BKS(1U)
526
527#define S_ORG 5
528#define V_ORG(x) ((x) << S_ORG)
529#define F_ORG V_ORG(1U)
530
531#define S_DEN 2
532#define M_DEN 0x7
533#define V_DEN(x) ((x) << S_DEN)
534#define G_DEN(x) (((x) >> S_DEN) & M_DEN)
535
536#define S_RDY 1
537#define V_RDY(x) ((x) << S_RDY)
538#define F_RDY V_RDY(1U)
539
540#define S_CLKEN 0
541#define V_CLKEN(x) ((x) << S_CLKEN)
542#define F_CLKEN V_CLKEN(1U)
543
544#define A_MC7_MODE 0x104
545
546#define S_BUSY 31
547#define V_BUSY(x) ((x) << S_BUSY)
548#define F_BUSY V_BUSY(1U)
549
550#define S_BUSY 31
551#define V_BUSY(x) ((x) << S_BUSY)
552#define F_BUSY V_BUSY(1U)
553
554#define A_MC7_EXT_MODE1 0x108
555
556#define A_MC7_EXT_MODE2 0x10c
557
558#define A_MC7_EXT_MODE3 0x110
559
560#define A_MC7_PRE 0x114
561
562#define A_MC7_REF 0x118
563
564#define S_PREREFDIV 1
565#define M_PREREFDIV 0x3fff
566#define V_PREREFDIV(x) ((x) << S_PREREFDIV)
567
568#define S_PERREFEN 0
569#define V_PERREFEN(x) ((x) << S_PERREFEN)
570#define F_PERREFEN V_PERREFEN(1U)
571
572#define A_MC7_DLL 0x11c
573
574#define S_DLLENB 1
575#define V_DLLENB(x) ((x) << S_DLLENB)
576#define F_DLLENB V_DLLENB(1U)
577
578#define S_DLLRST 0
579#define V_DLLRST(x) ((x) << S_DLLRST)
580#define F_DLLRST V_DLLRST(1U)
581
582#define A_MC7_PARM 0x120
583
584#define S_ACTTOPREDLY 26
585#define M_ACTTOPREDLY 0xf
586#define V_ACTTOPREDLY(x) ((x) << S_ACTTOPREDLY)
587
588#define S_ACTTORDWRDLY 23
589#define M_ACTTORDWRDLY 0x7
590#define V_ACTTORDWRDLY(x) ((x) << S_ACTTORDWRDLY)
591
592#define S_PRECYC 20
593#define M_PRECYC 0x7
594#define V_PRECYC(x) ((x) << S_PRECYC)
595
596#define S_REFCYC 13
597#define M_REFCYC 0x7f
598#define V_REFCYC(x) ((x) << S_REFCYC)
599
600#define S_BKCYC 8
601#define M_BKCYC 0x1f
602#define V_BKCYC(x) ((x) << S_BKCYC)
603
604#define S_WRTORDDLY 4
605#define M_WRTORDDLY 0xf
606#define V_WRTORDDLY(x) ((x) << S_WRTORDDLY)
607
608#define S_RDTOWRDLY 0
609#define M_RDTOWRDLY 0xf
610#define V_RDTOWRDLY(x) ((x) << S_RDTOWRDLY)
611
612#define A_MC7_CAL 0x128
613
614#define S_BUSY 31
615#define V_BUSY(x) ((x) << S_BUSY)
616#define F_BUSY V_BUSY(1U)
617
618#define S_BUSY 31
619#define V_BUSY(x) ((x) << S_BUSY)
620#define F_BUSY V_BUSY(1U)
621
622#define S_CAL_FAULT 30
623#define V_CAL_FAULT(x) ((x) << S_CAL_FAULT)
624#define F_CAL_FAULT V_CAL_FAULT(1U)
625
626#define S_SGL_CAL_EN 20
627#define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN)
628#define F_SGL_CAL_EN V_SGL_CAL_EN(1U)
629
630#define A_MC7_ERR_ADDR 0x12c
631
632#define A_MC7_ECC 0x130
633
634#define S_ECCCHKEN 1
635#define V_ECCCHKEN(x) ((x) << S_ECCCHKEN)
636#define F_ECCCHKEN V_ECCCHKEN(1U)
637
638#define S_ECCGENEN 0
639#define V_ECCGENEN(x) ((x) << S_ECCGENEN)
640#define F_ECCGENEN V_ECCGENEN(1U)
641
642#define A_MC7_CE_ADDR 0x134
643
644#define A_MC7_CE_DATA0 0x138
645
646#define A_MC7_CE_DATA1 0x13c
647
648#define A_MC7_CE_DATA2 0x140
649
650#define S_DATA 0
651#define M_DATA 0xff
652
653#define G_DATA(x) (((x) >> S_DATA) & M_DATA)
654
655#define A_MC7_UE_ADDR 0x144
656
657#define A_MC7_UE_DATA0 0x148
658
659#define A_MC7_UE_DATA1 0x14c
660
661#define A_MC7_UE_DATA2 0x150
662
663#define A_MC7_BD_ADDR 0x154
664
665#define S_ADDR 3
666
667#define M_ADDR 0x1fffffff
668
669#define A_MC7_BD_DATA0 0x158
670
671#define A_MC7_BD_DATA1 0x15c
672
673#define A_MC7_BD_OP 0x164
674
675#define S_OP 0
676
677#define V_OP(x) ((x) << S_OP)
678#define F_OP V_OP(1U)
679
680#define F_OP V_OP(1U)
681#define A_SF_OP 0x6dc
682
683#define A_MC7_BIST_ADDR_BEG 0x168
684
685#define A_MC7_BIST_ADDR_END 0x16c
686
687#define A_MC7_BIST_DATA 0x170
688
689#define A_MC7_BIST_OP 0x174
690
691#define S_CONT 3
692#define V_CONT(x) ((x) << S_CONT)
693#define F_CONT V_CONT(1U)
694
695#define F_CONT V_CONT(1U)
696
697#define A_MC7_INT_ENABLE 0x178
698
699#define S_AE 17
700#define V_AE(x) ((x) << S_AE)
701#define F_AE V_AE(1U)
702
703#define S_PE 2
704#define M_PE 0x7fff
705
706#define V_PE(x) ((x) << S_PE)
707
708#define G_PE(x) (((x) >> S_PE) & M_PE)
709
710#define S_UE 1
711#define V_UE(x) ((x) << S_UE)
712#define F_UE V_UE(1U)
713
714#define S_CE 0
715#define V_CE(x) ((x) << S_CE)
716#define F_CE V_CE(1U)
717
718#define A_MC7_INT_CAUSE 0x17c
719
720#define MC7_PMTX_BASE_ADDR 0x180
721
722#define MC7_CM_BASE_ADDR 0x200
723
724#define A_CIM_BOOT_CFG 0x280
725
726#define S_BOOTADDR 2
727#define M_BOOTADDR 0x3fffffff
728#define V_BOOTADDR(x) ((x) << S_BOOTADDR)
729
730#define A_CIM_SDRAM_BASE_ADDR 0x28c
731
732#define A_CIM_SDRAM_ADDR_SIZE 0x290
733
734#define A_CIM_HOST_INT_ENABLE 0x298
735
736#define A_CIM_HOST_INT_CAUSE 0x29c
737
738#define S_BLKWRPLINT 12
739#define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
740#define F_BLKWRPLINT V_BLKWRPLINT(1U)
741
742#define S_BLKRDPLINT 11
743#define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
744#define F_BLKRDPLINT V_BLKRDPLINT(1U)
745
746#define S_BLKWRCTLINT 10
747#define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
748#define F_BLKWRCTLINT V_BLKWRCTLINT(1U)
749
750#define S_BLKRDCTLINT 9
751#define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
752#define F_BLKRDCTLINT V_BLKRDCTLINT(1U)
753
754#define S_BLKWRFLASHINT 8
755#define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
756#define F_BLKWRFLASHINT V_BLKWRFLASHINT(1U)
757
758#define S_BLKRDFLASHINT 7
759#define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
760#define F_BLKRDFLASHINT V_BLKRDFLASHINT(1U)
761
762#define S_SGLWRFLASHINT 6
763#define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
764#define F_SGLWRFLASHINT V_SGLWRFLASHINT(1U)
765
766#define S_WRBLKFLASHINT 5
767#define V_WRBLKFLASHINT(x) ((x) << S_WRBLKFLASHINT)
768#define F_WRBLKFLASHINT V_WRBLKFLASHINT(1U)
769
770#define S_BLKWRBOOTINT 4
771#define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
772#define F_BLKWRBOOTINT V_BLKWRBOOTINT(1U)
773
774#define S_FLASHRANGEINT 2
775#define V_FLASHRANGEINT(x) ((x) << S_FLASHRANGEINT)
776#define F_FLASHRANGEINT V_FLASHRANGEINT(1U)
777
778#define S_SDRAMRANGEINT 1
779#define V_SDRAMRANGEINT(x) ((x) << S_SDRAMRANGEINT)
780#define F_SDRAMRANGEINT V_SDRAMRANGEINT(1U)
781
782#define S_RSVDSPACEINT 0
783#define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
784#define F_RSVDSPACEINT V_RSVDSPACEINT(1U)
785
786#define A_CIM_HOST_ACC_CTRL 0x2b0
787
788#define S_HOSTBUSY 17
789#define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
790#define F_HOSTBUSY V_HOSTBUSY(1U)
791
792#define A_CIM_HOST_ACC_DATA 0x2b4
793
794#define A_TP_IN_CONFIG 0x300
795
796#define S_NICMODE 14
797#define V_NICMODE(x) ((x) << S_NICMODE)
798#define F_NICMODE V_NICMODE(1U)
799
800#define F_NICMODE V_NICMODE(1U)
801
802#define S_IPV6ENABLE 15
803#define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE)
804#define F_IPV6ENABLE V_IPV6ENABLE(1U)
805
806#define A_TP_OUT_CONFIG 0x304
807
808#define S_VLANEXTRACTIONENABLE 12
809
810#define A_TP_GLOBAL_CONFIG 0x308
811
812#define S_TXPACINGENABLE 24
813#define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
814#define F_TXPACINGENABLE V_TXPACINGENABLE(1U)
815
816#define S_PATHMTU 15
817#define V_PATHMTU(x) ((x) << S_PATHMTU)
818#define F_PATHMTU V_PATHMTU(1U)
819
820#define S_IPCHECKSUMOFFLOAD 13
821#define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
822#define F_IPCHECKSUMOFFLOAD V_IPCHECKSUMOFFLOAD(1U)
823
824#define S_UDPCHECKSUMOFFLOAD 12
825#define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
826#define F_UDPCHECKSUMOFFLOAD V_UDPCHECKSUMOFFLOAD(1U)
827
828#define S_TCPCHECKSUMOFFLOAD 11
829#define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
830#define F_TCPCHECKSUMOFFLOAD V_TCPCHECKSUMOFFLOAD(1U)
831
832#define S_IPTTL 0
833#define M_IPTTL 0xff
834#define V_IPTTL(x) ((x) << S_IPTTL)
835
836#define A_TP_CMM_MM_BASE 0x314
837
838#define A_TP_CMM_TIMER_BASE 0x318
839
840#define S_CMTIMERMAXNUM 28
841#define M_CMTIMERMAXNUM 0x3
842#define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM)
843
844#define A_TP_PMM_SIZE 0x31c
845
846#define A_TP_PMM_TX_BASE 0x320
847
848#define A_TP_PMM_RX_BASE 0x328
849
850#define A_TP_PMM_RX_PAGE_SIZE 0x32c
851
852#define A_TP_PMM_RX_MAX_PAGE 0x330
853
854#define A_TP_PMM_TX_PAGE_SIZE 0x334
855
856#define A_TP_PMM_TX_MAX_PAGE 0x338
857
858#define A_TP_TCP_OPTIONS 0x340
859
860#define S_MTUDEFAULT 16
861#define M_MTUDEFAULT 0xffff
862#define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT)
863
864#define S_MTUENABLE 10
865#define V_MTUENABLE(x) ((x) << S_MTUENABLE)
866#define F_MTUENABLE V_MTUENABLE(1U)
867
868#define S_SACKRX 8
869#define V_SACKRX(x) ((x) << S_SACKRX)
870#define F_SACKRX V_SACKRX(1U)
871
872#define S_SACKMODE 4
873
874#define M_SACKMODE 0x3
875
876#define V_SACKMODE(x) ((x) << S_SACKMODE)
877
878#define S_WINDOWSCALEMODE 2
879#define M_WINDOWSCALEMODE 0x3
880#define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE)
881
882#define S_TIMESTAMPSMODE 0
883
884#define M_TIMESTAMPSMODE 0x3
885
886#define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE)
887
888#define A_TP_DACK_CONFIG 0x344
889
890#define S_AUTOSTATE3 30
891#define M_AUTOSTATE3 0x3
892#define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
893
894#define S_AUTOSTATE2 28
895#define M_AUTOSTATE2 0x3
896#define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
897
898#define S_AUTOSTATE1 26
899#define M_AUTOSTATE1 0x3
900#define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
901
902#define S_BYTETHRESHOLD 5
903#define M_BYTETHRESHOLD 0xfffff
904#define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
905
906#define S_MSSTHRESHOLD 3
907#define M_MSSTHRESHOLD 0x3
908#define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
909
910#define S_AUTOCAREFUL 2
911#define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL)
912#define F_AUTOCAREFUL V_AUTOCAREFUL(1U)
913
914#define S_AUTOENABLE 1
915#define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
916#define F_AUTOENABLE V_AUTOENABLE(1U)
917
918#define S_DACK_MODE 0
919#define V_DACK_MODE(x) ((x) << S_DACK_MODE)
920#define F_DACK_MODE V_DACK_MODE(1U)
921
922#define A_TP_PC_CONFIG 0x348
923
924#define S_TXTOSQUEUEMAPMODE 26
925#define V_TXTOSQUEUEMAPMODE(x) ((x) << S_TXTOSQUEUEMAPMODE)
926#define F_TXTOSQUEUEMAPMODE V_TXTOSQUEUEMAPMODE(1U)
927
928#define S_ENABLEEPCMDAFULL 23
929#define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL)
930#define F_ENABLEEPCMDAFULL V_ENABLEEPCMDAFULL(1U)
931
932#define S_MODULATEUNIONMODE 22
933#define V_MODULATEUNIONMODE(x) ((x) << S_MODULATEUNIONMODE)
934#define F_MODULATEUNIONMODE V_MODULATEUNIONMODE(1U)
935
936#define S_TXDEFERENABLE 20
937#define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE)
938#define F_TXDEFERENABLE V_TXDEFERENABLE(1U)
939
940#define S_RXCONGESTIONMODE 19
941#define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE)
942#define F_RXCONGESTIONMODE V_RXCONGESTIONMODE(1U)
943
944#define S_HEARBEATDACK 16
945#define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK)
946#define F_HEARBEATDACK V_HEARBEATDACK(1U)
947
948#define S_TXCONGESTIONMODE 15
949#define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE)
950#define F_TXCONGESTIONMODE V_TXCONGESTIONMODE(1U)
951
952#define S_ENABLEOCSPIFULL 30
953#define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL)
954#define F_ENABLEOCSPIFULL V_ENABLEOCSPIFULL(1U)
955
956#define S_LOCKTID 28
957#define V_LOCKTID(x) ((x) << S_LOCKTID)
958#define F_LOCKTID V_LOCKTID(1U)
959
960#define A_TP_PC_CONFIG2 0x34c
961
962#define S_CHDRAFULL 4
963#define V_CHDRAFULL(x) ((x) << S_CHDRAFULL)
964#define F_CHDRAFULL V_CHDRAFULL(1U)
965
966#define A_TP_TCP_BACKOFF_REG0 0x350
967
968#define A_TP_TCP_BACKOFF_REG1 0x354
969
970#define A_TP_TCP_BACKOFF_REG2 0x358
971
972#define A_TP_TCP_BACKOFF_REG3 0x35c
973
974#define A_TP_PARA_REG2 0x368
975
976#define S_MAXRXDATA 16
977#define M_MAXRXDATA 0xffff
978#define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
979
980#define S_RXCOALESCESIZE 0
981#define M_RXCOALESCESIZE 0xffff
982#define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
983
984#define A_TP_PARA_REG3 0x36c
985
986#define S_TXDATAACKIDX 16
987#define M_TXDATAACKIDX 0xf
988
989#define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX)
990
991#define S_TXPACEAUTOSTRICT 10
992#define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT)
993#define F_TXPACEAUTOSTRICT V_TXPACEAUTOSTRICT(1U)
994
995#define S_TXPACEFIXED 9
996#define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED)
997#define F_TXPACEFIXED V_TXPACEFIXED(1U)
998
999#define S_TXPACEAUTO 8
1000#define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO)
1001#define F_TXPACEAUTO V_TXPACEAUTO(1U)
1002
1003#define S_RXCOALESCEENABLE 1
1004#define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE)
1005#define F_RXCOALESCEENABLE V_RXCOALESCEENABLE(1U)
1006
1007#define S_RXCOALESCEPSHEN 0
1008#define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN)
1009#define F_RXCOALESCEPSHEN V_RXCOALESCEPSHEN(1U)
1010
1011#define A_TP_PARA_REG4 0x370
1012
1013#define A_TP_PARA_REG6 0x378
1014
1015#define S_T3A_ENABLEESND 13
1016#define V_T3A_ENABLEESND(x) ((x) << S_T3A_ENABLEESND)
1017#define F_T3A_ENABLEESND V_T3A_ENABLEESND(1U)
1018
1019#define S_ENABLEESND 11
1020#define V_ENABLEESND(x) ((x) << S_ENABLEESND)
1021#define F_ENABLEESND V_ENABLEESND(1U)
1022
1023#define A_TP_PARA_REG7 0x37c
1024
1025#define S_PMMAXXFERLEN1 16
1026#define M_PMMAXXFERLEN1 0xffff
1027#define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1)
1028
1029#define S_PMMAXXFERLEN0 0
1030#define M_PMMAXXFERLEN0 0xffff
1031#define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0)
1032
1033#define A_TP_TIMER_RESOLUTION 0x390
1034
1035#define S_TIMERRESOLUTION 16
1036#define M_TIMERRESOLUTION 0xff
1037#define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
1038
1039#define S_TIMESTAMPRESOLUTION 8
1040#define M_TIMESTAMPRESOLUTION 0xff
1041#define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
1042
1043#define S_DELAYEDACKRESOLUTION 0
1044#define M_DELAYEDACKRESOLUTION 0xff
1045#define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
1046
1047#define A_TP_MSL 0x394
1048
1049#define A_TP_RXT_MIN 0x398
1050
1051#define A_TP_RXT_MAX 0x39c
1052
1053#define A_TP_PERS_MIN 0x3a0
1054
1055#define A_TP_PERS_MAX 0x3a4
1056
1057#define A_TP_KEEP_IDLE 0x3a8
1058
1059#define A_TP_KEEP_INTVL 0x3ac
1060
1061#define A_TP_INIT_SRTT 0x3b0
1062
1063#define A_TP_DACK_TIMER 0x3b4
1064
1065#define A_TP_FINWAIT2_TIMER 0x3b8
1066
1067#define A_TP_SHIFT_CNT 0x3c0
1068
1069#define S_SYNSHIFTMAX 24
1070
1071#define M_SYNSHIFTMAX 0xff
1072
1073#define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
1074
1075#define S_RXTSHIFTMAXR1 20
1076
1077#define M_RXTSHIFTMAXR1 0xf
1078
1079#define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
1080
1081#define S_RXTSHIFTMAXR2 16
1082
1083#define M_RXTSHIFTMAXR2 0xf
1084
1085#define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
1086
1087#define S_PERSHIFTBACKOFFMAX 12
1088#define M_PERSHIFTBACKOFFMAX 0xf
1089#define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
1090
1091#define S_PERSHIFTMAX 8
1092#define M_PERSHIFTMAX 0xf
1093#define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
1094
1095#define S_KEEPALIVEMAX 0
1096
1097#define M_KEEPALIVEMAX 0xff
1098
1099#define V_KEEPALIVEMAX(x) ((x) << S_KEEPALIVEMAX)
1100
1101#define A_TP_MTU_PORT_TABLE 0x3d0
1102
1103#define A_TP_CCTRL_TABLE 0x3dc
1104
1105#define A_TP_MTU_TABLE 0x3e4
1106
1107#define A_TP_RSS_MAP_TABLE 0x3e8
1108
1109#define A_TP_RSS_LKP_TABLE 0x3ec
1110
1111#define A_TP_RSS_CONFIG 0x3f0
1112
1113#define S_TNL4TUPEN 29
1114#define V_TNL4TUPEN(x) ((x) << S_TNL4TUPEN)
1115#define F_TNL4TUPEN V_TNL4TUPEN(1U)
1116
1117#define S_TNL2TUPEN 28
1118#define V_TNL2TUPEN(x) ((x) << S_TNL2TUPEN)
1119#define F_TNL2TUPEN V_TNL2TUPEN(1U)
1120
1121#define S_TNLPRTEN 26
1122#define V_TNLPRTEN(x) ((x) << S_TNLPRTEN)
1123#define F_TNLPRTEN V_TNLPRTEN(1U)
1124
1125#define S_TNLMAPEN 25
1126#define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
1127#define F_TNLMAPEN V_TNLMAPEN(1U)
1128
1129#define S_TNLLKPEN 24
1130#define V_TNLLKPEN(x) ((x) << S_TNLLKPEN)
1131#define F_TNLLKPEN V_TNLLKPEN(1U)
1132
1133#define S_RRCPLCPUSIZE 4
1134#define M_RRCPLCPUSIZE 0x7
1135#define V_RRCPLCPUSIZE(x) ((x) << S_RRCPLCPUSIZE)
1136
1137#define S_RQFEEDBACKENABLE 3
1138#define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE)
1139#define F_RQFEEDBACKENABLE V_RQFEEDBACKENABLE(1U)
1140
1141#define S_DISABLE 0
1142
1143#define A_TP_TM_PIO_ADDR 0x418
1144
1145#define A_TP_TM_PIO_DATA 0x41c
1146
1147#define A_TP_TX_MOD_QUE_TABLE 0x420
1148
1149#define A_TP_TX_RESOURCE_LIMIT 0x424
1150
1151#define A_TP_TX_MOD_QUEUE_REQ_MAP 0x428
1152
1153#define S_TX_MOD_QUEUE_REQ_MAP 0
1154#define M_TX_MOD_QUEUE_REQ_MAP 0xff
1155#define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
1156
1157#define A_TP_TX_MOD_QUEUE_WEIGHT1 0x42c
1158
1159#define A_TP_TX_MOD_QUEUE_WEIGHT0 0x430
1160
1161#define A_TP_MOD_CHANNEL_WEIGHT 0x434
1162
Divy Le Ray8a9fab22007-05-30 21:10:52 -07001163#define A_TP_MOD_RATE_LIMIT 0x438
1164
Divy Le Ray4d22de32007-01-18 22:04:14 -05001165#define A_TP_PIO_ADDR 0x440
1166
1167#define A_TP_PIO_DATA 0x444
1168
1169#define A_TP_RESET 0x44c
1170
1171#define S_FLSTINITENABLE 1
1172#define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE)
1173#define F_FLSTINITENABLE V_FLSTINITENABLE(1U)
1174
1175#define S_TPRESET 0
1176#define V_TPRESET(x) ((x) << S_TPRESET)
1177#define F_TPRESET V_TPRESET(1U)
1178
1179#define A_TP_CMM_MM_RX_FLST_BASE 0x460
1180
1181#define A_TP_CMM_MM_TX_FLST_BASE 0x464
1182
1183#define A_TP_CMM_MM_PS_FLST_BASE 0x468
1184
1185#define A_TP_MIB_INDEX 0x450
1186
1187#define A_TP_MIB_RDATA 0x454
1188
1189#define A_TP_CMM_MM_MAX_PSTRUCT 0x46c
1190
1191#define A_TP_INT_ENABLE 0x470
1192
1193#define A_TP_INT_CAUSE 0x474
1194
1195#define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
1196
1197#define A_TP_TX_DROP_CFG_CH0 0x12b
1198
1199#define A_TP_TX_DROP_MODE 0x12f
1200
1201#define A_TP_EGRESS_CONFIG 0x145
1202
1203#define S_REWRITEFORCETOSIZE 0
1204#define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
1205#define F_REWRITEFORCETOSIZE V_REWRITEFORCETOSIZE(1U)
1206
1207#define A_TP_TX_TRC_KEY0 0x20
1208
1209#define A_TP_RX_TRC_KEY0 0x120
1210
Divy Le Rayfc906642007-03-18 13:10:12 -07001211#define A_TP_TX_DROP_CNT_CH0 0x12d
1212
1213#define S_TXDROPCNTCH0RCVD 0
1214#define M_TXDROPCNTCH0RCVD 0xffff
1215#define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
1216#define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & \
1217 M_TXDROPCNTCH0RCVD)
1218
Divy Le Ray8a9fab22007-05-30 21:10:52 -07001219#define A_TP_PROXY_FLOW_CNTL 0x4b0
1220
Divy Le Ray480fe1a2007-05-30 21:10:58 -07001221#define A_TP_EMBED_OP_FIELD0 0x4e8
1222#define A_TP_EMBED_OP_FIELD1 0x4ec
1223#define A_TP_EMBED_OP_FIELD2 0x4f0
1224#define A_TP_EMBED_OP_FIELD3 0x4f4
1225#define A_TP_EMBED_OP_FIELD4 0x4f8
1226#define A_TP_EMBED_OP_FIELD5 0x4fc
1227
Divy Le Ray4d22de32007-01-18 22:04:14 -05001228#define A_ULPRX_CTL 0x500
1229
1230#define S_ROUND_ROBIN 4
1231#define V_ROUND_ROBIN(x) ((x) << S_ROUND_ROBIN)
1232#define F_ROUND_ROBIN V_ROUND_ROBIN(1U)
1233
1234#define A_ULPRX_INT_ENABLE 0x504
1235
1236#define S_PARERR 0
1237#define V_PARERR(x) ((x) << S_PARERR)
1238#define F_PARERR V_PARERR(1U)
1239
1240#define A_ULPRX_INT_CAUSE 0x508
1241
1242#define A_ULPRX_ISCSI_LLIMIT 0x50c
1243
1244#define A_ULPRX_ISCSI_ULIMIT 0x510
1245
1246#define A_ULPRX_ISCSI_TAGMASK 0x514
1247
Divy Le Ray6cdbd772007-04-09 20:10:33 -07001248#define S_HPZ0 0
1249#define M_HPZ0 0xf
1250#define V_HPZ0(x) ((x) << S_HPZ0)
1251#define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
1252
Divy Le Ray4d22de32007-01-18 22:04:14 -05001253#define A_ULPRX_TDDP_LLIMIT 0x51c
1254
1255#define A_ULPRX_TDDP_ULIMIT 0x520
Divy Le Ray6cdbd772007-04-09 20:10:33 -07001256#define A_ULPRX_TDDP_PSZ 0x528
Divy Le Ray4d22de32007-01-18 22:04:14 -05001257
1258#define A_ULPRX_STAG_LLIMIT 0x52c
1259
1260#define A_ULPRX_STAG_ULIMIT 0x530
1261
1262#define A_ULPRX_RQ_LLIMIT 0x534
1263#define A_ULPRX_RQ_LLIMIT 0x534
1264
1265#define A_ULPRX_RQ_ULIMIT 0x538
1266#define A_ULPRX_RQ_ULIMIT 0x538
1267
1268#define A_ULPRX_PBL_LLIMIT 0x53c
1269
1270#define A_ULPRX_PBL_ULIMIT 0x540
1271#define A_ULPRX_PBL_ULIMIT 0x540
1272
1273#define A_ULPRX_TDDP_TAGMASK 0x524
1274
1275#define A_ULPRX_RQ_LLIMIT 0x534
1276#define A_ULPRX_RQ_LLIMIT 0x534
1277
1278#define A_ULPRX_RQ_ULIMIT 0x538
1279#define A_ULPRX_RQ_ULIMIT 0x538
1280
1281#define A_ULPRX_PBL_ULIMIT 0x540
1282#define A_ULPRX_PBL_ULIMIT 0x540
1283
1284#define A_ULPTX_CONFIG 0x580
1285
1286#define S_CFG_RR_ARB 0
1287#define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB)
1288#define F_CFG_RR_ARB V_CFG_RR_ARB(1U)
1289
1290#define A_ULPTX_INT_ENABLE 0x584
1291
1292#define S_PBL_BOUND_ERR_CH1 1
1293#define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
1294#define F_PBL_BOUND_ERR_CH1 V_PBL_BOUND_ERR_CH1(1U)
1295
1296#define S_PBL_BOUND_ERR_CH0 0
1297#define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
1298#define F_PBL_BOUND_ERR_CH0 V_PBL_BOUND_ERR_CH0(1U)
1299
1300#define A_ULPTX_INT_CAUSE 0x588
1301
1302#define A_ULPTX_TPT_LLIMIT 0x58c
1303
1304#define A_ULPTX_TPT_ULIMIT 0x590
1305
1306#define A_ULPTX_PBL_LLIMIT 0x594
1307
1308#define A_ULPTX_PBL_ULIMIT 0x598
1309
1310#define A_ULPTX_DMA_WEIGHT 0x5ac
1311
1312#define S_D1_WEIGHT 16
1313#define M_D1_WEIGHT 0xffff
1314#define V_D1_WEIGHT(x) ((x) << S_D1_WEIGHT)
1315
1316#define S_D0_WEIGHT 0
1317#define M_D0_WEIGHT 0xffff
1318#define V_D0_WEIGHT(x) ((x) << S_D0_WEIGHT)
1319
1320#define A_PM1_RX_CFG 0x5c0
1321
1322#define A_PM1_RX_INT_ENABLE 0x5d8
1323
1324#define S_ZERO_E_CMD_ERROR 18
1325#define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
1326#define F_ZERO_E_CMD_ERROR V_ZERO_E_CMD_ERROR(1U)
1327
1328#define S_IESPI0_FIFO2X_RX_FRAMING_ERROR 17
1329#define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
1330#define F_IESPI0_FIFO2X_RX_FRAMING_ERROR V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
1331
1332#define S_IESPI1_FIFO2X_RX_FRAMING_ERROR 16
1333#define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
1334#define F_IESPI1_FIFO2X_RX_FRAMING_ERROR V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
1335
1336#define S_IESPI0_RX_FRAMING_ERROR 15
1337#define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
1338#define F_IESPI0_RX_FRAMING_ERROR V_IESPI0_RX_FRAMING_ERROR(1U)
1339
1340#define S_IESPI1_RX_FRAMING_ERROR 14
1341#define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
1342#define F_IESPI1_RX_FRAMING_ERROR V_IESPI1_RX_FRAMING_ERROR(1U)
1343
1344#define S_IESPI0_TX_FRAMING_ERROR 13
1345#define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
1346#define F_IESPI0_TX_FRAMING_ERROR V_IESPI0_TX_FRAMING_ERROR(1U)
1347
1348#define S_IESPI1_TX_FRAMING_ERROR 12
1349#define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
1350#define F_IESPI1_TX_FRAMING_ERROR V_IESPI1_TX_FRAMING_ERROR(1U)
1351
1352#define S_OCSPI0_RX_FRAMING_ERROR 11
1353#define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
1354#define F_OCSPI0_RX_FRAMING_ERROR V_OCSPI0_RX_FRAMING_ERROR(1U)
1355
1356#define S_OCSPI1_RX_FRAMING_ERROR 10
1357#define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
1358#define F_OCSPI1_RX_FRAMING_ERROR V_OCSPI1_RX_FRAMING_ERROR(1U)
1359
1360#define S_OCSPI0_TX_FRAMING_ERROR 9
1361#define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
1362#define F_OCSPI0_TX_FRAMING_ERROR V_OCSPI0_TX_FRAMING_ERROR(1U)
1363
1364#define S_OCSPI1_TX_FRAMING_ERROR 8
1365#define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
1366#define F_OCSPI1_TX_FRAMING_ERROR V_OCSPI1_TX_FRAMING_ERROR(1U)
1367
1368#define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR 7
1369#define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
1370#define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
1371
1372#define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR 6
1373#define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
1374#define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
1375
1376#define S_IESPI_PAR_ERROR 3
1377#define M_IESPI_PAR_ERROR 0x7
1378
1379#define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
1380
1381#define S_OCSPI_PAR_ERROR 0
1382#define M_OCSPI_PAR_ERROR 0x7
1383
1384#define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
1385
1386#define A_PM1_RX_INT_CAUSE 0x5dc
1387
1388#define A_PM1_TX_CFG 0x5e0
1389
1390#define A_PM1_TX_INT_ENABLE 0x5f8
1391
1392#define S_ZERO_C_CMD_ERROR 18
1393#define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
1394#define F_ZERO_C_CMD_ERROR V_ZERO_C_CMD_ERROR(1U)
1395
1396#define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR 17
1397#define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
1398#define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
1399
1400#define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR 16
1401#define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
1402#define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
1403
1404#define S_ICSPI0_RX_FRAMING_ERROR 15
1405#define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
1406#define F_ICSPI0_RX_FRAMING_ERROR V_ICSPI0_RX_FRAMING_ERROR(1U)
1407
1408#define S_ICSPI1_RX_FRAMING_ERROR 14
1409#define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
1410#define F_ICSPI1_RX_FRAMING_ERROR V_ICSPI1_RX_FRAMING_ERROR(1U)
1411
1412#define S_ICSPI0_TX_FRAMING_ERROR 13
1413#define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
1414#define F_ICSPI0_TX_FRAMING_ERROR V_ICSPI0_TX_FRAMING_ERROR(1U)
1415
1416#define S_ICSPI1_TX_FRAMING_ERROR 12
1417#define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
1418#define F_ICSPI1_TX_FRAMING_ERROR V_ICSPI1_TX_FRAMING_ERROR(1U)
1419
1420#define S_OESPI0_RX_FRAMING_ERROR 11
1421#define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
1422#define F_OESPI0_RX_FRAMING_ERROR V_OESPI0_RX_FRAMING_ERROR(1U)
1423
1424#define S_OESPI1_RX_FRAMING_ERROR 10
1425#define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
1426#define F_OESPI1_RX_FRAMING_ERROR V_OESPI1_RX_FRAMING_ERROR(1U)
1427
1428#define S_OESPI0_TX_FRAMING_ERROR 9
1429#define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
1430#define F_OESPI0_TX_FRAMING_ERROR V_OESPI0_TX_FRAMING_ERROR(1U)
1431
1432#define S_OESPI1_TX_FRAMING_ERROR 8
1433#define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
1434#define F_OESPI1_TX_FRAMING_ERROR V_OESPI1_TX_FRAMING_ERROR(1U)
1435
1436#define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR 7
1437#define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
1438#define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
1439
1440#define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR 6
1441#define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
1442#define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
1443
1444#define S_ICSPI_PAR_ERROR 3
1445#define M_ICSPI_PAR_ERROR 0x7
1446
1447#define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
1448
1449#define S_OESPI_PAR_ERROR 0
1450#define M_OESPI_PAR_ERROR 0x7
1451
1452#define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
1453
1454#define A_PM1_TX_INT_CAUSE 0x5fc
1455
1456#define A_MPS_CFG 0x600
1457
1458#define S_TPRXPORTEN 4
1459#define V_TPRXPORTEN(x) ((x) << S_TPRXPORTEN)
1460#define F_TPRXPORTEN V_TPRXPORTEN(1U)
1461
1462#define S_TPTXPORT1EN 3
1463#define V_TPTXPORT1EN(x) ((x) << S_TPTXPORT1EN)
1464#define F_TPTXPORT1EN V_TPTXPORT1EN(1U)
1465
1466#define S_TPTXPORT0EN 2
1467#define V_TPTXPORT0EN(x) ((x) << S_TPTXPORT0EN)
1468#define F_TPTXPORT0EN V_TPTXPORT0EN(1U)
1469
1470#define S_PORT1ACTIVE 1
1471#define V_PORT1ACTIVE(x) ((x) << S_PORT1ACTIVE)
1472#define F_PORT1ACTIVE V_PORT1ACTIVE(1U)
1473
1474#define S_PORT0ACTIVE 0
1475#define V_PORT0ACTIVE(x) ((x) << S_PORT0ACTIVE)
1476#define F_PORT0ACTIVE V_PORT0ACTIVE(1U)
1477
1478#define S_ENFORCEPKT 11
1479#define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT)
1480#define F_ENFORCEPKT V_ENFORCEPKT(1U)
1481
1482#define A_MPS_INT_ENABLE 0x61c
1483
1484#define S_MCAPARERRENB 6
1485#define M_MCAPARERRENB 0x7
1486
1487#define V_MCAPARERRENB(x) ((x) << S_MCAPARERRENB)
1488
1489#define S_RXTPPARERRENB 4
1490#define M_RXTPPARERRENB 0x3
1491
1492#define V_RXTPPARERRENB(x) ((x) << S_RXTPPARERRENB)
1493
1494#define S_TX1TPPARERRENB 2
1495#define M_TX1TPPARERRENB 0x3
1496
1497#define V_TX1TPPARERRENB(x) ((x) << S_TX1TPPARERRENB)
1498
1499#define S_TX0TPPARERRENB 0
1500#define M_TX0TPPARERRENB 0x3
1501
1502#define V_TX0TPPARERRENB(x) ((x) << S_TX0TPPARERRENB)
1503
1504#define A_MPS_INT_CAUSE 0x620
1505
1506#define S_MCAPARERR 6
1507#define M_MCAPARERR 0x7
1508
1509#define V_MCAPARERR(x) ((x) << S_MCAPARERR)
1510
1511#define S_RXTPPARERR 4
1512#define M_RXTPPARERR 0x3
1513
1514#define V_RXTPPARERR(x) ((x) << S_RXTPPARERR)
1515
1516#define S_TX1TPPARERR 2
1517#define M_TX1TPPARERR 0x3
1518
1519#define V_TX1TPPARERR(x) ((x) << S_TX1TPPARERR)
1520
1521#define S_TX0TPPARERR 0
1522#define M_TX0TPPARERR 0x3
1523
1524#define V_TX0TPPARERR(x) ((x) << S_TX0TPPARERR)
1525
1526#define A_CPL_SWITCH_CNTRL 0x640
1527
1528#define A_CPL_INTR_ENABLE 0x650
1529
1530#define S_CIM_OVFL_ERROR 4
1531#define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
1532#define F_CIM_OVFL_ERROR V_CIM_OVFL_ERROR(1U)
1533
1534#define S_TP_FRAMING_ERROR 3
1535#define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
1536#define F_TP_FRAMING_ERROR V_TP_FRAMING_ERROR(1U)
1537
1538#define S_SGE_FRAMING_ERROR 2
1539#define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
1540#define F_SGE_FRAMING_ERROR V_SGE_FRAMING_ERROR(1U)
1541
1542#define S_CIM_FRAMING_ERROR 1
1543#define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
1544#define F_CIM_FRAMING_ERROR V_CIM_FRAMING_ERROR(1U)
1545
1546#define S_ZERO_SWITCH_ERROR 0
1547#define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
1548#define F_ZERO_SWITCH_ERROR V_ZERO_SWITCH_ERROR(1U)
1549
1550#define A_CPL_INTR_CAUSE 0x654
1551
1552#define A_CPL_MAP_TBL_DATA 0x65c
1553
1554#define A_SMB_GLOBAL_TIME_CFG 0x660
1555
1556#define A_I2C_CFG 0x6a0
1557
1558#define S_I2C_CLKDIV 0
1559#define M_I2C_CLKDIV 0xfff
1560#define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
1561
1562#define A_MI1_CFG 0x6b0
1563
1564#define S_CLKDIV 5
1565#define M_CLKDIV 0xff
1566#define V_CLKDIV(x) ((x) << S_CLKDIV)
1567
1568#define S_ST 3
1569
1570#define M_ST 0x3
1571
1572#define V_ST(x) ((x) << S_ST)
1573
1574#define G_ST(x) (((x) >> S_ST) & M_ST)
1575
1576#define S_PREEN 2
1577#define V_PREEN(x) ((x) << S_PREEN)
1578#define F_PREEN V_PREEN(1U)
1579
1580#define S_MDIINV 1
1581#define V_MDIINV(x) ((x) << S_MDIINV)
1582#define F_MDIINV V_MDIINV(1U)
1583
1584#define S_MDIEN 0
1585#define V_MDIEN(x) ((x) << S_MDIEN)
1586#define F_MDIEN V_MDIEN(1U)
1587
1588#define A_MI1_ADDR 0x6b4
1589
1590#define S_PHYADDR 5
1591#define M_PHYADDR 0x1f
1592#define V_PHYADDR(x) ((x) << S_PHYADDR)
1593
1594#define S_REGADDR 0
1595#define M_REGADDR 0x1f
1596#define V_REGADDR(x) ((x) << S_REGADDR)
1597
1598#define A_MI1_DATA 0x6b8
1599
1600#define A_MI1_OP 0x6bc
1601
1602#define S_MDI_OP 0
1603#define M_MDI_OP 0x3
1604#define V_MDI_OP(x) ((x) << S_MDI_OP)
1605
1606#define A_SF_DATA 0x6d8
1607
1608#define A_SF_OP 0x6dc
1609
1610#define S_BYTECNT 1
1611#define M_BYTECNT 0x3
1612#define V_BYTECNT(x) ((x) << S_BYTECNT)
1613
1614#define A_PL_INT_ENABLE0 0x6e0
1615
1616#define S_T3DBG 23
1617#define V_T3DBG(x) ((x) << S_T3DBG)
1618#define F_T3DBG V_T3DBG(1U)
1619
1620#define S_XGMAC0_1 20
1621#define V_XGMAC0_1(x) ((x) << S_XGMAC0_1)
1622#define F_XGMAC0_1 V_XGMAC0_1(1U)
1623
1624#define S_XGMAC0_0 19
1625#define V_XGMAC0_0(x) ((x) << S_XGMAC0_0)
1626#define F_XGMAC0_0 V_XGMAC0_0(1U)
1627
1628#define S_MC5A 18
1629#define V_MC5A(x) ((x) << S_MC5A)
1630#define F_MC5A V_MC5A(1U)
1631
1632#define S_CPL_SWITCH 12
1633#define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
1634#define F_CPL_SWITCH V_CPL_SWITCH(1U)
1635
1636#define S_MPS0 11
1637#define V_MPS0(x) ((x) << S_MPS0)
1638#define F_MPS0 V_MPS0(1U)
1639
1640#define S_PM1_TX 10
1641#define V_PM1_TX(x) ((x) << S_PM1_TX)
1642#define F_PM1_TX V_PM1_TX(1U)
1643
1644#define S_PM1_RX 9
1645#define V_PM1_RX(x) ((x) << S_PM1_RX)
1646#define F_PM1_RX V_PM1_RX(1U)
1647
1648#define S_ULP2_TX 8
1649#define V_ULP2_TX(x) ((x) << S_ULP2_TX)
1650#define F_ULP2_TX V_ULP2_TX(1U)
1651
1652#define S_ULP2_RX 7
1653#define V_ULP2_RX(x) ((x) << S_ULP2_RX)
1654#define F_ULP2_RX V_ULP2_RX(1U)
1655
1656#define S_TP1 6
1657#define V_TP1(x) ((x) << S_TP1)
1658#define F_TP1 V_TP1(1U)
1659
1660#define S_CIM 5
1661#define V_CIM(x) ((x) << S_CIM)
1662#define F_CIM V_CIM(1U)
1663
1664#define S_MC7_CM 4
1665#define V_MC7_CM(x) ((x) << S_MC7_CM)
1666#define F_MC7_CM V_MC7_CM(1U)
1667
1668#define S_MC7_PMTX 3
1669#define V_MC7_PMTX(x) ((x) << S_MC7_PMTX)
1670#define F_MC7_PMTX V_MC7_PMTX(1U)
1671
1672#define S_MC7_PMRX 2
1673#define V_MC7_PMRX(x) ((x) << S_MC7_PMRX)
1674#define F_MC7_PMRX V_MC7_PMRX(1U)
1675
1676#define S_PCIM0 1
1677#define V_PCIM0(x) ((x) << S_PCIM0)
1678#define F_PCIM0 V_PCIM0(1U)
1679
1680#define S_SGE3 0
1681#define V_SGE3(x) ((x) << S_SGE3)
1682#define F_SGE3 V_SGE3(1U)
1683
1684#define A_PL_INT_CAUSE0 0x6e4
1685
1686#define A_PL_RST 0x6f0
1687
1688#define S_CRSTWRM 1
1689#define V_CRSTWRM(x) ((x) << S_CRSTWRM)
1690#define F_CRSTWRM V_CRSTWRM(1U)
1691
1692#define A_PL_REV 0x6f4
1693
1694#define A_PL_CLI 0x6f8
1695
1696#define A_MC5_DB_CONFIG 0x704
1697
1698#define S_TMTYPEHI 30
1699#define V_TMTYPEHI(x) ((x) << S_TMTYPEHI)
1700#define F_TMTYPEHI V_TMTYPEHI(1U)
1701
1702#define S_TMPARTSIZE 28
1703#define M_TMPARTSIZE 0x3
1704#define V_TMPARTSIZE(x) ((x) << S_TMPARTSIZE)
1705#define G_TMPARTSIZE(x) (((x) >> S_TMPARTSIZE) & M_TMPARTSIZE)
1706
1707#define S_TMTYPE 26
1708#define M_TMTYPE 0x3
1709#define V_TMTYPE(x) ((x) << S_TMTYPE)
1710#define G_TMTYPE(x) (((x) >> S_TMTYPE) & M_TMTYPE)
1711
1712#define S_COMPEN 17
1713#define V_COMPEN(x) ((x) << S_COMPEN)
1714#define F_COMPEN V_COMPEN(1U)
1715
1716#define S_PRTYEN 6
1717#define V_PRTYEN(x) ((x) << S_PRTYEN)
1718#define F_PRTYEN V_PRTYEN(1U)
1719
1720#define S_MBUSEN 5
1721#define V_MBUSEN(x) ((x) << S_MBUSEN)
1722#define F_MBUSEN V_MBUSEN(1U)
1723
1724#define S_DBGIEN 4
1725#define V_DBGIEN(x) ((x) << S_DBGIEN)
1726#define F_DBGIEN V_DBGIEN(1U)
1727
1728#define S_TMRDY 2
1729#define V_TMRDY(x) ((x) << S_TMRDY)
1730#define F_TMRDY V_TMRDY(1U)
1731
1732#define S_TMRST 1
1733#define V_TMRST(x) ((x) << S_TMRST)
1734#define F_TMRST V_TMRST(1U)
1735
1736#define S_TMMODE 0
1737#define V_TMMODE(x) ((x) << S_TMMODE)
1738#define F_TMMODE V_TMMODE(1U)
1739
1740#define F_TMMODE V_TMMODE(1U)
1741
1742#define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c
1743
1744#define A_MC5_DB_FILTER_TABLE 0x710
1745
1746#define A_MC5_DB_SERVER_INDEX 0x714
1747
1748#define A_MC5_DB_RSP_LATENCY 0x720
1749
1750#define S_RDLAT 16
1751#define M_RDLAT 0x1f
1752#define V_RDLAT(x) ((x) << S_RDLAT)
1753
1754#define S_LRNLAT 8
1755#define M_LRNLAT 0x1f
1756#define V_LRNLAT(x) ((x) << S_LRNLAT)
1757
1758#define S_SRCHLAT 0
1759#define M_SRCHLAT 0x1f
1760#define V_SRCHLAT(x) ((x) << S_SRCHLAT)
1761
1762#define A_MC5_DB_PART_ID_INDEX 0x72c
1763
1764#define A_MC5_DB_INT_ENABLE 0x740
1765
1766#define S_DELACTEMPTY 18
1767#define V_DELACTEMPTY(x) ((x) << S_DELACTEMPTY)
1768#define F_DELACTEMPTY V_DELACTEMPTY(1U)
1769
1770#define S_DISPQPARERR 17
1771#define V_DISPQPARERR(x) ((x) << S_DISPQPARERR)
1772#define F_DISPQPARERR V_DISPQPARERR(1U)
1773
1774#define S_REQQPARERR 16
1775#define V_REQQPARERR(x) ((x) << S_REQQPARERR)
1776#define F_REQQPARERR V_REQQPARERR(1U)
1777
1778#define S_UNKNOWNCMD 15
1779#define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
1780#define F_UNKNOWNCMD V_UNKNOWNCMD(1U)
1781
1782#define S_NFASRCHFAIL 8
1783#define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
1784#define F_NFASRCHFAIL V_NFASRCHFAIL(1U)
1785
1786#define S_ACTRGNFULL 7
1787#define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
1788#define F_ACTRGNFULL V_ACTRGNFULL(1U)
1789
1790#define S_PARITYERR 6
1791#define V_PARITYERR(x) ((x) << S_PARITYERR)
1792#define F_PARITYERR V_PARITYERR(1U)
1793
1794#define A_MC5_DB_INT_CAUSE 0x744
1795
1796#define A_MC5_DB_DBGI_CONFIG 0x774
1797
1798#define A_MC5_DB_DBGI_REQ_CMD 0x778
1799
1800#define A_MC5_DB_DBGI_REQ_ADDR0 0x77c
1801
1802#define A_MC5_DB_DBGI_REQ_ADDR1 0x780
1803
1804#define A_MC5_DB_DBGI_REQ_ADDR2 0x784
1805
1806#define A_MC5_DB_DBGI_REQ_DATA0 0x788
1807
1808#define A_MC5_DB_DBGI_REQ_DATA1 0x78c
1809
1810#define A_MC5_DB_DBGI_REQ_DATA2 0x790
1811
1812#define A_MC5_DB_DBGI_RSP_STATUS 0x7b0
1813
1814#define S_DBGIRSPVALID 0
1815#define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
1816#define F_DBGIRSPVALID V_DBGIRSPVALID(1U)
1817
1818#define A_MC5_DB_DBGI_RSP_DATA0 0x7b4
1819
1820#define A_MC5_DB_DBGI_RSP_DATA1 0x7b8
1821
1822#define A_MC5_DB_DBGI_RSP_DATA2 0x7bc
1823
1824#define A_MC5_DB_POPEN_DATA_WR_CMD 0x7cc
1825
1826#define A_MC5_DB_POPEN_MASK_WR_CMD 0x7d0
1827
1828#define A_MC5_DB_AOPEN_SRCH_CMD 0x7d4
1829
1830#define A_MC5_DB_AOPEN_LRN_CMD 0x7d8
1831
1832#define A_MC5_DB_SYN_SRCH_CMD 0x7dc
1833
1834#define A_MC5_DB_SYN_LRN_CMD 0x7e0
1835
1836#define A_MC5_DB_ACK_SRCH_CMD 0x7e4
1837
1838#define A_MC5_DB_ACK_LRN_CMD 0x7e8
1839
1840#define A_MC5_DB_ILOOKUP_CMD 0x7ec
1841
1842#define A_MC5_DB_ELOOKUP_CMD 0x7f0
1843
1844#define A_MC5_DB_DATA_WRITE_CMD 0x7f4
1845
1846#define A_MC5_DB_DATA_READ_CMD 0x7f8
1847
1848#define XGMAC0_0_BASE_ADDR 0x800
1849
1850#define A_XGM_TX_CTRL 0x800
1851
1852#define S_TXEN 0
1853#define V_TXEN(x) ((x) << S_TXEN)
1854#define F_TXEN V_TXEN(1U)
1855
1856#define A_XGM_TX_CFG 0x804
1857
1858#define S_TXPAUSEEN 0
1859#define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
1860#define F_TXPAUSEEN V_TXPAUSEEN(1U)
1861
Divy Le Rayfc906642007-03-18 13:10:12 -07001862#define A_XGM_TX_PAUSE_QUANTA 0x808
1863
Divy Le Ray4d22de32007-01-18 22:04:14 -05001864#define A_XGM_RX_CTRL 0x80c
1865
1866#define S_RXEN 0
1867#define V_RXEN(x) ((x) << S_RXEN)
1868#define F_RXEN V_RXEN(1U)
1869
1870#define A_XGM_RX_CFG 0x810
1871
1872#define S_DISPAUSEFRAMES 9
1873#define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES)
1874#define F_DISPAUSEFRAMES V_DISPAUSEFRAMES(1U)
1875
1876#define S_EN1536BFRAMES 8
1877#define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES)
1878#define F_EN1536BFRAMES V_EN1536BFRAMES(1U)
1879
1880#define S_ENJUMBO 7
1881#define V_ENJUMBO(x) ((x) << S_ENJUMBO)
1882#define F_ENJUMBO V_ENJUMBO(1U)
1883
1884#define S_RMFCS 6
1885#define V_RMFCS(x) ((x) << S_RMFCS)
1886#define F_RMFCS V_RMFCS(1U)
1887
1888#define S_ENHASHMCAST 2
1889#define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST)
1890#define F_ENHASHMCAST V_ENHASHMCAST(1U)
1891
1892#define S_COPYALLFRAMES 0
1893#define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES)
1894#define F_COPYALLFRAMES V_COPYALLFRAMES(1U)
1895
Divy Le Ray7b581a02007-05-30 10:01:44 -07001896#define S_DISBCAST 1
1897#define V_DISBCAST(x) ((x) << S_DISBCAST)
1898#define F_DISBCAST V_DISBCAST(1U)
1899
Divy Le Ray4d22de32007-01-18 22:04:14 -05001900#define A_XGM_RX_HASH_LOW 0x814
1901
1902#define A_XGM_RX_HASH_HIGH 0x818
1903
1904#define A_XGM_RX_EXACT_MATCH_LOW_1 0x81c
1905
1906#define A_XGM_RX_EXACT_MATCH_HIGH_1 0x820
1907
1908#define A_XGM_RX_EXACT_MATCH_LOW_2 0x824
1909
1910#define A_XGM_RX_EXACT_MATCH_LOW_3 0x82c
1911
1912#define A_XGM_RX_EXACT_MATCH_LOW_4 0x834
1913
1914#define A_XGM_RX_EXACT_MATCH_LOW_5 0x83c
1915
1916#define A_XGM_RX_EXACT_MATCH_LOW_6 0x844
1917
1918#define A_XGM_RX_EXACT_MATCH_LOW_7 0x84c
1919
1920#define A_XGM_RX_EXACT_MATCH_LOW_8 0x854
1921
1922#define A_XGM_STAT_CTRL 0x880
1923
1924#define S_CLRSTATS 2
1925#define V_CLRSTATS(x) ((x) << S_CLRSTATS)
1926#define F_CLRSTATS V_CLRSTATS(1U)
1927
1928#define A_XGM_RXFIFO_CFG 0x884
1929
1930#define S_RXFIFOPAUSEHWM 17
1931#define M_RXFIFOPAUSEHWM 0xfff
1932
1933#define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM)
1934
1935#define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM)
1936
1937#define S_RXFIFOPAUSELWM 5
1938#define M_RXFIFOPAUSELWM 0xfff
1939
1940#define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM)
1941
1942#define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM)
1943
1944#define S_RXSTRFRWRD 1
1945#define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD)
1946#define F_RXSTRFRWRD V_RXSTRFRWRD(1U)
1947
1948#define S_DISERRFRAMES 0
1949#define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES)
1950#define F_DISERRFRAMES V_DISERRFRAMES(1U)
1951
1952#define A_XGM_TXFIFO_CFG 0x888
1953
Divy Le Rayfc906642007-03-18 13:10:12 -07001954#define S_TXIPG 13
1955#define M_TXIPG 0xff
1956#define V_TXIPG(x) ((x) << S_TXIPG)
1957#define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG)
1958
Divy Le Ray4d22de32007-01-18 22:04:14 -05001959#define S_TXFIFOTHRESH 4
1960#define M_TXFIFOTHRESH 0x1ff
1961
1962#define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH)
1963
Divy Le Ray6d6daba2007-03-31 00:23:24 -07001964#define S_ENDROPPKT 21
1965#define V_ENDROPPKT(x) ((x) << S_ENDROPPKT)
1966#define F_ENDROPPKT V_ENDROPPKT(1U)
1967
Divy Le Ray4d22de32007-01-18 22:04:14 -05001968#define A_XGM_SERDES_CTRL 0x890
1969#define A_XGM_SERDES_CTRL0 0x8e0
1970
1971#define S_SERDESRESET_ 24
1972#define V_SERDESRESET_(x) ((x) << S_SERDESRESET_)
1973#define F_SERDESRESET_ V_SERDESRESET_(1U)
1974
1975#define S_RXENABLE 4
1976#define V_RXENABLE(x) ((x) << S_RXENABLE)
1977#define F_RXENABLE V_RXENABLE(1U)
1978
1979#define S_TXENABLE 3
1980#define V_TXENABLE(x) ((x) << S_TXENABLE)
1981#define F_TXENABLE V_TXENABLE(1U)
1982
1983#define A_XGM_PAUSE_TIMER 0x890
1984
1985#define A_XGM_RGMII_IMP 0x89c
1986
1987#define S_XGM_IMPSETUPDATE 6
1988#define V_XGM_IMPSETUPDATE(x) ((x) << S_XGM_IMPSETUPDATE)
1989#define F_XGM_IMPSETUPDATE V_XGM_IMPSETUPDATE(1U)
1990
1991#define S_RGMIIIMPPD 3
1992#define M_RGMIIIMPPD 0x7
1993#define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD)
1994
1995#define S_RGMIIIMPPU 0
1996#define M_RGMIIIMPPU 0x7
1997#define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU)
1998
1999#define S_CALRESET 8
2000#define V_CALRESET(x) ((x) << S_CALRESET)
2001#define F_CALRESET V_CALRESET(1U)
2002
2003#define S_CALUPDATE 7
2004#define V_CALUPDATE(x) ((x) << S_CALUPDATE)
2005#define F_CALUPDATE V_CALUPDATE(1U)
2006
2007#define A_XGM_XAUI_IMP 0x8a0
2008
2009#define S_CALBUSY 31
2010#define V_CALBUSY(x) ((x) << S_CALBUSY)
2011#define F_CALBUSY V_CALBUSY(1U)
2012
2013#define S_XGM_CALFAULT 29
2014#define V_XGM_CALFAULT(x) ((x) << S_XGM_CALFAULT)
2015#define F_XGM_CALFAULT V_XGM_CALFAULT(1U)
2016
2017#define S_CALIMP 24
2018#define M_CALIMP 0x1f
2019#define V_CALIMP(x) ((x) << S_CALIMP)
2020#define G_CALIMP(x) (((x) >> S_CALIMP) & M_CALIMP)
2021
2022#define S_XAUIIMP 0
2023#define M_XAUIIMP 0x7
2024#define V_XAUIIMP(x) ((x) << S_XAUIIMP)
2025
2026#define A_XGM_RX_MAX_PKT_SIZE 0x8a8
2027#define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4
2028
2029#define A_XGM_RESET_CTRL 0x8ac
2030
2031#define S_XG2G_RESET_ 3
2032#define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_)
2033#define F_XG2G_RESET_ V_XG2G_RESET_(1U)
2034
2035#define S_RGMII_RESET_ 2
2036#define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_)
2037#define F_RGMII_RESET_ V_RGMII_RESET_(1U)
2038
2039#define S_PCS_RESET_ 1
2040#define V_PCS_RESET_(x) ((x) << S_PCS_RESET_)
2041#define F_PCS_RESET_ V_PCS_RESET_(1U)
2042
2043#define S_MAC_RESET_ 0
2044#define V_MAC_RESET_(x) ((x) << S_MAC_RESET_)
2045#define F_MAC_RESET_ V_MAC_RESET_(1U)
2046
2047#define A_XGM_PORT_CFG 0x8b8
2048
2049#define S_CLKDIVRESET_ 3
2050#define V_CLKDIVRESET_(x) ((x) << S_CLKDIVRESET_)
2051#define F_CLKDIVRESET_ V_CLKDIVRESET_(1U)
2052
2053#define S_PORTSPEED 1
2054#define M_PORTSPEED 0x3
2055
2056#define V_PORTSPEED(x) ((x) << S_PORTSPEED)
2057
2058#define S_ENRGMII 0
2059#define V_ENRGMII(x) ((x) << S_ENRGMII)
2060#define F_ENRGMII V_ENRGMII(1U)
2061
2062#define A_XGM_INT_ENABLE 0x8d4
2063
2064#define S_TXFIFO_PRTY_ERR 17
2065#define M_TXFIFO_PRTY_ERR 0x7
2066
2067#define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
2068
2069#define S_RXFIFO_PRTY_ERR 14
2070#define M_RXFIFO_PRTY_ERR 0x7
2071
2072#define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
2073
2074#define S_TXFIFO_UNDERRUN 13
2075#define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN)
2076#define F_TXFIFO_UNDERRUN V_TXFIFO_UNDERRUN(1U)
2077
2078#define S_RXFIFO_OVERFLOW 12
2079#define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW)
2080#define F_RXFIFO_OVERFLOW V_RXFIFO_OVERFLOW(1U)
2081
2082#define S_SERDES_LOS 4
2083#define M_SERDES_LOS 0xf
2084
2085#define V_SERDES_LOS(x) ((x) << S_SERDES_LOS)
2086
2087#define S_XAUIPCSCTCERR 3
2088#define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR)
2089#define F_XAUIPCSCTCERR V_XAUIPCSCTCERR(1U)
2090
2091#define S_XAUIPCSALIGNCHANGE 2
2092#define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE)
2093#define F_XAUIPCSALIGNCHANGE V_XAUIPCSALIGNCHANGE(1U)
2094
2095#define A_XGM_INT_CAUSE 0x8d8
2096
2097#define A_XGM_XAUI_ACT_CTRL 0x8dc
2098
2099#define S_TXACTENABLE 1
2100#define V_TXACTENABLE(x) ((x) << S_TXACTENABLE)
2101#define F_TXACTENABLE V_TXACTENABLE(1U)
2102
2103#define A_XGM_SERDES_CTRL0 0x8e0
2104
2105#define S_RESET3 23
2106#define V_RESET3(x) ((x) << S_RESET3)
2107#define F_RESET3 V_RESET3(1U)
2108
2109#define S_RESET2 22
2110#define V_RESET2(x) ((x) << S_RESET2)
2111#define F_RESET2 V_RESET2(1U)
2112
2113#define S_RESET1 21
2114#define V_RESET1(x) ((x) << S_RESET1)
2115#define F_RESET1 V_RESET1(1U)
2116
2117#define S_RESET0 20
2118#define V_RESET0(x) ((x) << S_RESET0)
2119#define F_RESET0 V_RESET0(1U)
2120
2121#define S_PWRDN3 19
2122#define V_PWRDN3(x) ((x) << S_PWRDN3)
2123#define F_PWRDN3 V_PWRDN3(1U)
2124
2125#define S_PWRDN2 18
2126#define V_PWRDN2(x) ((x) << S_PWRDN2)
2127#define F_PWRDN2 V_PWRDN2(1U)
2128
2129#define S_PWRDN1 17
2130#define V_PWRDN1(x) ((x) << S_PWRDN1)
2131#define F_PWRDN1 V_PWRDN1(1U)
2132
2133#define S_PWRDN0 16
2134#define V_PWRDN0(x) ((x) << S_PWRDN0)
2135#define F_PWRDN0 V_PWRDN0(1U)
2136
2137#define S_RESETPLL23 15
2138#define V_RESETPLL23(x) ((x) << S_RESETPLL23)
2139#define F_RESETPLL23 V_RESETPLL23(1U)
2140
2141#define S_RESETPLL01 14
2142#define V_RESETPLL01(x) ((x) << S_RESETPLL01)
2143#define F_RESETPLL01 V_RESETPLL01(1U)
2144
2145#define A_XGM_SERDES_STAT0 0x8f0
Divy Le Rayc706bfb2007-05-30 10:01:39 -07002146#define A_XGM_SERDES_STAT1 0x8f4
2147#define A_XGM_SERDES_STAT2 0x8f8
Divy Le Ray4d22de32007-01-18 22:04:14 -05002148
2149#define S_LOWSIG0 0
2150#define V_LOWSIG0(x) ((x) << S_LOWSIG0)
2151#define F_LOWSIG0 V_LOWSIG0(1U)
2152
2153#define A_XGM_SERDES_STAT3 0x8fc
2154
2155#define A_XGM_STAT_TX_BYTE_LOW 0x900
2156
2157#define A_XGM_STAT_TX_BYTE_HIGH 0x904
2158
2159#define A_XGM_STAT_TX_FRAME_LOW 0x908
2160
2161#define A_XGM_STAT_TX_FRAME_HIGH 0x90c
2162
2163#define A_XGM_STAT_TX_BCAST 0x910
2164
2165#define A_XGM_STAT_TX_MCAST 0x914
2166
2167#define A_XGM_STAT_TX_PAUSE 0x918
2168
2169#define A_XGM_STAT_TX_64B_FRAMES 0x91c
2170
2171#define A_XGM_STAT_TX_65_127B_FRAMES 0x920
2172
2173#define A_XGM_STAT_TX_128_255B_FRAMES 0x924
2174
2175#define A_XGM_STAT_TX_256_511B_FRAMES 0x928
2176
2177#define A_XGM_STAT_TX_512_1023B_FRAMES 0x92c
2178
2179#define A_XGM_STAT_TX_1024_1518B_FRAMES 0x930
2180
2181#define A_XGM_STAT_TX_1519_MAXB_FRAMES 0x934
2182
2183#define A_XGM_STAT_TX_ERR_FRAMES 0x938
2184
2185#define A_XGM_STAT_RX_BYTES_LOW 0x93c
2186
2187#define A_XGM_STAT_RX_BYTES_HIGH 0x940
2188
2189#define A_XGM_STAT_RX_FRAMES_LOW 0x944
2190
2191#define A_XGM_STAT_RX_FRAMES_HIGH 0x948
2192
2193#define A_XGM_STAT_RX_BCAST_FRAMES 0x94c
2194
2195#define A_XGM_STAT_RX_MCAST_FRAMES 0x950
2196
2197#define A_XGM_STAT_RX_PAUSE_FRAMES 0x954
2198
2199#define A_XGM_STAT_RX_64B_FRAMES 0x958
2200
2201#define A_XGM_STAT_RX_65_127B_FRAMES 0x95c
2202
2203#define A_XGM_STAT_RX_128_255B_FRAMES 0x960
2204
2205#define A_XGM_STAT_RX_256_511B_FRAMES 0x964
2206
2207#define A_XGM_STAT_RX_512_1023B_FRAMES 0x968
2208
2209#define A_XGM_STAT_RX_1024_1518B_FRAMES 0x96c
2210
2211#define A_XGM_STAT_RX_1519_MAXB_FRAMES 0x970
2212
2213#define A_XGM_STAT_RX_SHORT_FRAMES 0x974
2214
2215#define A_XGM_STAT_RX_OVERSIZE_FRAMES 0x978
2216
2217#define A_XGM_STAT_RX_JABBER_FRAMES 0x97c
2218
2219#define A_XGM_STAT_RX_CRC_ERR_FRAMES 0x980
2220
2221#define A_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x984
2222
2223#define A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x988
2224
2225#define A_XGM_SERDES_STATUS0 0x98c
2226
2227#define A_XGM_SERDES_STATUS1 0x990
2228
2229#define S_CMULOCK 31
2230#define V_CMULOCK(x) ((x) << S_CMULOCK)
2231#define F_CMULOCK V_CMULOCK(1U)
2232
2233#define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4
2234
Divy Le Rayfc906642007-03-18 13:10:12 -07002235#define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8
2236
2237#define S_TXSPI4SOPCNT 16
2238#define M_TXSPI4SOPCNT 0xffff
2239#define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT)
2240#define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT)
2241
Divy Le Ray4d22de32007-01-18 22:04:14 -05002242#define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac
2243
2244#define XGMAC0_1_BASE_ADDR 0xa00