Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2007 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | */ |
| 26 | |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 27 | #include <linux/dmi.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/drmP.h> |
| 31 | #include <drm/drm_crtc.h> |
| 32 | #include <drm/drm_crtc_helper.h> |
| 33 | #include <drm/drm_edid.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 34 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 35 | #include <drm/i915_drm.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include "i915_drv.h" |
| 37 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 38 | /* Here's the desired hotplug mode */ |
| 39 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ |
| 40 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ |
| 41 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ |
| 42 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ |
| 43 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ |
| 44 | ADPA_CRT_HOTPLUG_ENABLE) |
| 45 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 46 | struct intel_crt { |
| 47 | struct intel_encoder base; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 48 | bool force_hotplug_required; |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 49 | u32 adpa_reg; |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 50 | }; |
| 51 | |
| 52 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
| 53 | { |
| 54 | return container_of(intel_attached_encoder(connector), |
| 55 | struct intel_crt, base); |
| 56 | } |
| 57 | |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 58 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
| 59 | { |
| 60 | return container_of(encoder, struct intel_crt, base); |
| 61 | } |
| 62 | |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 63 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
| 64 | enum pipe *pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 65 | { |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 66 | struct drm_device *dev = encoder->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 67 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 68 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
| 69 | u32 tmp; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 70 | |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 71 | tmp = I915_READ(crt->adpa_reg); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 72 | |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 73 | if (!(tmp & ADPA_DAC_ENABLE)) |
| 74 | return false; |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 75 | |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 76 | if (HAS_PCH_CPT(dev)) |
| 77 | *pipe = PORT_TO_PIPE_CPT(tmp); |
| 78 | else |
| 79 | *pipe = PORT_TO_PIPE(tmp); |
| 80 | |
| 81 | return true; |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 82 | } |
| 83 | |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 84 | static void intel_disable_crt(struct intel_encoder *encoder) |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 85 | { |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 86 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 87 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 88 | u32 temp; |
| 89 | |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 90 | temp = I915_READ(crt->adpa_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 91 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
ling.ma@intel.com | febc769 | 2009-06-25 11:55:57 +0800 | [diff] [blame] | 92 | temp &= ~ADPA_DAC_ENABLE; |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 93 | I915_WRITE(crt->adpa_reg, temp); |
| 94 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 95 | |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 96 | static void intel_enable_crt(struct intel_encoder *encoder) |
| 97 | { |
| 98 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 99 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
| 100 | u32 temp; |
| 101 | |
| 102 | temp = I915_READ(crt->adpa_reg); |
| 103 | temp |= ADPA_DAC_ENABLE; |
| 104 | I915_WRITE(crt->adpa_reg, temp); |
| 105 | } |
| 106 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 107 | /* Note: The caller is required to filter out dpms modes not supported by the |
| 108 | * platform. */ |
| 109 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 110 | { |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 111 | struct drm_device *dev = encoder->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 112 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 113 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 114 | u32 temp; |
| 115 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 116 | temp = I915_READ(crt->adpa_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 117 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
| 118 | temp &= ~ADPA_DAC_ENABLE; |
Jesse Barnes | bd9e841 | 2012-06-15 11:55:18 -0700 | [diff] [blame] | 119 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 120 | switch (mode) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 121 | case DRM_MODE_DPMS_ON: |
| 122 | temp |= ADPA_DAC_ENABLE; |
| 123 | break; |
| 124 | case DRM_MODE_DPMS_STANDBY: |
| 125 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
| 126 | break; |
| 127 | case DRM_MODE_DPMS_SUSPEND: |
| 128 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
| 129 | break; |
| 130 | case DRM_MODE_DPMS_OFF: |
| 131 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
| 132 | break; |
| 133 | } |
| 134 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 135 | I915_WRITE(crt->adpa_reg, temp); |
| 136 | } |
| 137 | |
| 138 | static void intel_crt_dpms(struct drm_connector *connector, int mode) |
| 139 | { |
| 140 | struct drm_device *dev = connector->dev; |
| 141 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
| 142 | struct drm_crtc *crtc; |
| 143 | int old_dpms; |
| 144 | |
| 145 | /* PCH platforms and VLV only support on/off. */ |
| 146 | if (INTEL_INFO(dev)->gen < 5 && mode != DRM_MODE_DPMS_ON) |
| 147 | mode = DRM_MODE_DPMS_OFF; |
| 148 | |
| 149 | if (mode == connector->dpms) |
| 150 | return; |
| 151 | |
| 152 | old_dpms = connector->dpms; |
| 153 | connector->dpms = mode; |
| 154 | |
| 155 | /* Only need to change hw state when actually enabled */ |
| 156 | crtc = encoder->base.crtc; |
| 157 | if (!crtc) { |
| 158 | encoder->connectors_active = false; |
| 159 | return; |
| 160 | } |
| 161 | |
| 162 | /* We need the pipe to run for anything but OFF. */ |
| 163 | if (mode == DRM_MODE_DPMS_OFF) |
| 164 | encoder->connectors_active = false; |
| 165 | else |
| 166 | encoder->connectors_active = true; |
| 167 | |
| 168 | if (mode < old_dpms) { |
| 169 | /* From off to on, enable the pipe first. */ |
| 170 | intel_crtc_update_dpms(crtc); |
| 171 | |
| 172 | intel_crt_set_dpms(encoder, mode); |
| 173 | } else { |
| 174 | intel_crt_set_dpms(encoder, mode); |
| 175 | |
| 176 | intel_crtc_update_dpms(crtc); |
| 177 | } |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 178 | |
Daniel Vetter | b980514 | 2012-08-31 17:37:33 +0200 | [diff] [blame] | 179 | intel_modeset_check_state(connector->dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 180 | } |
| 181 | |
| 182 | static int intel_crt_mode_valid(struct drm_connector *connector, |
| 183 | struct drm_display_mode *mode) |
| 184 | { |
Zhao Yakui | 6bcdcd9 | 2009-03-03 18:06:42 +0800 | [diff] [blame] | 185 | struct drm_device *dev = connector->dev; |
| 186 | |
| 187 | int max_clock = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 188 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 189 | return MODE_NO_DBLESCAN; |
| 190 | |
Zhao Yakui | 6bcdcd9 | 2009-03-03 18:06:42 +0800 | [diff] [blame] | 191 | if (mode->clock < 25000) |
| 192 | return MODE_CLOCK_LOW; |
| 193 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 194 | if (IS_GEN2(dev)) |
Zhao Yakui | 6bcdcd9 | 2009-03-03 18:06:42 +0800 | [diff] [blame] | 195 | max_clock = 350000; |
| 196 | else |
| 197 | max_clock = 400000; |
| 198 | if (mode->clock > max_clock) |
| 199 | return MODE_CLOCK_HIGH; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 200 | |
| 201 | return MODE_OK; |
| 202 | } |
| 203 | |
| 204 | static bool intel_crt_mode_fixup(struct drm_encoder *encoder, |
Laurent Pinchart | e811f5a | 2012-07-17 17:56:50 +0200 | [diff] [blame] | 205 | const struct drm_display_mode *mode, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 206 | struct drm_display_mode *adjusted_mode) |
| 207 | { |
| 208 | return true; |
| 209 | } |
| 210 | |
| 211 | static void intel_crt_mode_set(struct drm_encoder *encoder, |
| 212 | struct drm_display_mode *mode, |
| 213 | struct drm_display_mode *adjusted_mode) |
| 214 | { |
| 215 | |
| 216 | struct drm_device *dev = encoder->dev; |
| 217 | struct drm_crtc *crtc = encoder->crtc; |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 218 | struct intel_crt *crt = |
| 219 | intel_encoder_to_crt(to_intel_encoder(encoder)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 220 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 221 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 222 | int dpll_md_reg; |
| 223 | u32 adpa, dpll_md; |
| 224 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 225 | dpll_md_reg = DPLL_MD(intel_crtc->pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 226 | |
| 227 | /* |
| 228 | * Disable separate mode multiplier used when cloning SDVO to CRT |
| 229 | * XXX this needs to be adjusted when we really are cloning |
| 230 | */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 231 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 232 | dpll_md = I915_READ(dpll_md_reg); |
| 233 | I915_WRITE(dpll_md_reg, |
| 234 | dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); |
| 235 | } |
| 236 | |
Daniel Vetter | 912d812 | 2012-10-11 20:08:23 +0200 | [diff] [blame] | 237 | if (HAS_PCH_SPLIT(dev)) |
| 238 | adpa = ADPA_HOTPLUG_BITS; |
| 239 | else |
| 240 | adpa = 0; |
| 241 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 242 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 243 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
| 244 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 245 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
| 246 | |
Jesse Barnes | 7577056 | 2011-10-12 09:01:58 -0700 | [diff] [blame] | 247 | /* For CPT allow 3 pipe config, for others just use A or B */ |
Paulo Zanoni | 4837813 | 2012-10-31 18:12:20 -0200 | [diff] [blame^] | 248 | if (HAS_PCH_LPT(dev)) |
| 249 | ; /* Those bits don't exist here */ |
| 250 | else if (HAS_PCH_CPT(dev)) |
Jesse Barnes | 7577056 | 2011-10-12 09:01:58 -0700 | [diff] [blame] | 251 | adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
| 252 | else if (intel_crtc->pipe == 0) |
| 253 | adpa |= ADPA_PIPE_A_SELECT; |
| 254 | else |
| 255 | adpa |= ADPA_PIPE_B_SELECT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 256 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 257 | if (!HAS_PCH_SPLIT(dev)) |
| 258 | I915_WRITE(BCLRPAT(intel_crtc->pipe), 0); |
| 259 | |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 260 | I915_WRITE(crt->adpa_reg, adpa); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 261 | } |
| 262 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 263 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 264 | { |
| 265 | struct drm_device *dev = connector->dev; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 266 | struct intel_crt *crt = intel_attached_crt(connector); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 267 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 268 | u32 adpa; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 269 | bool ret; |
| 270 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 271 | /* The first time through, trigger an explicit detection cycle */ |
| 272 | if (crt->force_hotplug_required) { |
| 273 | bool turn_off_dac = HAS_PCH_SPLIT(dev); |
| 274 | u32 save_adpa; |
Zhenyu Wang | 67941da | 2009-07-24 01:00:33 +0800 | [diff] [blame] | 275 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 276 | crt->force_hotplug_required = 0; |
Dave Airlie | d5dd96c | 2010-08-04 15:52:19 +1000 | [diff] [blame] | 277 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 278 | save_adpa = adpa = I915_READ(PCH_ADPA); |
| 279 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
Dave Airlie | d5dd96c | 2010-08-04 15:52:19 +1000 | [diff] [blame] | 280 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 281 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
| 282 | if (turn_off_dac) |
| 283 | adpa &= ~ADPA_DAC_ENABLE; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 284 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 285 | I915_WRITE(PCH_ADPA, adpa); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 286 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 287 | if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
| 288 | 1000)) |
| 289 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 290 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 291 | if (turn_off_dac) { |
| 292 | I915_WRITE(PCH_ADPA, save_adpa); |
| 293 | POSTING_READ(PCH_ADPA); |
| 294 | } |
Zhenyu Wang | a4a6b90 | 2010-04-07 16:15:55 +0800 | [diff] [blame] | 295 | } |
| 296 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 297 | /* Check the status to see if both blue and green are on now */ |
| 298 | adpa = I915_READ(PCH_ADPA); |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 299 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 300 | ret = true; |
| 301 | else |
| 302 | ret = false; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 303 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 304 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 305 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 306 | } |
| 307 | |
Jesse Barnes | 7d2c24e | 2012-06-15 11:55:15 -0700 | [diff] [blame] | 308 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
| 309 | { |
| 310 | struct drm_device *dev = connector->dev; |
| 311 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 312 | u32 adpa; |
| 313 | bool ret; |
| 314 | u32 save_adpa; |
| 315 | |
| 316 | save_adpa = adpa = I915_READ(ADPA); |
| 317 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
| 318 | |
| 319 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
| 320 | |
| 321 | I915_WRITE(ADPA, adpa); |
| 322 | |
| 323 | if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
| 324 | 1000)) { |
| 325 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
| 326 | I915_WRITE(ADPA, save_adpa); |
| 327 | } |
| 328 | |
| 329 | /* Check the status to see if both blue and green are on now */ |
| 330 | adpa = I915_READ(ADPA); |
| 331 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
| 332 | ret = true; |
| 333 | else |
| 334 | ret = false; |
| 335 | |
| 336 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); |
| 337 | |
| 338 | /* FIXME: debug force function and remove */ |
| 339 | ret = true; |
| 340 | |
| 341 | return ret; |
| 342 | } |
| 343 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 344 | /** |
| 345 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. |
| 346 | * |
| 347 | * Not for i915G/i915GM |
| 348 | * |
| 349 | * \return true if CRT is connected. |
| 350 | * \return false if CRT is disconnected. |
| 351 | */ |
| 352 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
| 353 | { |
| 354 | struct drm_device *dev = connector->dev; |
| 355 | struct drm_i915_private *dev_priv = dev->dev_private; |
Adam Jackson | 7a772c4 | 2010-05-24 16:46:29 -0400 | [diff] [blame] | 356 | u32 hotplug_en, orig, stat; |
| 357 | bool ret = false; |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 358 | int i, tries = 0; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 359 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 360 | if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 361 | return intel_ironlake_crt_detect_hotplug(connector); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 362 | |
Jesse Barnes | 7d2c24e | 2012-06-15 11:55:15 -0700 | [diff] [blame] | 363 | if (IS_VALLEYVIEW(dev)) |
| 364 | return valleyview_crt_detect_hotplug(connector); |
| 365 | |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 366 | /* |
| 367 | * On 4 series desktop, CRT detect sequence need to be done twice |
| 368 | * to get a reliable result. |
| 369 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 370 | |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 371 | if (IS_G4X(dev) && !IS_GM45(dev)) |
| 372 | tries = 2; |
| 373 | else |
| 374 | tries = 1; |
Adam Jackson | 7a772c4 | 2010-05-24 16:46:29 -0400 | [diff] [blame] | 375 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 376 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 377 | |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 378 | for (i = 0; i < tries ; i++) { |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 379 | /* turn on the FORCE_DETECT */ |
| 380 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 381 | /* wait for FORCE_DETECT to go off */ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 382 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
| 383 | CRT_HOTPLUG_FORCE_DETECT) == 0, |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 384 | 1000)) |
Chris Wilson | 7907731 | 2010-09-12 19:58:04 +0100 | [diff] [blame] | 385 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 386 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 387 | |
Adam Jackson | 7a772c4 | 2010-05-24 16:46:29 -0400 | [diff] [blame] | 388 | stat = I915_READ(PORT_HOTPLUG_STAT); |
| 389 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) |
| 390 | ret = true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 391 | |
Adam Jackson | 7a772c4 | 2010-05-24 16:46:29 -0400 | [diff] [blame] | 392 | /* clear the interrupt we just generated, if any */ |
| 393 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); |
| 394 | |
| 395 | /* and put the bits back */ |
| 396 | I915_WRITE(PORT_HOTPLUG_EN, orig); |
| 397 | |
| 398 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 399 | } |
| 400 | |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 401 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
| 402 | struct i2c_adapter *i2c) |
| 403 | { |
| 404 | struct edid *edid; |
| 405 | |
| 406 | edid = drm_get_edid(connector, i2c); |
| 407 | |
| 408 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { |
| 409 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); |
| 410 | intel_gmbus_force_bit(i2c, true); |
| 411 | edid = drm_get_edid(connector, i2c); |
| 412 | intel_gmbus_force_bit(i2c, false); |
| 413 | } |
| 414 | |
| 415 | return edid; |
| 416 | } |
| 417 | |
| 418 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ |
| 419 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, |
| 420 | struct i2c_adapter *adapter) |
| 421 | { |
| 422 | struct edid *edid; |
Jani Nikula | ebda95a | 2012-10-19 14:51:51 +0300 | [diff] [blame] | 423 | int ret; |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 424 | |
| 425 | edid = intel_crt_get_edid(connector, adapter); |
| 426 | if (!edid) |
| 427 | return 0; |
| 428 | |
Jani Nikula | ebda95a | 2012-10-19 14:51:51 +0300 | [diff] [blame] | 429 | ret = intel_connector_update_modes(connector, edid); |
| 430 | kfree(edid); |
| 431 | |
| 432 | return ret; |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 433 | } |
| 434 | |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 435 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 436 | { |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 437 | struct intel_crt *crt = intel_attached_crt(connector); |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 438 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 439 | struct edid *edid; |
| 440 | struct i2c_adapter *i2c; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 441 | |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 442 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 443 | |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 444 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin); |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 445 | edid = intel_crt_get_edid(connector, i2c); |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 446 | |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 447 | if (edid) { |
| 448 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; |
| 449 | |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 450 | /* |
| 451 | * This may be a DVI-I connector with a shared DDC |
| 452 | * link between analog and digital outputs, so we |
| 453 | * have to check the EDID input spec of the attached device. |
| 454 | */ |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 455 | if (!is_digital) { |
| 456 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); |
| 457 | return true; |
| 458 | } |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 459 | |
| 460 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); |
| 461 | } else { |
| 462 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); |
Chris Wilson | 6ec3d0c | 2010-09-22 18:17:01 +0100 | [diff] [blame] | 463 | } |
| 464 | |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 465 | kfree(edid); |
| 466 | |
Chris Wilson | 6ec3d0c | 2010-09-22 18:17:01 +0100 | [diff] [blame] | 467 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 468 | } |
| 469 | |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 470 | static enum drm_connector_status |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 471 | intel_crt_load_detect(struct intel_crt *crt) |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 472 | { |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 473 | struct drm_device *dev = crt->base.base.dev; |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 474 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 475 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 476 | uint32_t save_bclrpat; |
| 477 | uint32_t save_vtotal; |
| 478 | uint32_t vtotal, vactive; |
| 479 | uint32_t vsample; |
| 480 | uint32_t vblank, vblank_start, vblank_end; |
| 481 | uint32_t dsl; |
| 482 | uint32_t bclrpat_reg; |
| 483 | uint32_t vtotal_reg; |
| 484 | uint32_t vblank_reg; |
| 485 | uint32_t vsync_reg; |
| 486 | uint32_t pipeconf_reg; |
| 487 | uint32_t pipe_dsl_reg; |
| 488 | uint8_t st00; |
| 489 | enum drm_connector_status status; |
| 490 | |
Chris Wilson | 6ec3d0c | 2010-09-22 18:17:01 +0100 | [diff] [blame] | 491 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
| 492 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 493 | bclrpat_reg = BCLRPAT(pipe); |
| 494 | vtotal_reg = VTOTAL(pipe); |
| 495 | vblank_reg = VBLANK(pipe); |
| 496 | vsync_reg = VSYNC(pipe); |
| 497 | pipeconf_reg = PIPECONF(pipe); |
| 498 | pipe_dsl_reg = PIPEDSL(pipe); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 499 | |
| 500 | save_bclrpat = I915_READ(bclrpat_reg); |
| 501 | save_vtotal = I915_READ(vtotal_reg); |
| 502 | vblank = I915_READ(vblank_reg); |
| 503 | |
| 504 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; |
| 505 | vactive = (save_vtotal & 0x7ff) + 1; |
| 506 | |
| 507 | vblank_start = (vblank & 0xfff) + 1; |
| 508 | vblank_end = ((vblank >> 16) & 0xfff) + 1; |
| 509 | |
| 510 | /* Set the border color to purple. */ |
| 511 | I915_WRITE(bclrpat_reg, 0x500050); |
| 512 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 513 | if (!IS_GEN2(dev)) { |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 514 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
| 515 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
Chris Wilson | 19c55da | 2010-08-09 14:50:53 +0100 | [diff] [blame] | 516 | POSTING_READ(pipeconf_reg); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 517 | /* Wait for next Vblank to substitue |
| 518 | * border color for Color info */ |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 519 | intel_wait_for_vblank(dev, pipe); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 520 | st00 = I915_READ8(VGA_MSR_WRITE); |
| 521 | status = ((st00 & (1 << 4)) != 0) ? |
| 522 | connector_status_connected : |
| 523 | connector_status_disconnected; |
| 524 | |
| 525 | I915_WRITE(pipeconf_reg, pipeconf); |
| 526 | } else { |
| 527 | bool restore_vblank = false; |
| 528 | int count, detect; |
| 529 | |
| 530 | /* |
| 531 | * If there isn't any border, add some. |
| 532 | * Yes, this will flicker |
| 533 | */ |
| 534 | if (vblank_start <= vactive && vblank_end >= vtotal) { |
| 535 | uint32_t vsync = I915_READ(vsync_reg); |
| 536 | uint32_t vsync_start = (vsync & 0xffff) + 1; |
| 537 | |
| 538 | vblank_start = vsync_start; |
| 539 | I915_WRITE(vblank_reg, |
| 540 | (vblank_start - 1) | |
| 541 | ((vblank_end - 1) << 16)); |
| 542 | restore_vblank = true; |
| 543 | } |
| 544 | /* sample in the vertical border, selecting the larger one */ |
| 545 | if (vblank_start - vactive >= vtotal - vblank_end) |
| 546 | vsample = (vblank_start + vactive) >> 1; |
| 547 | else |
| 548 | vsample = (vtotal + vblank_end) >> 1; |
| 549 | |
| 550 | /* |
| 551 | * Wait for the border to be displayed |
| 552 | */ |
| 553 | while (I915_READ(pipe_dsl_reg) >= vactive) |
| 554 | ; |
| 555 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) |
| 556 | ; |
| 557 | /* |
| 558 | * Watch ST00 for an entire scanline |
| 559 | */ |
| 560 | detect = 0; |
| 561 | count = 0; |
| 562 | do { |
| 563 | count++; |
| 564 | /* Read the ST00 VGA status register */ |
| 565 | st00 = I915_READ8(VGA_MSR_WRITE); |
| 566 | if (st00 & (1 << 4)) |
| 567 | detect++; |
| 568 | } while ((I915_READ(pipe_dsl_reg) == dsl)); |
| 569 | |
| 570 | /* restore vblank if necessary */ |
| 571 | if (restore_vblank) |
| 572 | I915_WRITE(vblank_reg, vblank); |
| 573 | /* |
| 574 | * If more than 3/4 of the scanline detected a monitor, |
| 575 | * then it is assumed to be present. This works even on i830, |
| 576 | * where there isn't any way to force the border color across |
| 577 | * the screen |
| 578 | */ |
| 579 | status = detect * 4 > count * 3 ? |
| 580 | connector_status_connected : |
| 581 | connector_status_disconnected; |
| 582 | } |
| 583 | |
| 584 | /* Restore previous settings */ |
| 585 | I915_WRITE(bclrpat_reg, save_bclrpat); |
| 586 | |
| 587 | return status; |
| 588 | } |
| 589 | |
Chris Wilson | 7b334fc | 2010-09-09 23:51:02 +0100 | [diff] [blame] | 590 | static enum drm_connector_status |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 591 | intel_crt_detect(struct drm_connector *connector, bool force) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 592 | { |
| 593 | struct drm_device *dev = connector->dev; |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 594 | struct intel_crt *crt = intel_attached_crt(connector); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 595 | enum drm_connector_status status; |
Daniel Vetter | e95c843 | 2012-04-20 21:03:36 +0200 | [diff] [blame] | 596 | struct intel_load_detect_pipe tmp; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 597 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 598 | if (I915_HAS_HOTPLUG(dev)) { |
Daniel Vetter | aaa3773 | 2012-06-16 15:30:32 +0200 | [diff] [blame] | 599 | /* We can not rely on the HPD pin always being correctly wired |
| 600 | * up, for example many KVM do not pass it through, and so |
| 601 | * only trust an assertion that the monitor is connected. |
| 602 | */ |
Chris Wilson | 6ec3d0c | 2010-09-22 18:17:01 +0100 | [diff] [blame] | 603 | if (intel_crt_detect_hotplug(connector)) { |
| 604 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 605 | return connector_status_connected; |
Daniel Vetter | aaa3773 | 2012-06-16 15:30:32 +0200 | [diff] [blame] | 606 | } else |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 607 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 608 | } |
| 609 | |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 610 | if (intel_crt_detect_ddc(connector)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 611 | return connector_status_connected; |
| 612 | |
Daniel Vetter | aaa3773 | 2012-06-16 15:30:32 +0200 | [diff] [blame] | 613 | /* Load detection is broken on HPD capable machines. Whoever wants a |
| 614 | * broken monitor (without edid) to work behind a broken kvm (that fails |
| 615 | * to have the right resistors for HP detection) needs to fix this up. |
| 616 | * For now just bail out. */ |
| 617 | if (I915_HAS_HOTPLUG(dev)) |
| 618 | return connector_status_disconnected; |
| 619 | |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 620 | if (!force) |
Chris Wilson | 7b334fc | 2010-09-09 23:51:02 +0100 | [diff] [blame] | 621 | return connector->status; |
| 622 | |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 623 | /* for pre-945g platforms use load detect */ |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 624 | if (intel_get_load_detect_pipe(connector, NULL, &tmp)) { |
Daniel Vetter | e95c843 | 2012-04-20 21:03:36 +0200 | [diff] [blame] | 625 | if (intel_crt_detect_ddc(connector)) |
| 626 | status = connector_status_connected; |
| 627 | else |
| 628 | status = intel_crt_load_detect(crt); |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 629 | intel_release_load_detect_pipe(connector, &tmp); |
Daniel Vetter | e95c843 | 2012-04-20 21:03:36 +0200 | [diff] [blame] | 630 | } else |
| 631 | status = connector_status_unknown; |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 632 | |
| 633 | return status; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 634 | } |
| 635 | |
| 636 | static void intel_crt_destroy(struct drm_connector *connector) |
| 637 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 638 | drm_sysfs_connector_remove(connector); |
| 639 | drm_connector_cleanup(connector); |
| 640 | kfree(connector); |
| 641 | } |
| 642 | |
| 643 | static int intel_crt_get_modes(struct drm_connector *connector) |
| 644 | { |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 645 | struct drm_device *dev = connector->dev; |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 646 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 647 | int ret; |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 648 | struct i2c_adapter *i2c; |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 649 | |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 650 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin); |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 651 | ret = intel_crt_ddc_get_modes(connector, i2c); |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 652 | if (ret || !IS_G4X(dev)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 653 | return ret; |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 654 | |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 655 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 656 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 657 | return intel_crt_ddc_get_modes(connector, i2c); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 658 | } |
| 659 | |
| 660 | static int intel_crt_set_property(struct drm_connector *connector, |
| 661 | struct drm_property *property, |
| 662 | uint64_t value) |
| 663 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 664 | return 0; |
| 665 | } |
| 666 | |
Chris Wilson | f326905 | 2011-01-24 15:17:08 +0000 | [diff] [blame] | 667 | static void intel_crt_reset(struct drm_connector *connector) |
| 668 | { |
| 669 | struct drm_device *dev = connector->dev; |
Daniel Vetter | 2e93889 | 2012-10-11 20:08:24 +0200 | [diff] [blame] | 670 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | f326905 | 2011-01-24 15:17:08 +0000 | [diff] [blame] | 671 | struct intel_crt *crt = intel_attached_crt(connector); |
| 672 | |
Daniel Vetter | 2e93889 | 2012-10-11 20:08:24 +0200 | [diff] [blame] | 673 | if (HAS_PCH_SPLIT(dev)) { |
| 674 | u32 adpa; |
| 675 | |
| 676 | adpa = I915_READ(PCH_ADPA); |
| 677 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
| 678 | adpa |= ADPA_HOTPLUG_BITS; |
| 679 | I915_WRITE(PCH_ADPA, adpa); |
| 680 | POSTING_READ(PCH_ADPA); |
| 681 | |
| 682 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); |
Chris Wilson | f326905 | 2011-01-24 15:17:08 +0000 | [diff] [blame] | 683 | crt->force_hotplug_required = 1; |
Daniel Vetter | 2e93889 | 2012-10-11 20:08:24 +0200 | [diff] [blame] | 684 | } |
| 685 | |
Chris Wilson | f326905 | 2011-01-24 15:17:08 +0000 | [diff] [blame] | 686 | } |
| 687 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 688 | /* |
| 689 | * Routines for controlling stuff on the analog port |
| 690 | */ |
| 691 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 692 | static const struct drm_encoder_helper_funcs crt_encoder_funcs = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 693 | .mode_fixup = intel_crt_mode_fixup, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 694 | .mode_set = intel_crt_mode_set, |
Daniel Vetter | 1f70385 | 2012-07-11 16:51:39 +0200 | [diff] [blame] | 695 | .disable = intel_encoder_noop, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 696 | }; |
| 697 | |
| 698 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
Chris Wilson | f326905 | 2011-01-24 15:17:08 +0000 | [diff] [blame] | 699 | .reset = intel_crt_reset, |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 700 | .dpms = intel_crt_dpms, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 701 | .detect = intel_crt_detect, |
| 702 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 703 | .destroy = intel_crt_destroy, |
| 704 | .set_property = intel_crt_set_property, |
| 705 | }; |
| 706 | |
| 707 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { |
| 708 | .mode_valid = intel_crt_mode_valid, |
| 709 | .get_modes = intel_crt_get_modes, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 710 | .best_encoder = intel_best_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 711 | }; |
| 712 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 713 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 714 | .destroy = intel_encoder_destroy, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 715 | }; |
| 716 | |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 717 | static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
| 718 | { |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 719 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 720 | return 1; |
| 721 | } |
| 722 | |
| 723 | static const struct dmi_system_id intel_no_crt[] = { |
| 724 | { |
| 725 | .callback = intel_no_crt_dmi_callback, |
| 726 | .ident = "ACER ZGB", |
| 727 | .matches = { |
| 728 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), |
| 729 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), |
| 730 | }, |
| 731 | }, |
| 732 | { } |
| 733 | }; |
| 734 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 735 | void intel_crt_init(struct drm_device *dev) |
| 736 | { |
| 737 | struct drm_connector *connector; |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 738 | struct intel_crt *crt; |
Zhenyu Wang | 454c1ca | 2010-03-29 15:53:23 +0800 | [diff] [blame] | 739 | struct intel_connector *intel_connector; |
David Müller (ELSOFT AG) | db54501 | 2009-08-29 08:54:45 +0200 | [diff] [blame] | 740 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 741 | |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 742 | /* Skip machines without VGA that falsely report hotplug events */ |
| 743 | if (dmi_check_system(intel_no_crt)) |
| 744 | return; |
| 745 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 746 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
| 747 | if (!crt) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 748 | return; |
| 749 | |
Zhenyu Wang | 454c1ca | 2010-03-29 15:53:23 +0800 | [diff] [blame] | 750 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
| 751 | if (!intel_connector) { |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 752 | kfree(crt); |
Zhenyu Wang | 454c1ca | 2010-03-29 15:53:23 +0800 | [diff] [blame] | 753 | return; |
| 754 | } |
| 755 | |
| 756 | connector = &intel_connector->base; |
| 757 | drm_connector_init(dev, &intel_connector->base, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 758 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
| 759 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 760 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 761 | DRM_MODE_ENCODER_DAC); |
| 762 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 763 | intel_connector_attach_encoder(intel_connector, &crt->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 764 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 765 | crt->base.type = INTEL_OUTPUT_ANALOG; |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 766 | crt->base.cloneable = true; |
Eugeni Dodonov | 59c859d | 2012-05-09 15:37:19 -0300 | [diff] [blame] | 767 | if (IS_HASWELL(dev)) |
| 768 | crt->base.crtc_mask = (1 << 0); |
| 769 | else |
Keith Packard | 0826874 | 2012-08-13 21:34:45 -0700 | [diff] [blame] | 770 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
Eugeni Dodonov | 59c859d | 2012-05-09 15:37:19 -0300 | [diff] [blame] | 771 | |
Daniel Vetter | dbb0257 | 2012-01-28 14:49:23 +0100 | [diff] [blame] | 772 | if (IS_GEN2(dev)) |
| 773 | connector->interlace_allowed = 0; |
| 774 | else |
| 775 | connector->interlace_allowed = 1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 776 | connector->doublescan_allowed = 0; |
| 777 | |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 778 | if (HAS_PCH_SPLIT(dev)) |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 779 | crt->adpa_reg = PCH_ADPA; |
| 780 | else if (IS_VALLEYVIEW(dev)) |
| 781 | crt->adpa_reg = VLV_ADPA; |
| 782 | else |
| 783 | crt->adpa_reg = ADPA; |
| 784 | |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 785 | crt->base.disable = intel_disable_crt; |
| 786 | crt->base.enable = intel_enable_crt; |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 787 | crt->base.get_hw_state = intel_crt_get_hw_state; |
| 788 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 789 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 790 | drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 791 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
| 792 | |
| 793 | drm_sysfs_connector_add(connector); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 794 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 795 | if (I915_HAS_HOTPLUG(dev)) |
| 796 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 797 | else |
| 798 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
| 799 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 800 | /* |
| 801 | * Configure the automatic hotplug detection stuff |
| 802 | */ |
| 803 | crt->force_hotplug_required = 0; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 804 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 805 | dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 806 | } |