Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2010 Atheros Communications Inc. |
| 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
| 17 | #include "hw.h" |
| 18 | #include "ar9003_phy.h" |
| 19 | #include "ar9003_eeprom.h" |
| 20 | |
| 21 | #define COMP_HDR_LEN 4 |
| 22 | #define COMP_CKSUM_LEN 2 |
| 23 | |
| 24 | #define AR_CH0_TOP (0x00016288) |
Vasanthakumar Thiagarajan | 52a0e24 | 2010-11-10 05:03:11 -0800 | [diff] [blame] | 25 | #define AR_CH0_TOP_XPABIASLVL (0x300) |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 26 | #define AR_CH0_TOP_XPABIASLVL_S (8) |
| 27 | |
| 28 | #define AR_CH0_THERM (0x00016290) |
Vasanthakumar Thiagarajan | 52a0e24 | 2010-11-10 05:03:11 -0800 | [diff] [blame] | 29 | #define AR_CH0_THERM_XPABIASLVL_MSB 0x3 |
| 30 | #define AR_CH0_THERM_XPABIASLVL_MSB_S 0 |
| 31 | #define AR_CH0_THERM_XPASHORT2GND 0x4 |
| 32 | #define AR_CH0_THERM_XPASHORT2GND_S 2 |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 33 | |
| 34 | #define AR_SWITCH_TABLE_COM_ALL (0xffff) |
| 35 | #define AR_SWITCH_TABLE_COM_ALL_S (0) |
| 36 | |
| 37 | #define AR_SWITCH_TABLE_COM2_ALL (0xffffff) |
| 38 | #define AR_SWITCH_TABLE_COM2_ALL_S (0) |
| 39 | |
| 40 | #define AR_SWITCH_TABLE_ALL (0xfff) |
| 41 | #define AR_SWITCH_TABLE_ALL_S (0) |
| 42 | |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 43 | #define LE16(x) __constant_cpu_to_le16(x) |
| 44 | #define LE32(x) __constant_cpu_to_le32(x) |
| 45 | |
Luis R. Rodriguez | 824b185 | 2010-08-01 02:25:16 -0400 | [diff] [blame] | 46 | /* Local defines to distinguish between extension and control CTL's */ |
| 47 | #define EXT_ADDITIVE (0x8000) |
| 48 | #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) |
| 49 | #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) |
| 50 | #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) |
| 51 | #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ |
| 52 | #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */ |
| 53 | #define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */ |
| 54 | #define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */ |
| 55 | #define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */ |
| 56 | |
| 57 | #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */ |
| 58 | #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ |
| 59 | |
Vasanthakumar Thiagarajan | f4475a6 | 2010-11-10 05:03:12 -0800 | [diff] [blame] | 60 | static int ar9003_hw_power_interpolate(int32_t x, |
| 61 | int32_t *px, int32_t *py, u_int16_t np); |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 62 | static const struct ar9300_eeprom ar9300_default = { |
| 63 | .eepromVersion = 2, |
| 64 | .templateVersion = 2, |
| 65 | .macAddr = {1, 2, 3, 4, 5, 6}, |
| 66 | .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 67 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, |
| 68 | .baseEepHeader = { |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 69 | .regDmn = { LE16(0), LE16(0x1f) }, |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 70 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ |
| 71 | .opCapFlags = { |
| 72 | .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, |
| 73 | .eepMisc = 0, |
| 74 | }, |
| 75 | .rfSilent = 0, |
| 76 | .blueToothOptions = 0, |
| 77 | .deviceCap = 0, |
| 78 | .deviceType = 5, /* takes lower byte in eeprom location */ |
| 79 | .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, |
| 80 | .params_for_tuning_caps = {0, 0}, |
| 81 | .featureEnable = 0x0c, |
| 82 | /* |
| 83 | * bit0 - enable tx temp comp - disabled |
| 84 | * bit1 - enable tx volt comp - disabled |
| 85 | * bit2 - enable fastClock - enabled |
| 86 | * bit3 - enable doubling - enabled |
| 87 | * bit4 - enable internal regulator - disabled |
Felix Fietkau | 4935250 | 2010-06-12 00:33:59 -0400 | [diff] [blame] | 88 | * bit5 - enable pa predistortion - disabled |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 89 | */ |
| 90 | .miscConfiguration = 0, /* bit0 - turn down drivestrength */ |
| 91 | .eepromWriteEnableGpio = 3, |
| 92 | .wlanDisableGpio = 0, |
| 93 | .wlanLedGpio = 8, |
| 94 | .rxBandSelectGpio = 0xff, |
| 95 | .txrxgain = 0, |
| 96 | .swreg = 0, |
| 97 | }, |
| 98 | .modalHeader2G = { |
| 99 | /* ar9300_modal_eep_header 2g */ |
| 100 | /* 4 idle,t1,t2,b(4 bits per setting) */ |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 101 | .antCtrlCommon = LE32(0x110), |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 102 | /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 103 | .antCtrlCommon2 = LE32(0x22222), |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 104 | |
| 105 | /* |
| 106 | * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, |
| 107 | * rx1, rx12, b (2 bits each) |
| 108 | */ |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 109 | .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) }, |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 110 | |
| 111 | /* |
| 112 | * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db |
| 113 | * for ar9280 (0xa20c/b20c 5:0) |
| 114 | */ |
| 115 | .xatten1DB = {0, 0, 0}, |
| 116 | |
| 117 | /* |
| 118 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin |
| 119 | * for ar9280 (0xa20c/b20c 16:12 |
| 120 | */ |
| 121 | .xatten1Margin = {0, 0, 0}, |
| 122 | .tempSlope = 36, |
| 123 | .voltSlope = 0, |
| 124 | |
| 125 | /* |
| 126 | * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur |
| 127 | * channels in usual fbin coding format |
| 128 | */ |
| 129 | .spurChans = {0, 0, 0, 0, 0}, |
| 130 | |
| 131 | /* |
| 132 | * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check |
| 133 | * if the register is per chain |
| 134 | */ |
| 135 | .noiseFloorThreshCh = {-1, 0, 0}, |
| 136 | .ob = {1, 1, 1},/* 3 chain */ |
| 137 | .db_stage2 = {1, 1, 1}, /* 3 chain */ |
| 138 | .db_stage3 = {0, 0, 0}, |
| 139 | .db_stage4 = {0, 0, 0}, |
| 140 | .xpaBiasLvl = 0, |
| 141 | .txFrameToDataStart = 0x0e, |
| 142 | .txFrameToPaOn = 0x0e, |
| 143 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ |
| 144 | .antennaGain = 0, |
| 145 | .switchSettling = 0x2c, |
| 146 | .adcDesiredSize = -30, |
| 147 | .txEndToXpaOff = 0, |
| 148 | .txEndToRxOn = 0x2, |
| 149 | .txFrameToXpaOn = 0xe, |
| 150 | .thresh62 = 28, |
Senthil Balasubramanian | 3ceb801 | 2010-11-10 05:03:09 -0800 | [diff] [blame] | 151 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), |
| 152 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), |
Felix Fietkau | 4935250 | 2010-06-12 00:33:59 -0400 | [diff] [blame] | 153 | .futureModal = { |
Senthil Balasubramanian | b3dd6bc | 2010-11-10 05:03:07 -0800 | [diff] [blame] | 154 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 155 | }, |
| 156 | }, |
Senthil Balasubramanian | b3dd6bc | 2010-11-10 05:03:07 -0800 | [diff] [blame] | 157 | .base_ext1 = { |
| 158 | .ant_div_control = 0, |
| 159 | .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} |
| 160 | }, |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 161 | .calFreqPier2G = { |
| 162 | FREQ2FBIN(2412, 1), |
| 163 | FREQ2FBIN(2437, 1), |
| 164 | FREQ2FBIN(2472, 1), |
| 165 | }, |
| 166 | /* ar9300_cal_data_per_freq_op_loop 2g */ |
| 167 | .calPierData2G = { |
| 168 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, |
| 169 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, |
| 170 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, |
| 171 | }, |
| 172 | .calTarget_freqbin_Cck = { |
| 173 | FREQ2FBIN(2412, 1), |
| 174 | FREQ2FBIN(2484, 1), |
| 175 | }, |
| 176 | .calTarget_freqbin_2G = { |
| 177 | FREQ2FBIN(2412, 1), |
| 178 | FREQ2FBIN(2437, 1), |
| 179 | FREQ2FBIN(2472, 1) |
| 180 | }, |
| 181 | .calTarget_freqbin_2GHT20 = { |
| 182 | FREQ2FBIN(2412, 1), |
| 183 | FREQ2FBIN(2437, 1), |
| 184 | FREQ2FBIN(2472, 1) |
| 185 | }, |
| 186 | .calTarget_freqbin_2GHT40 = { |
| 187 | FREQ2FBIN(2412, 1), |
| 188 | FREQ2FBIN(2437, 1), |
| 189 | FREQ2FBIN(2472, 1) |
| 190 | }, |
| 191 | .calTargetPowerCck = { |
| 192 | /* 1L-5L,5S,11L,11S */ |
| 193 | { {36, 36, 36, 36} }, |
| 194 | { {36, 36, 36, 36} }, |
| 195 | }, |
| 196 | .calTargetPower2G = { |
| 197 | /* 6-24,36,48,54 */ |
| 198 | { {32, 32, 28, 24} }, |
| 199 | { {32, 32, 28, 24} }, |
| 200 | { {32, 32, 28, 24} }, |
| 201 | }, |
| 202 | .calTargetPower2GHT20 = { |
| 203 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, |
| 204 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, |
| 205 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, |
| 206 | }, |
| 207 | .calTargetPower2GHT40 = { |
| 208 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, |
| 209 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, |
| 210 | { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, |
| 211 | }, |
| 212 | .ctlIndex_2G = { |
| 213 | 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, |
| 214 | 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, |
| 215 | }, |
| 216 | .ctl_freqbin_2G = { |
| 217 | { |
| 218 | FREQ2FBIN(2412, 1), |
| 219 | FREQ2FBIN(2417, 1), |
| 220 | FREQ2FBIN(2457, 1), |
| 221 | FREQ2FBIN(2462, 1) |
| 222 | }, |
| 223 | { |
| 224 | FREQ2FBIN(2412, 1), |
| 225 | FREQ2FBIN(2417, 1), |
| 226 | FREQ2FBIN(2462, 1), |
| 227 | 0xFF, |
| 228 | }, |
| 229 | |
| 230 | { |
| 231 | FREQ2FBIN(2412, 1), |
| 232 | FREQ2FBIN(2417, 1), |
| 233 | FREQ2FBIN(2462, 1), |
| 234 | 0xFF, |
| 235 | }, |
| 236 | { |
| 237 | FREQ2FBIN(2422, 1), |
| 238 | FREQ2FBIN(2427, 1), |
| 239 | FREQ2FBIN(2447, 1), |
| 240 | FREQ2FBIN(2452, 1) |
| 241 | }, |
| 242 | |
| 243 | { |
| 244 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 245 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 246 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 247 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), |
| 248 | }, |
| 249 | |
| 250 | { |
| 251 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 252 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 253 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 254 | 0, |
| 255 | }, |
| 256 | |
| 257 | { |
| 258 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 259 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 260 | FREQ2FBIN(2472, 1), |
| 261 | 0, |
| 262 | }, |
| 263 | |
| 264 | { |
| 265 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), |
| 266 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), |
| 267 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), |
| 268 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), |
| 269 | }, |
| 270 | |
| 271 | { |
| 272 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 273 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 274 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 275 | }, |
| 276 | |
| 277 | { |
| 278 | /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 279 | /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 280 | /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 281 | 0 |
| 282 | }, |
| 283 | |
| 284 | { |
| 285 | /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 286 | /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 287 | /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 288 | 0 |
| 289 | }, |
| 290 | |
| 291 | { |
| 292 | /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), |
| 293 | /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), |
| 294 | /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), |
Senthil Balasubramanian | b3dd6bc | 2010-11-10 05:03:07 -0800 | [diff] [blame] | 295 | /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 296 | } |
| 297 | }, |
| 298 | .ctlPowerData_2G = { |
| 299 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 300 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 301 | { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } }, |
| 302 | |
| 303 | { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } }, |
| 304 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 305 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 306 | |
| 307 | { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } }, |
| 308 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 309 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 310 | |
| 311 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 312 | { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } }, |
Senthil Balasubramanian | ef5a6a7 | 2010-11-10 05:03:08 -0800 | [diff] [blame] | 313 | { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } }, |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 314 | }, |
| 315 | .modalHeader5G = { |
| 316 | /* 4 idle,t1,t2,b (4 bits per setting) */ |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 317 | .antCtrlCommon = LE32(0x110), |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 318 | /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 319 | .antCtrlCommon2 = LE32(0x22222), |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 320 | /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ |
| 321 | .antCtrlChain = { |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 322 | LE16(0x000), LE16(0x000), LE16(0x000), |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 323 | }, |
| 324 | /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ |
| 325 | .xatten1DB = {0, 0, 0}, |
| 326 | |
| 327 | /* |
| 328 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin |
| 329 | * for merlin (0xa20c/b20c 16:12 |
| 330 | */ |
| 331 | .xatten1Margin = {0, 0, 0}, |
| 332 | .tempSlope = 68, |
| 333 | .voltSlope = 0, |
| 334 | /* spurChans spur channels in usual fbin coding format */ |
| 335 | .spurChans = {0, 0, 0, 0, 0}, |
| 336 | /* noiseFloorThreshCh Check if the register is per chain */ |
| 337 | .noiseFloorThreshCh = {-1, 0, 0}, |
| 338 | .ob = {3, 3, 3}, /* 3 chain */ |
| 339 | .db_stage2 = {3, 3, 3}, /* 3 chain */ |
| 340 | .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */ |
| 341 | .db_stage4 = {3, 3, 3}, /* don't exist for 2G */ |
| 342 | .xpaBiasLvl = 0, |
| 343 | .txFrameToDataStart = 0x0e, |
| 344 | .txFrameToPaOn = 0x0e, |
| 345 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ |
| 346 | .antennaGain = 0, |
| 347 | .switchSettling = 0x2d, |
| 348 | .adcDesiredSize = -30, |
| 349 | .txEndToXpaOff = 0, |
| 350 | .txEndToRxOn = 0x2, |
| 351 | .txFrameToXpaOn = 0xe, |
| 352 | .thresh62 = 28, |
Senthil Balasubramanian | 3ceb801 | 2010-11-10 05:03:09 -0800 | [diff] [blame] | 353 | .papdRateMaskHt20 = LE32(0x0c80c080), |
| 354 | .papdRateMaskHt40 = LE32(0x0080c080), |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 355 | .futureModal = { |
Senthil Balasubramanian | b3dd6bc | 2010-11-10 05:03:07 -0800 | [diff] [blame] | 356 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 357 | }, |
| 358 | }, |
Senthil Balasubramanian | b3dd6bc | 2010-11-10 05:03:07 -0800 | [diff] [blame] | 359 | .base_ext2 = { |
| 360 | .tempSlopeLow = 0, |
| 361 | .tempSlopeHigh = 0, |
| 362 | .xatten1DBLow = {0, 0, 0}, |
| 363 | .xatten1MarginLow = {0, 0, 0}, |
| 364 | .xatten1DBHigh = {0, 0, 0}, |
| 365 | .xatten1MarginHigh = {0, 0, 0} |
| 366 | }, |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 367 | .calFreqPier5G = { |
| 368 | FREQ2FBIN(5180, 0), |
| 369 | FREQ2FBIN(5220, 0), |
| 370 | FREQ2FBIN(5320, 0), |
| 371 | FREQ2FBIN(5400, 0), |
| 372 | FREQ2FBIN(5500, 0), |
| 373 | FREQ2FBIN(5600, 0), |
| 374 | FREQ2FBIN(5725, 0), |
| 375 | FREQ2FBIN(5825, 0) |
| 376 | }, |
| 377 | .calPierData5G = { |
| 378 | { |
| 379 | {0, 0, 0, 0, 0}, |
| 380 | {0, 0, 0, 0, 0}, |
| 381 | {0, 0, 0, 0, 0}, |
| 382 | {0, 0, 0, 0, 0}, |
| 383 | {0, 0, 0, 0, 0}, |
| 384 | {0, 0, 0, 0, 0}, |
| 385 | {0, 0, 0, 0, 0}, |
| 386 | {0, 0, 0, 0, 0}, |
| 387 | }, |
| 388 | { |
| 389 | {0, 0, 0, 0, 0}, |
| 390 | {0, 0, 0, 0, 0}, |
| 391 | {0, 0, 0, 0, 0}, |
| 392 | {0, 0, 0, 0, 0}, |
| 393 | {0, 0, 0, 0, 0}, |
| 394 | {0, 0, 0, 0, 0}, |
| 395 | {0, 0, 0, 0, 0}, |
| 396 | {0, 0, 0, 0, 0}, |
| 397 | }, |
| 398 | { |
| 399 | {0, 0, 0, 0, 0}, |
| 400 | {0, 0, 0, 0, 0}, |
| 401 | {0, 0, 0, 0, 0}, |
| 402 | {0, 0, 0, 0, 0}, |
| 403 | {0, 0, 0, 0, 0}, |
| 404 | {0, 0, 0, 0, 0}, |
| 405 | {0, 0, 0, 0, 0}, |
| 406 | {0, 0, 0, 0, 0}, |
| 407 | }, |
| 408 | |
| 409 | }, |
| 410 | .calTarget_freqbin_5G = { |
| 411 | FREQ2FBIN(5180, 0), |
| 412 | FREQ2FBIN(5220, 0), |
| 413 | FREQ2FBIN(5320, 0), |
| 414 | FREQ2FBIN(5400, 0), |
| 415 | FREQ2FBIN(5500, 0), |
| 416 | FREQ2FBIN(5600, 0), |
| 417 | FREQ2FBIN(5725, 0), |
| 418 | FREQ2FBIN(5825, 0) |
| 419 | }, |
| 420 | .calTarget_freqbin_5GHT20 = { |
| 421 | FREQ2FBIN(5180, 0), |
| 422 | FREQ2FBIN(5240, 0), |
| 423 | FREQ2FBIN(5320, 0), |
| 424 | FREQ2FBIN(5500, 0), |
| 425 | FREQ2FBIN(5700, 0), |
| 426 | FREQ2FBIN(5745, 0), |
| 427 | FREQ2FBIN(5725, 0), |
| 428 | FREQ2FBIN(5825, 0) |
| 429 | }, |
| 430 | .calTarget_freqbin_5GHT40 = { |
| 431 | FREQ2FBIN(5180, 0), |
| 432 | FREQ2FBIN(5240, 0), |
| 433 | FREQ2FBIN(5320, 0), |
| 434 | FREQ2FBIN(5500, 0), |
| 435 | FREQ2FBIN(5700, 0), |
| 436 | FREQ2FBIN(5745, 0), |
| 437 | FREQ2FBIN(5725, 0), |
| 438 | FREQ2FBIN(5825, 0) |
| 439 | }, |
| 440 | .calTargetPower5G = { |
| 441 | /* 6-24,36,48,54 */ |
| 442 | { {20, 20, 20, 10} }, |
| 443 | { {20, 20, 20, 10} }, |
| 444 | { {20, 20, 20, 10} }, |
| 445 | { {20, 20, 20, 10} }, |
| 446 | { {20, 20, 20, 10} }, |
| 447 | { {20, 20, 20, 10} }, |
| 448 | { {20, 20, 20, 10} }, |
| 449 | { {20, 20, 20, 10} }, |
| 450 | }, |
| 451 | .calTargetPower5GHT20 = { |
| 452 | /* |
| 453 | * 0_8_16,1-3_9-11_17-19, |
| 454 | * 4,5,6,7,12,13,14,15,20,21,22,23 |
| 455 | */ |
| 456 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, |
| 457 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, |
| 458 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, |
| 459 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, |
| 460 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, |
| 461 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, |
| 462 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, |
| 463 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, |
| 464 | }, |
| 465 | .calTargetPower5GHT40 = { |
| 466 | /* |
| 467 | * 0_8_16,1-3_9-11_17-19, |
| 468 | * 4,5,6,7,12,13,14,15,20,21,22,23 |
| 469 | */ |
| 470 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, |
| 471 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, |
| 472 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, |
| 473 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, |
| 474 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, |
| 475 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, |
| 476 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, |
| 477 | { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, |
| 478 | }, |
| 479 | .ctlIndex_5G = { |
| 480 | 0x10, 0x16, 0x18, 0x40, 0x46, |
| 481 | 0x48, 0x30, 0x36, 0x38 |
| 482 | }, |
| 483 | .ctl_freqbin_5G = { |
| 484 | { |
| 485 | /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 486 | /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), |
| 487 | /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), |
| 488 | /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), |
| 489 | /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), |
| 490 | /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), |
| 491 | /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), |
| 492 | /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) |
| 493 | }, |
| 494 | { |
| 495 | /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 496 | /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), |
| 497 | /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), |
| 498 | /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), |
| 499 | /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), |
| 500 | /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), |
| 501 | /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), |
| 502 | /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) |
| 503 | }, |
| 504 | |
| 505 | { |
| 506 | /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), |
| 507 | /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), |
| 508 | /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), |
| 509 | /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), |
| 510 | /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), |
| 511 | /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), |
| 512 | /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), |
| 513 | /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) |
| 514 | }, |
| 515 | |
| 516 | { |
| 517 | /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 518 | /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), |
| 519 | /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), |
| 520 | /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), |
| 521 | /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), |
| 522 | /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), |
| 523 | /* Data[3].ctlEdges[6].bChannel */ 0xFF, |
| 524 | /* Data[3].ctlEdges[7].bChannel */ 0xFF, |
| 525 | }, |
| 526 | |
| 527 | { |
| 528 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 529 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), |
| 530 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), |
| 531 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), |
| 532 | /* Data[4].ctlEdges[4].bChannel */ 0xFF, |
| 533 | /* Data[4].ctlEdges[5].bChannel */ 0xFF, |
| 534 | /* Data[4].ctlEdges[6].bChannel */ 0xFF, |
| 535 | /* Data[4].ctlEdges[7].bChannel */ 0xFF, |
| 536 | }, |
| 537 | |
| 538 | { |
| 539 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), |
| 540 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), |
| 541 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), |
| 542 | /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), |
| 543 | /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), |
| 544 | /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), |
| 545 | /* Data[5].ctlEdges[6].bChannel */ 0xFF, |
| 546 | /* Data[5].ctlEdges[7].bChannel */ 0xFF |
| 547 | }, |
| 548 | |
| 549 | { |
| 550 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 551 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), |
| 552 | /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), |
| 553 | /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), |
| 554 | /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), |
| 555 | /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), |
| 556 | /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), |
| 557 | /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) |
| 558 | }, |
| 559 | |
| 560 | { |
| 561 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 562 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), |
| 563 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), |
| 564 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), |
| 565 | /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), |
| 566 | /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), |
| 567 | /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), |
| 568 | /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) |
| 569 | }, |
| 570 | |
| 571 | { |
| 572 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), |
| 573 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), |
| 574 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), |
| 575 | /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), |
| 576 | /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), |
| 577 | /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), |
| 578 | /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), |
| 579 | /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) |
| 580 | } |
| 581 | }, |
| 582 | .ctlPowerData_5G = { |
| 583 | { |
| 584 | { |
| 585 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 586 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 587 | } |
| 588 | }, |
| 589 | { |
| 590 | { |
| 591 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 592 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 593 | } |
| 594 | }, |
| 595 | { |
| 596 | { |
| 597 | {60, 0}, {60, 1}, {60, 0}, {60, 1}, |
| 598 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 599 | } |
| 600 | }, |
| 601 | { |
| 602 | { |
| 603 | {60, 0}, {60, 1}, {60, 1}, {60, 0}, |
| 604 | {60, 1}, {60, 0}, {60, 0}, {60, 0}, |
| 605 | } |
| 606 | }, |
| 607 | { |
| 608 | { |
| 609 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 610 | {60, 0}, {60, 0}, {60, 0}, {60, 0}, |
| 611 | } |
| 612 | }, |
| 613 | { |
| 614 | { |
| 615 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 616 | {60, 1}, {60, 0}, {60, 0}, {60, 0}, |
| 617 | } |
| 618 | }, |
| 619 | { |
| 620 | { |
| 621 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 622 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 623 | } |
| 624 | }, |
| 625 | { |
| 626 | { |
| 627 | {60, 1}, {60, 1}, {60, 0}, {60, 1}, |
| 628 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 629 | } |
| 630 | }, |
| 631 | { |
| 632 | { |
| 633 | {60, 1}, {60, 0}, {60, 1}, {60, 1}, |
| 634 | {60, 1}, {60, 1}, {60, 0}, {60, 1}, |
| 635 | } |
| 636 | }, |
| 637 | } |
| 638 | }; |
| 639 | |
Senthil Balasubramanian | 3092354 | 2010-11-10 05:03:10 -0800 | [diff] [blame] | 640 | static const struct ar9300_eeprom ar9300_x113 = { |
| 641 | .eepromVersion = 2, |
| 642 | .templateVersion = 6, |
| 643 | .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, |
| 644 | .custData = {"x113-023-f0000"}, |
| 645 | .baseEepHeader = { |
| 646 | .regDmn = { LE16(0), LE16(0x1f) }, |
| 647 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ |
| 648 | .opCapFlags = { |
| 649 | .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, |
| 650 | .eepMisc = 0, |
| 651 | }, |
| 652 | .rfSilent = 0, |
| 653 | .blueToothOptions = 0, |
| 654 | .deviceCap = 0, |
| 655 | .deviceType = 5, /* takes lower byte in eeprom location */ |
| 656 | .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, |
| 657 | .params_for_tuning_caps = {0, 0}, |
| 658 | .featureEnable = 0x0d, |
| 659 | /* |
| 660 | * bit0 - enable tx temp comp - disabled |
| 661 | * bit1 - enable tx volt comp - disabled |
| 662 | * bit2 - enable fastClock - enabled |
| 663 | * bit3 - enable doubling - enabled |
| 664 | * bit4 - enable internal regulator - disabled |
| 665 | * bit5 - enable pa predistortion - disabled |
| 666 | */ |
| 667 | .miscConfiguration = 0, /* bit0 - turn down drivestrength */ |
| 668 | .eepromWriteEnableGpio = 6, |
| 669 | .wlanDisableGpio = 0, |
| 670 | .wlanLedGpio = 8, |
| 671 | .rxBandSelectGpio = 0xff, |
| 672 | .txrxgain = 0x21, |
| 673 | .swreg = 0, |
| 674 | }, |
| 675 | .modalHeader2G = { |
| 676 | /* ar9300_modal_eep_header 2g */ |
| 677 | /* 4 idle,t1,t2,b(4 bits per setting) */ |
| 678 | .antCtrlCommon = LE32(0x110), |
| 679 | /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ |
| 680 | .antCtrlCommon2 = LE32(0x44444), |
| 681 | |
| 682 | /* |
| 683 | * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, |
| 684 | * rx1, rx12, b (2 bits each) |
| 685 | */ |
| 686 | .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) }, |
| 687 | |
| 688 | /* |
| 689 | * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db |
| 690 | * for ar9280 (0xa20c/b20c 5:0) |
| 691 | */ |
| 692 | .xatten1DB = {0, 0, 0}, |
| 693 | |
| 694 | /* |
| 695 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin |
| 696 | * for ar9280 (0xa20c/b20c 16:12 |
| 697 | */ |
| 698 | .xatten1Margin = {0, 0, 0}, |
| 699 | .tempSlope = 25, |
| 700 | .voltSlope = 0, |
| 701 | |
| 702 | /* |
| 703 | * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur |
| 704 | * channels in usual fbin coding format |
| 705 | */ |
| 706 | .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, |
| 707 | |
| 708 | /* |
| 709 | * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check |
| 710 | * if the register is per chain |
| 711 | */ |
| 712 | .noiseFloorThreshCh = {-1, 0, 0}, |
| 713 | .ob = {1, 1, 1},/* 3 chain */ |
| 714 | .db_stage2 = {1, 1, 1}, /* 3 chain */ |
| 715 | .db_stage3 = {0, 0, 0}, |
| 716 | .db_stage4 = {0, 0, 0}, |
| 717 | .xpaBiasLvl = 0, |
| 718 | .txFrameToDataStart = 0x0e, |
| 719 | .txFrameToPaOn = 0x0e, |
| 720 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ |
| 721 | .antennaGain = 0, |
| 722 | .switchSettling = 0x2c, |
| 723 | .adcDesiredSize = -30, |
| 724 | .txEndToXpaOff = 0, |
| 725 | .txEndToRxOn = 0x2, |
| 726 | .txFrameToXpaOn = 0xe, |
| 727 | .thresh62 = 28, |
| 728 | .papdRateMaskHt20 = LE32(0x0c80c080), |
| 729 | .papdRateMaskHt40 = LE32(0x0080c080), |
| 730 | .futureModal = { |
| 731 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 732 | }, |
| 733 | }, |
| 734 | .base_ext1 = { |
| 735 | .ant_div_control = 0, |
| 736 | .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} |
| 737 | }, |
| 738 | .calFreqPier2G = { |
| 739 | FREQ2FBIN(2412, 1), |
| 740 | FREQ2FBIN(2437, 1), |
| 741 | FREQ2FBIN(2472, 1), |
| 742 | }, |
| 743 | /* ar9300_cal_data_per_freq_op_loop 2g */ |
| 744 | .calPierData2G = { |
| 745 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, |
| 746 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, |
| 747 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, |
| 748 | }, |
| 749 | .calTarget_freqbin_Cck = { |
| 750 | FREQ2FBIN(2412, 1), |
| 751 | FREQ2FBIN(2472, 1), |
| 752 | }, |
| 753 | .calTarget_freqbin_2G = { |
| 754 | FREQ2FBIN(2412, 1), |
| 755 | FREQ2FBIN(2437, 1), |
| 756 | FREQ2FBIN(2472, 1) |
| 757 | }, |
| 758 | .calTarget_freqbin_2GHT20 = { |
| 759 | FREQ2FBIN(2412, 1), |
| 760 | FREQ2FBIN(2437, 1), |
| 761 | FREQ2FBIN(2472, 1) |
| 762 | }, |
| 763 | .calTarget_freqbin_2GHT40 = { |
| 764 | FREQ2FBIN(2412, 1), |
| 765 | FREQ2FBIN(2437, 1), |
| 766 | FREQ2FBIN(2472, 1) |
| 767 | }, |
| 768 | .calTargetPowerCck = { |
| 769 | /* 1L-5L,5S,11L,11S */ |
| 770 | { {34, 34, 34, 34} }, |
| 771 | { {34, 34, 34, 34} }, |
| 772 | }, |
| 773 | .calTargetPower2G = { |
| 774 | /* 6-24,36,48,54 */ |
| 775 | { {34, 34, 32, 32} }, |
| 776 | { {34, 34, 32, 32} }, |
| 777 | { {34, 34, 32, 32} }, |
| 778 | }, |
| 779 | .calTargetPower2GHT20 = { |
| 780 | { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} }, |
| 781 | { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} }, |
| 782 | { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} }, |
| 783 | }, |
| 784 | .calTargetPower2GHT40 = { |
| 785 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, |
| 786 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, |
| 787 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, |
| 788 | }, |
| 789 | .ctlIndex_2G = { |
| 790 | 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, |
| 791 | 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, |
| 792 | }, |
| 793 | .ctl_freqbin_2G = { |
| 794 | { |
| 795 | FREQ2FBIN(2412, 1), |
| 796 | FREQ2FBIN(2417, 1), |
| 797 | FREQ2FBIN(2457, 1), |
| 798 | FREQ2FBIN(2462, 1) |
| 799 | }, |
| 800 | { |
| 801 | FREQ2FBIN(2412, 1), |
| 802 | FREQ2FBIN(2417, 1), |
| 803 | FREQ2FBIN(2462, 1), |
| 804 | 0xFF, |
| 805 | }, |
| 806 | |
| 807 | { |
| 808 | FREQ2FBIN(2412, 1), |
| 809 | FREQ2FBIN(2417, 1), |
| 810 | FREQ2FBIN(2462, 1), |
| 811 | 0xFF, |
| 812 | }, |
| 813 | { |
| 814 | FREQ2FBIN(2422, 1), |
| 815 | FREQ2FBIN(2427, 1), |
| 816 | FREQ2FBIN(2447, 1), |
| 817 | FREQ2FBIN(2452, 1) |
| 818 | }, |
| 819 | |
| 820 | { |
| 821 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 822 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 823 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 824 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), |
| 825 | }, |
| 826 | |
| 827 | { |
| 828 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 829 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 830 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 831 | 0, |
| 832 | }, |
| 833 | |
| 834 | { |
| 835 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 836 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 837 | FREQ2FBIN(2472, 1), |
| 838 | 0, |
| 839 | }, |
| 840 | |
| 841 | { |
| 842 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), |
| 843 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), |
| 844 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), |
| 845 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), |
| 846 | }, |
| 847 | |
| 848 | { |
| 849 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 850 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 851 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 852 | }, |
| 853 | |
| 854 | { |
| 855 | /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 856 | /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 857 | /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 858 | 0 |
| 859 | }, |
| 860 | |
| 861 | { |
| 862 | /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 863 | /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 864 | /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 865 | 0 |
| 866 | }, |
| 867 | |
| 868 | { |
| 869 | /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), |
| 870 | /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), |
| 871 | /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), |
| 872 | /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), |
| 873 | } |
| 874 | }, |
| 875 | .ctlPowerData_2G = { |
| 876 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 877 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 878 | { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } }, |
| 879 | |
| 880 | { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } }, |
| 881 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 882 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 883 | |
| 884 | { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } }, |
| 885 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 886 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 887 | |
| 888 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 889 | { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } }, |
| 890 | { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } }, |
| 891 | }, |
| 892 | .modalHeader5G = { |
| 893 | /* 4 idle,t1,t2,b (4 bits per setting) */ |
| 894 | .antCtrlCommon = LE32(0x220), |
| 895 | /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ |
| 896 | .antCtrlCommon2 = LE32(0x11111), |
| 897 | /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ |
| 898 | .antCtrlChain = { |
| 899 | LE16(0x150), LE16(0x150), LE16(0x150), |
| 900 | }, |
| 901 | /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ |
| 902 | .xatten1DB = {0, 0, 0}, |
| 903 | |
| 904 | /* |
| 905 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin |
| 906 | * for merlin (0xa20c/b20c 16:12 |
| 907 | */ |
| 908 | .xatten1Margin = {0, 0, 0}, |
| 909 | .tempSlope = 68, |
| 910 | .voltSlope = 0, |
| 911 | /* spurChans spur channels in usual fbin coding format */ |
| 912 | .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0}, |
| 913 | /* noiseFloorThreshCh Check if the register is per chain */ |
| 914 | .noiseFloorThreshCh = {-1, 0, 0}, |
| 915 | .ob = {3, 3, 3}, /* 3 chain */ |
| 916 | .db_stage2 = {3, 3, 3}, /* 3 chain */ |
| 917 | .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */ |
| 918 | .db_stage4 = {3, 3, 3}, /* don't exist for 2G */ |
| 919 | .xpaBiasLvl = 0, |
| 920 | .txFrameToDataStart = 0x0e, |
| 921 | .txFrameToPaOn = 0x0e, |
| 922 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ |
| 923 | .antennaGain = 0, |
| 924 | .switchSettling = 0x2d, |
| 925 | .adcDesiredSize = -30, |
| 926 | .txEndToXpaOff = 0, |
| 927 | .txEndToRxOn = 0x2, |
| 928 | .txFrameToXpaOn = 0xe, |
| 929 | .thresh62 = 28, |
| 930 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), |
| 931 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), |
| 932 | .futureModal = { |
| 933 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 934 | }, |
| 935 | }, |
| 936 | .base_ext2 = { |
| 937 | .tempSlopeLow = 72, |
| 938 | .tempSlopeHigh = 105, |
| 939 | .xatten1DBLow = {0, 0, 0}, |
| 940 | .xatten1MarginLow = {0, 0, 0}, |
| 941 | .xatten1DBHigh = {0, 0, 0}, |
| 942 | .xatten1MarginHigh = {0, 0, 0} |
| 943 | }, |
| 944 | .calFreqPier5G = { |
| 945 | FREQ2FBIN(5180, 0), |
| 946 | FREQ2FBIN(5240, 0), |
| 947 | FREQ2FBIN(5320, 0), |
| 948 | FREQ2FBIN(5400, 0), |
| 949 | FREQ2FBIN(5500, 0), |
| 950 | FREQ2FBIN(5600, 0), |
| 951 | FREQ2FBIN(5745, 0), |
| 952 | FREQ2FBIN(5785, 0) |
| 953 | }, |
| 954 | .calPierData5G = { |
| 955 | { |
| 956 | {0, 0, 0, 0, 0}, |
| 957 | {0, 0, 0, 0, 0}, |
| 958 | {0, 0, 0, 0, 0}, |
| 959 | {0, 0, 0, 0, 0}, |
| 960 | {0, 0, 0, 0, 0}, |
| 961 | {0, 0, 0, 0, 0}, |
| 962 | {0, 0, 0, 0, 0}, |
| 963 | {0, 0, 0, 0, 0}, |
| 964 | }, |
| 965 | { |
| 966 | {0, 0, 0, 0, 0}, |
| 967 | {0, 0, 0, 0, 0}, |
| 968 | {0, 0, 0, 0, 0}, |
| 969 | {0, 0, 0, 0, 0}, |
| 970 | {0, 0, 0, 0, 0}, |
| 971 | {0, 0, 0, 0, 0}, |
| 972 | {0, 0, 0, 0, 0}, |
| 973 | {0, 0, 0, 0, 0}, |
| 974 | }, |
| 975 | { |
| 976 | {0, 0, 0, 0, 0}, |
| 977 | {0, 0, 0, 0, 0}, |
| 978 | {0, 0, 0, 0, 0}, |
| 979 | {0, 0, 0, 0, 0}, |
| 980 | {0, 0, 0, 0, 0}, |
| 981 | {0, 0, 0, 0, 0}, |
| 982 | {0, 0, 0, 0, 0}, |
| 983 | {0, 0, 0, 0, 0}, |
| 984 | }, |
| 985 | |
| 986 | }, |
| 987 | .calTarget_freqbin_5G = { |
| 988 | FREQ2FBIN(5180, 0), |
| 989 | FREQ2FBIN(5220, 0), |
| 990 | FREQ2FBIN(5320, 0), |
| 991 | FREQ2FBIN(5400, 0), |
| 992 | FREQ2FBIN(5500, 0), |
| 993 | FREQ2FBIN(5600, 0), |
| 994 | FREQ2FBIN(5745, 0), |
| 995 | FREQ2FBIN(5785, 0) |
| 996 | }, |
| 997 | .calTarget_freqbin_5GHT20 = { |
| 998 | FREQ2FBIN(5180, 0), |
| 999 | FREQ2FBIN(5240, 0), |
| 1000 | FREQ2FBIN(5320, 0), |
| 1001 | FREQ2FBIN(5400, 0), |
| 1002 | FREQ2FBIN(5500, 0), |
| 1003 | FREQ2FBIN(5700, 0), |
| 1004 | FREQ2FBIN(5745, 0), |
| 1005 | FREQ2FBIN(5825, 0) |
| 1006 | }, |
| 1007 | .calTarget_freqbin_5GHT40 = { |
| 1008 | FREQ2FBIN(5190, 0), |
| 1009 | FREQ2FBIN(5230, 0), |
| 1010 | FREQ2FBIN(5320, 0), |
| 1011 | FREQ2FBIN(5410, 0), |
| 1012 | FREQ2FBIN(5510, 0), |
| 1013 | FREQ2FBIN(5670, 0), |
| 1014 | FREQ2FBIN(5755, 0), |
| 1015 | FREQ2FBIN(5825, 0) |
| 1016 | }, |
| 1017 | .calTargetPower5G = { |
| 1018 | /* 6-24,36,48,54 */ |
| 1019 | { {42, 40, 40, 34} }, |
| 1020 | { {42, 40, 40, 34} }, |
| 1021 | { {42, 40, 40, 34} }, |
| 1022 | { {42, 40, 40, 34} }, |
| 1023 | { {42, 40, 40, 34} }, |
| 1024 | { {42, 40, 40, 34} }, |
| 1025 | { {42, 40, 40, 34} }, |
| 1026 | { {42, 40, 40, 34} }, |
| 1027 | }, |
| 1028 | .calTargetPower5GHT20 = { |
| 1029 | /* |
| 1030 | * 0_8_16,1-3_9-11_17-19, |
| 1031 | * 4,5,6,7,12,13,14,15,20,21,22,23 |
| 1032 | */ |
| 1033 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, |
| 1034 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, |
| 1035 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, |
| 1036 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, |
| 1037 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, |
| 1038 | { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, |
| 1039 | { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} }, |
| 1040 | { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} }, |
| 1041 | }, |
| 1042 | .calTargetPower5GHT40 = { |
| 1043 | /* |
| 1044 | * 0_8_16,1-3_9-11_17-19, |
| 1045 | * 4,5,6,7,12,13,14,15,20,21,22,23 |
| 1046 | */ |
| 1047 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, |
| 1048 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, |
| 1049 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, |
| 1050 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, |
| 1051 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, |
| 1052 | { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, |
| 1053 | { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} }, |
| 1054 | { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} }, |
| 1055 | }, |
| 1056 | .ctlIndex_5G = { |
| 1057 | 0x10, 0x16, 0x18, 0x40, 0x46, |
| 1058 | 0x48, 0x30, 0x36, 0x38 |
| 1059 | }, |
| 1060 | .ctl_freqbin_5G = { |
| 1061 | { |
| 1062 | /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 1063 | /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), |
| 1064 | /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), |
| 1065 | /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), |
| 1066 | /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), |
| 1067 | /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), |
| 1068 | /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), |
| 1069 | /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) |
| 1070 | }, |
| 1071 | { |
| 1072 | /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 1073 | /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), |
| 1074 | /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), |
| 1075 | /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), |
| 1076 | /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), |
| 1077 | /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), |
| 1078 | /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), |
| 1079 | /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) |
| 1080 | }, |
| 1081 | |
| 1082 | { |
| 1083 | /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), |
| 1084 | /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), |
| 1085 | /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), |
| 1086 | /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), |
| 1087 | /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), |
| 1088 | /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), |
| 1089 | /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), |
| 1090 | /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) |
| 1091 | }, |
| 1092 | |
| 1093 | { |
| 1094 | /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 1095 | /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), |
| 1096 | /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), |
| 1097 | /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), |
| 1098 | /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), |
| 1099 | /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), |
| 1100 | /* Data[3].ctlEdges[6].bChannel */ 0xFF, |
| 1101 | /* Data[3].ctlEdges[7].bChannel */ 0xFF, |
| 1102 | }, |
| 1103 | |
| 1104 | { |
| 1105 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 1106 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), |
| 1107 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), |
| 1108 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), |
| 1109 | /* Data[4].ctlEdges[4].bChannel */ 0xFF, |
| 1110 | /* Data[4].ctlEdges[5].bChannel */ 0xFF, |
| 1111 | /* Data[4].ctlEdges[6].bChannel */ 0xFF, |
| 1112 | /* Data[4].ctlEdges[7].bChannel */ 0xFF, |
| 1113 | }, |
| 1114 | |
| 1115 | { |
| 1116 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), |
| 1117 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), |
| 1118 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), |
| 1119 | /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), |
| 1120 | /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), |
| 1121 | /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), |
| 1122 | /* Data[5].ctlEdges[6].bChannel */ 0xFF, |
| 1123 | /* Data[5].ctlEdges[7].bChannel */ 0xFF |
| 1124 | }, |
| 1125 | |
| 1126 | { |
| 1127 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 1128 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), |
| 1129 | /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), |
| 1130 | /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), |
| 1131 | /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), |
| 1132 | /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), |
| 1133 | /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), |
| 1134 | /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) |
| 1135 | }, |
| 1136 | |
| 1137 | { |
| 1138 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 1139 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), |
| 1140 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), |
| 1141 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), |
| 1142 | /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), |
| 1143 | /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), |
| 1144 | /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), |
| 1145 | /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) |
| 1146 | }, |
| 1147 | |
| 1148 | { |
| 1149 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), |
| 1150 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), |
| 1151 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), |
| 1152 | /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), |
| 1153 | /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), |
| 1154 | /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), |
| 1155 | /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), |
| 1156 | /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) |
| 1157 | } |
| 1158 | }, |
| 1159 | .ctlPowerData_5G = { |
| 1160 | { |
| 1161 | { |
| 1162 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 1163 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 1164 | } |
| 1165 | }, |
| 1166 | { |
| 1167 | { |
| 1168 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 1169 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 1170 | } |
| 1171 | }, |
| 1172 | { |
| 1173 | { |
| 1174 | {60, 0}, {60, 1}, {60, 0}, {60, 1}, |
| 1175 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 1176 | } |
| 1177 | }, |
| 1178 | { |
| 1179 | { |
| 1180 | {60, 0}, {60, 1}, {60, 1}, {60, 0}, |
| 1181 | {60, 1}, {60, 0}, {60, 0}, {60, 0}, |
| 1182 | } |
| 1183 | }, |
| 1184 | { |
| 1185 | { |
| 1186 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 1187 | {60, 0}, {60, 0}, {60, 0}, {60, 0}, |
| 1188 | } |
| 1189 | }, |
| 1190 | { |
| 1191 | { |
| 1192 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 1193 | {60, 1}, {60, 0}, {60, 0}, {60, 0}, |
| 1194 | } |
| 1195 | }, |
| 1196 | { |
| 1197 | { |
| 1198 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 1199 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 1200 | } |
| 1201 | }, |
| 1202 | { |
| 1203 | { |
| 1204 | {60, 1}, {60, 1}, {60, 0}, {60, 1}, |
| 1205 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 1206 | } |
| 1207 | }, |
| 1208 | { |
| 1209 | { |
| 1210 | {60, 1}, {60, 0}, {60, 1}, {60, 1}, |
| 1211 | {60, 1}, {60, 1}, {60, 0}, {60, 1}, |
| 1212 | } |
| 1213 | }, |
| 1214 | } |
| 1215 | }; |
| 1216 | |
| 1217 | |
| 1218 | static const struct ar9300_eeprom ar9300_h112 = { |
| 1219 | .eepromVersion = 2, |
| 1220 | .templateVersion = 3, |
| 1221 | .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, |
| 1222 | .custData = {"h112-241-f0000"}, |
| 1223 | .baseEepHeader = { |
| 1224 | .regDmn = { LE16(0), LE16(0x1f) }, |
| 1225 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ |
| 1226 | .opCapFlags = { |
| 1227 | .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, |
| 1228 | .eepMisc = 0, |
| 1229 | }, |
| 1230 | .rfSilent = 0, |
| 1231 | .blueToothOptions = 0, |
| 1232 | .deviceCap = 0, |
| 1233 | .deviceType = 5, /* takes lower byte in eeprom location */ |
| 1234 | .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, |
| 1235 | .params_for_tuning_caps = {0, 0}, |
| 1236 | .featureEnable = 0x0d, |
| 1237 | /* |
| 1238 | * bit0 - enable tx temp comp - disabled |
| 1239 | * bit1 - enable tx volt comp - disabled |
| 1240 | * bit2 - enable fastClock - enabled |
| 1241 | * bit3 - enable doubling - enabled |
| 1242 | * bit4 - enable internal regulator - disabled |
| 1243 | * bit5 - enable pa predistortion - disabled |
| 1244 | */ |
| 1245 | .miscConfiguration = 0, /* bit0 - turn down drivestrength */ |
| 1246 | .eepromWriteEnableGpio = 6, |
| 1247 | .wlanDisableGpio = 0, |
| 1248 | .wlanLedGpio = 8, |
| 1249 | .rxBandSelectGpio = 0xff, |
| 1250 | .txrxgain = 0x10, |
| 1251 | .swreg = 0, |
| 1252 | }, |
| 1253 | .modalHeader2G = { |
| 1254 | /* ar9300_modal_eep_header 2g */ |
| 1255 | /* 4 idle,t1,t2,b(4 bits per setting) */ |
| 1256 | .antCtrlCommon = LE32(0x110), |
| 1257 | /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ |
| 1258 | .antCtrlCommon2 = LE32(0x44444), |
| 1259 | |
| 1260 | /* |
| 1261 | * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, |
| 1262 | * rx1, rx12, b (2 bits each) |
| 1263 | */ |
| 1264 | .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) }, |
| 1265 | |
| 1266 | /* |
| 1267 | * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db |
| 1268 | * for ar9280 (0xa20c/b20c 5:0) |
| 1269 | */ |
| 1270 | .xatten1DB = {0, 0, 0}, |
| 1271 | |
| 1272 | /* |
| 1273 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin |
| 1274 | * for ar9280 (0xa20c/b20c 16:12 |
| 1275 | */ |
| 1276 | .xatten1Margin = {0, 0, 0}, |
| 1277 | .tempSlope = 25, |
| 1278 | .voltSlope = 0, |
| 1279 | |
| 1280 | /* |
| 1281 | * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur |
| 1282 | * channels in usual fbin coding format |
| 1283 | */ |
| 1284 | .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, |
| 1285 | |
| 1286 | /* |
| 1287 | * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check |
| 1288 | * if the register is per chain |
| 1289 | */ |
| 1290 | .noiseFloorThreshCh = {-1, 0, 0}, |
| 1291 | .ob = {1, 1, 1},/* 3 chain */ |
| 1292 | .db_stage2 = {1, 1, 1}, /* 3 chain */ |
| 1293 | .db_stage3 = {0, 0, 0}, |
| 1294 | .db_stage4 = {0, 0, 0}, |
| 1295 | .xpaBiasLvl = 0, |
| 1296 | .txFrameToDataStart = 0x0e, |
| 1297 | .txFrameToPaOn = 0x0e, |
| 1298 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ |
| 1299 | .antennaGain = 0, |
| 1300 | .switchSettling = 0x2c, |
| 1301 | .adcDesiredSize = -30, |
| 1302 | .txEndToXpaOff = 0, |
| 1303 | .txEndToRxOn = 0x2, |
| 1304 | .txFrameToXpaOn = 0xe, |
| 1305 | .thresh62 = 28, |
| 1306 | .papdRateMaskHt20 = LE32(0x80c080), |
| 1307 | .papdRateMaskHt40 = LE32(0x80c080), |
| 1308 | .futureModal = { |
| 1309 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 1310 | }, |
| 1311 | }, |
| 1312 | .base_ext1 = { |
| 1313 | .ant_div_control = 0, |
| 1314 | .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} |
| 1315 | }, |
| 1316 | .calFreqPier2G = { |
| 1317 | FREQ2FBIN(2412, 1), |
| 1318 | FREQ2FBIN(2437, 1), |
| 1319 | FREQ2FBIN(2472, 1), |
| 1320 | }, |
| 1321 | /* ar9300_cal_data_per_freq_op_loop 2g */ |
| 1322 | .calPierData2G = { |
| 1323 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, |
| 1324 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, |
| 1325 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, |
| 1326 | }, |
| 1327 | .calTarget_freqbin_Cck = { |
| 1328 | FREQ2FBIN(2412, 1), |
| 1329 | FREQ2FBIN(2484, 1), |
| 1330 | }, |
| 1331 | .calTarget_freqbin_2G = { |
| 1332 | FREQ2FBIN(2412, 1), |
| 1333 | FREQ2FBIN(2437, 1), |
| 1334 | FREQ2FBIN(2472, 1) |
| 1335 | }, |
| 1336 | .calTarget_freqbin_2GHT20 = { |
| 1337 | FREQ2FBIN(2412, 1), |
| 1338 | FREQ2FBIN(2437, 1), |
| 1339 | FREQ2FBIN(2472, 1) |
| 1340 | }, |
| 1341 | .calTarget_freqbin_2GHT40 = { |
| 1342 | FREQ2FBIN(2412, 1), |
| 1343 | FREQ2FBIN(2437, 1), |
| 1344 | FREQ2FBIN(2472, 1) |
| 1345 | }, |
| 1346 | .calTargetPowerCck = { |
| 1347 | /* 1L-5L,5S,11L,11S */ |
| 1348 | { {34, 34, 34, 34} }, |
| 1349 | { {34, 34, 34, 34} }, |
| 1350 | }, |
| 1351 | .calTargetPower2G = { |
| 1352 | /* 6-24,36,48,54 */ |
| 1353 | { {34, 34, 32, 32} }, |
| 1354 | { {34, 34, 32, 32} }, |
| 1355 | { {34, 34, 32, 32} }, |
| 1356 | }, |
| 1357 | .calTargetPower2GHT20 = { |
| 1358 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} }, |
| 1359 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} }, |
| 1360 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} }, |
| 1361 | }, |
| 1362 | .calTargetPower2GHT40 = { |
| 1363 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} }, |
| 1364 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} }, |
| 1365 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} }, |
| 1366 | }, |
| 1367 | .ctlIndex_2G = { |
| 1368 | 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, |
| 1369 | 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, |
| 1370 | }, |
| 1371 | .ctl_freqbin_2G = { |
| 1372 | { |
| 1373 | FREQ2FBIN(2412, 1), |
| 1374 | FREQ2FBIN(2417, 1), |
| 1375 | FREQ2FBIN(2457, 1), |
| 1376 | FREQ2FBIN(2462, 1) |
| 1377 | }, |
| 1378 | { |
| 1379 | FREQ2FBIN(2412, 1), |
| 1380 | FREQ2FBIN(2417, 1), |
| 1381 | FREQ2FBIN(2462, 1), |
| 1382 | 0xFF, |
| 1383 | }, |
| 1384 | |
| 1385 | { |
| 1386 | FREQ2FBIN(2412, 1), |
| 1387 | FREQ2FBIN(2417, 1), |
| 1388 | FREQ2FBIN(2462, 1), |
| 1389 | 0xFF, |
| 1390 | }, |
| 1391 | { |
| 1392 | FREQ2FBIN(2422, 1), |
| 1393 | FREQ2FBIN(2427, 1), |
| 1394 | FREQ2FBIN(2447, 1), |
| 1395 | FREQ2FBIN(2452, 1) |
| 1396 | }, |
| 1397 | |
| 1398 | { |
| 1399 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 1400 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 1401 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 1402 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), |
| 1403 | }, |
| 1404 | |
| 1405 | { |
| 1406 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 1407 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 1408 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 1409 | 0, |
| 1410 | }, |
| 1411 | |
| 1412 | { |
| 1413 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 1414 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 1415 | FREQ2FBIN(2472, 1), |
| 1416 | 0, |
| 1417 | }, |
| 1418 | |
| 1419 | { |
| 1420 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), |
| 1421 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), |
| 1422 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), |
| 1423 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), |
| 1424 | }, |
| 1425 | |
| 1426 | { |
| 1427 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 1428 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 1429 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 1430 | }, |
| 1431 | |
| 1432 | { |
| 1433 | /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 1434 | /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 1435 | /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 1436 | 0 |
| 1437 | }, |
| 1438 | |
| 1439 | { |
| 1440 | /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 1441 | /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 1442 | /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 1443 | 0 |
| 1444 | }, |
| 1445 | |
| 1446 | { |
| 1447 | /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), |
| 1448 | /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), |
| 1449 | /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), |
| 1450 | /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), |
| 1451 | } |
| 1452 | }, |
| 1453 | .ctlPowerData_2G = { |
| 1454 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 1455 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 1456 | { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } }, |
| 1457 | |
| 1458 | { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } }, |
| 1459 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 1460 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 1461 | |
| 1462 | { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } }, |
| 1463 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 1464 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 1465 | |
| 1466 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 1467 | { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } }, |
| 1468 | { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } }, |
| 1469 | }, |
| 1470 | .modalHeader5G = { |
| 1471 | /* 4 idle,t1,t2,b (4 bits per setting) */ |
| 1472 | .antCtrlCommon = LE32(0x220), |
| 1473 | /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ |
| 1474 | .antCtrlCommon2 = LE32(0x44444), |
| 1475 | /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ |
| 1476 | .antCtrlChain = { |
| 1477 | LE16(0x150), LE16(0x150), LE16(0x150), |
| 1478 | }, |
| 1479 | /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ |
| 1480 | .xatten1DB = {0, 0, 0}, |
| 1481 | |
| 1482 | /* |
| 1483 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin |
| 1484 | * for merlin (0xa20c/b20c 16:12 |
| 1485 | */ |
| 1486 | .xatten1Margin = {0, 0, 0}, |
| 1487 | .tempSlope = 45, |
| 1488 | .voltSlope = 0, |
| 1489 | /* spurChans spur channels in usual fbin coding format */ |
| 1490 | .spurChans = {0, 0, 0, 0, 0}, |
| 1491 | /* noiseFloorThreshCh Check if the register is per chain */ |
| 1492 | .noiseFloorThreshCh = {-1, 0, 0}, |
| 1493 | .ob = {3, 3, 3}, /* 3 chain */ |
| 1494 | .db_stage2 = {3, 3, 3}, /* 3 chain */ |
| 1495 | .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */ |
| 1496 | .db_stage4 = {3, 3, 3}, /* don't exist for 2G */ |
| 1497 | .xpaBiasLvl = 0, |
| 1498 | .txFrameToDataStart = 0x0e, |
| 1499 | .txFrameToPaOn = 0x0e, |
| 1500 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ |
| 1501 | .antennaGain = 0, |
| 1502 | .switchSettling = 0x2d, |
| 1503 | .adcDesiredSize = -30, |
| 1504 | .txEndToXpaOff = 0, |
| 1505 | .txEndToRxOn = 0x2, |
| 1506 | .txFrameToXpaOn = 0xe, |
| 1507 | .thresh62 = 28, |
| 1508 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), |
| 1509 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), |
| 1510 | .futureModal = { |
| 1511 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 1512 | }, |
| 1513 | }, |
| 1514 | .base_ext2 = { |
| 1515 | .tempSlopeLow = 40, |
| 1516 | .tempSlopeHigh = 50, |
| 1517 | .xatten1DBLow = {0, 0, 0}, |
| 1518 | .xatten1MarginLow = {0, 0, 0}, |
| 1519 | .xatten1DBHigh = {0, 0, 0}, |
| 1520 | .xatten1MarginHigh = {0, 0, 0} |
| 1521 | }, |
| 1522 | .calFreqPier5G = { |
| 1523 | FREQ2FBIN(5180, 0), |
| 1524 | FREQ2FBIN(5220, 0), |
| 1525 | FREQ2FBIN(5320, 0), |
| 1526 | FREQ2FBIN(5400, 0), |
| 1527 | FREQ2FBIN(5500, 0), |
| 1528 | FREQ2FBIN(5600, 0), |
| 1529 | FREQ2FBIN(5700, 0), |
| 1530 | FREQ2FBIN(5825, 0) |
| 1531 | }, |
| 1532 | .calPierData5G = { |
| 1533 | { |
| 1534 | {0, 0, 0, 0, 0}, |
| 1535 | {0, 0, 0, 0, 0}, |
| 1536 | {0, 0, 0, 0, 0}, |
| 1537 | {0, 0, 0, 0, 0}, |
| 1538 | {0, 0, 0, 0, 0}, |
| 1539 | {0, 0, 0, 0, 0}, |
| 1540 | {0, 0, 0, 0, 0}, |
| 1541 | {0, 0, 0, 0, 0}, |
| 1542 | }, |
| 1543 | { |
| 1544 | {0, 0, 0, 0, 0}, |
| 1545 | {0, 0, 0, 0, 0}, |
| 1546 | {0, 0, 0, 0, 0}, |
| 1547 | {0, 0, 0, 0, 0}, |
| 1548 | {0, 0, 0, 0, 0}, |
| 1549 | {0, 0, 0, 0, 0}, |
| 1550 | {0, 0, 0, 0, 0}, |
| 1551 | {0, 0, 0, 0, 0}, |
| 1552 | }, |
| 1553 | { |
| 1554 | {0, 0, 0, 0, 0}, |
| 1555 | {0, 0, 0, 0, 0}, |
| 1556 | {0, 0, 0, 0, 0}, |
| 1557 | {0, 0, 0, 0, 0}, |
| 1558 | {0, 0, 0, 0, 0}, |
| 1559 | {0, 0, 0, 0, 0}, |
| 1560 | {0, 0, 0, 0, 0}, |
| 1561 | {0, 0, 0, 0, 0}, |
| 1562 | }, |
| 1563 | |
| 1564 | }, |
| 1565 | .calTarget_freqbin_5G = { |
| 1566 | FREQ2FBIN(5180, 0), |
| 1567 | FREQ2FBIN(5240, 0), |
| 1568 | FREQ2FBIN(5320, 0), |
| 1569 | FREQ2FBIN(5400, 0), |
| 1570 | FREQ2FBIN(5500, 0), |
| 1571 | FREQ2FBIN(5600, 0), |
| 1572 | FREQ2FBIN(5700, 0), |
| 1573 | FREQ2FBIN(5825, 0) |
| 1574 | }, |
| 1575 | .calTarget_freqbin_5GHT20 = { |
| 1576 | FREQ2FBIN(5180, 0), |
| 1577 | FREQ2FBIN(5240, 0), |
| 1578 | FREQ2FBIN(5320, 0), |
| 1579 | FREQ2FBIN(5400, 0), |
| 1580 | FREQ2FBIN(5500, 0), |
| 1581 | FREQ2FBIN(5700, 0), |
| 1582 | FREQ2FBIN(5745, 0), |
| 1583 | FREQ2FBIN(5825, 0) |
| 1584 | }, |
| 1585 | .calTarget_freqbin_5GHT40 = { |
| 1586 | FREQ2FBIN(5180, 0), |
| 1587 | FREQ2FBIN(5240, 0), |
| 1588 | FREQ2FBIN(5320, 0), |
| 1589 | FREQ2FBIN(5400, 0), |
| 1590 | FREQ2FBIN(5500, 0), |
| 1591 | FREQ2FBIN(5700, 0), |
| 1592 | FREQ2FBIN(5745, 0), |
| 1593 | FREQ2FBIN(5825, 0) |
| 1594 | }, |
| 1595 | .calTargetPower5G = { |
| 1596 | /* 6-24,36,48,54 */ |
| 1597 | { {30, 30, 28, 24} }, |
| 1598 | { {30, 30, 28, 24} }, |
| 1599 | { {30, 30, 28, 24} }, |
| 1600 | { {30, 30, 28, 24} }, |
| 1601 | { {30, 30, 28, 24} }, |
| 1602 | { {30, 30, 28, 24} }, |
| 1603 | { {30, 30, 28, 24} }, |
| 1604 | { {30, 30, 28, 24} }, |
| 1605 | }, |
| 1606 | .calTargetPower5GHT20 = { |
| 1607 | /* |
| 1608 | * 0_8_16,1-3_9-11_17-19, |
| 1609 | * 4,5,6,7,12,13,14,15,20,21,22,23 |
| 1610 | */ |
| 1611 | { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} }, |
| 1612 | { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} }, |
| 1613 | { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} }, |
| 1614 | { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} }, |
| 1615 | { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} }, |
| 1616 | { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} }, |
| 1617 | { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} }, |
| 1618 | { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} }, |
| 1619 | }, |
| 1620 | .calTargetPower5GHT40 = { |
| 1621 | /* |
| 1622 | * 0_8_16,1-3_9-11_17-19, |
| 1623 | * 4,5,6,7,12,13,14,15,20,21,22,23 |
| 1624 | */ |
| 1625 | { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} }, |
| 1626 | { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} }, |
| 1627 | { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} }, |
| 1628 | { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} }, |
| 1629 | { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} }, |
| 1630 | { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} }, |
| 1631 | { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} }, |
| 1632 | { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} }, |
| 1633 | }, |
| 1634 | .ctlIndex_5G = { |
| 1635 | 0x10, 0x16, 0x18, 0x40, 0x46, |
| 1636 | 0x48, 0x30, 0x36, 0x38 |
| 1637 | }, |
| 1638 | .ctl_freqbin_5G = { |
| 1639 | { |
| 1640 | /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 1641 | /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), |
| 1642 | /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), |
| 1643 | /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), |
| 1644 | /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), |
| 1645 | /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), |
| 1646 | /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), |
| 1647 | /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) |
| 1648 | }, |
| 1649 | { |
| 1650 | /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 1651 | /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), |
| 1652 | /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), |
| 1653 | /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), |
| 1654 | /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), |
| 1655 | /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), |
| 1656 | /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), |
| 1657 | /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) |
| 1658 | }, |
| 1659 | |
| 1660 | { |
| 1661 | /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), |
| 1662 | /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), |
| 1663 | /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), |
| 1664 | /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), |
| 1665 | /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), |
| 1666 | /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), |
| 1667 | /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), |
| 1668 | /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) |
| 1669 | }, |
| 1670 | |
| 1671 | { |
| 1672 | /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 1673 | /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), |
| 1674 | /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), |
| 1675 | /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), |
| 1676 | /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), |
| 1677 | /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), |
| 1678 | /* Data[3].ctlEdges[6].bChannel */ 0xFF, |
| 1679 | /* Data[3].ctlEdges[7].bChannel */ 0xFF, |
| 1680 | }, |
| 1681 | |
| 1682 | { |
| 1683 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 1684 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), |
| 1685 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), |
| 1686 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), |
| 1687 | /* Data[4].ctlEdges[4].bChannel */ 0xFF, |
| 1688 | /* Data[4].ctlEdges[5].bChannel */ 0xFF, |
| 1689 | /* Data[4].ctlEdges[6].bChannel */ 0xFF, |
| 1690 | /* Data[4].ctlEdges[7].bChannel */ 0xFF, |
| 1691 | }, |
| 1692 | |
| 1693 | { |
| 1694 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), |
| 1695 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), |
| 1696 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), |
| 1697 | /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), |
| 1698 | /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), |
| 1699 | /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), |
| 1700 | /* Data[5].ctlEdges[6].bChannel */ 0xFF, |
| 1701 | /* Data[5].ctlEdges[7].bChannel */ 0xFF |
| 1702 | }, |
| 1703 | |
| 1704 | { |
| 1705 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 1706 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), |
| 1707 | /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), |
| 1708 | /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), |
| 1709 | /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), |
| 1710 | /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), |
| 1711 | /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), |
| 1712 | /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) |
| 1713 | }, |
| 1714 | |
| 1715 | { |
| 1716 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 1717 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), |
| 1718 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), |
| 1719 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), |
| 1720 | /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), |
| 1721 | /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), |
| 1722 | /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), |
| 1723 | /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) |
| 1724 | }, |
| 1725 | |
| 1726 | { |
| 1727 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), |
| 1728 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), |
| 1729 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), |
| 1730 | /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), |
| 1731 | /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), |
| 1732 | /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), |
| 1733 | /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), |
| 1734 | /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) |
| 1735 | } |
| 1736 | }, |
| 1737 | .ctlPowerData_5G = { |
| 1738 | { |
| 1739 | { |
| 1740 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 1741 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 1742 | } |
| 1743 | }, |
| 1744 | { |
| 1745 | { |
| 1746 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 1747 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 1748 | } |
| 1749 | }, |
| 1750 | { |
| 1751 | { |
| 1752 | {60, 0}, {60, 1}, {60, 0}, {60, 1}, |
| 1753 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 1754 | } |
| 1755 | }, |
| 1756 | { |
| 1757 | { |
| 1758 | {60, 0}, {60, 1}, {60, 1}, {60, 0}, |
| 1759 | {60, 1}, {60, 0}, {60, 0}, {60, 0}, |
| 1760 | } |
| 1761 | }, |
| 1762 | { |
| 1763 | { |
| 1764 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 1765 | {60, 0}, {60, 0}, {60, 0}, {60, 0}, |
| 1766 | } |
| 1767 | }, |
| 1768 | { |
| 1769 | { |
| 1770 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 1771 | {60, 1}, {60, 0}, {60, 0}, {60, 0}, |
| 1772 | } |
| 1773 | }, |
| 1774 | { |
| 1775 | { |
| 1776 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 1777 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 1778 | } |
| 1779 | }, |
| 1780 | { |
| 1781 | { |
| 1782 | {60, 1}, {60, 1}, {60, 0}, {60, 1}, |
| 1783 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 1784 | } |
| 1785 | }, |
| 1786 | { |
| 1787 | { |
| 1788 | {60, 1}, {60, 0}, {60, 1}, {60, 1}, |
| 1789 | {60, 1}, {60, 1}, {60, 0}, {60, 1}, |
| 1790 | } |
| 1791 | }, |
| 1792 | } |
| 1793 | }; |
| 1794 | |
| 1795 | |
| 1796 | static const struct ar9300_eeprom ar9300_x112 = { |
| 1797 | .eepromVersion = 2, |
| 1798 | .templateVersion = 5, |
| 1799 | .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, |
| 1800 | .custData = {"x112-041-f0000"}, |
| 1801 | .baseEepHeader = { |
| 1802 | .regDmn = { LE16(0), LE16(0x1f) }, |
| 1803 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ |
| 1804 | .opCapFlags = { |
| 1805 | .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, |
| 1806 | .eepMisc = 0, |
| 1807 | }, |
| 1808 | .rfSilent = 0, |
| 1809 | .blueToothOptions = 0, |
| 1810 | .deviceCap = 0, |
| 1811 | .deviceType = 5, /* takes lower byte in eeprom location */ |
| 1812 | .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, |
| 1813 | .params_for_tuning_caps = {0, 0}, |
| 1814 | .featureEnable = 0x0d, |
| 1815 | /* |
| 1816 | * bit0 - enable tx temp comp - disabled |
| 1817 | * bit1 - enable tx volt comp - disabled |
| 1818 | * bit2 - enable fastclock - enabled |
| 1819 | * bit3 - enable doubling - enabled |
| 1820 | * bit4 - enable internal regulator - disabled |
| 1821 | * bit5 - enable pa predistortion - disabled |
| 1822 | */ |
| 1823 | .miscConfiguration = 0, /* bit0 - turn down drivestrength */ |
| 1824 | .eepromWriteEnableGpio = 6, |
| 1825 | .wlanDisableGpio = 0, |
| 1826 | .wlanLedGpio = 8, |
| 1827 | .rxBandSelectGpio = 0xff, |
| 1828 | .txrxgain = 0x0, |
| 1829 | .swreg = 0, |
| 1830 | }, |
| 1831 | .modalHeader2G = { |
| 1832 | /* ar9300_modal_eep_header 2g */ |
| 1833 | /* 4 idle,t1,t2,b(4 bits per setting) */ |
| 1834 | .antCtrlCommon = LE32(0x110), |
| 1835 | /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ |
| 1836 | .antCtrlCommon2 = LE32(0x22222), |
| 1837 | |
| 1838 | /* |
| 1839 | * antCtrlChain[ar9300_max_chains]; 6 idle, t, r, |
| 1840 | * rx1, rx12, b (2 bits each) |
| 1841 | */ |
| 1842 | .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) }, |
| 1843 | |
| 1844 | /* |
| 1845 | * xatten1DB[AR9300_max_chains]; 3 xatten1_db |
| 1846 | * for ar9280 (0xa20c/b20c 5:0) |
| 1847 | */ |
| 1848 | .xatten1DB = {0x1b, 0x1b, 0x1b}, |
| 1849 | |
| 1850 | /* |
| 1851 | * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin |
| 1852 | * for ar9280 (0xa20c/b20c 16:12 |
| 1853 | */ |
| 1854 | .xatten1Margin = {0x15, 0x15, 0x15}, |
| 1855 | .tempSlope = 50, |
| 1856 | .voltSlope = 0, |
| 1857 | |
| 1858 | /* |
| 1859 | * spurChans[OSPrey_eeprom_modal_sPURS]; spur |
| 1860 | * channels in usual fbin coding format |
| 1861 | */ |
| 1862 | .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, |
| 1863 | |
| 1864 | /* |
| 1865 | * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check |
| 1866 | * if the register is per chain |
| 1867 | */ |
| 1868 | .noiseFloorThreshCh = {-1, 0, 0}, |
| 1869 | .ob = {1, 1, 1},/* 3 chain */ |
| 1870 | .db_stage2 = {1, 1, 1}, /* 3 chain */ |
| 1871 | .db_stage3 = {0, 0, 0}, |
| 1872 | .db_stage4 = {0, 0, 0}, |
| 1873 | .xpaBiasLvl = 0, |
| 1874 | .txFrameToDataStart = 0x0e, |
| 1875 | .txFrameToPaOn = 0x0e, |
| 1876 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ |
| 1877 | .antennaGain = 0, |
| 1878 | .switchSettling = 0x2c, |
| 1879 | .adcDesiredSize = -30, |
| 1880 | .txEndToXpaOff = 0, |
| 1881 | .txEndToRxOn = 0x2, |
| 1882 | .txFrameToXpaOn = 0xe, |
| 1883 | .thresh62 = 28, |
| 1884 | .papdRateMaskHt20 = LE32(0x0c80c080), |
| 1885 | .papdRateMaskHt40 = LE32(0x0080c080), |
| 1886 | .futureModal = { |
| 1887 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 1888 | }, |
| 1889 | }, |
| 1890 | .base_ext1 = { |
| 1891 | .ant_div_control = 0, |
| 1892 | .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} |
| 1893 | }, |
| 1894 | .calFreqPier2G = { |
| 1895 | FREQ2FBIN(2412, 1), |
| 1896 | FREQ2FBIN(2437, 1), |
| 1897 | FREQ2FBIN(2472, 1), |
| 1898 | }, |
| 1899 | /* ar9300_cal_data_per_freq_op_loop 2g */ |
| 1900 | .calPierData2G = { |
| 1901 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, |
| 1902 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, |
| 1903 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, |
| 1904 | }, |
| 1905 | .calTarget_freqbin_Cck = { |
| 1906 | FREQ2FBIN(2412, 1), |
| 1907 | FREQ2FBIN(2472, 1), |
| 1908 | }, |
| 1909 | .calTarget_freqbin_2G = { |
| 1910 | FREQ2FBIN(2412, 1), |
| 1911 | FREQ2FBIN(2437, 1), |
| 1912 | FREQ2FBIN(2472, 1) |
| 1913 | }, |
| 1914 | .calTarget_freqbin_2GHT20 = { |
| 1915 | FREQ2FBIN(2412, 1), |
| 1916 | FREQ2FBIN(2437, 1), |
| 1917 | FREQ2FBIN(2472, 1) |
| 1918 | }, |
| 1919 | .calTarget_freqbin_2GHT40 = { |
| 1920 | FREQ2FBIN(2412, 1), |
| 1921 | FREQ2FBIN(2437, 1), |
| 1922 | FREQ2FBIN(2472, 1) |
| 1923 | }, |
| 1924 | .calTargetPowerCck = { |
| 1925 | /* 1L-5L,5S,11L,11s */ |
| 1926 | { {38, 38, 38, 38} }, |
| 1927 | { {38, 38, 38, 38} }, |
| 1928 | }, |
| 1929 | .calTargetPower2G = { |
| 1930 | /* 6-24,36,48,54 */ |
| 1931 | { {38, 38, 36, 34} }, |
| 1932 | { {38, 38, 36, 34} }, |
| 1933 | { {38, 38, 34, 32} }, |
| 1934 | }, |
| 1935 | .calTargetPower2GHT20 = { |
| 1936 | { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} }, |
| 1937 | { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} }, |
| 1938 | { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} }, |
| 1939 | }, |
| 1940 | .calTargetPower2GHT40 = { |
| 1941 | { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} }, |
| 1942 | { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} }, |
| 1943 | { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} }, |
| 1944 | }, |
| 1945 | .ctlIndex_2G = { |
| 1946 | 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, |
| 1947 | 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, |
| 1948 | }, |
| 1949 | .ctl_freqbin_2G = { |
| 1950 | { |
| 1951 | FREQ2FBIN(2412, 1), |
| 1952 | FREQ2FBIN(2417, 1), |
| 1953 | FREQ2FBIN(2457, 1), |
| 1954 | FREQ2FBIN(2462, 1) |
| 1955 | }, |
| 1956 | { |
| 1957 | FREQ2FBIN(2412, 1), |
| 1958 | FREQ2FBIN(2417, 1), |
| 1959 | FREQ2FBIN(2462, 1), |
| 1960 | 0xFF, |
| 1961 | }, |
| 1962 | |
| 1963 | { |
| 1964 | FREQ2FBIN(2412, 1), |
| 1965 | FREQ2FBIN(2417, 1), |
| 1966 | FREQ2FBIN(2462, 1), |
| 1967 | 0xFF, |
| 1968 | }, |
| 1969 | { |
| 1970 | FREQ2FBIN(2422, 1), |
| 1971 | FREQ2FBIN(2427, 1), |
| 1972 | FREQ2FBIN(2447, 1), |
| 1973 | FREQ2FBIN(2452, 1) |
| 1974 | }, |
| 1975 | |
| 1976 | { |
| 1977 | /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), |
| 1978 | /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), |
| 1979 | /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), |
| 1980 | /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1), |
| 1981 | }, |
| 1982 | |
| 1983 | { |
| 1984 | /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), |
| 1985 | /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), |
| 1986 | /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), |
| 1987 | 0, |
| 1988 | }, |
| 1989 | |
| 1990 | { |
| 1991 | /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), |
| 1992 | /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), |
| 1993 | FREQ2FBIN(2472, 1), |
| 1994 | 0, |
| 1995 | }, |
| 1996 | |
| 1997 | { |
| 1998 | /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1), |
| 1999 | /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1), |
| 2000 | /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1), |
| 2001 | /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1), |
| 2002 | }, |
| 2003 | |
| 2004 | { |
| 2005 | /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), |
| 2006 | /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), |
| 2007 | /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), |
| 2008 | }, |
| 2009 | |
| 2010 | { |
| 2011 | /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), |
| 2012 | /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), |
| 2013 | /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), |
| 2014 | 0 |
| 2015 | }, |
| 2016 | |
| 2017 | { |
| 2018 | /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), |
| 2019 | /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), |
| 2020 | /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), |
| 2021 | 0 |
| 2022 | }, |
| 2023 | |
| 2024 | { |
| 2025 | /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1), |
| 2026 | /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1), |
| 2027 | /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1), |
| 2028 | /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1), |
| 2029 | } |
| 2030 | }, |
| 2031 | .ctlPowerData_2G = { |
| 2032 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 2033 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 2034 | { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } }, |
| 2035 | |
| 2036 | { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } }, |
| 2037 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 2038 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 2039 | |
| 2040 | { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } }, |
| 2041 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 2042 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 2043 | |
| 2044 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 2045 | { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } }, |
| 2046 | { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } }, |
| 2047 | }, |
| 2048 | .modalHeader5G = { |
| 2049 | /* 4 idle,t1,t2,b (4 bits per setting) */ |
| 2050 | .antCtrlCommon = LE32(0x110), |
| 2051 | /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ |
| 2052 | .antCtrlCommon2 = LE32(0x22222), |
| 2053 | /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ |
| 2054 | .antCtrlChain = { |
| 2055 | LE16(0x0), LE16(0x0), LE16(0x0), |
| 2056 | }, |
| 2057 | /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */ |
| 2058 | .xatten1DB = {0x13, 0x19, 0x17}, |
| 2059 | |
| 2060 | /* |
| 2061 | * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin |
| 2062 | * for merlin (0xa20c/b20c 16:12 |
| 2063 | */ |
| 2064 | .xatten1Margin = {0x19, 0x19, 0x19}, |
| 2065 | .tempSlope = 70, |
| 2066 | .voltSlope = 15, |
| 2067 | /* spurChans spur channels in usual fbin coding format */ |
| 2068 | .spurChans = {0, 0, 0, 0, 0}, |
| 2069 | /* noiseFloorThreshch check if the register is per chain */ |
| 2070 | .noiseFloorThreshCh = {-1, 0, 0}, |
| 2071 | .ob = {3, 3, 3}, /* 3 chain */ |
| 2072 | .db_stage2 = {3, 3, 3}, /* 3 chain */ |
| 2073 | .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */ |
| 2074 | .db_stage4 = {3, 3, 3}, /* don't exist for 2G */ |
| 2075 | .xpaBiasLvl = 0, |
| 2076 | .txFrameToDataStart = 0x0e, |
| 2077 | .txFrameToPaOn = 0x0e, |
| 2078 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ |
| 2079 | .antennaGain = 0, |
| 2080 | .switchSettling = 0x2d, |
| 2081 | .adcDesiredSize = -30, |
| 2082 | .txEndToXpaOff = 0, |
| 2083 | .txEndToRxOn = 0x2, |
| 2084 | .txFrameToXpaOn = 0xe, |
| 2085 | .thresh62 = 28, |
| 2086 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), |
| 2087 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), |
| 2088 | .futureModal = { |
| 2089 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 2090 | }, |
| 2091 | }, |
| 2092 | .base_ext2 = { |
| 2093 | .tempSlopeLow = 72, |
| 2094 | .tempSlopeHigh = 105, |
| 2095 | .xatten1DBLow = {0x10, 0x14, 0x10}, |
| 2096 | .xatten1MarginLow = {0x19, 0x19 , 0x19}, |
| 2097 | .xatten1DBHigh = {0x1d, 0x20, 0x24}, |
| 2098 | .xatten1MarginHigh = {0x10, 0x10, 0x10} |
| 2099 | }, |
| 2100 | .calFreqPier5G = { |
| 2101 | FREQ2FBIN(5180, 0), |
| 2102 | FREQ2FBIN(5220, 0), |
| 2103 | FREQ2FBIN(5320, 0), |
| 2104 | FREQ2FBIN(5400, 0), |
| 2105 | FREQ2FBIN(5500, 0), |
| 2106 | FREQ2FBIN(5600, 0), |
| 2107 | FREQ2FBIN(5700, 0), |
| 2108 | FREQ2FBIN(5785, 0) |
| 2109 | }, |
| 2110 | .calPierData5G = { |
| 2111 | { |
| 2112 | {0, 0, 0, 0, 0}, |
| 2113 | {0, 0, 0, 0, 0}, |
| 2114 | {0, 0, 0, 0, 0}, |
| 2115 | {0, 0, 0, 0, 0}, |
| 2116 | {0, 0, 0, 0, 0}, |
| 2117 | {0, 0, 0, 0, 0}, |
| 2118 | {0, 0, 0, 0, 0}, |
| 2119 | {0, 0, 0, 0, 0}, |
| 2120 | }, |
| 2121 | { |
| 2122 | {0, 0, 0, 0, 0}, |
| 2123 | {0, 0, 0, 0, 0}, |
| 2124 | {0, 0, 0, 0, 0}, |
| 2125 | {0, 0, 0, 0, 0}, |
| 2126 | {0, 0, 0, 0, 0}, |
| 2127 | {0, 0, 0, 0, 0}, |
| 2128 | {0, 0, 0, 0, 0}, |
| 2129 | {0, 0, 0, 0, 0}, |
| 2130 | }, |
| 2131 | { |
| 2132 | {0, 0, 0, 0, 0}, |
| 2133 | {0, 0, 0, 0, 0}, |
| 2134 | {0, 0, 0, 0, 0}, |
| 2135 | {0, 0, 0, 0, 0}, |
| 2136 | {0, 0, 0, 0, 0}, |
| 2137 | {0, 0, 0, 0, 0}, |
| 2138 | {0, 0, 0, 0, 0}, |
| 2139 | {0, 0, 0, 0, 0}, |
| 2140 | }, |
| 2141 | |
| 2142 | }, |
| 2143 | .calTarget_freqbin_5G = { |
| 2144 | FREQ2FBIN(5180, 0), |
| 2145 | FREQ2FBIN(5220, 0), |
| 2146 | FREQ2FBIN(5320, 0), |
| 2147 | FREQ2FBIN(5400, 0), |
| 2148 | FREQ2FBIN(5500, 0), |
| 2149 | FREQ2FBIN(5600, 0), |
| 2150 | FREQ2FBIN(5725, 0), |
| 2151 | FREQ2FBIN(5825, 0) |
| 2152 | }, |
| 2153 | .calTarget_freqbin_5GHT20 = { |
| 2154 | FREQ2FBIN(5180, 0), |
| 2155 | FREQ2FBIN(5220, 0), |
| 2156 | FREQ2FBIN(5320, 0), |
| 2157 | FREQ2FBIN(5400, 0), |
| 2158 | FREQ2FBIN(5500, 0), |
| 2159 | FREQ2FBIN(5600, 0), |
| 2160 | FREQ2FBIN(5725, 0), |
| 2161 | FREQ2FBIN(5825, 0) |
| 2162 | }, |
| 2163 | .calTarget_freqbin_5GHT40 = { |
| 2164 | FREQ2FBIN(5180, 0), |
| 2165 | FREQ2FBIN(5220, 0), |
| 2166 | FREQ2FBIN(5320, 0), |
| 2167 | FREQ2FBIN(5400, 0), |
| 2168 | FREQ2FBIN(5500, 0), |
| 2169 | FREQ2FBIN(5600, 0), |
| 2170 | FREQ2FBIN(5725, 0), |
| 2171 | FREQ2FBIN(5825, 0) |
| 2172 | }, |
| 2173 | .calTargetPower5G = { |
| 2174 | /* 6-24,36,48,54 */ |
| 2175 | { {32, 32, 28, 26} }, |
| 2176 | { {32, 32, 28, 26} }, |
| 2177 | { {32, 32, 28, 26} }, |
| 2178 | { {32, 32, 26, 24} }, |
| 2179 | { {32, 32, 26, 24} }, |
| 2180 | { {32, 32, 24, 22} }, |
| 2181 | { {30, 30, 24, 22} }, |
| 2182 | { {30, 30, 24, 22} }, |
| 2183 | }, |
| 2184 | .calTargetPower5GHT20 = { |
| 2185 | /* |
| 2186 | * 0_8_16,1-3_9-11_17-19, |
| 2187 | * 4,5,6,7,12,13,14,15,20,21,22,23 |
| 2188 | */ |
| 2189 | { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} }, |
| 2190 | { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} }, |
| 2191 | { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} }, |
| 2192 | { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} }, |
| 2193 | { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} }, |
| 2194 | { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} }, |
| 2195 | { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} }, |
| 2196 | { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} }, |
| 2197 | }, |
| 2198 | .calTargetPower5GHT40 = { |
| 2199 | /* |
| 2200 | * 0_8_16,1-3_9-11_17-19, |
| 2201 | * 4,5,6,7,12,13,14,15,20,21,22,23 |
| 2202 | */ |
| 2203 | { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} }, |
| 2204 | { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} }, |
| 2205 | { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} }, |
| 2206 | { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} }, |
| 2207 | { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} }, |
| 2208 | { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} }, |
| 2209 | { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} }, |
| 2210 | { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} }, |
| 2211 | }, |
| 2212 | .ctlIndex_5G = { |
| 2213 | 0x10, 0x16, 0x18, 0x40, 0x46, |
| 2214 | 0x48, 0x30, 0x36, 0x38 |
| 2215 | }, |
| 2216 | .ctl_freqbin_5G = { |
| 2217 | { |
| 2218 | /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), |
| 2219 | /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), |
| 2220 | /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0), |
| 2221 | /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), |
| 2222 | /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0), |
| 2223 | /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), |
| 2224 | /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), |
| 2225 | /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) |
| 2226 | }, |
| 2227 | { |
| 2228 | /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), |
| 2229 | /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), |
| 2230 | /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0), |
| 2231 | /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), |
| 2232 | /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0), |
| 2233 | /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), |
| 2234 | /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), |
| 2235 | /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) |
| 2236 | }, |
| 2237 | |
| 2238 | { |
| 2239 | /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), |
| 2240 | /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0), |
| 2241 | /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0), |
| 2242 | /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0), |
| 2243 | /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0), |
| 2244 | /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0), |
| 2245 | /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0), |
| 2246 | /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0) |
| 2247 | }, |
| 2248 | |
| 2249 | { |
| 2250 | /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), |
| 2251 | /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0), |
| 2252 | /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0), |
| 2253 | /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0), |
| 2254 | /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0), |
| 2255 | /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), |
| 2256 | /* Data[3].ctledges[6].bchannel */ 0xFF, |
| 2257 | /* Data[3].ctledges[7].bchannel */ 0xFF, |
| 2258 | }, |
| 2259 | |
| 2260 | { |
| 2261 | /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), |
| 2262 | /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), |
| 2263 | /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0), |
| 2264 | /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0), |
| 2265 | /* Data[4].ctledges[4].bchannel */ 0xFF, |
| 2266 | /* Data[4].ctledges[5].bchannel */ 0xFF, |
| 2267 | /* Data[4].ctledges[6].bchannel */ 0xFF, |
| 2268 | /* Data[4].ctledges[7].bchannel */ 0xFF, |
| 2269 | }, |
| 2270 | |
| 2271 | { |
| 2272 | /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), |
| 2273 | /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0), |
| 2274 | /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0), |
| 2275 | /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0), |
| 2276 | /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0), |
| 2277 | /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0), |
| 2278 | /* Data[5].ctledges[6].bchannel */ 0xFF, |
| 2279 | /* Data[5].ctledges[7].bchannel */ 0xFF |
| 2280 | }, |
| 2281 | |
| 2282 | { |
| 2283 | /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), |
| 2284 | /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0), |
| 2285 | /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0), |
| 2286 | /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0), |
| 2287 | /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0), |
| 2288 | /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0), |
| 2289 | /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0), |
| 2290 | /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0) |
| 2291 | }, |
| 2292 | |
| 2293 | { |
| 2294 | /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), |
| 2295 | /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), |
| 2296 | /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0), |
| 2297 | /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), |
| 2298 | /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0), |
| 2299 | /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), |
| 2300 | /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), |
| 2301 | /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) |
| 2302 | }, |
| 2303 | |
| 2304 | { |
| 2305 | /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), |
| 2306 | /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0), |
| 2307 | /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0), |
| 2308 | /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0), |
| 2309 | /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0), |
| 2310 | /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0), |
| 2311 | /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0), |
| 2312 | /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0) |
| 2313 | } |
| 2314 | }, |
| 2315 | .ctlPowerData_5G = { |
| 2316 | { |
| 2317 | { |
| 2318 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 2319 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 2320 | } |
| 2321 | }, |
| 2322 | { |
| 2323 | { |
| 2324 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 2325 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 2326 | } |
| 2327 | }, |
| 2328 | { |
| 2329 | { |
| 2330 | {60, 0}, {60, 1}, {60, 0}, {60, 1}, |
| 2331 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 2332 | } |
| 2333 | }, |
| 2334 | { |
| 2335 | { |
| 2336 | {60, 0}, {60, 1}, {60, 1}, {60, 0}, |
| 2337 | {60, 1}, {60, 0}, {60, 0}, {60, 0}, |
| 2338 | } |
| 2339 | }, |
| 2340 | { |
| 2341 | { |
| 2342 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 2343 | {60, 0}, {60, 0}, {60, 0}, {60, 0}, |
| 2344 | } |
| 2345 | }, |
| 2346 | { |
| 2347 | { |
| 2348 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 2349 | {60, 1}, {60, 0}, {60, 0}, {60, 0}, |
| 2350 | } |
| 2351 | }, |
| 2352 | { |
| 2353 | { |
| 2354 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 2355 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 2356 | } |
| 2357 | }, |
| 2358 | { |
| 2359 | { |
| 2360 | {60, 1}, {60, 1}, {60, 0}, {60, 1}, |
| 2361 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 2362 | } |
| 2363 | }, |
| 2364 | { |
| 2365 | { |
| 2366 | {60, 1}, {60, 0}, {60, 1}, {60, 1}, |
| 2367 | {60, 1}, {60, 1}, {60, 0}, {60, 1}, |
| 2368 | } |
| 2369 | }, |
| 2370 | } |
| 2371 | }; |
| 2372 | |
| 2373 | static const struct ar9300_eeprom ar9300_h116 = { |
| 2374 | .eepromVersion = 2, |
| 2375 | .templateVersion = 4, |
| 2376 | .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, |
| 2377 | .custData = {"h116-041-f0000"}, |
| 2378 | .baseEepHeader = { |
| 2379 | .regDmn = { LE16(0), LE16(0x1f) }, |
| 2380 | .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */ |
| 2381 | .opCapFlags = { |
| 2382 | .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, |
| 2383 | .eepMisc = 0, |
| 2384 | }, |
| 2385 | .rfSilent = 0, |
| 2386 | .blueToothOptions = 0, |
| 2387 | .deviceCap = 0, |
| 2388 | .deviceType = 5, /* takes lower byte in eeprom location */ |
| 2389 | .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, |
| 2390 | .params_for_tuning_caps = {0, 0}, |
| 2391 | .featureEnable = 0x0d, |
| 2392 | /* |
| 2393 | * bit0 - enable tx temp comp - disabled |
| 2394 | * bit1 - enable tx volt comp - disabled |
| 2395 | * bit2 - enable fastClock - enabled |
| 2396 | * bit3 - enable doubling - enabled |
| 2397 | * bit4 - enable internal regulator - disabled |
| 2398 | * bit5 - enable pa predistortion - disabled |
| 2399 | */ |
| 2400 | .miscConfiguration = 0, /* bit0 - turn down drivestrength */ |
| 2401 | .eepromWriteEnableGpio = 6, |
| 2402 | .wlanDisableGpio = 0, |
| 2403 | .wlanLedGpio = 8, |
| 2404 | .rxBandSelectGpio = 0xff, |
| 2405 | .txrxgain = 0x10, |
| 2406 | .swreg = 0, |
| 2407 | }, |
| 2408 | .modalHeader2G = { |
| 2409 | /* ar9300_modal_eep_header 2g */ |
| 2410 | /* 4 idle,t1,t2,b(4 bits per setting) */ |
| 2411 | .antCtrlCommon = LE32(0x110), |
| 2412 | /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ |
| 2413 | .antCtrlCommon2 = LE32(0x44444), |
| 2414 | |
| 2415 | /* |
| 2416 | * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, |
| 2417 | * rx1, rx12, b (2 bits each) |
| 2418 | */ |
| 2419 | .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) }, |
| 2420 | |
| 2421 | /* |
| 2422 | * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db |
| 2423 | * for ar9280 (0xa20c/b20c 5:0) |
| 2424 | */ |
| 2425 | .xatten1DB = {0x1f, 0x1f, 0x1f}, |
| 2426 | |
| 2427 | /* |
| 2428 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin |
| 2429 | * for ar9280 (0xa20c/b20c 16:12 |
| 2430 | */ |
| 2431 | .xatten1Margin = {0x12, 0x12, 0x12}, |
| 2432 | .tempSlope = 25, |
| 2433 | .voltSlope = 0, |
| 2434 | |
| 2435 | /* |
| 2436 | * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur |
| 2437 | * channels in usual fbin coding format |
| 2438 | */ |
| 2439 | .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, |
| 2440 | |
| 2441 | /* |
| 2442 | * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check |
| 2443 | * if the register is per chain |
| 2444 | */ |
| 2445 | .noiseFloorThreshCh = {-1, 0, 0}, |
| 2446 | .ob = {1, 1, 1},/* 3 chain */ |
| 2447 | .db_stage2 = {1, 1, 1}, /* 3 chain */ |
| 2448 | .db_stage3 = {0, 0, 0}, |
| 2449 | .db_stage4 = {0, 0, 0}, |
| 2450 | .xpaBiasLvl = 0, |
| 2451 | .txFrameToDataStart = 0x0e, |
| 2452 | .txFrameToPaOn = 0x0e, |
| 2453 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ |
| 2454 | .antennaGain = 0, |
| 2455 | .switchSettling = 0x2c, |
| 2456 | .adcDesiredSize = -30, |
| 2457 | .txEndToXpaOff = 0, |
| 2458 | .txEndToRxOn = 0x2, |
| 2459 | .txFrameToXpaOn = 0xe, |
| 2460 | .thresh62 = 28, |
| 2461 | .papdRateMaskHt20 = LE32(0x0c80C080), |
| 2462 | .papdRateMaskHt40 = LE32(0x0080C080), |
| 2463 | .futureModal = { |
| 2464 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 2465 | }, |
| 2466 | }, |
| 2467 | .base_ext1 = { |
| 2468 | .ant_div_control = 0, |
| 2469 | .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} |
| 2470 | }, |
| 2471 | .calFreqPier2G = { |
| 2472 | FREQ2FBIN(2412, 1), |
| 2473 | FREQ2FBIN(2437, 1), |
| 2474 | FREQ2FBIN(2472, 1), |
| 2475 | }, |
| 2476 | /* ar9300_cal_data_per_freq_op_loop 2g */ |
| 2477 | .calPierData2G = { |
| 2478 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, |
| 2479 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, |
| 2480 | { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, |
| 2481 | }, |
| 2482 | .calTarget_freqbin_Cck = { |
| 2483 | FREQ2FBIN(2412, 1), |
| 2484 | FREQ2FBIN(2472, 1), |
| 2485 | }, |
| 2486 | .calTarget_freqbin_2G = { |
| 2487 | FREQ2FBIN(2412, 1), |
| 2488 | FREQ2FBIN(2437, 1), |
| 2489 | FREQ2FBIN(2472, 1) |
| 2490 | }, |
| 2491 | .calTarget_freqbin_2GHT20 = { |
| 2492 | FREQ2FBIN(2412, 1), |
| 2493 | FREQ2FBIN(2437, 1), |
| 2494 | FREQ2FBIN(2472, 1) |
| 2495 | }, |
| 2496 | .calTarget_freqbin_2GHT40 = { |
| 2497 | FREQ2FBIN(2412, 1), |
| 2498 | FREQ2FBIN(2437, 1), |
| 2499 | FREQ2FBIN(2472, 1) |
| 2500 | }, |
| 2501 | .calTargetPowerCck = { |
| 2502 | /* 1L-5L,5S,11L,11S */ |
| 2503 | { {34, 34, 34, 34} }, |
| 2504 | { {34, 34, 34, 34} }, |
| 2505 | }, |
| 2506 | .calTargetPower2G = { |
| 2507 | /* 6-24,36,48,54 */ |
| 2508 | { {34, 34, 32, 32} }, |
| 2509 | { {34, 34, 32, 32} }, |
| 2510 | { {34, 34, 32, 32} }, |
| 2511 | }, |
| 2512 | .calTargetPower2GHT20 = { |
| 2513 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} }, |
| 2514 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} }, |
| 2515 | { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} }, |
| 2516 | }, |
| 2517 | .calTargetPower2GHT40 = { |
| 2518 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, |
| 2519 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, |
| 2520 | { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, |
| 2521 | }, |
| 2522 | .ctlIndex_2G = { |
| 2523 | 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, |
| 2524 | 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, |
| 2525 | }, |
| 2526 | .ctl_freqbin_2G = { |
| 2527 | { |
| 2528 | FREQ2FBIN(2412, 1), |
| 2529 | FREQ2FBIN(2417, 1), |
| 2530 | FREQ2FBIN(2457, 1), |
| 2531 | FREQ2FBIN(2462, 1) |
| 2532 | }, |
| 2533 | { |
| 2534 | FREQ2FBIN(2412, 1), |
| 2535 | FREQ2FBIN(2417, 1), |
| 2536 | FREQ2FBIN(2462, 1), |
| 2537 | 0xFF, |
| 2538 | }, |
| 2539 | |
| 2540 | { |
| 2541 | FREQ2FBIN(2412, 1), |
| 2542 | FREQ2FBIN(2417, 1), |
| 2543 | FREQ2FBIN(2462, 1), |
| 2544 | 0xFF, |
| 2545 | }, |
| 2546 | { |
| 2547 | FREQ2FBIN(2422, 1), |
| 2548 | FREQ2FBIN(2427, 1), |
| 2549 | FREQ2FBIN(2447, 1), |
| 2550 | FREQ2FBIN(2452, 1) |
| 2551 | }, |
| 2552 | |
| 2553 | { |
| 2554 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 2555 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 2556 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 2557 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), |
| 2558 | }, |
| 2559 | |
| 2560 | { |
| 2561 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 2562 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 2563 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 2564 | 0, |
| 2565 | }, |
| 2566 | |
| 2567 | { |
| 2568 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 2569 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 2570 | FREQ2FBIN(2472, 1), |
| 2571 | 0, |
| 2572 | }, |
| 2573 | |
| 2574 | { |
| 2575 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), |
| 2576 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), |
| 2577 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), |
| 2578 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), |
| 2579 | }, |
| 2580 | |
| 2581 | { |
| 2582 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 2583 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 2584 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 2585 | }, |
| 2586 | |
| 2587 | { |
| 2588 | /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 2589 | /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 2590 | /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 2591 | 0 |
| 2592 | }, |
| 2593 | |
| 2594 | { |
| 2595 | /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), |
| 2596 | /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), |
| 2597 | /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), |
| 2598 | 0 |
| 2599 | }, |
| 2600 | |
| 2601 | { |
| 2602 | /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), |
| 2603 | /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), |
| 2604 | /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), |
| 2605 | /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), |
| 2606 | } |
| 2607 | }, |
| 2608 | .ctlPowerData_2G = { |
| 2609 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 2610 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 2611 | { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } }, |
| 2612 | |
| 2613 | { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } }, |
| 2614 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 2615 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 2616 | |
| 2617 | { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } }, |
| 2618 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 2619 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 2620 | |
| 2621 | { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, |
| 2622 | { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } }, |
| 2623 | { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } }, |
| 2624 | }, |
| 2625 | .modalHeader5G = { |
| 2626 | /* 4 idle,t1,t2,b (4 bits per setting) */ |
| 2627 | .antCtrlCommon = LE32(0x220), |
| 2628 | /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ |
| 2629 | .antCtrlCommon2 = LE32(0x44444), |
| 2630 | /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ |
| 2631 | .antCtrlChain = { |
| 2632 | LE16(0x150), LE16(0x150), LE16(0x150), |
| 2633 | }, |
| 2634 | /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ |
| 2635 | .xatten1DB = {0x19, 0x19, 0x19}, |
| 2636 | |
| 2637 | /* |
| 2638 | * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin |
| 2639 | * for merlin (0xa20c/b20c 16:12 |
| 2640 | */ |
| 2641 | .xatten1Margin = {0x14, 0x14, 0x14}, |
| 2642 | .tempSlope = 70, |
| 2643 | .voltSlope = 0, |
| 2644 | /* spurChans spur channels in usual fbin coding format */ |
| 2645 | .spurChans = {0, 0, 0, 0, 0}, |
| 2646 | /* noiseFloorThreshCh Check if the register is per chain */ |
| 2647 | .noiseFloorThreshCh = {-1, 0, 0}, |
| 2648 | .ob = {3, 3, 3}, /* 3 chain */ |
| 2649 | .db_stage2 = {3, 3, 3}, /* 3 chain */ |
| 2650 | .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */ |
| 2651 | .db_stage4 = {3, 3, 3}, /* don't exist for 2G */ |
| 2652 | .xpaBiasLvl = 0, |
| 2653 | .txFrameToDataStart = 0x0e, |
| 2654 | .txFrameToPaOn = 0x0e, |
| 2655 | .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ |
| 2656 | .antennaGain = 0, |
| 2657 | .switchSettling = 0x2d, |
| 2658 | .adcDesiredSize = -30, |
| 2659 | .txEndToXpaOff = 0, |
| 2660 | .txEndToRxOn = 0x2, |
| 2661 | .txFrameToXpaOn = 0xe, |
| 2662 | .thresh62 = 28, |
| 2663 | .papdRateMaskHt20 = LE32(0x0cf0e0e0), |
| 2664 | .papdRateMaskHt40 = LE32(0x6cf0e0e0), |
| 2665 | .futureModal = { |
| 2666 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 2667 | }, |
| 2668 | }, |
| 2669 | .base_ext2 = { |
| 2670 | .tempSlopeLow = 35, |
| 2671 | .tempSlopeHigh = 50, |
| 2672 | .xatten1DBLow = {0, 0, 0}, |
| 2673 | .xatten1MarginLow = {0, 0, 0}, |
| 2674 | .xatten1DBHigh = {0, 0, 0}, |
| 2675 | .xatten1MarginHigh = {0, 0, 0} |
| 2676 | }, |
| 2677 | .calFreqPier5G = { |
| 2678 | FREQ2FBIN(5180, 0), |
| 2679 | FREQ2FBIN(5220, 0), |
| 2680 | FREQ2FBIN(5320, 0), |
| 2681 | FREQ2FBIN(5400, 0), |
| 2682 | FREQ2FBIN(5500, 0), |
| 2683 | FREQ2FBIN(5600, 0), |
| 2684 | FREQ2FBIN(5700, 0), |
| 2685 | FREQ2FBIN(5785, 0) |
| 2686 | }, |
| 2687 | .calPierData5G = { |
| 2688 | { |
| 2689 | {0, 0, 0, 0, 0}, |
| 2690 | {0, 0, 0, 0, 0}, |
| 2691 | {0, 0, 0, 0, 0}, |
| 2692 | {0, 0, 0, 0, 0}, |
| 2693 | {0, 0, 0, 0, 0}, |
| 2694 | {0, 0, 0, 0, 0}, |
| 2695 | {0, 0, 0, 0, 0}, |
| 2696 | {0, 0, 0, 0, 0}, |
| 2697 | }, |
| 2698 | { |
| 2699 | {0, 0, 0, 0, 0}, |
| 2700 | {0, 0, 0, 0, 0}, |
| 2701 | {0, 0, 0, 0, 0}, |
| 2702 | {0, 0, 0, 0, 0}, |
| 2703 | {0, 0, 0, 0, 0}, |
| 2704 | {0, 0, 0, 0, 0}, |
| 2705 | {0, 0, 0, 0, 0}, |
| 2706 | {0, 0, 0, 0, 0}, |
| 2707 | }, |
| 2708 | { |
| 2709 | {0, 0, 0, 0, 0}, |
| 2710 | {0, 0, 0, 0, 0}, |
| 2711 | {0, 0, 0, 0, 0}, |
| 2712 | {0, 0, 0, 0, 0}, |
| 2713 | {0, 0, 0, 0, 0}, |
| 2714 | {0, 0, 0, 0, 0}, |
| 2715 | {0, 0, 0, 0, 0}, |
| 2716 | {0, 0, 0, 0, 0}, |
| 2717 | }, |
| 2718 | |
| 2719 | }, |
| 2720 | .calTarget_freqbin_5G = { |
| 2721 | FREQ2FBIN(5180, 0), |
| 2722 | FREQ2FBIN(5240, 0), |
| 2723 | FREQ2FBIN(5320, 0), |
| 2724 | FREQ2FBIN(5400, 0), |
| 2725 | FREQ2FBIN(5500, 0), |
| 2726 | FREQ2FBIN(5600, 0), |
| 2727 | FREQ2FBIN(5700, 0), |
| 2728 | FREQ2FBIN(5825, 0) |
| 2729 | }, |
| 2730 | .calTarget_freqbin_5GHT20 = { |
| 2731 | FREQ2FBIN(5180, 0), |
| 2732 | FREQ2FBIN(5240, 0), |
| 2733 | FREQ2FBIN(5320, 0), |
| 2734 | FREQ2FBIN(5400, 0), |
| 2735 | FREQ2FBIN(5500, 0), |
| 2736 | FREQ2FBIN(5700, 0), |
| 2737 | FREQ2FBIN(5745, 0), |
| 2738 | FREQ2FBIN(5825, 0) |
| 2739 | }, |
| 2740 | .calTarget_freqbin_5GHT40 = { |
| 2741 | FREQ2FBIN(5180, 0), |
| 2742 | FREQ2FBIN(5240, 0), |
| 2743 | FREQ2FBIN(5320, 0), |
| 2744 | FREQ2FBIN(5400, 0), |
| 2745 | FREQ2FBIN(5500, 0), |
| 2746 | FREQ2FBIN(5700, 0), |
| 2747 | FREQ2FBIN(5745, 0), |
| 2748 | FREQ2FBIN(5825, 0) |
| 2749 | }, |
| 2750 | .calTargetPower5G = { |
| 2751 | /* 6-24,36,48,54 */ |
| 2752 | { {30, 30, 28, 24} }, |
| 2753 | { {30, 30, 28, 24} }, |
| 2754 | { {30, 30, 28, 24} }, |
| 2755 | { {30, 30, 28, 24} }, |
| 2756 | { {30, 30, 28, 24} }, |
| 2757 | { {30, 30, 28, 24} }, |
| 2758 | { {30, 30, 28, 24} }, |
| 2759 | { {30, 30, 28, 24} }, |
| 2760 | }, |
| 2761 | .calTargetPower5GHT20 = { |
| 2762 | /* |
| 2763 | * 0_8_16,1-3_9-11_17-19, |
| 2764 | * 4,5,6,7,12,13,14,15,20,21,22,23 |
| 2765 | */ |
| 2766 | { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} }, |
| 2767 | { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} }, |
| 2768 | { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} }, |
| 2769 | { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} }, |
| 2770 | { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} }, |
| 2771 | { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} }, |
| 2772 | { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} }, |
| 2773 | { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} }, |
| 2774 | }, |
| 2775 | .calTargetPower5GHT40 = { |
| 2776 | /* |
| 2777 | * 0_8_16,1-3_9-11_17-19, |
| 2778 | * 4,5,6,7,12,13,14,15,20,21,22,23 |
| 2779 | */ |
| 2780 | { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} }, |
| 2781 | { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} }, |
| 2782 | { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} }, |
| 2783 | { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} }, |
| 2784 | { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} }, |
| 2785 | { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} }, |
| 2786 | { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} }, |
| 2787 | { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} }, |
| 2788 | }, |
| 2789 | .ctlIndex_5G = { |
| 2790 | 0x10, 0x16, 0x18, 0x40, 0x46, |
| 2791 | 0x48, 0x30, 0x36, 0x38 |
| 2792 | }, |
| 2793 | .ctl_freqbin_5G = { |
| 2794 | { |
| 2795 | /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 2796 | /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), |
| 2797 | /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), |
| 2798 | /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), |
| 2799 | /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), |
| 2800 | /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), |
| 2801 | /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), |
| 2802 | /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) |
| 2803 | }, |
| 2804 | { |
| 2805 | /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 2806 | /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), |
| 2807 | /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), |
| 2808 | /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), |
| 2809 | /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), |
| 2810 | /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), |
| 2811 | /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), |
| 2812 | /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) |
| 2813 | }, |
| 2814 | |
| 2815 | { |
| 2816 | /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), |
| 2817 | /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), |
| 2818 | /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), |
| 2819 | /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), |
| 2820 | /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), |
| 2821 | /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), |
| 2822 | /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), |
| 2823 | /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) |
| 2824 | }, |
| 2825 | |
| 2826 | { |
| 2827 | /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 2828 | /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), |
| 2829 | /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), |
| 2830 | /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), |
| 2831 | /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), |
| 2832 | /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), |
| 2833 | /* Data[3].ctlEdges[6].bChannel */ 0xFF, |
| 2834 | /* Data[3].ctlEdges[7].bChannel */ 0xFF, |
| 2835 | }, |
| 2836 | |
| 2837 | { |
| 2838 | /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 2839 | /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), |
| 2840 | /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), |
| 2841 | /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), |
| 2842 | /* Data[4].ctlEdges[4].bChannel */ 0xFF, |
| 2843 | /* Data[4].ctlEdges[5].bChannel */ 0xFF, |
| 2844 | /* Data[4].ctlEdges[6].bChannel */ 0xFF, |
| 2845 | /* Data[4].ctlEdges[7].bChannel */ 0xFF, |
| 2846 | }, |
| 2847 | |
| 2848 | { |
| 2849 | /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), |
| 2850 | /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), |
| 2851 | /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), |
| 2852 | /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), |
| 2853 | /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), |
| 2854 | /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), |
| 2855 | /* Data[5].ctlEdges[6].bChannel */ 0xFF, |
| 2856 | /* Data[5].ctlEdges[7].bChannel */ 0xFF |
| 2857 | }, |
| 2858 | |
| 2859 | { |
| 2860 | /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 2861 | /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), |
| 2862 | /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), |
| 2863 | /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), |
| 2864 | /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), |
| 2865 | /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), |
| 2866 | /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), |
| 2867 | /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) |
| 2868 | }, |
| 2869 | |
| 2870 | { |
| 2871 | /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), |
| 2872 | /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), |
| 2873 | /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), |
| 2874 | /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), |
| 2875 | /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), |
| 2876 | /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), |
| 2877 | /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), |
| 2878 | /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) |
| 2879 | }, |
| 2880 | |
| 2881 | { |
| 2882 | /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), |
| 2883 | /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), |
| 2884 | /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), |
| 2885 | /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), |
| 2886 | /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), |
| 2887 | /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), |
| 2888 | /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), |
| 2889 | /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) |
| 2890 | } |
| 2891 | }, |
| 2892 | .ctlPowerData_5G = { |
| 2893 | { |
| 2894 | { |
| 2895 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 2896 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 2897 | } |
| 2898 | }, |
| 2899 | { |
| 2900 | { |
| 2901 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 2902 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 2903 | } |
| 2904 | }, |
| 2905 | { |
| 2906 | { |
| 2907 | {60, 0}, {60, 1}, {60, 0}, {60, 1}, |
| 2908 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 2909 | } |
| 2910 | }, |
| 2911 | { |
| 2912 | { |
| 2913 | {60, 0}, {60, 1}, {60, 1}, {60, 0}, |
| 2914 | {60, 1}, {60, 0}, {60, 0}, {60, 0}, |
| 2915 | } |
| 2916 | }, |
| 2917 | { |
| 2918 | { |
| 2919 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 2920 | {60, 0}, {60, 0}, {60, 0}, {60, 0}, |
| 2921 | } |
| 2922 | }, |
| 2923 | { |
| 2924 | { |
| 2925 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 2926 | {60, 1}, {60, 0}, {60, 0}, {60, 0}, |
| 2927 | } |
| 2928 | }, |
| 2929 | { |
| 2930 | { |
| 2931 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 2932 | {60, 1}, {60, 1}, {60, 1}, {60, 1}, |
| 2933 | } |
| 2934 | }, |
| 2935 | { |
| 2936 | { |
| 2937 | {60, 1}, {60, 1}, {60, 0}, {60, 1}, |
| 2938 | {60, 1}, {60, 1}, {60, 1}, {60, 0}, |
| 2939 | } |
| 2940 | }, |
| 2941 | { |
| 2942 | { |
| 2943 | {60, 1}, {60, 0}, {60, 1}, {60, 1}, |
| 2944 | {60, 1}, {60, 1}, {60, 0}, {60, 1}, |
| 2945 | } |
| 2946 | }, |
| 2947 | } |
| 2948 | }; |
| 2949 | |
| 2950 | |
| 2951 | static const struct ar9300_eeprom *ar9300_eep_templates[] = { |
| 2952 | &ar9300_default, |
| 2953 | &ar9300_x112, |
| 2954 | &ar9300_h116, |
| 2955 | &ar9300_h112, |
| 2956 | &ar9300_x113, |
| 2957 | }; |
| 2958 | |
| 2959 | static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id) |
| 2960 | { |
| 2961 | #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0])) |
| 2962 | int it; |
| 2963 | |
| 2964 | for (it = 0; it < N_LOOP; it++) |
| 2965 | if (ar9300_eep_templates[it]->templateVersion == id) |
| 2966 | return ar9300_eep_templates[it]; |
| 2967 | return NULL; |
| 2968 | #undef N_LOOP |
| 2969 | } |
| 2970 | |
| 2971 | |
Luis R. Rodriguez | 824b185 | 2010-08-01 02:25:16 -0400 | [diff] [blame] | 2972 | static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) |
| 2973 | { |
| 2974 | if (fbin == AR9300_BCHAN_UNUSED) |
| 2975 | return fbin; |
| 2976 | |
| 2977 | return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); |
| 2978 | } |
| 2979 | |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 2980 | static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah) |
| 2981 | { |
| 2982 | return 0; |
| 2983 | } |
| 2984 | |
Vasanthakumar Thiagarajan | bc20680 | 2010-11-10 05:03:14 -0800 | [diff] [blame] | 2985 | static int interpolate(int x, int xa, int xb, int ya, int yb) |
| 2986 | { |
| 2987 | int bf, factor, plus; |
| 2988 | |
| 2989 | bf = 2 * (yb - ya) * (x - xa) / (xb - xa); |
| 2990 | factor = bf / 2; |
| 2991 | plus = bf % 2; |
| 2992 | return ya + factor + plus; |
| 2993 | } |
| 2994 | |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 2995 | static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, |
| 2996 | enum eeprom_param param) |
| 2997 | { |
| 2998 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
| 2999 | struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; |
| 3000 | |
| 3001 | switch (param) { |
| 3002 | case EEP_MAC_LSW: |
| 3003 | return eep->macAddr[0] << 8 | eep->macAddr[1]; |
| 3004 | case EEP_MAC_MID: |
| 3005 | return eep->macAddr[2] << 8 | eep->macAddr[3]; |
| 3006 | case EEP_MAC_MSW: |
| 3007 | return eep->macAddr[4] << 8 | eep->macAddr[5]; |
| 3008 | case EEP_REG_0: |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3009 | return le16_to_cpu(pBase->regDmn[0]); |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3010 | case EEP_REG_1: |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3011 | return le16_to_cpu(pBase->regDmn[1]); |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3012 | case EEP_OP_CAP: |
| 3013 | return pBase->deviceCap; |
| 3014 | case EEP_OP_MODE: |
| 3015 | return pBase->opCapFlags.opFlags; |
| 3016 | case EEP_RF_SILENT: |
| 3017 | return pBase->rfSilent; |
| 3018 | case EEP_TX_MASK: |
| 3019 | return (pBase->txrxMask >> 4) & 0xf; |
| 3020 | case EEP_RX_MASK: |
| 3021 | return pBase->txrxMask & 0xf; |
| 3022 | case EEP_DRIVE_STRENGTH: |
| 3023 | #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1 |
| 3024 | return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH; |
| 3025 | case EEP_INTERNAL_REGULATOR: |
| 3026 | /* Bit 4 is internal regulator flag */ |
| 3027 | return (pBase->featureEnable & 0x10) >> 4; |
| 3028 | case EEP_SWREG: |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3029 | return le32_to_cpu(pBase->swreg); |
Felix Fietkau | 4935250 | 2010-06-12 00:33:59 -0400 | [diff] [blame] | 3030 | case EEP_PAPRD: |
| 3031 | return !!(pBase->featureEnable & BIT(5)); |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3032 | default: |
| 3033 | return 0; |
| 3034 | } |
| 3035 | } |
| 3036 | |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3037 | static bool ar9300_eeprom_read_byte(struct ath_common *common, int address, |
| 3038 | u8 *buffer) |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3039 | { |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3040 | u16 val; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3041 | |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3042 | if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val))) |
| 3043 | return false; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3044 | |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3045 | *buffer = (val >> (8 * (address % 2))) & 0xff; |
| 3046 | return true; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3047 | } |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3048 | |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3049 | static bool ar9300_eeprom_read_word(struct ath_common *common, int address, |
| 3050 | u8 *buffer) |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3051 | { |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3052 | u16 val; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3053 | |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3054 | if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val))) |
| 3055 | return false; |
| 3056 | |
| 3057 | buffer[0] = val >> 8; |
| 3058 | buffer[1] = val & 0xff; |
| 3059 | |
| 3060 | return true; |
| 3061 | } |
| 3062 | |
| 3063 | static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer, |
| 3064 | int count) |
| 3065 | { |
| 3066 | struct ath_common *common = ath9k_hw_common(ah); |
| 3067 | int i; |
| 3068 | |
| 3069 | if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) { |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3070 | ath_print(common, ATH_DBG_EEPROM, |
| 3071 | "eeprom address not in range\n"); |
| 3072 | return false; |
| 3073 | } |
| 3074 | |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3075 | /* |
| 3076 | * Since we're reading the bytes in reverse order from a little-endian |
| 3077 | * word stream, an even address means we only use the lower half of |
| 3078 | * the 16-bit word at that address |
| 3079 | */ |
| 3080 | if (address % 2 == 0) { |
| 3081 | if (!ar9300_eeprom_read_byte(common, address--, buffer++)) |
| 3082 | goto error; |
| 3083 | |
| 3084 | count--; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3085 | } |
| 3086 | |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3087 | for (i = 0; i < count / 2; i++) { |
| 3088 | if (!ar9300_eeprom_read_word(common, address, buffer)) |
| 3089 | goto error; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3090 | |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3091 | address -= 2; |
| 3092 | buffer += 2; |
| 3093 | } |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3094 | |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3095 | if (count % 2) |
| 3096 | if (!ar9300_eeprom_read_byte(common, address, buffer)) |
| 3097 | goto error; |
| 3098 | |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3099 | return true; |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3100 | |
| 3101 | error: |
| 3102 | ath_print(common, ATH_DBG_EEPROM, |
| 3103 | "unable to read eeprom region at offset %d\n", address); |
| 3104 | return false; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3105 | } |
| 3106 | |
| 3107 | static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference, |
| 3108 | int *length, int *major, int *minor) |
| 3109 | { |
| 3110 | unsigned long value[4]; |
| 3111 | |
| 3112 | value[0] = best[0]; |
| 3113 | value[1] = best[1]; |
| 3114 | value[2] = best[2]; |
| 3115 | value[3] = best[3]; |
| 3116 | *code = ((value[0] >> 5) & 0x0007); |
| 3117 | *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020); |
| 3118 | *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f); |
| 3119 | *major = (value[2] & 0x000f); |
| 3120 | *minor = (value[3] & 0x00ff); |
| 3121 | } |
| 3122 | |
| 3123 | static u16 ar9300_comp_cksum(u8 *data, int dsize) |
| 3124 | { |
| 3125 | int it, checksum = 0; |
| 3126 | |
| 3127 | for (it = 0; it < dsize; it++) { |
| 3128 | checksum += data[it]; |
| 3129 | checksum &= 0xffff; |
| 3130 | } |
| 3131 | |
| 3132 | return checksum; |
| 3133 | } |
| 3134 | |
| 3135 | static bool ar9300_uncompress_block(struct ath_hw *ah, |
| 3136 | u8 *mptr, |
| 3137 | int mdataSize, |
| 3138 | u8 *block, |
| 3139 | int size) |
| 3140 | { |
| 3141 | int it; |
| 3142 | int spot; |
| 3143 | int offset; |
| 3144 | int length; |
| 3145 | struct ath_common *common = ath9k_hw_common(ah); |
| 3146 | |
| 3147 | spot = 0; |
| 3148 | |
| 3149 | for (it = 0; it < size; it += (length+2)) { |
| 3150 | offset = block[it]; |
| 3151 | offset &= 0xff; |
| 3152 | spot += offset; |
| 3153 | length = block[it+1]; |
| 3154 | length &= 0xff; |
| 3155 | |
Luis R. Rodriguez | 803288e | 2010-08-30 19:26:32 -0400 | [diff] [blame] | 3156 | if (length > 0 && spot >= 0 && spot+length <= mdataSize) { |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3157 | ath_print(common, ATH_DBG_EEPROM, |
| 3158 | "Restore at %d: spot=%d " |
| 3159 | "offset=%d length=%d\n", |
| 3160 | it, spot, offset, length); |
| 3161 | memcpy(&mptr[spot], &block[it+2], length); |
| 3162 | spot += length; |
| 3163 | } else if (length > 0) { |
| 3164 | ath_print(common, ATH_DBG_EEPROM, |
| 3165 | "Bad restore at %d: spot=%d " |
| 3166 | "offset=%d length=%d\n", |
| 3167 | it, spot, offset, length); |
| 3168 | return false; |
| 3169 | } |
| 3170 | } |
| 3171 | return true; |
| 3172 | } |
| 3173 | |
| 3174 | static int ar9300_compress_decision(struct ath_hw *ah, |
| 3175 | int it, |
| 3176 | int code, |
| 3177 | int reference, |
| 3178 | u8 *mptr, |
| 3179 | u8 *word, int length, int mdata_size) |
| 3180 | { |
| 3181 | struct ath_common *common = ath9k_hw_common(ah); |
| 3182 | u8 *dptr; |
Senthil Balasubramanian | 3092354 | 2010-11-10 05:03:10 -0800 | [diff] [blame] | 3183 | const struct ar9300_eeprom *eep = NULL; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3184 | |
| 3185 | switch (code) { |
| 3186 | case _CompressNone: |
| 3187 | if (length != mdata_size) { |
| 3188 | ath_print(common, ATH_DBG_EEPROM, |
| 3189 | "EEPROM structure size mismatch" |
| 3190 | "memory=%d eeprom=%d\n", mdata_size, length); |
| 3191 | return -1; |
| 3192 | } |
| 3193 | memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length); |
| 3194 | ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:" |
| 3195 | " uncompressed, length %d\n", it, length); |
| 3196 | break; |
| 3197 | case _CompressBlock: |
| 3198 | if (reference == 0) { |
| 3199 | dptr = mptr; |
| 3200 | } else { |
Senthil Balasubramanian | 3092354 | 2010-11-10 05:03:10 -0800 | [diff] [blame] | 3201 | eep = ar9003_eeprom_struct_find_by_id(reference); |
| 3202 | if (eep == NULL) { |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3203 | ath_print(common, ATH_DBG_EEPROM, |
| 3204 | "cant find reference eeprom" |
| 3205 | "struct %d\n", reference); |
| 3206 | return -1; |
| 3207 | } |
Senthil Balasubramanian | 3092354 | 2010-11-10 05:03:10 -0800 | [diff] [blame] | 3208 | memcpy(mptr, eep, mdata_size); |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3209 | } |
| 3210 | ath_print(common, ATH_DBG_EEPROM, |
| 3211 | "restore eeprom %d: block, reference %d," |
| 3212 | " length %d\n", it, reference, length); |
| 3213 | ar9300_uncompress_block(ah, mptr, mdata_size, |
| 3214 | (u8 *) (word + COMP_HDR_LEN), length); |
| 3215 | break; |
| 3216 | default: |
| 3217 | ath_print(common, ATH_DBG_EEPROM, "unknown compression" |
| 3218 | " code %d\n", code); |
| 3219 | return -1; |
| 3220 | } |
| 3221 | return 0; |
| 3222 | } |
| 3223 | |
| 3224 | /* |
| 3225 | * Read the configuration data from the eeprom. |
| 3226 | * The data can be put in any specified memory buffer. |
| 3227 | * |
| 3228 | * Returns -1 on error. |
| 3229 | * Returns address of next memory location on success. |
| 3230 | */ |
| 3231 | static int ar9300_eeprom_restore_internal(struct ath_hw *ah, |
| 3232 | u8 *mptr, int mdata_size) |
| 3233 | { |
| 3234 | #define MDEFAULT 15 |
| 3235 | #define MSTATE 100 |
| 3236 | int cptr; |
| 3237 | u8 *word; |
| 3238 | int code; |
| 3239 | int reference, length, major, minor; |
| 3240 | int osize; |
| 3241 | int it; |
| 3242 | u16 checksum, mchecksum; |
| 3243 | struct ath_common *common = ath9k_hw_common(ah); |
| 3244 | |
| 3245 | word = kzalloc(2048, GFP_KERNEL); |
| 3246 | if (!word) |
| 3247 | return -1; |
| 3248 | |
| 3249 | memcpy(mptr, &ar9300_default, mdata_size); |
| 3250 | |
| 3251 | cptr = AR9300_BASE_ADDR; |
| 3252 | for (it = 0; it < MSTATE; it++) { |
| 3253 | if (!ar9300_read_eeprom(ah, cptr, word, COMP_HDR_LEN)) |
| 3254 | goto fail; |
| 3255 | |
| 3256 | if ((word[0] == 0 && word[1] == 0 && word[2] == 0 && |
| 3257 | word[3] == 0) || (word[0] == 0xff && word[1] == 0xff |
| 3258 | && word[2] == 0xff && word[3] == 0xff)) |
| 3259 | break; |
| 3260 | |
| 3261 | ar9300_comp_hdr_unpack(word, &code, &reference, |
| 3262 | &length, &major, &minor); |
| 3263 | ath_print(common, ATH_DBG_EEPROM, |
| 3264 | "Found block at %x: code=%d ref=%d" |
| 3265 | "length=%d major=%d minor=%d\n", cptr, code, |
| 3266 | reference, length, major, minor); |
| 3267 | if (length >= 1024) { |
| 3268 | ath_print(common, ATH_DBG_EEPROM, |
| 3269 | "Skipping bad header\n"); |
| 3270 | cptr -= COMP_HDR_LEN; |
| 3271 | continue; |
| 3272 | } |
| 3273 | |
| 3274 | osize = length; |
| 3275 | ar9300_read_eeprom(ah, cptr, word, |
| 3276 | COMP_HDR_LEN + osize + COMP_CKSUM_LEN); |
| 3277 | checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length); |
| 3278 | mchecksum = word[COMP_HDR_LEN + osize] | |
| 3279 | (word[COMP_HDR_LEN + osize + 1] << 8); |
| 3280 | ath_print(common, ATH_DBG_EEPROM, |
| 3281 | "checksum %x %x\n", checksum, mchecksum); |
| 3282 | if (checksum == mchecksum) { |
| 3283 | ar9300_compress_decision(ah, it, code, reference, mptr, |
| 3284 | word, length, mdata_size); |
| 3285 | } else { |
| 3286 | ath_print(common, ATH_DBG_EEPROM, |
| 3287 | "skipping block with bad checksum\n"); |
| 3288 | } |
| 3289 | cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN); |
| 3290 | } |
| 3291 | |
| 3292 | kfree(word); |
| 3293 | return cptr; |
| 3294 | |
| 3295 | fail: |
| 3296 | kfree(word); |
| 3297 | return -1; |
| 3298 | } |
| 3299 | |
| 3300 | /* |
| 3301 | * Restore the configuration structure by reading the eeprom. |
| 3302 | * This function destroys any existing in-memory structure |
| 3303 | * content. |
| 3304 | */ |
| 3305 | static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah) |
| 3306 | { |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3307 | u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3308 | |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3309 | if (ar9300_eeprom_restore_internal(ah, mptr, |
| 3310 | sizeof(struct ar9300_eeprom)) < 0) |
| 3311 | return false; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3312 | |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3313 | return true; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3314 | } |
| 3315 | |
| 3316 | /* XXX: review hardware docs */ |
| 3317 | static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah) |
| 3318 | { |
| 3319 | return ah->eeprom.ar9300_eep.eepromVersion; |
| 3320 | } |
| 3321 | |
| 3322 | /* XXX: could be read from the eepromVersion, not sure yet */ |
| 3323 | static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah) |
| 3324 | { |
| 3325 | return 0; |
| 3326 | } |
| 3327 | |
| 3328 | static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah, |
Rajkumar Manoharan | f799a30 | 2010-09-16 11:40:06 +0530 | [diff] [blame] | 3329 | enum ath9k_hal_freq_band freq_band) |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3330 | { |
| 3331 | return 1; |
| 3332 | } |
| 3333 | |
Felix Fietkau | 601e0cb | 2010-07-11 12:48:39 +0200 | [diff] [blame] | 3334 | static u32 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah, |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3335 | struct ath9k_channel *chan) |
| 3336 | { |
| 3337 | return -EINVAL; |
| 3338 | } |
| 3339 | |
| 3340 | static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz) |
| 3341 | { |
| 3342 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
| 3343 | |
| 3344 | if (is2ghz) |
| 3345 | return eep->modalHeader2G.xpaBiasLvl; |
| 3346 | else |
| 3347 | return eep->modalHeader5G.xpaBiasLvl; |
| 3348 | } |
| 3349 | |
| 3350 | static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) |
| 3351 | { |
| 3352 | int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz); |
Vasanthakumar Thiagarajan | 52a0e24 | 2010-11-10 05:03:11 -0800 | [diff] [blame] | 3353 | REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); |
| 3354 | REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB, bias >> 2); |
| 3355 | REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1); |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3356 | } |
| 3357 | |
| 3358 | static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz) |
| 3359 | { |
| 3360 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3361 | __le32 val; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3362 | |
| 3363 | if (is2ghz) |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3364 | val = eep->modalHeader2G.antCtrlCommon; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3365 | else |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3366 | val = eep->modalHeader5G.antCtrlCommon; |
| 3367 | return le32_to_cpu(val); |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3368 | } |
| 3369 | |
| 3370 | static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz) |
| 3371 | { |
| 3372 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3373 | __le32 val; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3374 | |
| 3375 | if (is2ghz) |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3376 | val = eep->modalHeader2G.antCtrlCommon2; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3377 | else |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3378 | val = eep->modalHeader5G.antCtrlCommon2; |
| 3379 | return le32_to_cpu(val); |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3380 | } |
| 3381 | |
| 3382 | static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, |
| 3383 | int chain, |
| 3384 | bool is2ghz) |
| 3385 | { |
| 3386 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3387 | __le16 val = 0; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3388 | |
| 3389 | if (chain >= 0 && chain < AR9300_MAX_CHAINS) { |
| 3390 | if (is2ghz) |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3391 | val = eep->modalHeader2G.antCtrlChain[chain]; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3392 | else |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3393 | val = eep->modalHeader5G.antCtrlChain[chain]; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3394 | } |
| 3395 | |
Felix Fietkau | ffdc4cb | 2010-05-11 17:23:03 +0200 | [diff] [blame] | 3396 | return le16_to_cpu(val); |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3397 | } |
| 3398 | |
| 3399 | static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) |
| 3400 | { |
| 3401 | u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz); |
| 3402 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value); |
| 3403 | |
| 3404 | value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz); |
| 3405 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value); |
| 3406 | |
| 3407 | value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz); |
| 3408 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value); |
| 3409 | |
| 3410 | value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz); |
| 3411 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value); |
| 3412 | |
| 3413 | value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz); |
| 3414 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value); |
| 3415 | } |
| 3416 | |
| 3417 | static void ar9003_hw_drive_strength_apply(struct ath_hw *ah) |
| 3418 | { |
| 3419 | int drive_strength; |
| 3420 | unsigned long reg; |
| 3421 | |
| 3422 | drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH); |
| 3423 | |
| 3424 | if (!drive_strength) |
| 3425 | return; |
| 3426 | |
| 3427 | reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1); |
| 3428 | reg &= ~0x00ffffc0; |
| 3429 | reg |= 0x5 << 21; |
| 3430 | reg |= 0x5 << 18; |
| 3431 | reg |= 0x5 << 15; |
| 3432 | reg |= 0x5 << 12; |
| 3433 | reg |= 0x5 << 9; |
| 3434 | reg |= 0x5 << 6; |
| 3435 | REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg); |
| 3436 | |
| 3437 | reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2); |
| 3438 | reg &= ~0xffffffe0; |
| 3439 | reg |= 0x5 << 29; |
| 3440 | reg |= 0x5 << 26; |
| 3441 | reg |= 0x5 << 23; |
| 3442 | reg |= 0x5 << 20; |
| 3443 | reg |= 0x5 << 17; |
| 3444 | reg |= 0x5 << 14; |
| 3445 | reg |= 0x5 << 11; |
| 3446 | reg |= 0x5 << 8; |
| 3447 | reg |= 0x5 << 5; |
| 3448 | REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg); |
| 3449 | |
| 3450 | reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4); |
| 3451 | reg &= ~0xff800000; |
| 3452 | reg |= 0x5 << 29; |
| 3453 | reg |= 0x5 << 26; |
| 3454 | reg |= 0x5 << 23; |
| 3455 | REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg); |
| 3456 | } |
| 3457 | |
Vasanthakumar Thiagarajan | f4475a6 | 2010-11-10 05:03:12 -0800 | [diff] [blame] | 3458 | static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain, |
| 3459 | struct ath9k_channel *chan) |
| 3460 | { |
| 3461 | int f[3], t[3]; |
| 3462 | u16 value; |
| 3463 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
| 3464 | |
| 3465 | if (chain >= 0 && chain < 3) { |
| 3466 | if (IS_CHAN_2GHZ(chan)) |
| 3467 | return eep->modalHeader2G.xatten1DB[chain]; |
| 3468 | else if (eep->base_ext2.xatten1DBLow[chain] != 0) { |
| 3469 | t[0] = eep->base_ext2.xatten1DBLow[chain]; |
| 3470 | f[0] = 5180; |
| 3471 | t[1] = eep->modalHeader5G.xatten1DB[chain]; |
| 3472 | f[1] = 5500; |
| 3473 | t[2] = eep->base_ext2.xatten1DBHigh[chain]; |
| 3474 | f[2] = 5785; |
| 3475 | value = ar9003_hw_power_interpolate((s32) chan->channel, |
| 3476 | f, t, 3); |
| 3477 | return value; |
| 3478 | } else |
| 3479 | return eep->modalHeader5G.xatten1DB[chain]; |
| 3480 | } |
| 3481 | |
| 3482 | return 0; |
| 3483 | } |
| 3484 | |
| 3485 | |
| 3486 | static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain, |
| 3487 | struct ath9k_channel *chan) |
| 3488 | { |
| 3489 | int f[3], t[3]; |
| 3490 | u16 value; |
| 3491 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
| 3492 | |
| 3493 | if (chain >= 0 && chain < 3) { |
| 3494 | if (IS_CHAN_2GHZ(chan)) |
| 3495 | return eep->modalHeader2G.xatten1Margin[chain]; |
| 3496 | else if (eep->base_ext2.xatten1MarginLow[chain] != 0) { |
| 3497 | t[0] = eep->base_ext2.xatten1MarginLow[chain]; |
| 3498 | f[0] = 5180; |
| 3499 | t[1] = eep->modalHeader5G.xatten1Margin[chain]; |
| 3500 | f[1] = 5500; |
| 3501 | t[2] = eep->base_ext2.xatten1MarginHigh[chain]; |
| 3502 | f[2] = 5785; |
| 3503 | value = ar9003_hw_power_interpolate((s32) chan->channel, |
| 3504 | f, t, 3); |
| 3505 | return value; |
| 3506 | } else |
| 3507 | return eep->modalHeader5G.xatten1Margin[chain]; |
| 3508 | } |
| 3509 | |
| 3510 | return 0; |
| 3511 | } |
| 3512 | |
| 3513 | static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan) |
| 3514 | { |
| 3515 | int i; |
| 3516 | u16 value; |
| 3517 | unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0, |
| 3518 | AR_PHY_EXT_ATTEN_CTL_1, |
| 3519 | AR_PHY_EXT_ATTEN_CTL_2, |
| 3520 | }; |
| 3521 | |
| 3522 | /* Test value. if 0 then attenuation is unused. Don't load anything. */ |
| 3523 | for (i = 0; i < 3; i++) { |
| 3524 | value = ar9003_hw_atten_chain_get(ah, i, chan); |
| 3525 | REG_RMW_FIELD(ah, ext_atten_reg[i], |
| 3526 | AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value); |
| 3527 | |
| 3528 | value = ar9003_hw_atten_chain_get_margin(ah, i, chan); |
| 3529 | REG_RMW_FIELD(ah, ext_atten_reg[i], |
| 3530 | AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, value); |
| 3531 | } |
| 3532 | } |
| 3533 | |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3534 | static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) |
| 3535 | { |
| 3536 | int internal_regulator = |
| 3537 | ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR); |
| 3538 | |
| 3539 | if (internal_regulator) { |
| 3540 | /* Internal regulator is ON. Write swreg register. */ |
| 3541 | int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG); |
| 3542 | REG_WRITE(ah, AR_RTC_REG_CONTROL1, |
| 3543 | REG_READ(ah, AR_RTC_REG_CONTROL1) & |
| 3544 | (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM)); |
| 3545 | REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg); |
| 3546 | /* Set REG_CONTROL1.SWREG_PROGRAM */ |
| 3547 | REG_WRITE(ah, AR_RTC_REG_CONTROL1, |
| 3548 | REG_READ(ah, |
| 3549 | AR_RTC_REG_CONTROL1) | |
| 3550 | AR_RTC_REG_CONTROL1_SWREG_PROGRAM); |
| 3551 | } else { |
| 3552 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, |
| 3553 | (REG_READ(ah, |
| 3554 | AR_RTC_SLEEP_CLK) | |
| 3555 | AR_RTC_FORCE_SWREG_PRD)); |
| 3556 | } |
| 3557 | } |
| 3558 | |
| 3559 | static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, |
| 3560 | struct ath9k_channel *chan) |
| 3561 | { |
| 3562 | ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan)); |
| 3563 | ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan)); |
| 3564 | ar9003_hw_drive_strength_apply(ah); |
Vasanthakumar Thiagarajan | f4475a6 | 2010-11-10 05:03:12 -0800 | [diff] [blame] | 3565 | ar9003_hw_atten_apply(ah, chan); |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3566 | ar9003_hw_internal_regulator_apply(ah); |
| 3567 | } |
| 3568 | |
| 3569 | static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah, |
| 3570 | struct ath9k_channel *chan) |
| 3571 | { |
| 3572 | } |
| 3573 | |
| 3574 | /* |
| 3575 | * Returns the interpolated y value corresponding to the specified x value |
| 3576 | * from the np ordered pairs of data (px,py). |
| 3577 | * The pairs do not have to be in any order. |
| 3578 | * If the specified x value is less than any of the px, |
| 3579 | * the returned y value is equal to the py for the lowest px. |
| 3580 | * If the specified x value is greater than any of the px, |
| 3581 | * the returned y value is equal to the py for the highest px. |
| 3582 | */ |
| 3583 | static int ar9003_hw_power_interpolate(int32_t x, |
| 3584 | int32_t *px, int32_t *py, u_int16_t np) |
| 3585 | { |
| 3586 | int ip = 0; |
| 3587 | int lx = 0, ly = 0, lhave = 0; |
| 3588 | int hx = 0, hy = 0, hhave = 0; |
| 3589 | int dx = 0; |
| 3590 | int y = 0; |
| 3591 | |
| 3592 | lhave = 0; |
| 3593 | hhave = 0; |
| 3594 | |
| 3595 | /* identify best lower and higher x calibration measurement */ |
| 3596 | for (ip = 0; ip < np; ip++) { |
| 3597 | dx = x - px[ip]; |
| 3598 | |
| 3599 | /* this measurement is higher than our desired x */ |
| 3600 | if (dx <= 0) { |
| 3601 | if (!hhave || dx > (x - hx)) { |
| 3602 | /* new best higher x measurement */ |
| 3603 | hx = px[ip]; |
| 3604 | hy = py[ip]; |
| 3605 | hhave = 1; |
| 3606 | } |
| 3607 | } |
| 3608 | /* this measurement is lower than our desired x */ |
| 3609 | if (dx >= 0) { |
| 3610 | if (!lhave || dx < (x - lx)) { |
| 3611 | /* new best lower x measurement */ |
| 3612 | lx = px[ip]; |
| 3613 | ly = py[ip]; |
| 3614 | lhave = 1; |
| 3615 | } |
| 3616 | } |
| 3617 | } |
| 3618 | |
| 3619 | /* the low x is good */ |
| 3620 | if (lhave) { |
| 3621 | /* so is the high x */ |
| 3622 | if (hhave) { |
| 3623 | /* they're the same, so just pick one */ |
| 3624 | if (hx == lx) |
| 3625 | y = ly; |
| 3626 | else /* interpolate */ |
Vasanthakumar Thiagarajan | bc20680 | 2010-11-10 05:03:14 -0800 | [diff] [blame] | 3627 | y = interpolate(x, lx, hx, ly, hy); |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3628 | } else /* only low is good, use it */ |
| 3629 | y = ly; |
| 3630 | } else if (hhave) /* only high is good, use it */ |
| 3631 | y = hy; |
| 3632 | else /* nothing is good,this should never happen unless np=0, ???? */ |
| 3633 | y = -(1 << 30); |
| 3634 | return y; |
| 3635 | } |
| 3636 | |
| 3637 | static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah, |
| 3638 | u16 rateIndex, u16 freq, bool is2GHz) |
| 3639 | { |
| 3640 | u16 numPiers, i; |
| 3641 | s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS]; |
| 3642 | s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS]; |
| 3643 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
| 3644 | struct cal_tgt_pow_legacy *pEepromTargetPwr; |
| 3645 | u8 *pFreqBin; |
| 3646 | |
| 3647 | if (is2GHz) { |
Felix Fietkau | d10baf9 | 2010-04-26 15:04:38 -0400 | [diff] [blame] | 3648 | numPiers = AR9300_NUM_2G_20_TARGET_POWERS; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3649 | pEepromTargetPwr = eep->calTargetPower2G; |
| 3650 | pFreqBin = eep->calTarget_freqbin_2G; |
| 3651 | } else { |
| 3652 | numPiers = AR9300_NUM_5G_20_TARGET_POWERS; |
| 3653 | pEepromTargetPwr = eep->calTargetPower5G; |
| 3654 | pFreqBin = eep->calTarget_freqbin_5G; |
| 3655 | } |
| 3656 | |
| 3657 | /* |
| 3658 | * create array of channels and targetpower from |
| 3659 | * targetpower piers stored on eeprom |
| 3660 | */ |
| 3661 | for (i = 0; i < numPiers; i++) { |
| 3662 | freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz); |
| 3663 | targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; |
| 3664 | } |
| 3665 | |
| 3666 | /* interpolate to get target power for given frequency */ |
| 3667 | return (u8) ar9003_hw_power_interpolate((s32) freq, |
| 3668 | freqArray, |
| 3669 | targetPowerArray, numPiers); |
| 3670 | } |
| 3671 | |
| 3672 | static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah, |
| 3673 | u16 rateIndex, |
| 3674 | u16 freq, bool is2GHz) |
| 3675 | { |
| 3676 | u16 numPiers, i; |
| 3677 | s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS]; |
| 3678 | s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS]; |
| 3679 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
| 3680 | struct cal_tgt_pow_ht *pEepromTargetPwr; |
| 3681 | u8 *pFreqBin; |
| 3682 | |
| 3683 | if (is2GHz) { |
Felix Fietkau | d10baf9 | 2010-04-26 15:04:38 -0400 | [diff] [blame] | 3684 | numPiers = AR9300_NUM_2G_20_TARGET_POWERS; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3685 | pEepromTargetPwr = eep->calTargetPower2GHT20; |
| 3686 | pFreqBin = eep->calTarget_freqbin_2GHT20; |
| 3687 | } else { |
| 3688 | numPiers = AR9300_NUM_5G_20_TARGET_POWERS; |
| 3689 | pEepromTargetPwr = eep->calTargetPower5GHT20; |
| 3690 | pFreqBin = eep->calTarget_freqbin_5GHT20; |
| 3691 | } |
| 3692 | |
| 3693 | /* |
| 3694 | * create array of channels and targetpower |
| 3695 | * from targetpower piers stored on eeprom |
| 3696 | */ |
| 3697 | for (i = 0; i < numPiers; i++) { |
| 3698 | freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz); |
| 3699 | targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; |
| 3700 | } |
| 3701 | |
| 3702 | /* interpolate to get target power for given frequency */ |
| 3703 | return (u8) ar9003_hw_power_interpolate((s32) freq, |
| 3704 | freqArray, |
| 3705 | targetPowerArray, numPiers); |
| 3706 | } |
| 3707 | |
| 3708 | static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah, |
| 3709 | u16 rateIndex, |
| 3710 | u16 freq, bool is2GHz) |
| 3711 | { |
| 3712 | u16 numPiers, i; |
| 3713 | s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS]; |
| 3714 | s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS]; |
| 3715 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
| 3716 | struct cal_tgt_pow_ht *pEepromTargetPwr; |
| 3717 | u8 *pFreqBin; |
| 3718 | |
| 3719 | if (is2GHz) { |
| 3720 | numPiers = AR9300_NUM_2G_40_TARGET_POWERS; |
| 3721 | pEepromTargetPwr = eep->calTargetPower2GHT40; |
| 3722 | pFreqBin = eep->calTarget_freqbin_2GHT40; |
| 3723 | } else { |
| 3724 | numPiers = AR9300_NUM_5G_40_TARGET_POWERS; |
| 3725 | pEepromTargetPwr = eep->calTargetPower5GHT40; |
| 3726 | pFreqBin = eep->calTarget_freqbin_5GHT40; |
| 3727 | } |
| 3728 | |
| 3729 | /* |
| 3730 | * create array of channels and targetpower from |
| 3731 | * targetpower piers stored on eeprom |
| 3732 | */ |
| 3733 | for (i = 0; i < numPiers; i++) { |
| 3734 | freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz); |
| 3735 | targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; |
| 3736 | } |
| 3737 | |
| 3738 | /* interpolate to get target power for given frequency */ |
| 3739 | return (u8) ar9003_hw_power_interpolate((s32) freq, |
| 3740 | freqArray, |
| 3741 | targetPowerArray, numPiers); |
| 3742 | } |
| 3743 | |
| 3744 | static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah, |
| 3745 | u16 rateIndex, u16 freq) |
| 3746 | { |
| 3747 | u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i; |
| 3748 | s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS]; |
| 3749 | s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS]; |
| 3750 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
| 3751 | struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck; |
| 3752 | u8 *pFreqBin = eep->calTarget_freqbin_Cck; |
| 3753 | |
| 3754 | /* |
| 3755 | * create array of channels and targetpower from |
| 3756 | * targetpower piers stored on eeprom |
| 3757 | */ |
| 3758 | for (i = 0; i < numPiers; i++) { |
| 3759 | freqArray[i] = FBIN2FREQ(pFreqBin[i], 1); |
| 3760 | targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; |
| 3761 | } |
| 3762 | |
| 3763 | /* interpolate to get target power for given frequency */ |
| 3764 | return (u8) ar9003_hw_power_interpolate((s32) freq, |
| 3765 | freqArray, |
| 3766 | targetPowerArray, numPiers); |
| 3767 | } |
| 3768 | |
| 3769 | /* Set tx power registers to array of values passed in */ |
| 3770 | static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray) |
| 3771 | { |
| 3772 | #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) |
| 3773 | /* make sure forced gain is not set */ |
| 3774 | REG_WRITE(ah, 0xa458, 0); |
| 3775 | |
| 3776 | /* Write the OFDM power per rate set */ |
| 3777 | |
| 3778 | /* 6 (LSB), 9, 12, 18 (MSB) */ |
| 3779 | REG_WRITE(ah, 0xa3c0, |
| 3780 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) | |
| 3781 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) | |
| 3782 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) | |
| 3783 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0)); |
| 3784 | |
| 3785 | /* 24 (LSB), 36, 48, 54 (MSB) */ |
| 3786 | REG_WRITE(ah, 0xa3c4, |
| 3787 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) | |
| 3788 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) | |
| 3789 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) | |
| 3790 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0)); |
| 3791 | |
| 3792 | /* Write the CCK power per rate set */ |
| 3793 | |
| 3794 | /* 1L (LSB), reserved, 2L, 2S (MSB) */ |
| 3795 | REG_WRITE(ah, 0xa3c8, |
| 3796 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) | |
| 3797 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) | |
| 3798 | /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */ |
| 3799 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)); |
| 3800 | |
| 3801 | /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ |
| 3802 | REG_WRITE(ah, 0xa3cc, |
| 3803 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) | |
| 3804 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) | |
| 3805 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) | |
| 3806 | POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0) |
| 3807 | ); |
| 3808 | |
| 3809 | /* Write the HT20 power per rate set */ |
| 3810 | |
| 3811 | /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ |
| 3812 | REG_WRITE(ah, 0xa3d0, |
| 3813 | POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) | |
| 3814 | POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) | |
| 3815 | POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) | |
| 3816 | POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0) |
| 3817 | ); |
| 3818 | |
| 3819 | /* 6 (LSB), 7, 12, 13 (MSB) */ |
| 3820 | REG_WRITE(ah, 0xa3d4, |
| 3821 | POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) | |
| 3822 | POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) | |
| 3823 | POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) | |
| 3824 | POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0) |
| 3825 | ); |
| 3826 | |
| 3827 | /* 14 (LSB), 15, 20, 21 */ |
| 3828 | REG_WRITE(ah, 0xa3e4, |
| 3829 | POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) | |
| 3830 | POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) | |
| 3831 | POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) | |
| 3832 | POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0) |
| 3833 | ); |
| 3834 | |
| 3835 | /* Mixed HT20 and HT40 rates */ |
| 3836 | |
| 3837 | /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ |
| 3838 | REG_WRITE(ah, 0xa3e8, |
| 3839 | POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) | |
| 3840 | POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) | |
| 3841 | POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) | |
| 3842 | POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0) |
| 3843 | ); |
| 3844 | |
| 3845 | /* |
| 3846 | * Write the HT40 power per rate set |
| 3847 | * correct PAR difference between HT40 and HT20/LEGACY |
| 3848 | * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) |
| 3849 | */ |
| 3850 | REG_WRITE(ah, 0xa3d8, |
| 3851 | POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) | |
| 3852 | POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) | |
| 3853 | POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) | |
| 3854 | POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0) |
| 3855 | ); |
| 3856 | |
| 3857 | /* 6 (LSB), 7, 12, 13 (MSB) */ |
| 3858 | REG_WRITE(ah, 0xa3dc, |
| 3859 | POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) | |
| 3860 | POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) | |
| 3861 | POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) | |
| 3862 | POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0) |
| 3863 | ); |
| 3864 | |
| 3865 | /* 14 (LSB), 15, 20, 21 */ |
| 3866 | REG_WRITE(ah, 0xa3ec, |
| 3867 | POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) | |
| 3868 | POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) | |
| 3869 | POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) | |
| 3870 | POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0) |
| 3871 | ); |
| 3872 | |
| 3873 | return 0; |
| 3874 | #undef POW_SM |
| 3875 | } |
| 3876 | |
Luis R. Rodriguez | 824b185 | 2010-08-01 02:25:16 -0400 | [diff] [blame] | 3877 | static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq, |
| 3878 | u8 *targetPowerValT2) |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3879 | { |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 3880 | /* XXX: hard code for now, need to get from eeprom struct */ |
| 3881 | u8 ht40PowerIncForPdadc = 0; |
| 3882 | bool is2GHz = false; |
| 3883 | unsigned int i = 0; |
| 3884 | struct ath_common *common = ath9k_hw_common(ah); |
| 3885 | |
| 3886 | if (freq < 4000) |
| 3887 | is2GHz = true; |
| 3888 | |
| 3889 | targetPowerValT2[ALL_TARGET_LEGACY_6_24] = |
| 3890 | ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq, |
| 3891 | is2GHz); |
| 3892 | targetPowerValT2[ALL_TARGET_LEGACY_36] = |
| 3893 | ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq, |
| 3894 | is2GHz); |
| 3895 | targetPowerValT2[ALL_TARGET_LEGACY_48] = |
| 3896 | ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq, |
| 3897 | is2GHz); |
| 3898 | targetPowerValT2[ALL_TARGET_LEGACY_54] = |
| 3899 | ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq, |
| 3900 | is2GHz); |
| 3901 | targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] = |
| 3902 | ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L, |
| 3903 | freq); |
| 3904 | targetPowerValT2[ALL_TARGET_LEGACY_5S] = |
| 3905 | ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq); |
| 3906 | targetPowerValT2[ALL_TARGET_LEGACY_11L] = |
| 3907 | ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq); |
| 3908 | targetPowerValT2[ALL_TARGET_LEGACY_11S] = |
| 3909 | ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq); |
| 3910 | targetPowerValT2[ALL_TARGET_HT20_0_8_16] = |
| 3911 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq, |
| 3912 | is2GHz); |
| 3913 | targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] = |
| 3914 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19, |
| 3915 | freq, is2GHz); |
| 3916 | targetPowerValT2[ALL_TARGET_HT20_4] = |
| 3917 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq, |
| 3918 | is2GHz); |
| 3919 | targetPowerValT2[ALL_TARGET_HT20_5] = |
| 3920 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq, |
| 3921 | is2GHz); |
| 3922 | targetPowerValT2[ALL_TARGET_HT20_6] = |
| 3923 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq, |
| 3924 | is2GHz); |
| 3925 | targetPowerValT2[ALL_TARGET_HT20_7] = |
| 3926 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq, |
| 3927 | is2GHz); |
| 3928 | targetPowerValT2[ALL_TARGET_HT20_12] = |
| 3929 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq, |
| 3930 | is2GHz); |
| 3931 | targetPowerValT2[ALL_TARGET_HT20_13] = |
| 3932 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq, |
| 3933 | is2GHz); |
| 3934 | targetPowerValT2[ALL_TARGET_HT20_14] = |
| 3935 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq, |
| 3936 | is2GHz); |
| 3937 | targetPowerValT2[ALL_TARGET_HT20_15] = |
| 3938 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq, |
| 3939 | is2GHz); |
| 3940 | targetPowerValT2[ALL_TARGET_HT20_20] = |
| 3941 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq, |
| 3942 | is2GHz); |
| 3943 | targetPowerValT2[ALL_TARGET_HT20_21] = |
| 3944 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq, |
| 3945 | is2GHz); |
| 3946 | targetPowerValT2[ALL_TARGET_HT20_22] = |
| 3947 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq, |
| 3948 | is2GHz); |
| 3949 | targetPowerValT2[ALL_TARGET_HT20_23] = |
| 3950 | ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq, |
| 3951 | is2GHz); |
| 3952 | targetPowerValT2[ALL_TARGET_HT40_0_8_16] = |
| 3953 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq, |
| 3954 | is2GHz) + ht40PowerIncForPdadc; |
| 3955 | targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] = |
| 3956 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19, |
| 3957 | freq, |
| 3958 | is2GHz) + ht40PowerIncForPdadc; |
| 3959 | targetPowerValT2[ALL_TARGET_HT40_4] = |
| 3960 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq, |
| 3961 | is2GHz) + ht40PowerIncForPdadc; |
| 3962 | targetPowerValT2[ALL_TARGET_HT40_5] = |
| 3963 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq, |
| 3964 | is2GHz) + ht40PowerIncForPdadc; |
| 3965 | targetPowerValT2[ALL_TARGET_HT40_6] = |
| 3966 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq, |
| 3967 | is2GHz) + ht40PowerIncForPdadc; |
| 3968 | targetPowerValT2[ALL_TARGET_HT40_7] = |
| 3969 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq, |
| 3970 | is2GHz) + ht40PowerIncForPdadc; |
| 3971 | targetPowerValT2[ALL_TARGET_HT40_12] = |
| 3972 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq, |
| 3973 | is2GHz) + ht40PowerIncForPdadc; |
| 3974 | targetPowerValT2[ALL_TARGET_HT40_13] = |
| 3975 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq, |
| 3976 | is2GHz) + ht40PowerIncForPdadc; |
| 3977 | targetPowerValT2[ALL_TARGET_HT40_14] = |
| 3978 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq, |
| 3979 | is2GHz) + ht40PowerIncForPdadc; |
| 3980 | targetPowerValT2[ALL_TARGET_HT40_15] = |
| 3981 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq, |
| 3982 | is2GHz) + ht40PowerIncForPdadc; |
| 3983 | targetPowerValT2[ALL_TARGET_HT40_20] = |
| 3984 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq, |
| 3985 | is2GHz) + ht40PowerIncForPdadc; |
| 3986 | targetPowerValT2[ALL_TARGET_HT40_21] = |
| 3987 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq, |
| 3988 | is2GHz) + ht40PowerIncForPdadc; |
| 3989 | targetPowerValT2[ALL_TARGET_HT40_22] = |
| 3990 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq, |
| 3991 | is2GHz) + ht40PowerIncForPdadc; |
| 3992 | targetPowerValT2[ALL_TARGET_HT40_23] = |
| 3993 | ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq, |
| 3994 | is2GHz) + ht40PowerIncForPdadc; |
| 3995 | |
| 3996 | while (i < ar9300RateSize) { |
| 3997 | ath_print(common, ATH_DBG_EEPROM, |
| 3998 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); |
| 3999 | i++; |
| 4000 | |
| 4001 | ath_print(common, ATH_DBG_EEPROM, |
| 4002 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); |
| 4003 | i++; |
| 4004 | |
| 4005 | ath_print(common, ATH_DBG_EEPROM, |
| 4006 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); |
| 4007 | i++; |
| 4008 | |
| 4009 | ath_print(common, ATH_DBG_EEPROM, |
| 4010 | "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]); |
| 4011 | i++; |
| 4012 | } |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 4013 | } |
| 4014 | |
| 4015 | static int ar9003_hw_cal_pier_get(struct ath_hw *ah, |
| 4016 | int mode, |
| 4017 | int ipier, |
| 4018 | int ichain, |
| 4019 | int *pfrequency, |
| 4020 | int *pcorrection, |
| 4021 | int *ptemperature, int *pvoltage) |
| 4022 | { |
| 4023 | u8 *pCalPier; |
| 4024 | struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct; |
| 4025 | int is2GHz; |
| 4026 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
| 4027 | struct ath_common *common = ath9k_hw_common(ah); |
| 4028 | |
| 4029 | if (ichain >= AR9300_MAX_CHAINS) { |
| 4030 | ath_print(common, ATH_DBG_EEPROM, |
| 4031 | "Invalid chain index, must be less than %d\n", |
| 4032 | AR9300_MAX_CHAINS); |
| 4033 | return -1; |
| 4034 | } |
| 4035 | |
| 4036 | if (mode) { /* 5GHz */ |
| 4037 | if (ipier >= AR9300_NUM_5G_CAL_PIERS) { |
| 4038 | ath_print(common, ATH_DBG_EEPROM, |
| 4039 | "Invalid 5GHz cal pier index, must " |
| 4040 | "be less than %d\n", |
| 4041 | AR9300_NUM_5G_CAL_PIERS); |
| 4042 | return -1; |
| 4043 | } |
| 4044 | pCalPier = &(eep->calFreqPier5G[ipier]); |
| 4045 | pCalPierStruct = &(eep->calPierData5G[ichain][ipier]); |
| 4046 | is2GHz = 0; |
| 4047 | } else { |
| 4048 | if (ipier >= AR9300_NUM_2G_CAL_PIERS) { |
| 4049 | ath_print(common, ATH_DBG_EEPROM, |
| 4050 | "Invalid 2GHz cal pier index, must " |
| 4051 | "be less than %d\n", AR9300_NUM_2G_CAL_PIERS); |
| 4052 | return -1; |
| 4053 | } |
| 4054 | |
| 4055 | pCalPier = &(eep->calFreqPier2G[ipier]); |
| 4056 | pCalPierStruct = &(eep->calPierData2G[ichain][ipier]); |
| 4057 | is2GHz = 1; |
| 4058 | } |
| 4059 | |
| 4060 | *pfrequency = FBIN2FREQ(*pCalPier, is2GHz); |
| 4061 | *pcorrection = pCalPierStruct->refPower; |
| 4062 | *ptemperature = pCalPierStruct->tempMeas; |
| 4063 | *pvoltage = pCalPierStruct->voltMeas; |
| 4064 | |
| 4065 | return 0; |
| 4066 | } |
| 4067 | |
| 4068 | static int ar9003_hw_power_control_override(struct ath_hw *ah, |
| 4069 | int frequency, |
| 4070 | int *correction, |
| 4071 | int *voltage, int *temperature) |
| 4072 | { |
| 4073 | int tempSlope = 0; |
| 4074 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
Vasanthakumar Thiagarajan | 15cbbc4 | 2010-11-10 05:03:13 -0800 | [diff] [blame] | 4075 | int f[3], t[3]; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 4076 | |
| 4077 | REG_RMW(ah, AR_PHY_TPC_11_B0, |
| 4078 | (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), |
| 4079 | AR_PHY_TPC_OLPC_GAIN_DELTA); |
| 4080 | REG_RMW(ah, AR_PHY_TPC_11_B1, |
| 4081 | (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), |
| 4082 | AR_PHY_TPC_OLPC_GAIN_DELTA); |
| 4083 | REG_RMW(ah, AR_PHY_TPC_11_B2, |
| 4084 | (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), |
| 4085 | AR_PHY_TPC_OLPC_GAIN_DELTA); |
| 4086 | |
| 4087 | /* enable open loop power control on chip */ |
| 4088 | REG_RMW(ah, AR_PHY_TPC_6_B0, |
| 4089 | (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), |
| 4090 | AR_PHY_TPC_6_ERROR_EST_MODE); |
| 4091 | REG_RMW(ah, AR_PHY_TPC_6_B1, |
| 4092 | (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), |
| 4093 | AR_PHY_TPC_6_ERROR_EST_MODE); |
| 4094 | REG_RMW(ah, AR_PHY_TPC_6_B2, |
| 4095 | (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), |
| 4096 | AR_PHY_TPC_6_ERROR_EST_MODE); |
| 4097 | |
| 4098 | /* |
| 4099 | * enable temperature compensation |
| 4100 | * Need to use register names |
| 4101 | */ |
| 4102 | if (frequency < 4000) |
| 4103 | tempSlope = eep->modalHeader2G.tempSlope; |
Vasanthakumar Thiagarajan | 15cbbc4 | 2010-11-10 05:03:13 -0800 | [diff] [blame] | 4104 | else if (eep->base_ext2.tempSlopeLow != 0) { |
| 4105 | t[0] = eep->base_ext2.tempSlopeLow; |
| 4106 | f[0] = 5180; |
| 4107 | t[1] = eep->modalHeader5G.tempSlope; |
| 4108 | f[1] = 5500; |
| 4109 | t[2] = eep->base_ext2.tempSlopeHigh; |
| 4110 | f[2] = 5785; |
| 4111 | tempSlope = ar9003_hw_power_interpolate((s32) frequency, |
| 4112 | f, t, 3); |
| 4113 | } else |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 4114 | tempSlope = eep->modalHeader5G.tempSlope; |
| 4115 | |
| 4116 | REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope); |
| 4117 | REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE, |
| 4118 | temperature[0]); |
| 4119 | |
| 4120 | return 0; |
| 4121 | } |
| 4122 | |
| 4123 | /* Apply the recorded correction values. */ |
| 4124 | static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency) |
| 4125 | { |
| 4126 | int ichain, ipier, npier; |
| 4127 | int mode; |
| 4128 | int lfrequency[AR9300_MAX_CHAINS], |
| 4129 | lcorrection[AR9300_MAX_CHAINS], |
| 4130 | ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS]; |
| 4131 | int hfrequency[AR9300_MAX_CHAINS], |
| 4132 | hcorrection[AR9300_MAX_CHAINS], |
| 4133 | htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS]; |
| 4134 | int fdiff; |
| 4135 | int correction[AR9300_MAX_CHAINS], |
| 4136 | voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS]; |
| 4137 | int pfrequency, pcorrection, ptemperature, pvoltage; |
| 4138 | struct ath_common *common = ath9k_hw_common(ah); |
| 4139 | |
| 4140 | mode = (frequency >= 4000); |
| 4141 | if (mode) |
| 4142 | npier = AR9300_NUM_5G_CAL_PIERS; |
| 4143 | else |
| 4144 | npier = AR9300_NUM_2G_CAL_PIERS; |
| 4145 | |
| 4146 | for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { |
| 4147 | lfrequency[ichain] = 0; |
| 4148 | hfrequency[ichain] = 100000; |
| 4149 | } |
| 4150 | /* identify best lower and higher frequency calibration measurement */ |
| 4151 | for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { |
| 4152 | for (ipier = 0; ipier < npier; ipier++) { |
| 4153 | if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain, |
| 4154 | &pfrequency, &pcorrection, |
| 4155 | &ptemperature, &pvoltage)) { |
| 4156 | fdiff = frequency - pfrequency; |
| 4157 | |
| 4158 | /* |
| 4159 | * this measurement is higher than |
| 4160 | * our desired frequency |
| 4161 | */ |
| 4162 | if (fdiff <= 0) { |
| 4163 | if (hfrequency[ichain] <= 0 || |
| 4164 | hfrequency[ichain] >= 100000 || |
| 4165 | fdiff > |
| 4166 | (frequency - hfrequency[ichain])) { |
| 4167 | /* |
| 4168 | * new best higher |
| 4169 | * frequency measurement |
| 4170 | */ |
| 4171 | hfrequency[ichain] = pfrequency; |
| 4172 | hcorrection[ichain] = |
| 4173 | pcorrection; |
| 4174 | htemperature[ichain] = |
| 4175 | ptemperature; |
| 4176 | hvoltage[ichain] = pvoltage; |
| 4177 | } |
| 4178 | } |
| 4179 | if (fdiff >= 0) { |
| 4180 | if (lfrequency[ichain] <= 0 |
| 4181 | || fdiff < |
| 4182 | (frequency - lfrequency[ichain])) { |
| 4183 | /* |
| 4184 | * new best lower |
| 4185 | * frequency measurement |
| 4186 | */ |
| 4187 | lfrequency[ichain] = pfrequency; |
| 4188 | lcorrection[ichain] = |
| 4189 | pcorrection; |
| 4190 | ltemperature[ichain] = |
| 4191 | ptemperature; |
| 4192 | lvoltage[ichain] = pvoltage; |
| 4193 | } |
| 4194 | } |
| 4195 | } |
| 4196 | } |
| 4197 | } |
| 4198 | |
| 4199 | /* interpolate */ |
| 4200 | for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { |
| 4201 | ath_print(common, ATH_DBG_EEPROM, |
| 4202 | "ch=%d f=%d low=%d %d h=%d %d\n", |
| 4203 | ichain, frequency, lfrequency[ichain], |
| 4204 | lcorrection[ichain], hfrequency[ichain], |
| 4205 | hcorrection[ichain]); |
| 4206 | /* they're the same, so just pick one */ |
| 4207 | if (hfrequency[ichain] == lfrequency[ichain]) { |
| 4208 | correction[ichain] = lcorrection[ichain]; |
| 4209 | voltage[ichain] = lvoltage[ichain]; |
| 4210 | temperature[ichain] = ltemperature[ichain]; |
| 4211 | } |
| 4212 | /* the low frequency is good */ |
| 4213 | else if (frequency - lfrequency[ichain] < 1000) { |
| 4214 | /* so is the high frequency, interpolate */ |
| 4215 | if (hfrequency[ichain] - frequency < 1000) { |
| 4216 | |
Vasanthakumar Thiagarajan | bc20680 | 2010-11-10 05:03:14 -0800 | [diff] [blame] | 4217 | correction[ichain] = interpolate(frequency, |
| 4218 | lfrequency[ichain], |
| 4219 | hfrequency[ichain], |
| 4220 | lcorrection[ichain], |
| 4221 | hcorrection[ichain]); |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 4222 | |
Vasanthakumar Thiagarajan | bc20680 | 2010-11-10 05:03:14 -0800 | [diff] [blame] | 4223 | temperature[ichain] = interpolate(frequency, |
| 4224 | lfrequency[ichain], |
| 4225 | hfrequency[ichain], |
| 4226 | ltemperature[ichain], |
| 4227 | htemperature[ichain]); |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 4228 | |
Vasanthakumar Thiagarajan | bc20680 | 2010-11-10 05:03:14 -0800 | [diff] [blame] | 4229 | voltage[ichain] = interpolate(frequency, |
| 4230 | lfrequency[ichain], |
| 4231 | hfrequency[ichain], |
| 4232 | lvoltage[ichain], |
| 4233 | hvoltage[ichain]); |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 4234 | } |
| 4235 | /* only low is good, use it */ |
| 4236 | else { |
| 4237 | correction[ichain] = lcorrection[ichain]; |
| 4238 | temperature[ichain] = ltemperature[ichain]; |
| 4239 | voltage[ichain] = lvoltage[ichain]; |
| 4240 | } |
| 4241 | } |
| 4242 | /* only high is good, use it */ |
| 4243 | else if (hfrequency[ichain] - frequency < 1000) { |
| 4244 | correction[ichain] = hcorrection[ichain]; |
| 4245 | temperature[ichain] = htemperature[ichain]; |
| 4246 | voltage[ichain] = hvoltage[ichain]; |
| 4247 | } else { /* nothing is good, presume 0???? */ |
| 4248 | correction[ichain] = 0; |
| 4249 | temperature[ichain] = 0; |
| 4250 | voltage[ichain] = 0; |
| 4251 | } |
| 4252 | } |
| 4253 | |
| 4254 | ar9003_hw_power_control_override(ah, frequency, correction, voltage, |
| 4255 | temperature); |
| 4256 | |
| 4257 | ath_print(common, ATH_DBG_EEPROM, |
| 4258 | "for frequency=%d, calibration correction = %d %d %d\n", |
| 4259 | frequency, correction[0], correction[1], correction[2]); |
| 4260 | |
| 4261 | return 0; |
| 4262 | } |
| 4263 | |
Luis R. Rodriguez | 824b185 | 2010-08-01 02:25:16 -0400 | [diff] [blame] | 4264 | static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep, |
| 4265 | int idx, |
| 4266 | int edge, |
| 4267 | bool is2GHz) |
| 4268 | { |
| 4269 | struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G; |
| 4270 | struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; |
| 4271 | |
| 4272 | if (is2GHz) |
| 4273 | return ctl_2g[idx].ctlEdges[edge].tPower; |
| 4274 | else |
| 4275 | return ctl_5g[idx].ctlEdges[edge].tPower; |
| 4276 | } |
| 4277 | |
| 4278 | static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep, |
| 4279 | int idx, |
| 4280 | unsigned int edge, |
| 4281 | u16 freq, |
| 4282 | bool is2GHz) |
| 4283 | { |
| 4284 | struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G; |
| 4285 | struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; |
| 4286 | |
| 4287 | u8 *ctl_freqbin = is2GHz ? |
| 4288 | &eep->ctl_freqbin_2G[idx][0] : |
| 4289 | &eep->ctl_freqbin_5G[idx][0]; |
| 4290 | |
| 4291 | if (is2GHz) { |
| 4292 | if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq && |
| 4293 | ctl_2g[idx].ctlEdges[edge - 1].flag) |
| 4294 | return ctl_2g[idx].ctlEdges[edge - 1].tPower; |
| 4295 | } else { |
| 4296 | if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq && |
| 4297 | ctl_5g[idx].ctlEdges[edge - 1].flag) |
| 4298 | return ctl_5g[idx].ctlEdges[edge - 1].tPower; |
| 4299 | } |
| 4300 | |
| 4301 | return AR9300_MAX_RATE_POWER; |
| 4302 | } |
| 4303 | |
| 4304 | /* |
| 4305 | * Find the maximum conformance test limit for the given channel and CTL info |
| 4306 | */ |
| 4307 | static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep, |
| 4308 | u16 freq, int idx, bool is2GHz) |
| 4309 | { |
| 4310 | u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER; |
| 4311 | u8 *ctl_freqbin = is2GHz ? |
| 4312 | &eep->ctl_freqbin_2G[idx][0] : |
| 4313 | &eep->ctl_freqbin_5G[idx][0]; |
| 4314 | u16 num_edges = is2GHz ? |
| 4315 | AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G; |
| 4316 | unsigned int edge; |
| 4317 | |
| 4318 | /* Get the edge power */ |
| 4319 | for (edge = 0; |
| 4320 | (edge < num_edges) && (ctl_freqbin[edge] != AR9300_BCHAN_UNUSED); |
| 4321 | edge++) { |
| 4322 | /* |
| 4323 | * If there's an exact channel match or an inband flag set |
| 4324 | * on the lower channel use the given rdEdgePower |
| 4325 | */ |
| 4326 | if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) { |
| 4327 | twiceMaxEdgePower = |
| 4328 | ar9003_hw_get_direct_edge_power(eep, idx, |
| 4329 | edge, is2GHz); |
| 4330 | break; |
| 4331 | } else if ((edge > 0) && |
| 4332 | (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge], |
| 4333 | is2GHz))) { |
| 4334 | twiceMaxEdgePower = |
| 4335 | ar9003_hw_get_indirect_edge_power(eep, idx, |
| 4336 | edge, freq, |
| 4337 | is2GHz); |
| 4338 | /* |
| 4339 | * Leave loop - no more affecting edges possible in |
| 4340 | * this monotonic increasing list |
| 4341 | */ |
| 4342 | break; |
| 4343 | } |
| 4344 | } |
| 4345 | return twiceMaxEdgePower; |
| 4346 | } |
| 4347 | |
| 4348 | static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, |
| 4349 | struct ath9k_channel *chan, |
| 4350 | u8 *pPwrArray, u16 cfgCtl, |
| 4351 | u8 twiceAntennaReduction, |
| 4352 | u8 twiceMaxRegulatoryPower, |
| 4353 | u16 powerLimit) |
| 4354 | { |
| 4355 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
| 4356 | struct ath_common *common = ath9k_hw_common(ah); |
| 4357 | struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep; |
| 4358 | u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER; |
| 4359 | static const u16 tpScaleReductionTable[5] = { |
| 4360 | 0, 3, 6, 9, AR9300_MAX_RATE_POWER |
| 4361 | }; |
| 4362 | int i; |
| 4363 | int16_t twiceLargestAntenna; |
| 4364 | u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; |
| 4365 | u16 ctlModesFor11a[] = { |
| 4366 | CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 |
| 4367 | }; |
| 4368 | u16 ctlModesFor11g[] = { |
| 4369 | CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, |
| 4370 | CTL_11G_EXT, CTL_2GHT40 |
| 4371 | }; |
| 4372 | u16 numCtlModes, *pCtlMode, ctlMode, freq; |
| 4373 | struct chan_centers centers; |
| 4374 | u8 *ctlIndex; |
| 4375 | u8 ctlNum; |
| 4376 | u16 twiceMinEdgePower; |
| 4377 | bool is2ghz = IS_CHAN_2GHZ(chan); |
| 4378 | |
| 4379 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); |
| 4380 | |
| 4381 | /* Compute TxPower reduction due to Antenna Gain */ |
| 4382 | if (is2ghz) |
| 4383 | twiceLargestAntenna = pEepData->modalHeader2G.antennaGain; |
| 4384 | else |
| 4385 | twiceLargestAntenna = pEepData->modalHeader5G.antennaGain; |
| 4386 | |
| 4387 | twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) - |
| 4388 | twiceLargestAntenna, 0); |
| 4389 | |
| 4390 | /* |
| 4391 | * scaledPower is the minimum of the user input power level |
| 4392 | * and the regulatory allowed power level |
| 4393 | */ |
| 4394 | maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; |
| 4395 | |
| 4396 | if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) { |
| 4397 | maxRegAllowedPower -= |
| 4398 | (tpScaleReductionTable[(regulatory->tp_scale)] * 2); |
| 4399 | } |
| 4400 | |
| 4401 | scaledPower = min(powerLimit, maxRegAllowedPower); |
| 4402 | |
| 4403 | /* |
| 4404 | * Reduce scaled Power by number of chains active to get |
| 4405 | * to per chain tx power level |
| 4406 | */ |
| 4407 | switch (ar5416_get_ntxchains(ah->txchainmask)) { |
| 4408 | case 1: |
| 4409 | break; |
| 4410 | case 2: |
| 4411 | scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN; |
| 4412 | break; |
| 4413 | case 3: |
| 4414 | scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN; |
| 4415 | break; |
| 4416 | } |
| 4417 | |
| 4418 | scaledPower = max((u16)0, scaledPower); |
| 4419 | |
| 4420 | /* |
| 4421 | * Get target powers from EEPROM - our baseline for TX Power |
| 4422 | */ |
| 4423 | if (is2ghz) { |
| 4424 | /* Setup for CTL modes */ |
| 4425 | /* CTL_11B, CTL_11G, CTL_2GHT20 */ |
| 4426 | numCtlModes = |
| 4427 | ARRAY_SIZE(ctlModesFor11g) - |
| 4428 | SUB_NUM_CTL_MODES_AT_2G_40; |
| 4429 | pCtlMode = ctlModesFor11g; |
| 4430 | if (IS_CHAN_HT40(chan)) |
| 4431 | /* All 2G CTL's */ |
| 4432 | numCtlModes = ARRAY_SIZE(ctlModesFor11g); |
| 4433 | } else { |
| 4434 | /* Setup for CTL modes */ |
| 4435 | /* CTL_11A, CTL_5GHT20 */ |
| 4436 | numCtlModes = ARRAY_SIZE(ctlModesFor11a) - |
| 4437 | SUB_NUM_CTL_MODES_AT_5G_40; |
| 4438 | pCtlMode = ctlModesFor11a; |
| 4439 | if (IS_CHAN_HT40(chan)) |
| 4440 | /* All 5G CTL's */ |
| 4441 | numCtlModes = ARRAY_SIZE(ctlModesFor11a); |
| 4442 | } |
| 4443 | |
| 4444 | /* |
| 4445 | * For MIMO, need to apply regulatory caps individually across |
| 4446 | * dynamically running modes: CCK, OFDM, HT20, HT40 |
| 4447 | * |
| 4448 | * The outer loop walks through each possible applicable runtime mode. |
| 4449 | * The inner loop walks through each ctlIndex entry in EEPROM. |
| 4450 | * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. |
| 4451 | */ |
| 4452 | for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { |
| 4453 | bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || |
| 4454 | (pCtlMode[ctlMode] == CTL_2GHT40); |
| 4455 | if (isHt40CtlMode) |
| 4456 | freq = centers.synth_center; |
| 4457 | else if (pCtlMode[ctlMode] & EXT_ADDITIVE) |
| 4458 | freq = centers.ext_center; |
| 4459 | else |
| 4460 | freq = centers.ctl_center; |
| 4461 | |
| 4462 | ath_print(common, ATH_DBG_REGULATORY, |
| 4463 | "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " |
| 4464 | "EXT_ADDITIVE %d\n", |
| 4465 | ctlMode, numCtlModes, isHt40CtlMode, |
| 4466 | (pCtlMode[ctlMode] & EXT_ADDITIVE)); |
| 4467 | |
| 4468 | /* walk through each CTL index stored in EEPROM */ |
| 4469 | if (is2ghz) { |
| 4470 | ctlIndex = pEepData->ctlIndex_2G; |
| 4471 | ctlNum = AR9300_NUM_CTLS_2G; |
| 4472 | } else { |
| 4473 | ctlIndex = pEepData->ctlIndex_5G; |
| 4474 | ctlNum = AR9300_NUM_CTLS_5G; |
| 4475 | } |
| 4476 | |
| 4477 | for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) { |
| 4478 | ath_print(common, ATH_DBG_REGULATORY, |
| 4479 | "LOOP-Ctlidx %d: cfgCtl 0x%2.2x " |
| 4480 | "pCtlMode 0x%2.2x ctlIndex 0x%2.2x " |
| 4481 | "chan %dn", |
| 4482 | i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i], |
| 4483 | chan->channel); |
| 4484 | |
| 4485 | /* |
| 4486 | * compare test group from regulatory |
| 4487 | * channel list with test mode from pCtlMode |
| 4488 | * list |
| 4489 | */ |
| 4490 | if ((((cfgCtl & ~CTL_MODE_M) | |
| 4491 | (pCtlMode[ctlMode] & CTL_MODE_M)) == |
| 4492 | ctlIndex[i]) || |
| 4493 | (((cfgCtl & ~CTL_MODE_M) | |
| 4494 | (pCtlMode[ctlMode] & CTL_MODE_M)) == |
| 4495 | ((ctlIndex[i] & CTL_MODE_M) | |
| 4496 | SD_NO_CTL))) { |
| 4497 | twiceMinEdgePower = |
| 4498 | ar9003_hw_get_max_edge_power(pEepData, |
| 4499 | freq, i, |
| 4500 | is2ghz); |
| 4501 | |
| 4502 | if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) |
| 4503 | /* |
| 4504 | * Find the minimum of all CTL |
| 4505 | * edge powers that apply to |
| 4506 | * this channel |
| 4507 | */ |
| 4508 | twiceMaxEdgePower = |
| 4509 | min(twiceMaxEdgePower, |
| 4510 | twiceMinEdgePower); |
| 4511 | else { |
| 4512 | /* specific */ |
| 4513 | twiceMaxEdgePower = |
| 4514 | twiceMinEdgePower; |
| 4515 | break; |
| 4516 | } |
| 4517 | } |
| 4518 | } |
| 4519 | |
| 4520 | minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); |
| 4521 | |
| 4522 | ath_print(common, ATH_DBG_REGULATORY, |
| 4523 | "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d " |
| 4524 | "sP %d minCtlPwr %d\n", |
| 4525 | ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, |
| 4526 | scaledPower, minCtlPower); |
| 4527 | |
| 4528 | /* Apply ctl mode to correct target power set */ |
| 4529 | switch (pCtlMode[ctlMode]) { |
| 4530 | case CTL_11B: |
| 4531 | for (i = ALL_TARGET_LEGACY_1L_5L; |
| 4532 | i <= ALL_TARGET_LEGACY_11S; i++) |
| 4533 | pPwrArray[i] = |
| 4534 | (u8)min((u16)pPwrArray[i], |
| 4535 | minCtlPower); |
| 4536 | break; |
| 4537 | case CTL_11A: |
| 4538 | case CTL_11G: |
| 4539 | for (i = ALL_TARGET_LEGACY_6_24; |
| 4540 | i <= ALL_TARGET_LEGACY_54; i++) |
| 4541 | pPwrArray[i] = |
| 4542 | (u8)min((u16)pPwrArray[i], |
| 4543 | minCtlPower); |
| 4544 | break; |
| 4545 | case CTL_5GHT20: |
| 4546 | case CTL_2GHT20: |
| 4547 | for (i = ALL_TARGET_HT20_0_8_16; |
| 4548 | i <= ALL_TARGET_HT20_21; i++) |
| 4549 | pPwrArray[i] = |
| 4550 | (u8)min((u16)pPwrArray[i], |
| 4551 | minCtlPower); |
| 4552 | pPwrArray[ALL_TARGET_HT20_22] = |
| 4553 | (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22], |
| 4554 | minCtlPower); |
| 4555 | pPwrArray[ALL_TARGET_HT20_23] = |
| 4556 | (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23], |
| 4557 | minCtlPower); |
| 4558 | break; |
| 4559 | case CTL_5GHT40: |
| 4560 | case CTL_2GHT40: |
| 4561 | for (i = ALL_TARGET_HT40_0_8_16; |
| 4562 | i <= ALL_TARGET_HT40_23; i++) |
| 4563 | pPwrArray[i] = |
| 4564 | (u8)min((u16)pPwrArray[i], |
| 4565 | minCtlPower); |
| 4566 | break; |
| 4567 | default: |
| 4568 | break; |
| 4569 | } |
| 4570 | } /* end ctl mode checking */ |
| 4571 | } |
| 4572 | |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 4573 | static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, |
| 4574 | struct ath9k_channel *chan, u16 cfgCtl, |
| 4575 | u8 twiceAntennaReduction, |
| 4576 | u8 twiceMaxRegulatoryPower, |
Felix Fietkau | de40f31 | 2010-10-20 03:08:53 +0200 | [diff] [blame] | 4577 | u8 powerLimit, bool test) |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 4578 | { |
Felix Fietkau | 6b7b6cf | 2010-10-20 02:09:44 +0200 | [diff] [blame] | 4579 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Luis R. Rodriguez | 824b185 | 2010-08-01 02:25:16 -0400 | [diff] [blame] | 4580 | struct ath_common *common = ath9k_hw_common(ah); |
| 4581 | u8 targetPowerValT2[ar9300RateSize]; |
| 4582 | unsigned int i = 0; |
| 4583 | |
| 4584 | ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2); |
| 4585 | ar9003_hw_set_power_per_rate_table(ah, chan, |
| 4586 | targetPowerValT2, cfgCtl, |
| 4587 | twiceAntennaReduction, |
| 4588 | twiceMaxRegulatoryPower, |
| 4589 | powerLimit); |
| 4590 | |
Felix Fietkau | de40f31 | 2010-10-20 03:08:53 +0200 | [diff] [blame] | 4591 | regulatory->max_power_level = 0; |
| 4592 | for (i = 0; i < ar9300RateSize; i++) { |
| 4593 | if (targetPowerValT2[i] > regulatory->max_power_level) |
| 4594 | regulatory->max_power_level = targetPowerValT2[i]; |
| 4595 | } |
| 4596 | |
| 4597 | if (test) |
| 4598 | return; |
| 4599 | |
| 4600 | for (i = 0; i < ar9300RateSize; i++) { |
Luis R. Rodriguez | 824b185 | 2010-08-01 02:25:16 -0400 | [diff] [blame] | 4601 | ath_print(common, ATH_DBG_EEPROM, |
| 4602 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); |
| 4603 | i++; |
| 4604 | ath_print(common, ATH_DBG_EEPROM, |
| 4605 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); |
| 4606 | i++; |
| 4607 | ath_print(common, ATH_DBG_EEPROM, |
| 4608 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); |
| 4609 | i++; |
| 4610 | ath_print(common, ATH_DBG_EEPROM, |
| 4611 | "TPC[%02d] 0x%08x\n\n", i, targetPowerValT2[i]); |
| 4612 | i++; |
| 4613 | } |
| 4614 | |
Luis R. Rodriguez | 824b185 | 2010-08-01 02:25:16 -0400 | [diff] [blame] | 4615 | /* |
| 4616 | * This is the TX power we send back to driver core, |
| 4617 | * and it can use to pass to userspace to display our |
| 4618 | * currently configured TX power setting. |
| 4619 | * |
| 4620 | * Since power is rate dependent, use one of the indices |
| 4621 | * from the AR9300_Rates enum to select an entry from |
| 4622 | * targetPowerValT2[] to report. Currently returns the |
| 4623 | * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps |
| 4624 | * as CCK power is less interesting (?). |
| 4625 | */ |
| 4626 | i = ALL_TARGET_LEGACY_6_24; /* legacy */ |
| 4627 | if (IS_CHAN_HT40(chan)) |
| 4628 | i = ALL_TARGET_HT40_0_8_16; /* ht40 */ |
| 4629 | else if (IS_CHAN_HT20(chan)) |
| 4630 | i = ALL_TARGET_HT20_0_8_16; /* ht20 */ |
| 4631 | |
| 4632 | ah->txpower_limit = targetPowerValT2[i]; |
Felix Fietkau | de40f31 | 2010-10-20 03:08:53 +0200 | [diff] [blame] | 4633 | regulatory->max_power_level = targetPowerValT2[i]; |
Luis R. Rodriguez | 824b185 | 2010-08-01 02:25:16 -0400 | [diff] [blame] | 4634 | |
Felix Fietkau | de40f31 | 2010-10-20 03:08:53 +0200 | [diff] [blame] | 4635 | /* Write target power array to registers */ |
| 4636 | ar9003_hw_tx_power_regwrite(ah, targetPowerValT2); |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 4637 | ar9003_hw_calibration_apply(ah, chan->channel); |
| 4638 | } |
| 4639 | |
| 4640 | static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah, |
| 4641 | u16 i, bool is2GHz) |
| 4642 | { |
| 4643 | return AR_NO_SPUR; |
| 4644 | } |
| 4645 | |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 4646 | s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah) |
| 4647 | { |
| 4648 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
| 4649 | |
| 4650 | return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */ |
| 4651 | } |
| 4652 | |
| 4653 | s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah) |
| 4654 | { |
| 4655 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
| 4656 | |
| 4657 | return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */ |
| 4658 | } |
| 4659 | |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 4660 | const struct eeprom_ops eep_ar9300_ops = { |
| 4661 | .check_eeprom = ath9k_hw_ar9300_check_eeprom, |
| 4662 | .get_eeprom = ath9k_hw_ar9300_get_eeprom, |
| 4663 | .fill_eeprom = ath9k_hw_ar9300_fill_eeprom, |
| 4664 | .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver, |
| 4665 | .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev, |
| 4666 | .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config, |
| 4667 | .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg, |
| 4668 | .set_board_values = ath9k_hw_ar9300_set_board_values, |
| 4669 | .set_addac = ath9k_hw_ar9300_set_addac, |
| 4670 | .set_txpower = ath9k_hw_ar9300_set_txpower, |
| 4671 | .get_spur_channel = ath9k_hw_ar9300_get_spur_channel |
| 4672 | }; |