Barry Song | 4898de3 | 2012-12-20 19:37:32 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * plat smp support for CSR Marco dual-core SMP SoCs |
| 3 | * |
| 4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. |
| 5 | * |
| 6 | * Licensed under GPLv2 or later. |
| 7 | */ |
| 8 | |
| 9 | #include <linux/init.h> |
| 10 | #include <linux/smp.h> |
| 11 | #include <linux/delay.h> |
| 12 | #include <linux/of.h> |
| 13 | #include <linux/of_address.h> |
| 14 | #include <asm/page.h> |
| 15 | #include <asm/mach/map.h> |
| 16 | #include <asm/smp_plat.h> |
| 17 | #include <asm/smp_scu.h> |
| 18 | #include <asm/cacheflush.h> |
| 19 | #include <asm/cputype.h> |
| 20 | #include <asm/hardware/gic.h> |
| 21 | #include <mach/map.h> |
| 22 | |
| 23 | #include "common.h" |
| 24 | |
| 25 | static void __iomem *scu_base; |
| 26 | static void __iomem *rsc_base; |
| 27 | |
| 28 | static DEFINE_SPINLOCK(boot_lock); |
| 29 | |
| 30 | static struct map_desc scu_io_desc __initdata = { |
| 31 | .length = SZ_4K, |
| 32 | .type = MT_DEVICE, |
| 33 | }; |
| 34 | |
| 35 | void __init sirfsoc_map_scu(void) |
| 36 | { |
| 37 | unsigned long base; |
| 38 | |
| 39 | /* Get SCU base */ |
| 40 | asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); |
| 41 | |
| 42 | scu_io_desc.virtual = SIRFSOC_VA(base); |
| 43 | scu_io_desc.pfn = __phys_to_pfn(base); |
| 44 | iotable_init(&scu_io_desc, 1); |
| 45 | |
| 46 | scu_base = (void __iomem *)SIRFSOC_VA(base); |
| 47 | } |
| 48 | |
| 49 | static void __cpuinit sirfsoc_secondary_init(unsigned int cpu) |
| 50 | { |
| 51 | /* |
| 52 | * if any interrupts are already enabled for the primary |
| 53 | * core (e.g. timer irq), then they will not have been enabled |
| 54 | * for us: do so |
| 55 | */ |
| 56 | gic_secondary_init(0); |
| 57 | |
| 58 | /* |
| 59 | * let the primary processor know we're out of the |
| 60 | * pen, then head off into the C entry point |
| 61 | */ |
| 62 | pen_release = -1; |
| 63 | smp_wmb(); |
| 64 | |
| 65 | /* |
| 66 | * Synchronise with the boot thread. |
| 67 | */ |
| 68 | spin_lock(&boot_lock); |
| 69 | spin_unlock(&boot_lock); |
| 70 | } |
| 71 | |
| 72 | static struct of_device_id rsc_ids[] = { |
| 73 | { .compatible = "sirf,marco-rsc" }, |
| 74 | {}, |
| 75 | }; |
| 76 | |
| 77 | static int __cpuinit sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 78 | { |
| 79 | unsigned long timeout; |
| 80 | struct device_node *np; |
| 81 | |
| 82 | np = of_find_matching_node(NULL, rsc_ids); |
| 83 | if (!np) |
| 84 | return -ENODEV; |
| 85 | |
| 86 | rsc_base = of_iomap(np, 0); |
| 87 | if (!rsc_base) |
| 88 | return -ENOMEM; |
| 89 | |
| 90 | /* |
| 91 | * write the address of secondary startup into the sram register |
| 92 | * at offset 0x2C, then write the magic number 0x3CAF5D62 to the |
| 93 | * RSC register at offset 0x28, which is what boot rom code is |
| 94 | * waiting for. This would wake up the secondary core from WFE |
| 95 | */ |
| 96 | #define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2C |
| 97 | __raw_writel(virt_to_phys(sirfsoc_secondary_startup), |
| 98 | rsc_base + SIRFSOC_CPU1_JUMPADDR_OFFSET); |
| 99 | |
| 100 | #define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x28 |
| 101 | __raw_writel(0x3CAF5D62, |
| 102 | rsc_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET); |
| 103 | |
| 104 | /* make sure write buffer is drained */ |
| 105 | mb(); |
| 106 | |
| 107 | spin_lock(&boot_lock); |
| 108 | |
| 109 | /* |
| 110 | * The secondary processor is waiting to be released from |
| 111 | * the holding pen - release it, then wait for it to flag |
| 112 | * that it has been released by resetting pen_release. |
| 113 | * |
| 114 | * Note that "pen_release" is the hardware CPU ID, whereas |
| 115 | * "cpu" is Linux's internal ID. |
| 116 | */ |
| 117 | pen_release = cpu_logical_map(cpu); |
| 118 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); |
| 119 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); |
| 120 | |
| 121 | /* |
| 122 | * Send the secondary CPU SEV, thereby causing the boot monitor to read |
| 123 | * the JUMPADDR and WAKEMAGIC, and branch to the address found there. |
| 124 | */ |
| 125 | dsb_sev(); |
| 126 | |
| 127 | timeout = jiffies + (1 * HZ); |
| 128 | while (time_before(jiffies, timeout)) { |
| 129 | smp_rmb(); |
| 130 | if (pen_release == -1) |
| 131 | break; |
| 132 | |
| 133 | udelay(10); |
| 134 | } |
| 135 | |
| 136 | /* |
| 137 | * now the secondary core is starting up let it run its |
| 138 | * calibrations, then wait for it to finish |
| 139 | */ |
| 140 | spin_unlock(&boot_lock); |
| 141 | |
| 142 | return pen_release != -1 ? -ENOSYS : 0; |
| 143 | } |
| 144 | |
| 145 | static void __init sirfsoc_smp_init_cpus(void) |
| 146 | { |
| 147 | set_smp_cross_call(gic_raise_softirq); |
| 148 | } |
| 149 | |
| 150 | static void __init sirfsoc_smp_prepare_cpus(unsigned int max_cpus) |
| 151 | { |
| 152 | scu_enable(scu_base); |
| 153 | } |
| 154 | |
| 155 | struct smp_operations sirfsoc_smp_ops __initdata = { |
| 156 | .smp_init_cpus = sirfsoc_smp_init_cpus, |
| 157 | .smp_prepare_cpus = sirfsoc_smp_prepare_cpus, |
| 158 | .smp_secondary_init = sirfsoc_secondary_init, |
| 159 | .smp_boot_secondary = sirfsoc_boot_secondary, |
| 160 | #ifdef CONFIG_HOTPLUG_CPU |
| 161 | .cpu_die = sirfsoc_cpu_die, |
| 162 | #endif |
| 163 | }; |