Paul Walmsley | a5ffef6 | 2011-09-14 16:01:21 -0600 | [diff] [blame] | 1 | /* |
| 2 | * OMAP3xxx clockdomains |
| 3 | * |
| 4 | * Copyright (C) 2008-2011 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2008-2010 Nokia Corporation |
| 6 | * |
| 7 | * Paul Walmsley, Jouni Högander |
| 8 | * |
| 9 | * This file contains clockdomains and clockdomain wakeup/sleep |
| 10 | * dependencies for the OMAP3xxx chips. Some notes: |
| 11 | * |
| 12 | * A useful validation rule for struct clockdomain: Any clockdomain |
| 13 | * referenced by a wkdep_srcs or sleepdep_srcs array must have a |
| 14 | * dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really just |
| 15 | * software-controllable dependencies. Non-software-controllable |
| 16 | * dependencies do exist, but they are not encoded below (yet). |
| 17 | * |
| 18 | * The overly-specific dep_bit names are due to a bit name collision |
| 19 | * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift |
| 20 | * value are the same for all powerdomains: 2 |
| 21 | * |
| 22 | * XXX should dep_bit be a mask, so we can test to see if it is 0 as a |
| 23 | * sanity check? |
| 24 | * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE |
| 25 | */ |
| 26 | |
| 27 | /* |
| 28 | * To-Do List |
| 29 | * -> Port the Sleep/Wakeup dependencies for the domains |
| 30 | * from the Power domain framework |
| 31 | */ |
| 32 | |
| 33 | #include <linux/kernel.h> |
| 34 | #include <linux/io.h> |
| 35 | |
| 36 | #include "clockdomain.h" |
| 37 | #include "prm2xxx_3xxx.h" |
| 38 | #include "cm2xxx_3xxx.h" |
| 39 | #include "cm-regbits-34xx.h" |
| 40 | #include "prm-regbits-34xx.h" |
| 41 | |
| 42 | /* |
| 43 | * Clockdomain dependencies for wkdeps/sleepdeps |
| 44 | * |
| 45 | * XXX Hardware dependencies (e.g., dependencies that cannot be |
| 46 | * changed in software) are not included here yet, but should be. |
| 47 | */ |
| 48 | |
| 49 | /* OMAP3-specific possible dependencies */ |
| 50 | |
| 51 | /* |
| 52 | * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE |
| 53 | * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE |
| 54 | */ |
| 55 | static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = { |
Mark A. Greer | 48a6884 | 2012-05-07 23:55:38 -0600 | [diff] [blame^] | 56 | { .clkdm_name = "iva2_clkdm" }, |
| 57 | { .clkdm_name = "mpu_clkdm" }, |
| 58 | { .clkdm_name = "wkup_clkdm" }, |
Paul Walmsley | a5ffef6 | 2011-09-14 16:01:21 -0600 | [diff] [blame] | 59 | { NULL }, |
| 60 | }; |
| 61 | |
| 62 | /* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */ |
| 63 | static struct clkdm_dep per_wkdeps[] = { |
| 64 | { .clkdm_name = "core_l3_clkdm" }, |
| 65 | { .clkdm_name = "core_l4_clkdm" }, |
| 66 | { .clkdm_name = "iva2_clkdm" }, |
| 67 | { .clkdm_name = "mpu_clkdm" }, |
| 68 | { .clkdm_name = "wkup_clkdm" }, |
| 69 | { NULL }, |
| 70 | }; |
| 71 | |
| 72 | /* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */ |
| 73 | static struct clkdm_dep usbhost_wkdeps[] = { |
| 74 | { .clkdm_name = "core_l3_clkdm" }, |
| 75 | { .clkdm_name = "core_l4_clkdm" }, |
| 76 | { .clkdm_name = "iva2_clkdm" }, |
| 77 | { .clkdm_name = "mpu_clkdm" }, |
| 78 | { .clkdm_name = "wkup_clkdm" }, |
| 79 | { NULL }, |
| 80 | }; |
| 81 | |
| 82 | /* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */ |
| 83 | static struct clkdm_dep mpu_3xxx_wkdeps[] = { |
| 84 | { .clkdm_name = "core_l3_clkdm" }, |
| 85 | { .clkdm_name = "core_l4_clkdm" }, |
| 86 | { .clkdm_name = "iva2_clkdm" }, |
| 87 | { .clkdm_name = "dss_clkdm" }, |
| 88 | { .clkdm_name = "per_clkdm" }, |
| 89 | { NULL }, |
| 90 | }; |
| 91 | |
| 92 | /* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */ |
| 93 | static struct clkdm_dep iva2_wkdeps[] = { |
| 94 | { .clkdm_name = "core_l3_clkdm" }, |
| 95 | { .clkdm_name = "core_l4_clkdm" }, |
| 96 | { .clkdm_name = "mpu_clkdm" }, |
| 97 | { .clkdm_name = "wkup_clkdm" }, |
| 98 | { .clkdm_name = "dss_clkdm" }, |
| 99 | { .clkdm_name = "per_clkdm" }, |
| 100 | { NULL }, |
| 101 | }; |
| 102 | |
| 103 | /* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */ |
| 104 | static struct clkdm_dep cam_wkdeps[] = { |
| 105 | { .clkdm_name = "iva2_clkdm" }, |
| 106 | { .clkdm_name = "mpu_clkdm" }, |
| 107 | { .clkdm_name = "wkup_clkdm" }, |
| 108 | { NULL }, |
| 109 | }; |
| 110 | |
| 111 | /* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */ |
| 112 | static struct clkdm_dep dss_wkdeps[] = { |
| 113 | { .clkdm_name = "iva2_clkdm" }, |
| 114 | { .clkdm_name = "mpu_clkdm" }, |
| 115 | { .clkdm_name = "wkup_clkdm" }, |
| 116 | { NULL }, |
| 117 | }; |
| 118 | |
| 119 | /* 3430: PM_WKDEP_NEON: MPU */ |
| 120 | static struct clkdm_dep neon_wkdeps[] = { |
| 121 | { .clkdm_name = "mpu_clkdm" }, |
| 122 | { NULL }, |
| 123 | }; |
| 124 | |
| 125 | /* Sleep dependency source arrays for OMAP3-specific clkdms */ |
| 126 | |
| 127 | /* 3430: CM_SLEEPDEP_DSS: MPU, IVA */ |
| 128 | static struct clkdm_dep dss_sleepdeps[] = { |
| 129 | { .clkdm_name = "mpu_clkdm" }, |
| 130 | { .clkdm_name = "iva2_clkdm" }, |
| 131 | { NULL }, |
| 132 | }; |
| 133 | |
| 134 | /* 3430: CM_SLEEPDEP_PER: MPU, IVA */ |
| 135 | static struct clkdm_dep per_sleepdeps[] = { |
| 136 | { .clkdm_name = "mpu_clkdm" }, |
| 137 | { .clkdm_name = "iva2_clkdm" }, |
| 138 | { NULL }, |
| 139 | }; |
| 140 | |
| 141 | /* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */ |
| 142 | static struct clkdm_dep usbhost_sleepdeps[] = { |
| 143 | { .clkdm_name = "mpu_clkdm" }, |
| 144 | { .clkdm_name = "iva2_clkdm" }, |
| 145 | { NULL }, |
| 146 | }; |
| 147 | |
| 148 | /* 3430: CM_SLEEPDEP_CAM: MPU */ |
| 149 | static struct clkdm_dep cam_sleepdeps[] = { |
| 150 | { .clkdm_name = "mpu_clkdm" }, |
| 151 | { NULL }, |
| 152 | }; |
| 153 | |
| 154 | /* |
| 155 | * 3430ES1: CM_SLEEPDEP_GFX: MPU |
| 156 | * 3430ES2: CM_SLEEPDEP_SGX: MPU |
| 157 | * These can share data since they will never be present simultaneously |
| 158 | * on the same device. |
| 159 | */ |
| 160 | static struct clkdm_dep gfx_sgx_sleepdeps[] = { |
| 161 | { .clkdm_name = "mpu_clkdm" }, |
| 162 | { NULL }, |
| 163 | }; |
| 164 | |
| 165 | /* |
| 166 | * OMAP3 clockdomains |
| 167 | */ |
| 168 | |
| 169 | static struct clockdomain mpu_3xxx_clkdm = { |
| 170 | .name = "mpu_clkdm", |
| 171 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 172 | .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, |
| 173 | .dep_bit = OMAP3430_EN_MPU_SHIFT, |
| 174 | .wkdep_srcs = mpu_3xxx_wkdeps, |
| 175 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, |
| 176 | }; |
| 177 | |
| 178 | static struct clockdomain neon_clkdm = { |
| 179 | .name = "neon_clkdm", |
| 180 | .pwrdm = { .name = "neon_pwrdm" }, |
| 181 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 182 | .wkdep_srcs = neon_wkdeps, |
| 183 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, |
| 184 | }; |
| 185 | |
| 186 | static struct clockdomain iva2_clkdm = { |
| 187 | .name = "iva2_clkdm", |
| 188 | .pwrdm = { .name = "iva2_pwrdm" }, |
| 189 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 190 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT, |
| 191 | .wkdep_srcs = iva2_wkdeps, |
| 192 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, |
| 193 | }; |
| 194 | |
| 195 | static struct clockdomain gfx_3430es1_clkdm = { |
| 196 | .name = "gfx_clkdm", |
| 197 | .pwrdm = { .name = "gfx_pwrdm" }, |
| 198 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 199 | .wkdep_srcs = gfx_sgx_3xxx_wkdeps, |
| 200 | .sleepdep_srcs = gfx_sgx_sleepdeps, |
| 201 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, |
| 202 | }; |
| 203 | |
| 204 | static struct clockdomain sgx_clkdm = { |
| 205 | .name = "sgx_clkdm", |
| 206 | .pwrdm = { .name = "sgx_pwrdm" }, |
| 207 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 208 | .wkdep_srcs = gfx_sgx_3xxx_wkdeps, |
| 209 | .sleepdep_srcs = gfx_sgx_sleepdeps, |
| 210 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, |
| 211 | }; |
| 212 | |
| 213 | /* |
| 214 | * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but |
| 215 | * then that information was removed from the 34xx ES2+ TRM. It is |
| 216 | * unclear whether the core is still there, but the clockdomain logic |
| 217 | * is there, and must be programmed to an appropriate state if the |
| 218 | * CORE clockdomain is to become inactive. |
| 219 | */ |
| 220 | static struct clockdomain d2d_clkdm = { |
| 221 | .name = "d2d_clkdm", |
| 222 | .pwrdm = { .name = "core_pwrdm" }, |
| 223 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 224 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, |
| 225 | }; |
| 226 | |
| 227 | /* |
| 228 | * XXX add usecounting for clkdm dependencies, otherwise the presence |
| 229 | * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm |
| 230 | * could cause trouble |
| 231 | */ |
| 232 | static struct clockdomain core_l3_3xxx_clkdm = { |
| 233 | .name = "core_l3_clkdm", |
| 234 | .pwrdm = { .name = "core_pwrdm" }, |
| 235 | .flags = CLKDM_CAN_HWSUP, |
| 236 | .dep_bit = OMAP3430_EN_CORE_SHIFT, |
| 237 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, |
| 238 | }; |
| 239 | |
| 240 | /* |
| 241 | * XXX add usecounting for clkdm dependencies, otherwise the presence |
| 242 | * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm |
| 243 | * could cause trouble |
| 244 | */ |
| 245 | static struct clockdomain core_l4_3xxx_clkdm = { |
| 246 | .name = "core_l4_clkdm", |
| 247 | .pwrdm = { .name = "core_pwrdm" }, |
| 248 | .flags = CLKDM_CAN_HWSUP, |
| 249 | .dep_bit = OMAP3430_EN_CORE_SHIFT, |
| 250 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, |
| 251 | }; |
| 252 | |
| 253 | /* Another case of bit name collisions between several registers: EN_DSS */ |
| 254 | static struct clockdomain dss_3xxx_clkdm = { |
| 255 | .name = "dss_clkdm", |
| 256 | .pwrdm = { .name = "dss_pwrdm" }, |
| 257 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 258 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT, |
| 259 | .wkdep_srcs = dss_wkdeps, |
| 260 | .sleepdep_srcs = dss_sleepdeps, |
| 261 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, |
| 262 | }; |
| 263 | |
| 264 | static struct clockdomain cam_clkdm = { |
| 265 | .name = "cam_clkdm", |
| 266 | .pwrdm = { .name = "cam_pwrdm" }, |
| 267 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 268 | .wkdep_srcs = cam_wkdeps, |
| 269 | .sleepdep_srcs = cam_sleepdeps, |
| 270 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, |
| 271 | }; |
| 272 | |
| 273 | static struct clockdomain usbhost_clkdm = { |
| 274 | .name = "usbhost_clkdm", |
| 275 | .pwrdm = { .name = "usbhost_pwrdm" }, |
| 276 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 277 | .wkdep_srcs = usbhost_wkdeps, |
| 278 | .sleepdep_srcs = usbhost_sleepdeps, |
| 279 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, |
| 280 | }; |
| 281 | |
| 282 | static struct clockdomain per_clkdm = { |
| 283 | .name = "per_clkdm", |
| 284 | .pwrdm = { .name = "per_pwrdm" }, |
| 285 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 286 | .dep_bit = OMAP3430_EN_PER_SHIFT, |
| 287 | .wkdep_srcs = per_wkdeps, |
| 288 | .sleepdep_srcs = per_sleepdeps, |
| 289 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, |
| 290 | }; |
| 291 | |
| 292 | /* |
| 293 | * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is |
| 294 | * switched of even if sdti is in use |
| 295 | */ |
| 296 | static struct clockdomain emu_clkdm = { |
| 297 | .name = "emu_clkdm", |
| 298 | .pwrdm = { .name = "emu_pwrdm" }, |
| 299 | .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP, |
| 300 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, |
| 301 | }; |
| 302 | |
| 303 | static struct clockdomain dpll1_clkdm = { |
| 304 | .name = "dpll1_clkdm", |
| 305 | .pwrdm = { .name = "dpll1_pwrdm" }, |
| 306 | }; |
| 307 | |
| 308 | static struct clockdomain dpll2_clkdm = { |
| 309 | .name = "dpll2_clkdm", |
| 310 | .pwrdm = { .name = "dpll2_pwrdm" }, |
| 311 | }; |
| 312 | |
| 313 | static struct clockdomain dpll3_clkdm = { |
| 314 | .name = "dpll3_clkdm", |
| 315 | .pwrdm = { .name = "dpll3_pwrdm" }, |
| 316 | }; |
| 317 | |
| 318 | static struct clockdomain dpll4_clkdm = { |
| 319 | .name = "dpll4_clkdm", |
| 320 | .pwrdm = { .name = "dpll4_pwrdm" }, |
| 321 | }; |
| 322 | |
| 323 | static struct clockdomain dpll5_clkdm = { |
| 324 | .name = "dpll5_clkdm", |
| 325 | .pwrdm = { .name = "dpll5_pwrdm" }, |
| 326 | }; |
| 327 | |
| 328 | /* |
| 329 | * Clockdomain hwsup dependencies |
| 330 | */ |
| 331 | |
| 332 | static struct clkdm_autodep clkdm_autodeps[] = { |
| 333 | { |
| 334 | .clkdm = { .name = "mpu_clkdm" }, |
| 335 | }, |
| 336 | { |
| 337 | .clkdm = { .name = "iva2_clkdm" }, |
| 338 | }, |
| 339 | { |
| 340 | .clkdm = { .name = NULL }, |
| 341 | } |
| 342 | }; |
| 343 | |
| 344 | /* |
| 345 | * |
| 346 | */ |
| 347 | |
| 348 | static struct clockdomain *clockdomains_omap3430_common[] __initdata = { |
| 349 | &wkup_common_clkdm, |
| 350 | &cm_common_clkdm, |
| 351 | &prm_common_clkdm, |
| 352 | &mpu_3xxx_clkdm, |
| 353 | &neon_clkdm, |
| 354 | &iva2_clkdm, |
| 355 | &d2d_clkdm, |
| 356 | &core_l3_3xxx_clkdm, |
| 357 | &core_l4_3xxx_clkdm, |
| 358 | &dss_3xxx_clkdm, |
| 359 | &cam_clkdm, |
| 360 | &per_clkdm, |
| 361 | &emu_clkdm, |
| 362 | &dpll1_clkdm, |
| 363 | &dpll2_clkdm, |
| 364 | &dpll3_clkdm, |
| 365 | &dpll4_clkdm, |
| 366 | NULL |
| 367 | }; |
| 368 | |
| 369 | static struct clockdomain *clockdomains_omap3430es1[] __initdata = { |
| 370 | &gfx_3430es1_clkdm, |
| 371 | NULL, |
| 372 | }; |
| 373 | |
| 374 | static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = { |
| 375 | &sgx_clkdm, |
| 376 | &dpll5_clkdm, |
| 377 | &usbhost_clkdm, |
| 378 | NULL, |
| 379 | }; |
| 380 | |
| 381 | void __init omap3xxx_clockdomains_init(void) |
| 382 | { |
| 383 | struct clockdomain **sc; |
| 384 | |
| 385 | if (!cpu_is_omap34xx()) |
| 386 | return; |
| 387 | |
| 388 | clkdm_register_platform_funcs(&omap3_clkdm_operations); |
| 389 | clkdm_register_clkdms(clockdomains_omap3430_common); |
| 390 | |
| 391 | sc = (omap_rev() == OMAP3430_REV_ES1_0) ? clockdomains_omap3430es1 : |
| 392 | clockdomains_omap3430es2plus; |
| 393 | |
| 394 | clkdm_register_clkdms(sc); |
| 395 | |
| 396 | clkdm_register_autodeps(clkdm_autodeps); |
| 397 | clkdm_complete_init(); |
| 398 | } |