Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1 | # |
| 2 | # Memory devices |
| 3 | # |
| 4 | |
| 5 | menuconfig MEMORY |
| 6 | bool "Memory Controller drivers" |
| 7 | |
| 8 | if MEMORY |
| 9 | |
Joachim Eastwood | 17c50b7 | 2015-07-13 23:20:11 +0200 | [diff] [blame] | 10 | config ARM_PL172_MPMC |
| 11 | tristate "ARM PL172 MPMC driver" |
| 12 | depends on ARM_AMBA && OF |
| 13 | help |
| 14 | This selects the ARM PrimeCell PL172 MultiPort Memory Controller. |
| 15 | If you have an embedded system with an AMBA bus and a PL172 |
| 16 | controller, say Y or M here. |
| 17 | |
Alexandre Belloni | e81b6ab | 2014-07-08 18:21:12 +0200 | [diff] [blame] | 18 | config ATMEL_SDRAMC |
| 19 | bool "Atmel (Multi-port DDR-)SDRAM Controller" |
| 20 | default y |
| 21 | depends on ARCH_AT91 && OF |
| 22 | help |
| 23 | This driver is for Atmel SDRAM Controller or Atmel Multi-port |
| 24 | DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs. |
| 25 | Starting with the at91sam9g45, this controller supports SDR, DDR and |
| 26 | LP-DDR memories. |
| 27 | |
Ivan Khoronzhuk | 5a7c815 | 2014-02-24 19:26:11 +0200 | [diff] [blame] | 28 | config TI_AEMIF |
| 29 | tristate "Texas Instruments AEMIF driver" |
| 30 | depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF |
| 31 | help |
| 32 | This driver is for the AEMIF module available in Texas Instruments |
| 33 | SoCs. AEMIF stands for Asynchronous External Memory Interface and |
| 34 | is intended to provide a glue-less interface to a variety of |
| 35 | asynchronuous memory devices like ASRAM, NOR and NAND memory. A total |
| 36 | of 256M bytes of any of these memories can be accessed at a given |
| 37 | time via four chip selects with 64M byte access per chip select. |
| 38 | |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 39 | config TI_EMIF |
| 40 | tristate "Texas Instruments EMIF driver" |
Santosh Shilimkar | 18e9a97 | 2012-05-04 11:38:11 +0530 | [diff] [blame] | 41 | depends on ARCH_OMAP2PLUS |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 42 | select DDR |
| 43 | help |
| 44 | This driver is for the EMIF module available in Texas Instruments |
| 45 | SoCs. EMIF is an SDRAM controller that, based on its revision, |
| 46 | supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols. |
| 47 | This driver takes care of only LPDDR2 memories presently. The |
| 48 | functions of the driver includes re-configuring AC timing |
| 49 | parameters and other settings during frequency, voltage and |
| 50 | temperature changes |
| 51 | |
Tony Lindgren | 1864019 | 2014-11-20 09:13:42 -0800 | [diff] [blame] | 52 | config OMAP_GPMC |
| 53 | bool |
Roger Quadros | d2d00862 | 2016-03-07 12:18:43 +0200 | [diff] [blame] | 54 | select GPIOLIB |
Tony Lindgren | 1864019 | 2014-11-20 09:13:42 -0800 | [diff] [blame] | 55 | help |
| 56 | This driver is for the General Purpose Memory Controller (GPMC) |
| 57 | present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows |
| 58 | interfacing to a variety of asynchronous as well as synchronous |
| 59 | memory drives like NOR, NAND, OneNAND, SRAM. |
| 60 | |
Tony Lindgren | 63aa945 | 2015-06-01 19:22:10 -0600 | [diff] [blame] | 61 | config OMAP_GPMC_DEBUG |
Tony Lindgren | be59b61 | 2015-10-12 16:19:54 -0700 | [diff] [blame] | 62 | bool "Enable GPMC debug output and skip reset of GPMC during init" |
Tony Lindgren | 63aa945 | 2015-06-01 19:22:10 -0600 | [diff] [blame] | 63 | depends on OMAP_GPMC |
| 64 | help |
| 65 | Enables verbose debugging mostly to decode the bootloader provided |
Tony Lindgren | be59b61 | 2015-10-12 16:19:54 -0700 | [diff] [blame] | 66 | timings. To preserve the bootloader provided timings, the reset |
| 67 | of GPMC is skipped during init. Enable this during development to |
| 68 | configure devices connected to the GPMC bus. |
| 69 | |
| 70 | NOTE: In addition to matching the register setup with the bootloader |
| 71 | you also need to match the GPMC FCLK frequency used by the |
| 72 | bootloader or else the GPMC timings won't be identical with the |
| 73 | bootloader timings. |
Tony Lindgren | 63aa945 | 2015-06-01 19:22:10 -0600 | [diff] [blame] | 74 | |
Ezequiel Garcia | 3edad32 | 2013-04-23 16:21:26 -0300 | [diff] [blame] | 75 | config MVEBU_DEVBUS |
| 76 | bool "Marvell EBU Device Bus Controller" |
| 77 | default y |
| 78 | depends on PLAT_ORION && OF |
| 79 | help |
| 80 | This driver is for the Device Bus controller available in some |
| 81 | Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and |
| 82 | Armada 370 and Armada XP. This controller allows to handle flash |
| 83 | devices such as NOR, NAND, SRAM, and FPGA. |
| 84 | |
Hiroshi DOYU | c542fb7 | 2012-05-10 10:42:30 +0300 | [diff] [blame] | 85 | config TEGRA20_MC |
Hiroshi DOYU | f0e33f9 | 2012-05-11 09:56:24 +0300 | [diff] [blame] | 86 | bool "Tegra20 Memory Controller(MC) driver" |
| 87 | default y |
Hiroshi DOYU | c542fb7 | 2012-05-10 10:42:30 +0300 | [diff] [blame] | 88 | depends on ARCH_TEGRA_2x_SOC |
Hiroshi DOYU | f0e33f9 | 2012-05-11 09:56:24 +0300 | [diff] [blame] | 89 | help |
| 90 | This driver is for the Memory Controller(MC) module available |
| 91 | in Tegra20 SoCs, mainly for a address translation fault |
| 92 | analysis, especially for IOMMU/GART(Graphics Address |
| 93 | Relocation Table) module. |
Hiroshi DOYU | c542fb7 | 2012-05-10 10:42:30 +0300 | [diff] [blame] | 94 | |
Scott Wood | 54afbec | 2014-07-02 18:52:11 -0500 | [diff] [blame] | 95 | config FSL_CORENET_CF |
| 96 | tristate "Freescale CoreNet Error Reporting" |
| 97 | depends on FSL_SOC_BOOKE |
| 98 | help |
| 99 | Say Y for reporting of errors from the Freescale CoreNet |
| 100 | Coherency Fabric. Errors reported include accesses to |
| 101 | physical addresses that mapped by no local access window |
| 102 | (LAW) or an invalid LAW, as well as bad cache state that |
| 103 | represents a coherency violation. |
| 104 | |
Paul Gortmaker | 42d87b1 | 2014-02-19 17:46:40 -0500 | [diff] [blame] | 105 | config FSL_IFC |
| 106 | bool |
| 107 | depends on FSL_SOC |
| 108 | |
Alex Smith | 911a888 | 2015-03-09 14:29:04 +0000 | [diff] [blame] | 109 | config JZ4780_NEMC |
| 110 | bool "Ingenic JZ4780 SoC NEMC driver" |
| 111 | default y |
| 112 | depends on MACH_JZ4780 |
| 113 | help |
| 114 | This driver is for the NAND/External Memory Controller (NEMC) in |
| 115 | the Ingenic JZ4780. This controller is used to handle external |
| 116 | memory devices such as NAND and SRAM. |
| 117 | |
Yong Wu | cc8bbe1 | 2016-02-23 01:20:49 +0800 | [diff] [blame] | 118 | config MTK_SMI |
| 119 | bool |
| 120 | depends on ARCH_MEDIATEK || COMPILE_TEST |
| 121 | help |
| 122 | This driver is for the Memory Controller module in MediaTek SoCs, |
| 123 | mainly help enable/disable iommu and control the power domain and |
| 124 | clocks for each local arbiter. |
| 125 | |
Pankaj Dubey | a8aabb9 | 2016-04-11 13:12:24 +0530 | [diff] [blame] | 126 | source "drivers/memory/samsung/Kconfig" |
Thierry Reding | 8918465 | 2014-04-16 09:24:44 +0200 | [diff] [blame] | 127 | source "drivers/memory/tegra/Kconfig" |
| 128 | |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 129 | endif |